projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| f9aece73 TK |
1 | /* |
| 2 | * R8A7796 processor support - PFC hardware block. | |
| 3 | * | |
| 4 | * Copyright (C) 2016 Renesas Electronics Corp. | |
| 5 | * | |
| 6 | * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c | |
| 7 | * | |
| 8 | * R-Car Gen3 processor support - PFC hardware block. | |
| 9 | * | |
| 10 | * Copyright (C) 2015 Renesas Electronics Corporation | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of the GNU General Public License as published by | |
| 14 | * the Free Software Foundation; version 2 of the License. | |
| 15 | */ | |
| 16 | ||
| 17 | #include <linux/kernel.h> | |
| 18 | ||
| 19 | #include "core.h" | |
| 20 | #include "sh_pfc.h" | |
| 21 | ||
| 2d40bd24 NS |
22 | #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ |
| 23 | SH_PFC_PIN_CFG_PULL_UP | \ | |
| 24 | SH_PFC_PIN_CFG_PULL_DOWN) | |
| 9e35d6fa | 25 | |
| f9aece73 | 26 | #define CPU_ALL_PORT(fn, sfx) \ |
| 9e35d6fa NS |
27 | PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ |
| 28 | PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ | |
| 29 | PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ | |
| 30 | PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ | |
| 31 | PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ | |
| 32 | PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ | |
| 33 | PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ | |
| 34 | PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ | |
| 35 | PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ | |
| 36 | PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ | |
| 37 | PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ | |
| 38 | PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) | |
| f9aece73 TK |
39 | /* |
| 40 | * F_() : just information | |
| 41 | * FM() : macro for FN_xxx / xxx_MARK | |
| 42 | */ | |
| 43 | ||
| 44 | /* GPSR0 */ | |
| 45 | #define GPSR0_15 F_(D15, IP7_11_8) | |
| 46 | #define GPSR0_14 F_(D14, IP7_7_4) | |
| 47 | #define GPSR0_13 F_(D13, IP7_3_0) | |
| 48 | #define GPSR0_12 F_(D12, IP6_31_28) | |
| 49 | #define GPSR0_11 F_(D11, IP6_27_24) | |
| 50 | #define GPSR0_10 F_(D10, IP6_23_20) | |
| 51 | #define GPSR0_9 F_(D9, IP6_19_16) | |
| 52 | #define GPSR0_8 F_(D8, IP6_15_12) | |
| 53 | #define GPSR0_7 F_(D7, IP6_11_8) | |
| 54 | #define GPSR0_6 F_(D6, IP6_7_4) | |
| 55 | #define GPSR0_5 F_(D5, IP6_3_0) | |
| 56 | #define GPSR0_4 F_(D4, IP5_31_28) | |
| 57 | #define GPSR0_3 F_(D3, IP5_27_24) | |
| 58 | #define GPSR0_2 F_(D2, IP5_23_20) | |
| 59 | #define GPSR0_1 F_(D1, IP5_19_16) | |
| 60 | #define GPSR0_0 F_(D0, IP5_15_12) | |
| 61 | ||
| 62 | /* GPSR1 */ | |
| 63 | #define GPSR1_28 FM(CLKOUT) | |
| 64 | #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) | |
| 65 | #define GPSR1_26 F_(WE1_N, IP5_7_4) | |
| 66 | #define GPSR1_25 F_(WE0_N, IP5_3_0) | |
| 67 | #define GPSR1_24 F_(RD_WR_N, IP4_31_28) | |
| 68 | #define GPSR1_23 F_(RD_N, IP4_27_24) | |
| 69 | #define GPSR1_22 F_(BS_N, IP4_23_20) | |
| 70 | #define GPSR1_21 F_(CS1_N_A26, IP4_19_16) | |
| 71 | #define GPSR1_20 F_(CS0_N, IP4_15_12) | |
| 72 | #define GPSR1_19 F_(A19, IP4_11_8) | |
| 73 | #define GPSR1_18 F_(A18, IP4_7_4) | |
| 74 | #define GPSR1_17 F_(A17, IP4_3_0) | |
| 75 | #define GPSR1_16 F_(A16, IP3_31_28) | |
| 76 | #define GPSR1_15 F_(A15, IP3_27_24) | |
| 77 | #define GPSR1_14 F_(A14, IP3_23_20) | |
| 78 | #define GPSR1_13 F_(A13, IP3_19_16) | |
| 79 | #define GPSR1_12 F_(A12, IP3_15_12) | |
| 80 | #define GPSR1_11 F_(A11, IP3_11_8) | |
| 81 | #define GPSR1_10 F_(A10, IP3_7_4) | |
| 82 | #define GPSR1_9 F_(A9, IP3_3_0) | |
| 83 | #define GPSR1_8 F_(A8, IP2_31_28) | |
| 84 | #define GPSR1_7 F_(A7, IP2_27_24) | |
| 85 | #define GPSR1_6 F_(A6, IP2_23_20) | |
| 86 | #define GPSR1_5 F_(A5, IP2_19_16) | |
| 87 | #define GPSR1_4 F_(A4, IP2_15_12) | |
| 88 | #define GPSR1_3 F_(A3, IP2_11_8) | |
| 89 | #define GPSR1_2 F_(A2, IP2_7_4) | |
| 90 | #define GPSR1_1 F_(A1, IP2_3_0) | |
| 91 | #define GPSR1_0 F_(A0, IP1_31_28) | |
| 92 | ||
| 93 | /* GPSR2 */ | |
| 94 | #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) | |
| 95 | #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) | |
| 96 | #define GPSR2_12 F_(AVB_LINK, IP0_15_12) | |
| 97 | #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) | |
| 98 | #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) | |
| 99 | #define GPSR2_9 F_(AVB_MDC, IP0_3_0) | |
| 100 | #define GPSR2_8 F_(PWM2_A, IP1_27_24) | |
| 101 | #define GPSR2_7 F_(PWM1_A, IP1_23_20) | |
| 102 | #define GPSR2_6 F_(PWM0, IP1_19_16) | |
| 103 | #define GPSR2_5 F_(IRQ5, IP1_15_12) | |
| 104 | #define GPSR2_4 F_(IRQ4, IP1_11_8) | |
| 105 | #define GPSR2_3 F_(IRQ3, IP1_7_4) | |
| 106 | #define GPSR2_2 F_(IRQ2, IP1_3_0) | |
| 107 | #define GPSR2_1 F_(IRQ1, IP0_31_28) | |
| 108 | #define GPSR2_0 F_(IRQ0, IP0_27_24) | |
| 109 | ||
| 110 | /* GPSR3 */ | |
| 111 | #define GPSR3_15 F_(SD1_WP, IP11_23_20) | |
| 112 | #define GPSR3_14 F_(SD1_CD, IP11_19_16) | |
| 113 | #define GPSR3_13 F_(SD0_WP, IP11_15_12) | |
| 114 | #define GPSR3_12 F_(SD0_CD, IP11_11_8) | |
| 115 | #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) | |
| 116 | #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) | |
| 117 | #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) | |
| 118 | #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) | |
| 119 | #define GPSR3_7 F_(SD1_CMD, IP8_15_12) | |
| 120 | #define GPSR3_6 F_(SD1_CLK, IP8_11_8) | |
| 121 | #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) | |
| 122 | #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) | |
| 123 | #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) | |
| 124 | #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) | |
| 125 | #define GPSR3_1 F_(SD0_CMD, IP7_23_20) | |
| 126 | #define GPSR3_0 F_(SD0_CLK, IP7_19_16) | |
| 127 | ||
| 128 | /* GPSR4 */ | |
| 0f866a96 GU |
129 | #define GPSR4_17 F_(SD3_DS, IP11_7_4) |
| 130 | #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) | |
| 131 | #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) | |
| 132 | #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) | |
| 133 | #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) | |
| f9aece73 TK |
134 | #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) |
| 135 | #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) | |
| 136 | #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) | |
| 137 | #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) | |
| 138 | #define GPSR4_8 F_(SD3_CMD, IP10_3_0) | |
| 139 | #define GPSR4_7 F_(SD3_CLK, IP9_31_28) | |
| 0f866a96 GU |
140 | #define GPSR4_6 F_(SD2_DS, IP9_27_24) |
| 141 | #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) | |
| 142 | #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) | |
| 143 | #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) | |
| 144 | #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) | |
| f9aece73 TK |
145 | #define GPSR4_1 F_(SD2_CMD, IP9_7_4) |
| 146 | #define GPSR4_0 F_(SD2_CLK, IP9_3_0) | |
| 147 | ||
| 148 | /* GPSR5 */ | |
| 149 | #define GPSR5_25 F_(MLB_DAT, IP14_19_16) | |
| 150 | #define GPSR5_24 F_(MLB_SIG, IP14_15_12) | |
| 151 | #define GPSR5_23 F_(MLB_CLK, IP14_11_8) | |
| 152 | #define GPSR5_22 FM(MSIOF0_RXD) | |
| 153 | #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) | |
| 154 | #define GPSR5_20 FM(MSIOF0_TXD) | |
| 155 | #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) | |
| 156 | #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) | |
| 157 | #define GPSR5_17 FM(MSIOF0_SCK) | |
| 158 | #define GPSR5_16 F_(HRTS0_N, IP13_27_24) | |
| 159 | #define GPSR5_15 F_(HCTS0_N, IP13_23_20) | |
| 160 | #define GPSR5_14 F_(HTX0, IP13_19_16) | |
| 161 | #define GPSR5_13 F_(HRX0, IP13_15_12) | |
| 162 | #define GPSR5_12 F_(HSCK0, IP13_11_8) | |
| 163 | #define GPSR5_11 F_(RX2_A, IP13_7_4) | |
| 164 | #define GPSR5_10 F_(TX2_A, IP13_3_0) | |
| 165 | #define GPSR5_9 F_(SCK2, IP12_31_28) | |
| 166 | #define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) | |
| 167 | #define GPSR5_7 F_(CTS1_N, IP12_23_20) | |
| 168 | #define GPSR5_6 F_(TX1_A, IP12_19_16) | |
| 169 | #define GPSR5_5 F_(RX1_A, IP12_15_12) | |
| 170 | #define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) | |
| 171 | #define GPSR5_3 F_(CTS0_N, IP12_7_4) | |
| 172 | #define GPSR5_2 F_(TX0, IP12_3_0) | |
| 173 | #define GPSR5_1 F_(RX0, IP11_31_28) | |
| 174 | #define GPSR5_0 F_(SCK0, IP11_27_24) | |
| 175 | ||
| 176 | /* GPSR6 */ | |
| 177 | #define GPSR6_31 F_(GP6_31, IP18_7_4) | |
| 178 | #define GPSR6_30 F_(GP6_30, IP18_3_0) | |
| 179 | #define GPSR6_29 F_(USB30_OVC, IP17_31_28) | |
| 180 | #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) | |
| 181 | #define GPSR6_27 F_(USB1_OVC, IP17_23_20) | |
| 182 | #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) | |
| 183 | #define GPSR6_25 F_(USB0_OVC, IP17_15_12) | |
| 184 | #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) | |
| 185 | #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) | |
| 186 | #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) | |
| 187 | #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) | |
| 188 | #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) | |
| 189 | #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) | |
| 190 | #define GPSR6_18 F_(SSI_WS78, IP16_19_16) | |
| 191 | #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) | |
| 192 | #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) | |
| 193 | #define GPSR6_15 F_(SSI_WS6, IP16_7_4) | |
| 194 | #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) | |
| 195 | #define GPSR6_13 FM(SSI_SDATA5) | |
| 196 | #define GPSR6_12 FM(SSI_WS5) | |
| 197 | #define GPSR6_11 FM(SSI_SCK5) | |
| 198 | #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) | |
| 199 | #define GPSR6_9 F_(SSI_WS4, IP15_27_24) | |
| 200 | #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) | |
| 201 | #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) | |
| 202 | #define GPSR6_6 F_(SSI_WS34, IP15_15_12) | |
| 203 | #define GPSR6_5 F_(SSI_SCK34, IP15_11_8) | |
| 204 | #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) | |
| 205 | #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) | |
| 206 | #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) | |
| 207 | #define GPSR6_1 F_(SSI_WS0129, IP14_27_24) | |
| 208 | #define GPSR6_0 F_(SSI_SCK0129, IP14_23_20) | |
| 209 | ||
| 210 | /* GPSR7 */ | |
| 211 | #define GPSR7_3 FM(GP7_03) | |
| 212 | #define GPSR7_2 FM(HDMI0_CEC) | |
| 213 | #define GPSR7_1 FM(AVS2) | |
| 214 | #define GPSR7_0 FM(AVS1) | |
| 215 | ||
| 216 | ||
| 217 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ | |
| 218 | #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 219 | #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 220 | #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 221 | #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 222 | #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 223 | #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 224 | #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 225 | #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 226 | #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 227 | #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 228 | #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 229 | #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 230 | #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 231 | #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 232 | #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 233 | #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 234 | #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 235 | #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 236 | #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 237 | #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 238 | #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 239 | #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 240 | #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 241 | #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 242 | #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 243 | #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 244 | #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 245 | ||
| 246 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ | |
| 247 | #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 248 | #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 249 | #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 250 | #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 251 | #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 252 | #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 253 | #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 254 | #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 255 | #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 256 | #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 257 | #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 258 | #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 259 | #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 260 | #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 261 | #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 262 | #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 263 | #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 264 | #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 265 | #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 266 | #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 267 | #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 268 | #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 269 | #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 270 | #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 271 | #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 272 | #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 273 | #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 274 | #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 275 | #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 276 | ||
| 277 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ | |
| 278 | #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 279 | #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 280 | #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 281 | #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 282 | #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 283 | #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 284 | #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 285 | #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 286 | #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 287 | #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 288 | #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 289 | #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 290 | #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 291 | #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 292 | #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 293 | #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 294 | #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 295 | #define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 296 | #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 297 | #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 298 | #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 299 | #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 300 | #define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 301 | #define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 302 | #define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 303 | #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 304 | #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 305 | #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 306 | #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 307 | #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 308 | #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 309 | #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 310 | #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 311 | #define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 312 | #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 313 | ||
| 314 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ | |
| 315 | #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 316 | #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 317 | #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 318 | #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 319 | #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 320 | #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 321 | #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 322 | #define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 323 | #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 324 | #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 325 | #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 326 | #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 327 | #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 328 | #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 329 | #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 330 | #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 331 | #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 332 | #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 333 | #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 334 | #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 335 | #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) | |
| 336 | #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 337 | #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 338 | #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 339 | #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 340 | #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 341 | #define IP14_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 342 | #define IP14_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 343 | ||
| 344 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ | |
| 345 | #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 346 | #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 347 | #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 348 | #define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 349 | #define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 350 | #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 351 | #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 352 | #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 353 | #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 354 | #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 355 | #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 356 | #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 357 | #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 358 | #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 359 | #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 360 | #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 361 | #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 362 | #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 363 | #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 364 | #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) | |
| 365 | #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) | |
| 366 | #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) | |
| 367 | #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) | |
| 368 | #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) | |
| 369 | #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 370 | #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) | |
| 371 | #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) | |
| 372 | ||
| 373 | #define PINMUX_GPSR \ | |
| 374 | \ | |
| 375 | GPSR6_31 \ | |
| 376 | GPSR6_30 \ | |
| 377 | GPSR6_29 \ | |
| 378 | GPSR1_28 GPSR6_28 \ | |
| 379 | GPSR1_27 GPSR6_27 \ | |
| 380 | GPSR1_26 GPSR6_26 \ | |
| 381 | GPSR1_25 GPSR5_25 GPSR6_25 \ | |
| 382 | GPSR1_24 GPSR5_24 GPSR6_24 \ | |
| 383 | GPSR1_23 GPSR5_23 GPSR6_23 \ | |
| 384 | GPSR1_22 GPSR5_22 GPSR6_22 \ | |
| 385 | GPSR1_21 GPSR5_21 GPSR6_21 \ | |
| 386 | GPSR1_20 GPSR5_20 GPSR6_20 \ | |
| 387 | GPSR1_19 GPSR5_19 GPSR6_19 \ | |
| 388 | GPSR1_18 GPSR5_18 GPSR6_18 \ | |
| 389 | GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ | |
| 390 | GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ | |
| 391 | GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ | |
| 392 | GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ | |
| 393 | GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ | |
| 394 | GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ | |
| 395 | GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ | |
| 396 | GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ | |
| 397 | GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ | |
| 398 | GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ | |
| 399 | GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ | |
| 400 | GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ | |
| 401 | GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ | |
| 402 | GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ | |
| 403 | GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ | |
| 404 | GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ | |
| 405 | GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ | |
| 406 | GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 | |
| 407 | ||
| 408 | #define PINMUX_IPSR \ | |
| 409 | \ | |
| 410 | FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ | |
| 411 | FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ | |
| 412 | FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ | |
| 413 | FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ | |
| 414 | FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ | |
| 415 | FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ | |
| 416 | FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ | |
| 417 | FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ | |
| 418 | \ | |
| 419 | FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ | |
| 420 | FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ | |
| 421 | FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ | |
| 422 | FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ | |
| 423 | FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ | |
| 424 | FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ | |
| 425 | FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ | |
| 426 | FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ | |
| 427 | \ | |
| 428 | FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ | |
| 429 | FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ | |
| 430 | FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ | |
| 431 | FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ | |
| 432 | FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ | |
| 433 | FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ | |
| 434 | FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ | |
| 435 | FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ | |
| 436 | \ | |
| 437 | FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ | |
| 438 | FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ | |
| 439 | FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ | |
| 440 | FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ | |
| 441 | FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ | |
| 442 | FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ | |
| 443 | FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ | |
| 444 | FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ | |
| 445 | \ | |
| 446 | FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ | |
| 447 | FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ | |
| 448 | FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ | |
| 449 | FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ | |
| 450 | FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ | |
| 451 | FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ | |
| 452 | FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ | |
| 453 | FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 | |
| 454 | ||
| 455 | /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ | |
| 456 | #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 457 | #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) | |
| 458 | #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) | |
| 459 | #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) | |
| 460 | #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) | |
| 461 | #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) | |
| 462 | #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) | |
| 463 | #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) | |
| 464 | #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) | |
| 465 | #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) | |
| 466 | #define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1) | |
| 467 | #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) | |
| 468 | #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) | |
| 469 | #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) | |
| 470 | #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) | |
| 471 | #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) | |
| 472 | #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) | |
| 473 | #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) | |
| 474 | #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) | |
| 475 | #define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1) | |
| 476 | ||
| 477 | /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ | |
| 478 | #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) | |
| 479 | #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 480 | #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) | |
| 481 | #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) | |
| 482 | #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 483 | #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) | |
| 484 | #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) | |
| 485 | #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) | |
| 486 | #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) | |
| 487 | #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) | |
| 488 | #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) | |
| 489 | #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) | |
| 490 | #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) | |
| 491 | #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) | |
| 492 | #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) | |
| 493 | #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) | |
| 494 | #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) | |
| 495 | #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) | |
| 496 | #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) | |
| 497 | #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) | |
| 498 | #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) | |
| 499 | #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) | |
| 500 | ||
| 501 | /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ | |
| 502 | #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) | |
| 503 | #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) | |
| 504 | #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) | |
| 505 | #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) | |
| 506 | #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) | |
| 507 | #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
| 508 | #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) | |
| 509 | #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) | |
| 510 | #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) | |
| 511 | #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) | |
| 512 | #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) | |
| 513 | #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) | |
| 514 | #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) | |
| 515 | ||
| 516 | #define PINMUX_MOD_SELS \ | |
| 517 | \ | |
| 518 | MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ | |
| 519 | MOD_SEL2_30 \ | |
| 520 | MOD_SEL1_29_28_27 MOD_SEL2_29 \ | |
| 521 | MOD_SEL0_28_27 MOD_SEL2_28_27 \ | |
| 522 | MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ | |
| 523 | MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ | |
| 524 | MOD_SEL0_23 MOD_SEL1_23_22_21 \ | |
| 525 | MOD_SEL0_22 MOD_SEL2_22 \ | |
| 526 | MOD_SEL0_21 MOD_SEL2_21 \ | |
| 527 | MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ | |
| 528 | MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ | |
| 529 | MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ | |
| 530 | MOD_SEL2_17 \ | |
| 531 | MOD_SEL0_16 MOD_SEL1_16 \ | |
| 532 | MOD_SEL0_15 MOD_SEL1_15_14 \ | |
| 533 | MOD_SEL0_14_13 \ | |
| 534 | MOD_SEL1_13 \ | |
| 535 | MOD_SEL0_12 MOD_SEL1_12 \ | |
| 536 | MOD_SEL0_11 MOD_SEL1_11 \ | |
| 537 | MOD_SEL0_10 MOD_SEL1_10 \ | |
| 538 | MOD_SEL0_9_8 MOD_SEL1_9 \ | |
| 539 | MOD_SEL0_7_6 \ | |
| 540 | MOD_SEL1_6 \ | |
| 541 | MOD_SEL0_5 MOD_SEL1_5 \ | |
| 542 | MOD_SEL0_4_3 MOD_SEL1_4 \ | |
| 543 | MOD_SEL1_3 \ | |
| 544 | MOD_SEL0_2 MOD_SEL1_2 \ | |
| 545 | MOD_SEL1_1 \ | |
| 546 | MOD_SEL1_0 MOD_SEL2_0 | |
| 547 | ||
| 9e35d6fa NS |
548 | /* |
| 549 | * These pins are not able to be muxed but have other properties | |
| 550 | * that can be set, such as drive-strength or pull-up/pull-down enable. | |
| 551 | */ | |
| 552 | #define PINMUX_STATIC \ | |
| 553 | FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ | |
| 554 | FM(QSPI0_IO2) FM(QSPI0_IO3) \ | |
| 555 | FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ | |
| 556 | FM(QSPI1_IO2) FM(QSPI1_IO3) \ | |
| 557 | FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ | |
| 558 | FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ | |
| 559 | FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ | |
| 560 | FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ | |
| 561 | FM(PRESETOUT) \ | |
| 562 | FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ | |
| 2d40bd24 | 563 | FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) |
| 9e35d6fa | 564 | |
| f9aece73 TK |
565 | enum { |
| 566 | PINMUX_RESERVED = 0, | |
| 567 | ||
| 568 | PINMUX_DATA_BEGIN, | |
| 569 | GP_ALL(DATA), | |
| 570 | PINMUX_DATA_END, | |
| 571 | ||
| 572 | #define F_(x, y) | |
| 573 | #define FM(x) FN_##x, | |
| 574 | PINMUX_FUNCTION_BEGIN, | |
| 575 | GP_ALL(FN), | |
| 576 | PINMUX_GPSR | |
| 577 | PINMUX_IPSR | |
| 578 | PINMUX_MOD_SELS | |
| 579 | PINMUX_FUNCTION_END, | |
| 580 | #undef F_ | |
| 581 | #undef FM | |
| 582 | ||
| 583 | #define F_(x, y) | |
| 584 | #define FM(x) x##_MARK, | |
| 585 | PINMUX_MARK_BEGIN, | |
| 586 | PINMUX_GPSR | |
| 587 | PINMUX_IPSR | |
| 588 | PINMUX_MOD_SELS | |
| 9e35d6fa | 589 | PINMUX_STATIC |
| f9aece73 TK |
590 | PINMUX_MARK_END, |
| 591 | #undef F_ | |
| 592 | #undef FM | |
| 593 | }; | |
| 594 | ||
| 595 | static const u16 pinmux_data[] = { | |
| 596 | PINMUX_DATA_GP_ALL(), | |
| 597 | ||
| 598 | PINMUX_SINGLE(AVS1), | |
| 599 | PINMUX_SINGLE(AVS2), | |
| 600 | PINMUX_SINGLE(CLKOUT), | |
| 601 | PINMUX_SINGLE(GP7_03), | |
| 602 | PINMUX_SINGLE(HDMI0_CEC), | |
| 603 | PINMUX_SINGLE(MSIOF0_RXD), | |
| 604 | PINMUX_SINGLE(MSIOF0_SCK), | |
| 605 | PINMUX_SINGLE(MSIOF0_TXD), | |
| 606 | PINMUX_SINGLE(SSI_SCK5), | |
| 607 | PINMUX_SINGLE(SSI_SDATA5), | |
| 608 | PINMUX_SINGLE(SSI_WS5), | |
| 609 | ||
| 610 | /* IPSR0 */ | |
| 611 | PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), | |
| 612 | PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), | |
| 613 | ||
| 614 | PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), | |
| 615 | PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), | |
| 616 | PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), | |
| 617 | ||
| 618 | PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), | |
| 619 | PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), | |
| 620 | PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), | |
| 621 | ||
| 622 | PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), | |
| 623 | PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), | |
| 624 | PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), | |
| 625 | ||
| 626 | PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), | |
| 627 | PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), | |
| 628 | PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), | |
| 629 | ||
| 630 | PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), | |
| 631 | PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), | |
| 632 | PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), | |
| 633 | ||
| 634 | PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), | |
| 635 | PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), | |
| 636 | PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), | |
| 637 | PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), | |
| 638 | PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), | |
| 639 | PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), | |
| 640 | PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), | |
| 641 | ||
| 642 | PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), | |
| 643 | PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), | |
| 644 | PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), | |
| 645 | PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), | |
| 646 | PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), | |
| 647 | PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), | |
| 648 | PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4), | |
| 649 | ||
| 650 | /* IPSR1 */ | |
| 651 | PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), | |
| 652 | PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), | |
| 653 | PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), | |
| 654 | PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), | |
| 655 | PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), | |
| 656 | PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), | |
| 657 | ||
| 658 | PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), | |
| 659 | PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), | |
| 660 | PINMUX_IPSR_GPSR(IP1_7_4, A25), | |
| 661 | PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), | |
| 662 | PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), | |
| 663 | PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), | |
| 664 | PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), | |
| 665 | ||
| 666 | PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), | |
| 667 | PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), | |
| 668 | PINMUX_IPSR_GPSR(IP1_11_8, A24), | |
| 669 | PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), | |
| 670 | PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), | |
| 671 | PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), | |
| 672 | PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), | |
| 673 | ||
| 674 | PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), | |
| 675 | PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), | |
| 676 | PINMUX_IPSR_GPSR(IP1_15_12, A23), | |
| 677 | PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), | |
| 678 | PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), | |
| 679 | PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), | |
| 680 | PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), | |
| 681 | ||
| 682 | PINMUX_IPSR_GPSR(IP1_19_16, PWM0), | |
| 683 | PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), | |
| 684 | PINMUX_IPSR_GPSR(IP1_19_16, A22), | |
| 685 | PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), | |
| 686 | PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), | |
| 687 | ||
| 688 | PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), | |
| 689 | PINMUX_IPSR_GPSR(IP1_23_20, A21), | |
| 690 | PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), | |
| 691 | PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), | |
| 692 | PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), | |
| 693 | ||
| 694 | PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), | |
| 695 | PINMUX_IPSR_GPSR(IP1_27_24, A20), | |
| 696 | PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), | |
| 697 | PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), | |
| 698 | ||
| 699 | PINMUX_IPSR_GPSR(IP1_31_28, A0), | |
| 700 | PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), | |
| 701 | PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), | |
| 702 | PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), | |
| 703 | PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), | |
| 704 | PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), | |
| 705 | ||
| 706 | /* IPSR2 */ | |
| 707 | PINMUX_IPSR_GPSR(IP2_3_0, A1), | |
| 708 | PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), | |
| 709 | PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), | |
| 710 | PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), | |
| 711 | PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), | |
| 712 | PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), | |
| 713 | ||
| 714 | PINMUX_IPSR_GPSR(IP2_7_4, A2), | |
| 715 | PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), | |
| 716 | PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), | |
| 717 | PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), | |
| 718 | PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), | |
| 719 | PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), | |
| 720 | ||
| 721 | PINMUX_IPSR_GPSR(IP2_11_8, A3), | |
| 722 | PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), | |
| 723 | PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), | |
| 724 | PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), | |
| 725 | PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), | |
| 726 | PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), | |
| 727 | ||
| 728 | PINMUX_IPSR_GPSR(IP2_15_12, A4), | |
| 729 | PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), | |
| 730 | PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), | |
| 731 | PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), | |
| 732 | PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), | |
| 733 | PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), | |
| 734 | ||
| 735 | PINMUX_IPSR_GPSR(IP2_19_16, A5), | |
| 736 | PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), | |
| 737 | PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), | |
| 738 | PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), | |
| 739 | PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), | |
| 740 | PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), | |
| 741 | PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), | |
| 742 | ||
| 743 | PINMUX_IPSR_GPSR(IP2_23_20, A6), | |
| 744 | PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), | |
| 745 | PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), | |
| 746 | PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), | |
| 747 | PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), | |
| 748 | PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), | |
| 749 | PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), | |
| 750 | ||
| 751 | PINMUX_IPSR_GPSR(IP2_27_24, A7), | |
| 752 | PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), | |
| 753 | PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), | |
| 754 | PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), | |
| 755 | PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), | |
| 756 | PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), | |
| 757 | PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), | |
| 758 | ||
| 759 | PINMUX_IPSR_GPSR(IP2_31_28, A8), | |
| 760 | PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), | |
| 761 | PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), | |
| 762 | PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), | |
| 763 | PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), | |
| 764 | PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), | |
| 765 | PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), | |
| 766 | ||
| 767 | /* IPSR3 */ | |
| 768 | PINMUX_IPSR_GPSR(IP3_3_0, A9), | |
| 769 | PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), | |
| 770 | PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), | |
| 771 | PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), | |
| 772 | ||
| 773 | PINMUX_IPSR_GPSR(IP3_7_4, A10), | |
| 774 | PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), | |
| 775 | PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), | |
| 776 | PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), | |
| 777 | ||
| 778 | PINMUX_IPSR_GPSR(IP3_11_8, A11), | |
| 779 | PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), | |
| 780 | PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), | |
| 781 | PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), | |
| 782 | PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), | |
| 783 | PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), | |
| 784 | PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), | |
| 785 | PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), | |
| 786 | PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), | |
| 787 | ||
| 788 | PINMUX_IPSR_GPSR(IP3_15_12, A12), | |
| 789 | PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), | |
| 790 | PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), | |
| 791 | PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), | |
| 792 | PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), | |
| 793 | PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), | |
| 794 | ||
| 795 | PINMUX_IPSR_GPSR(IP3_19_16, A13), | |
| 796 | PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), | |
| 797 | PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), | |
| 798 | PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), | |
| 799 | PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), | |
| 800 | PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), | |
| 801 | ||
| 802 | PINMUX_IPSR_GPSR(IP3_23_20, A14), | |
| 803 | PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), | |
| 804 | PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), | |
| 805 | PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), | |
| 806 | PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), | |
| 807 | PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), | |
| 808 | ||
| 809 | PINMUX_IPSR_GPSR(IP3_27_24, A15), | |
| 810 | PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), | |
| 811 | PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), | |
| 812 | PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), | |
| 813 | PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), | |
| 814 | PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), | |
| 815 | ||
| 816 | PINMUX_IPSR_GPSR(IP3_31_28, A16), | |
| 817 | PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), | |
| 818 | PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), | |
| 819 | PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), | |
| 820 | ||
| 821 | /* IPSR4 */ | |
| 822 | PINMUX_IPSR_GPSR(IP4_3_0, A17), | |
| 823 | PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), | |
| 824 | PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), | |
| 825 | PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), | |
| 826 | ||
| 827 | PINMUX_IPSR_GPSR(IP4_7_4, A18), | |
| 828 | PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), | |
| 829 | PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), | |
| 830 | PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), | |
| 831 | ||
| 832 | PINMUX_IPSR_GPSR(IP4_11_8, A19), | |
| 833 | PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), | |
| 834 | PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), | |
| 835 | PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), | |
| 836 | ||
| 837 | PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), | |
| 838 | PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), | |
| 839 | ||
| 840 | PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), | |
| 841 | PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), | |
| 842 | PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), | |
| 843 | ||
| 844 | PINMUX_IPSR_GPSR(IP4_23_20, BS_N), | |
| 845 | PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), | |
| 846 | PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), | |
| 847 | PINMUX_IPSR_GPSR(IP4_23_20, SCK3), | |
| 848 | PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), | |
| 849 | PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), | |
| 850 | PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), | |
| 851 | PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), | |
| 852 | ||
| 853 | PINMUX_IPSR_GPSR(IP4_27_24, RD_N), | |
| 854 | PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), | |
| 855 | PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), | |
| 856 | PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), | |
| 857 | PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), | |
| 858 | PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), | |
| 859 | ||
| 860 | PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), | |
| 861 | PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), | |
| 862 | PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), | |
| 863 | PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), | |
| 864 | PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), | |
| 865 | PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), | |
| 866 | ||
| 867 | /* IPSR5 */ | |
| 868 | PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), | |
| 869 | PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), | |
| 870 | PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), | |
| 871 | PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), | |
| 872 | PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), | |
| 873 | PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), | |
| 874 | PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), | |
| 875 | ||
| 876 | PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), | |
| 877 | PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), | |
| 878 | PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), | |
| 879 | PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), | |
| 880 | PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), | |
| 881 | PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), | |
| 882 | PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), | |
| 883 | PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), | |
| 884 | ||
| 885 | PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), | |
| 886 | PINMUX_IPSR_GPSR(IP5_11_8, QCLK), | |
| 887 | PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), | |
| 888 | PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), | |
| 889 | ||
| 890 | PINMUX_IPSR_GPSR(IP5_15_12, D0), | |
| 891 | PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), | |
| 892 | PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), | |
| 893 | PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), | |
| 894 | PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), | |
| 895 | ||
| 896 | PINMUX_IPSR_GPSR(IP5_19_16, D1), | |
| 897 | PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), | |
| 898 | PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), | |
| 899 | PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), | |
| 900 | PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), | |
| 901 | ||
| 902 | PINMUX_IPSR_GPSR(IP5_23_20, D2), | |
| 903 | PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), | |
| 904 | PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), | |
| 905 | PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), | |
| 906 | ||
| 907 | PINMUX_IPSR_GPSR(IP5_27_24, D3), | |
| 908 | PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), | |
| 909 | PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), | |
| 910 | PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), | |
| 911 | ||
| 912 | PINMUX_IPSR_GPSR(IP5_31_28, D4), | |
| 913 | PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), | |
| 914 | PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), | |
| 915 | PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), | |
| 916 | ||
| 917 | /* IPSR6 */ | |
| 918 | PINMUX_IPSR_GPSR(IP6_3_0, D5), | |
| 919 | PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), | |
| 920 | PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), | |
| 921 | PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), | |
| 922 | ||
| 923 | PINMUX_IPSR_GPSR(IP6_7_4, D6), | |
| 924 | PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), | |
| 925 | PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), | |
| 926 | PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), | |
| 927 | ||
| 928 | PINMUX_IPSR_GPSR(IP6_11_8, D7), | |
| 929 | PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), | |
| 930 | PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), | |
| 931 | PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), | |
| 932 | ||
| 933 | PINMUX_IPSR_GPSR(IP6_15_12, D8), | |
| 934 | PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), | |
| 935 | PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), | |
| 936 | PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), | |
| 937 | PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), | |
| 938 | PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), | |
| 939 | ||
| 940 | PINMUX_IPSR_GPSR(IP6_19_16, D9), | |
| 941 | PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), | |
| 942 | PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), | |
| 943 | PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), | |
| 944 | PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), | |
| 945 | ||
| 946 | PINMUX_IPSR_GPSR(IP6_23_20, D10), | |
| 947 | PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), | |
| 948 | PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), | |
| 949 | PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), | |
| 950 | PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), | |
| 951 | PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), | |
| 952 | PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), | |
| 953 | ||
| 954 | PINMUX_IPSR_GPSR(IP6_27_24, D11), | |
| 955 | PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), | |
| 956 | PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), | |
| 957 | PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), | |
| 958 | PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), | |
| 959 | PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), | |
| 960 | PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), | |
| 961 | ||
| 962 | PINMUX_IPSR_GPSR(IP6_31_28, D12), | |
| 963 | PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), | |
| 964 | PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), | |
| 965 | PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), | |
| 966 | PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), | |
| 967 | PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), | |
| 968 | ||
| 969 | /* IPSR7 */ | |
| 970 | PINMUX_IPSR_GPSR(IP7_3_0, D13), | |
| 971 | PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), | |
| 972 | PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), | |
| 973 | PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), | |
| 974 | PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), | |
| 975 | PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), | |
| 976 | ||
| 977 | PINMUX_IPSR_GPSR(IP7_7_4, D14), | |
| 978 | PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), | |
| 979 | PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), | |
| 980 | PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), | |
| 981 | PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), | |
| 982 | PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), | |
| 983 | PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), | |
| 984 | ||
| 985 | PINMUX_IPSR_GPSR(IP7_11_8, D15), | |
| 986 | PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), | |
| 987 | PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), | |
| 988 | PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), | |
| 989 | PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), | |
| 990 | PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), | |
| 991 | PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), | |
| 992 | ||
| 993 | PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), | |
| 994 | ||
| 995 | PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), | |
| 996 | PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), | |
| 997 | PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), | |
| 998 | ||
| 999 | PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), | |
| 1000 | PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), | |
| 1001 | PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), | |
| 1002 | ||
| 1003 | PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), | |
| 1004 | PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), | |
| 1005 | PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), | |
| 1006 | PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), | |
| 1007 | ||
| 1008 | PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), | |
| 1009 | PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), | |
| 1010 | PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), | |
| 1011 | PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), | |
| 1012 | ||
| 1013 | /* IPSR8 */ | |
| 1014 | PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), | |
| 1015 | PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), | |
| 1016 | PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), | |
| 1017 | PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), | |
| 1018 | ||
| 1019 | PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), | |
| 1020 | PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), | |
| 1021 | PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), | |
| 1022 | PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), | |
| 1023 | ||
| 1024 | PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), | |
| 1025 | PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), | |
| 1026 | PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), | |
| 1027 | ||
| 1028 | PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), | |
| 1029 | PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), | |
| 1030 | PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), | |
| 1031 | PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), | |
| 1032 | PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), | |
| 1033 | ||
| 1034 | PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), | |
| 1035 | PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), | |
| 1036 | PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), | |
| 1037 | PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), | |
| 1038 | PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), | |
| 1039 | PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), | |
| 1040 | ||
| 1041 | PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), | |
| 1042 | PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), | |
| 1043 | PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), | |
| 1044 | PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), | |
| 1045 | PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), | |
| 1046 | PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), | |
| 1047 | ||
| 1048 | PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), | |
| 1049 | PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), | |
| 1050 | PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), | |
| 1051 | PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), | |
| 1052 | PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), | |
| 1053 | PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), | |
| 1054 | ||
| 1055 | PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), | |
| 1056 | PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), | |
| 1057 | PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), | |
| 1058 | PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), | |
| 1059 | PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), | |
| 1060 | PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), | |
| 1061 | ||
| 1062 | /* IPSR9 */ | |
| 1063 | PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), | |
| 1064 | PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), | |
| 1065 | ||
| 1066 | PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), | |
| 1067 | PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), | |
| 1068 | ||
| 1069 | PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), | |
| 1070 | PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), | |
| 1071 | ||
| 1072 | PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), | |
| 1073 | PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), | |
| 1074 | ||
| 1075 | PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), | |
| 1076 | PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), | |
| 1077 | ||
| 1078 | PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), | |
| 1079 | PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), | |
| 1080 | ||
| 1081 | PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), | |
| 1082 | PINMUX_IPSR_GPSR(IP9_27_24, NFALE), | |
| 1083 | ||
| 1084 | PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), | |
| 1085 | PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), | |
| 1086 | ||
| 1087 | /* IPSR10 */ | |
| 1088 | PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), | |
| 1089 | PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), | |
| 1090 | ||
| 1091 | PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), | |
| 1092 | PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), | |
| 1093 | ||
| 1094 | PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), | |
| 1095 | PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), | |
| 1096 | ||
| 1097 | PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), | |
| 1098 | PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), | |
| 1099 | ||
| 1100 | PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), | |
| 1101 | PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), | |
| 1102 | ||
| 1103 | PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), | |
| 1104 | PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), | |
| 1105 | PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), | |
| 1106 | ||
| 1107 | PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), | |
| 1108 | PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), | |
| 1109 | PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), | |
| 1110 | ||
| 1111 | PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), | |
| 1112 | PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), | |
| 1113 | PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), | |
| 1114 | ||
| 1115 | /* IPSR11 */ | |
| 1116 | PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), | |
| 1117 | PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), | |
| 1118 | PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), | |
| 1119 | ||
| 1120 | PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), | |
| 1121 | PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), | |
| 1122 | ||
| 1123 | PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), | |
| 1124 | PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), | |
| 1125 | PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), | |
| 1126 | ||
| 1127 | PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), | |
| 1128 | PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), | |
| 1129 | ||
| 1130 | PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), | |
| 1131 | PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), | |
| 1132 | ||
| 1133 | PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), | |
| 1134 | PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), | |
| 1135 | ||
| 1136 | PINMUX_IPSR_GPSR(IP11_27_24, SCK0), | |
| 1137 | PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), | |
| 1138 | PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), | |
| 1139 | PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), | |
| 1140 | PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), | |
| 1141 | PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), | |
| 1142 | PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), | |
| 1143 | PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), | |
| 1144 | PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), | |
| 1145 | PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), | |
| 1146 | ||
| 1147 | PINMUX_IPSR_GPSR(IP11_31_28, RX0), | |
| 1148 | PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), | |
| 1149 | PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), | |
| 1150 | PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), | |
| 1151 | PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), | |
| 1152 | ||
| 1153 | /* IPSR12 */ | |
| 1154 | PINMUX_IPSR_GPSR(IP12_3_0, TX0), | |
| 1155 | PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), | |
| 1156 | PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), | |
| 1157 | PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), | |
| 1158 | PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), | |
| 1159 | ||
| 1160 | PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), | |
| 1161 | PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), | |
| 1162 | PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), | |
| 1163 | PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), | |
| 1164 | PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), | |
| 1165 | PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), | |
| 1166 | PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), | |
| 1167 | PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), | |
| 1168 | ||
| 1169 | PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), | |
| 1170 | PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), | |
| 1171 | PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), | |
| 1172 | PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), | |
| 1173 | PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), | |
| 1174 | PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), | |
| 1175 | PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), | |
| 1176 | PINMUX_IPSR_MSEL(IP12_11_8, FSO_TOE_A, SEL_FSO_0), | |
| 1177 | PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), | |
| 1178 | ||
| 1179 | PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), | |
| 1180 | PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), | |
| 1181 | PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), | |
| 1182 | PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), | |
| 1183 | PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), | |
| 1184 | ||
| 1185 | PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), | |
| 1186 | PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), | |
| 1187 | PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), | |
| 1188 | PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), | |
| 1189 | PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), | |
| 1190 | ||
| 1191 | PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), | |
| 1192 | PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), | |
| 1193 | PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), | |
| 1194 | PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), | |
| 1195 | PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), | |
| 1196 | PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), | |
| 1197 | PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), | |
| 1198 | ||
| 1199 | PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), | |
| 1200 | PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), | |
| 1201 | PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), | |
| 1202 | PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), | |
| 1203 | PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), | |
| 1204 | PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), | |
| 1205 | PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), | |
| 1206 | ||
| 1207 | PINMUX_IPSR_GPSR(IP12_31_28, SCK2), | |
| 1208 | PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1), | |
| 1209 | PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), | |
| 1210 | PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), | |
| 1211 | PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), | |
| 1212 | PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), | |
| 1213 | PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), | |
| 1214 | ||
| 1215 | /* IPSR13 */ | |
| 1216 | PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), | |
| 1217 | PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), | |
| 1218 | PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), | |
| 1219 | PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), | |
| 1220 | PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), | |
| 1221 | PINMUX_IPSR_MSEL(IP13_3_0, FSO_CFE_0_B, SEL_FSO_1), | |
| 1222 | ||
| 1223 | PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), | |
| 1224 | PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), | |
| 1225 | PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), | |
| 1226 | PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), | |
| 1227 | PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), | |
| 1228 | PINMUX_IPSR_MSEL(IP13_7_4, FSO_CFE_1_B, SEL_FSO_1), | |
| 1229 | ||
| 1230 | PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), | |
| 1231 | PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), | |
| 1232 | PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), | |
| 1233 | PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1), | |
| 1234 | PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), | |
| 1235 | PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), | |
| 1236 | PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), | |
| 1237 | PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), | |
| 1238 | ||
| 1239 | PINMUX_IPSR_GPSR(IP13_15_12, HRX0), | |
| 1240 | PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), | |
| 1241 | PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1), | |
| 1242 | PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), | |
| 1243 | PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), | |
| 1244 | PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), | |
| 1245 | ||
| 1246 | PINMUX_IPSR_GPSR(IP13_19_16, HTX0), | |
| 1247 | PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), | |
| 1248 | PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1), | |
| 1249 | PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), | |
| 1250 | PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), | |
| 1251 | PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), | |
| 1252 | ||
| 1253 | PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), | |
| 1254 | PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), | |
| 1255 | PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), | |
| 1256 | PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0), | |
| 1257 | PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), | |
| 1258 | PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), | |
| 1259 | PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), | |
| 1260 | PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), | |
| 1261 | ||
| 1262 | PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), | |
| 1263 | PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), | |
| 1264 | PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), | |
| 1265 | PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0), | |
| 1266 | PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), | |
| 1267 | PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), | |
| 1268 | PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), | |
| 1269 | ||
| 1270 | PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), | |
| 1271 | PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), | |
| 1272 | PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), | |
| 1273 | PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), | |
| 1274 | ||
| 1275 | /* IPSR14 */ | |
| 1276 | PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), | |
| 1277 | PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), | |
| 1278 | PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), | |
| 1279 | PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), | |
| 1280 | PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), | |
| 1281 | PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), | |
| 1282 | PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), | |
| 1283 | PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), | |
| 1284 | ||
| 1285 | PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), | |
| 1286 | PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), | |
| 1287 | PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), | |
| 1288 | PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), | |
| 1289 | PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0), | |
| 1290 | PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), | |
| 1291 | PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), | |
| 1292 | PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), | |
| 1293 | ||
| 1294 | PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), | |
| 1295 | PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), | |
| 1296 | PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), | |
| 1297 | ||
| 1298 | PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), | |
| 1299 | PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), | |
| 1300 | PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), | |
| 1301 | PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), | |
| 1302 | ||
| 1303 | PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), | |
| 1304 | PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), | |
| 1305 | PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), | |
| 1306 | ||
| 1307 | PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK0129), | |
| 1308 | PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), | |
| 1309 | ||
| 1310 | PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS0129), | |
| 1311 | PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), | |
| 1312 | ||
| 1313 | PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), | |
| 1314 | PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), | |
| 1315 | ||
| 1316 | /* IPSR15 */ | |
| 1317 | PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0), | |
| 1318 | ||
| 1319 | PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0), | |
| 1320 | PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1), | |
| 1321 | ||
| 1322 | PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34), | |
| 1323 | PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), | |
| 1324 | PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), | |
| 1325 | ||
| 1326 | PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34), | |
| 1327 | PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), | |
| 1328 | PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), | |
| 1329 | PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), | |
| 1330 | ||
| 1331 | PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), | |
| 1332 | PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), | |
| 1333 | PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), | |
| 1334 | PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), | |
| 1335 | PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), | |
| 1336 | PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), | |
| 1337 | PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), | |
| 1338 | ||
| 1339 | PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), | |
| 1340 | PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), | |
| 1341 | PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), | |
| 1342 | PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), | |
| 1343 | PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), | |
| 1344 | PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), | |
| 1345 | PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), | |
| 1346 | ||
| 1347 | PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), | |
| 1348 | PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), | |
| 1349 | PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), | |
| 1350 | PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), | |
| 1351 | PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), | |
| 1352 | PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), | |
| 1353 | PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), | |
| 1354 | ||
| 1355 | PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), | |
| 1356 | PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), | |
| 1357 | PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), | |
| 1358 | PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), | |
| 1359 | PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), | |
| 1360 | PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), | |
| 1361 | PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), | |
| 1362 | ||
| 1363 | /* IPSR16 */ | |
| 1364 | PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), | |
| 1365 | PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), | |
| 1366 | ||
| 1367 | PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), | |
| 1368 | PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), | |
| 1369 | ||
| 1370 | PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), | |
| 1371 | PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), | |
| 1372 | ||
| 1373 | PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), | |
| 1374 | PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), | |
| 1375 | PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), | |
| 1376 | PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), | |
| 1377 | PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), | |
| 1378 | PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), | |
| 1379 | PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), | |
| 1380 | ||
| 1381 | PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), | |
| 1382 | PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), | |
| 1383 | PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), | |
| 1384 | PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), | |
| 1385 | PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), | |
| 1386 | PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), | |
| 1387 | PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), | |
| 1388 | ||
| 1389 | PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), | |
| 1390 | PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), | |
| 1391 | PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), | |
| 1392 | PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), | |
| 1393 | PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), | |
| 1394 | PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), | |
| 1395 | PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), | |
| 1396 | PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0), | |
| 1397 | ||
| 1398 | PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), | |
| 1399 | PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), | |
| 1400 | PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), | |
| 1401 | PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), | |
| 1402 | PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), | |
| 1403 | PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), | |
| 1404 | PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), | |
| 1405 | ||
| 1406 | PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0), | |
| 1407 | PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), | |
| 1408 | PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), | |
| 1409 | PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), | |
| 1410 | PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), | |
| 1411 | PINMUX_IPSR_GPSR(IP16_31_28, SCK1), | |
| 1412 | PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), | |
| 1413 | PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A), | |
| 1414 | ||
| 1415 | /* IPSR17 */ | |
| 1416 | PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), | |
| 1417 | PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), | |
| 1418 | ||
| 1419 | PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), | |
| 1420 | PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0), | |
| 1421 | PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), | |
| 1422 | PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), | |
| 1423 | PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), | |
| 1424 | ||
| 1425 | PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), | |
| 1426 | PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), | |
| 1427 | PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), | |
| 1428 | PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), | |
| 1429 | PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), | |
| 1430 | PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), | |
| 1431 | PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), | |
| 1432 | ||
| 1433 | PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), | |
| 1434 | PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), | |
| 1435 | PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), | |
| 1436 | PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), | |
| 1437 | PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), | |
| 1438 | PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), | |
| 1439 | ||
| 1440 | PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), | |
| 1441 | PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), | |
| 1442 | PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0), | |
| 1443 | PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), | |
| 1444 | PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), | |
| 1445 | PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), | |
| 1446 | PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), | |
| 1447 | PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), | |
| 1448 | PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), | |
| 1449 | ||
| 1450 | PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), | |
| 1451 | PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), | |
| 1452 | PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0), | |
| 1453 | PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), | |
| 1454 | PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), | |
| 1455 | PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), | |
| 1456 | PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), | |
| 1457 | PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), | |
| 1458 | PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), | |
| 1459 | ||
| 1460 | PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), | |
| 1461 | PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), | |
| 1462 | PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), | |
| 1463 | PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), | |
| 1464 | PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), | |
| 1465 | PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), | |
| 1466 | PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), | |
| 1467 | PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1), | |
| 1468 | PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), | |
| 1469 | PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), | |
| 1470 | PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), | |
| 1471 | ||
| 1472 | PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), | |
| 1473 | PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), | |
| 1474 | PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1), | |
| 1475 | PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), | |
| 1476 | PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), | |
| 1477 | PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), | |
| 1478 | PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), | |
| 1479 | PINMUX_IPSR_MSEL(IP17_31_28, FSO_TOE_B, SEL_FSO_1), | |
| 1480 | PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), | |
| 1481 | ||
| 1482 | /* IPSR18 */ | |
| 1483 | PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), | |
| 1484 | PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), | |
| 1485 | PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), | |
| 1486 | PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), | |
| 1487 | PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), | |
| 1488 | PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), | |
| 1489 | PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), | |
| 1490 | PINMUX_IPSR_MSEL(IP18_3_0, FSO_CFE_0_A, SEL_FSO_0), | |
| 1491 | PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), | |
| 1492 | PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), | |
| 1493 | ||
| 1494 | PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), | |
| 1495 | PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), | |
| 1496 | PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), | |
| 1497 | PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), | |
| 1498 | PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), | |
| 1499 | PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), | |
| 1500 | PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), | |
| 1501 | PINMUX_IPSR_MSEL(IP18_7_4, FSO_CFE_1_A, SEL_FSO_0), | |
| 1502 | PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), | |
| 1503 | PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), | |
| 1504 | ||
| 1505 | /* I2C */ | |
| 1506 | PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), | |
| 1507 | PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), | |
| 1508 | PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), | |
| 9e35d6fa NS |
1509 | |
| 1510 | /* | |
| 1511 | * Static pins can not be muxed between different functions but | |
| 1512 | * still needs a mark entry in the pinmux list. Add each static | |
| 1513 | * pin to the list without an associated function. The sh-pfc | |
| 1514 | * core will do the right thing and skip trying to mux then pin | |
| 1515 | * while still applying configuration to it | |
| 1516 | */ | |
| 1517 | #define FM(x) PINMUX_DATA(x##_MARK, 0), | |
| 1518 | PINMUX_STATIC | |
| 1519 | #undef FM | |
| f9aece73 TK |
1520 | }; |
| 1521 | ||
| 9e35d6fa NS |
1522 | /* |
| 1523 | * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs. | |
| 1524 | * Physical layout rows: A - AW, cols: 1 - 39. | |
| 1525 | */ | |
| 1526 | #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) | |
| 1527 | #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) | |
| 1528 | #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) | |
| 1529 | ||
| f9aece73 TK |
1530 | static const struct sh_pfc_pin pinmux_pins[] = { |
| 1531 | PINMUX_GPIO_GP_ALL(), | |
| 9e35d6fa NS |
1532 | |
| 1533 | /* | |
| 1534 | * Pins not associated with a GPIO port. | |
| 1535 | * | |
| 1536 | * The pin positions are different between different r8a7796 | |
| 1537 | * packages, all that is needed for the pfc driver is a unique | |
| 1538 | * number for each pin. To this end use the pin layout from | |
| 1539 | * R-Car M3SiP to calculate a unique number for each pin. | |
| 1540 | */ | |
| 2d40bd24 NS |
1541 | SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), |
| 1542 | SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), | |
| 1543 | SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), | |
| 1544 | SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), | |
| 1545 | SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), | |
| 1546 | SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), | |
| 1547 | SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), | |
| 1548 | SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), | |
| 1549 | SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), | |
| 1550 | SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), | |
| 1551 | SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), | |
| 1552 | SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), | |
| 1553 | SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), | |
| 1554 | SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), | |
| 1555 | SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), | |
| 1556 | SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), | |
| 1557 | SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), | |
| 1558 | SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), | |
| 1559 | SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), | |
| 1560 | SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), | |
| 1561 | SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), | |
| 1562 | SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), | |
| 1563 | SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), | |
| 1564 | SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), | |
| 1565 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), | |
| 1566 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), | |
| 1567 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), | |
| 1568 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), | |
| 1569 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), | |
| 1570 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), | |
| 1571 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), | |
| 1572 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), | |
| 1573 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), | |
| 1574 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), | |
| 1575 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), | |
| 1576 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), | |
| 1577 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), | |
| 1578 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), | |
| 1579 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), | |
| 1580 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), | |
| 9e35d6fa | 1581 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), |
| 2d40bd24 | 1582 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), |
| f9aece73 TK |
1583 | }; |
| 1584 | ||
| 9c99a63e TK |
1585 | /* - EtherAVB --------------------------------------------------------------- */ |
| 1586 | static const unsigned int avb_link_pins[] = { | |
| 1587 | /* AVB_LINK */ | |
| 1588 | RCAR_GP_PIN(2, 12), | |
| 1589 | }; | |
| 1590 | static const unsigned int avb_link_mux[] = { | |
| 1591 | AVB_LINK_MARK, | |
| 1592 | }; | |
| 1593 | static const unsigned int avb_magic_pins[] = { | |
| 1594 | /* AVB_MAGIC_ */ | |
| 1595 | RCAR_GP_PIN(2, 10), | |
| 1596 | }; | |
| 1597 | static const unsigned int avb_magic_mux[] = { | |
| 1598 | AVB_MAGIC_MARK, | |
| 1599 | }; | |
| 1600 | static const unsigned int avb_phy_int_pins[] = { | |
| 1601 | /* AVB_PHY_INT */ | |
| 1602 | RCAR_GP_PIN(2, 11), | |
| 1603 | }; | |
| 1604 | static const unsigned int avb_phy_int_mux[] = { | |
| 1605 | AVB_PHY_INT_MARK, | |
| 1606 | }; | |
| 1607 | static const unsigned int avb_mdc_pins[] = { | |
| 1608 | /* AVB_MDC */ | |
| 1609 | RCAR_GP_PIN(2, 9), | |
| 1610 | }; | |
| 1611 | static const unsigned int avb_mdc_mux[] = { | |
| 1612 | AVB_MDC_MARK, | |
| 1613 | }; | |
| 1614 | static const unsigned int avb_avtp_pps_pins[] = { | |
| 1615 | /* AVB_AVTP_PPS */ | |
| 1616 | RCAR_GP_PIN(2, 6), | |
| 1617 | }; | |
| 1618 | static const unsigned int avb_avtp_pps_mux[] = { | |
| 1619 | AVB_AVTP_PPS_MARK, | |
| 1620 | }; | |
| 1621 | static const unsigned int avb_avtp_match_a_pins[] = { | |
| 1622 | /* AVB_AVTP_MATCH_A */ | |
| 1623 | RCAR_GP_PIN(2, 13), | |
| 1624 | }; | |
| 1625 | static const unsigned int avb_avtp_match_a_mux[] = { | |
| 1626 | AVB_AVTP_MATCH_A_MARK, | |
| 1627 | }; | |
| 1628 | static const unsigned int avb_avtp_capture_a_pins[] = { | |
| 1629 | /* AVB_AVTP_CAPTURE_A */ | |
| 1630 | RCAR_GP_PIN(2, 14), | |
| 1631 | }; | |
| 1632 | static const unsigned int avb_avtp_capture_a_mux[] = { | |
| 1633 | AVB_AVTP_CAPTURE_A_MARK, | |
| 1634 | }; | |
| 1635 | static const unsigned int avb_avtp_match_b_pins[] = { | |
| 1636 | /* AVB_AVTP_MATCH_B */ | |
| 1637 | RCAR_GP_PIN(1, 8), | |
| 1638 | }; | |
| 1639 | static const unsigned int avb_avtp_match_b_mux[] = { | |
| 1640 | AVB_AVTP_MATCH_B_MARK, | |
| 1641 | }; | |
| 1642 | static const unsigned int avb_avtp_capture_b_pins[] = { | |
| 1643 | /* AVB_AVTP_CAPTURE_B */ | |
| 1644 | RCAR_GP_PIN(1, 11), | |
| 1645 | }; | |
| 1646 | static const unsigned int avb_avtp_capture_b_mux[] = { | |
| 1647 | AVB_AVTP_CAPTURE_B_MARK, | |
| 1648 | }; | |
| 1649 | ||
| cf75341a CP |
1650 | /* - CAN ------------------------------------------------------------------ */ |
| 1651 | static const unsigned int can0_data_a_pins[] = { | |
| 1652 | /* TX, RX */ | |
| 1653 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), | |
| 1654 | }; | |
| 1655 | static const unsigned int can0_data_a_mux[] = { | |
| 1656 | CAN0_TX_A_MARK, CAN0_RX_A_MARK, | |
| 1657 | }; | |
| 1658 | static const unsigned int can0_data_b_pins[] = { | |
| 1659 | /* TX, RX */ | |
| 1660 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | |
| 1661 | }; | |
| 1662 | static const unsigned int can0_data_b_mux[] = { | |
| 1663 | CAN0_TX_B_MARK, CAN0_RX_B_MARK, | |
| 1664 | }; | |
| 1665 | static const unsigned int can1_data_pins[] = { | |
| 1666 | /* TX, RX */ | |
| 1667 | RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), | |
| 1668 | }; | |
| 1669 | static const unsigned int can1_data_mux[] = { | |
| 1670 | CAN1_TX_MARK, CAN1_RX_MARK, | |
| 1671 | }; | |
| 1672 | ||
| 1673 | /* - CAN Clock -------------------------------------------------------------- */ | |
| 1674 | static const unsigned int can_clk_pins[] = { | |
| 1675 | /* CLK */ | |
| 1676 | RCAR_GP_PIN(1, 25), | |
| 1677 | }; | |
| 1678 | static const unsigned int can_clk_mux[] = { | |
| 1679 | CAN_CLK_MARK, | |
| 1680 | }; | |
| 1681 | ||
| 3dc93dce CP |
1682 | /* - CAN FD --------------------------------------------------------------- */ |
| 1683 | static const unsigned int canfd0_data_a_pins[] = { | |
| 1684 | /* TX, RX */ | |
| 1685 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), | |
| 1686 | }; | |
| 1687 | static const unsigned int canfd0_data_a_mux[] = { | |
| 1688 | CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, | |
| 1689 | }; | |
| 1690 | static const unsigned int canfd0_data_b_pins[] = { | |
| 1691 | /* TX, RX */ | |
| 1692 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | |
| 1693 | }; | |
| 1694 | static const unsigned int canfd0_data_b_mux[] = { | |
| 1695 | CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, | |
| 1696 | }; | |
| 1697 | static const unsigned int canfd1_data_pins[] = { | |
| 1698 | /* TX, RX */ | |
| 1699 | RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), | |
| 1700 | }; | |
| 1701 | static const unsigned int canfd1_data_mux[] = { | |
| 1702 | CANFD1_TX_MARK, CANFD1_RX_MARK, | |
| 1703 | }; | |
| 1704 | ||
| fb082831 RS |
1705 | /* - DRIF0 --------------------------------------------------------------- */ |
| 1706 | static const unsigned int drif0_ctrl_a_pins[] = { | |
| 1707 | /* CLK, SYNC */ | |
| 1708 | RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), | |
| 1709 | }; | |
| 1710 | static const unsigned int drif0_ctrl_a_mux[] = { | |
| 1711 | RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, | |
| 1712 | }; | |
| 1713 | static const unsigned int drif0_data0_a_pins[] = { | |
| 1714 | /* D0 */ | |
| 1715 | RCAR_GP_PIN(6, 10), | |
| 1716 | }; | |
| 1717 | static const unsigned int drif0_data0_a_mux[] = { | |
| 1718 | RIF0_D0_A_MARK, | |
| 1719 | }; | |
| 1720 | static const unsigned int drif0_data1_a_pins[] = { | |
| 1721 | /* D1 */ | |
| 1722 | RCAR_GP_PIN(6, 7), | |
| 1723 | }; | |
| 1724 | static const unsigned int drif0_data1_a_mux[] = { | |
| 1725 | RIF0_D1_A_MARK, | |
| 1726 | }; | |
| 1727 | static const unsigned int drif0_ctrl_b_pins[] = { | |
| 1728 | /* CLK, SYNC */ | |
| 1729 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), | |
| 1730 | }; | |
| 1731 | static const unsigned int drif0_ctrl_b_mux[] = { | |
| 1732 | RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, | |
| 1733 | }; | |
| 1734 | static const unsigned int drif0_data0_b_pins[] = { | |
| 1735 | /* D0 */ | |
| 1736 | RCAR_GP_PIN(5, 1), | |
| 1737 | }; | |
| 1738 | static const unsigned int drif0_data0_b_mux[] = { | |
| 1739 | RIF0_D0_B_MARK, | |
| 1740 | }; | |
| 1741 | static const unsigned int drif0_data1_b_pins[] = { | |
| 1742 | /* D1 */ | |
| 1743 | RCAR_GP_PIN(5, 2), | |
| 1744 | }; | |
| 1745 | static const unsigned int drif0_data1_b_mux[] = { | |
| 1746 | RIF0_D1_B_MARK, | |
| 1747 | }; | |
| 1748 | static const unsigned int drif0_ctrl_c_pins[] = { | |
| 1749 | /* CLK, SYNC */ | |
| 1750 | RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), | |
| 1751 | }; | |
| 1752 | static const unsigned int drif0_ctrl_c_mux[] = { | |
| 1753 | RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, | |
| 1754 | }; | |
| 1755 | static const unsigned int drif0_data0_c_pins[] = { | |
| 1756 | /* D0 */ | |
| 1757 | RCAR_GP_PIN(5, 13), | |
| 1758 | }; | |
| 1759 | static const unsigned int drif0_data0_c_mux[] = { | |
| 1760 | RIF0_D0_C_MARK, | |
| 1761 | }; | |
| 1762 | static const unsigned int drif0_data1_c_pins[] = { | |
| 1763 | /* D1 */ | |
| 1764 | RCAR_GP_PIN(5, 14), | |
| 1765 | }; | |
| 1766 | static const unsigned int drif0_data1_c_mux[] = { | |
| 1767 | RIF0_D1_C_MARK, | |
| 1768 | }; | |
| 1769 | /* - DRIF1 --------------------------------------------------------------- */ | |
| 1770 | static const unsigned int drif1_ctrl_a_pins[] = { | |
| 1771 | /* CLK, SYNC */ | |
| 1772 | RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), | |
| 1773 | }; | |
| 1774 | static const unsigned int drif1_ctrl_a_mux[] = { | |
| 1775 | RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, | |
| 1776 | }; | |
| 1777 | static const unsigned int drif1_data0_a_pins[] = { | |
| 1778 | /* D0 */ | |
| 1779 | RCAR_GP_PIN(6, 19), | |
| 1780 | }; | |
| 1781 | static const unsigned int drif1_data0_a_mux[] = { | |
| 1782 | RIF1_D0_A_MARK, | |
| 1783 | }; | |
| 1784 | static const unsigned int drif1_data1_a_pins[] = { | |
| 1785 | /* D1 */ | |
| 1786 | RCAR_GP_PIN(6, 20), | |
| 1787 | }; | |
| 1788 | static const unsigned int drif1_data1_a_mux[] = { | |
| 1789 | RIF1_D1_A_MARK, | |
| 1790 | }; | |
| 1791 | static const unsigned int drif1_ctrl_b_pins[] = { | |
| 1792 | /* CLK, SYNC */ | |
| 1793 | RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), | |
| 1794 | }; | |
| 1795 | static const unsigned int drif1_ctrl_b_mux[] = { | |
| 1796 | RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, | |
| 1797 | }; | |
| 1798 | static const unsigned int drif1_data0_b_pins[] = { | |
| 1799 | /* D0 */ | |
| 1800 | RCAR_GP_PIN(5, 7), | |
| 1801 | }; | |
| 1802 | static const unsigned int drif1_data0_b_mux[] = { | |
| 1803 | RIF1_D0_B_MARK, | |
| 1804 | }; | |
| 1805 | static const unsigned int drif1_data1_b_pins[] = { | |
| 1806 | /* D1 */ | |
| 1807 | RCAR_GP_PIN(5, 8), | |
| 1808 | }; | |
| 1809 | static const unsigned int drif1_data1_b_mux[] = { | |
| 1810 | RIF1_D1_B_MARK, | |
| 1811 | }; | |
| 1812 | static const unsigned int drif1_ctrl_c_pins[] = { | |
| 1813 | /* CLK, SYNC */ | |
| 1814 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), | |
| 1815 | }; | |
| 1816 | static const unsigned int drif1_ctrl_c_mux[] = { | |
| 1817 | RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, | |
| 1818 | }; | |
| 1819 | static const unsigned int drif1_data0_c_pins[] = { | |
| 1820 | /* D0 */ | |
| 1821 | RCAR_GP_PIN(5, 6), | |
| 1822 | }; | |
| 1823 | static const unsigned int drif1_data0_c_mux[] = { | |
| 1824 | RIF1_D0_C_MARK, | |
| 1825 | }; | |
| 1826 | static const unsigned int drif1_data1_c_pins[] = { | |
| 1827 | /* D1 */ | |
| 1828 | RCAR_GP_PIN(5, 10), | |
| 1829 | }; | |
| 1830 | static const unsigned int drif1_data1_c_mux[] = { | |
| 1831 | RIF1_D1_C_MARK, | |
| 1832 | }; | |
| 1833 | /* - DRIF2 --------------------------------------------------------------- */ | |
| 1834 | static const unsigned int drif2_ctrl_a_pins[] = { | |
| 1835 | /* CLK, SYNC */ | |
| 1836 | RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), | |
| 1837 | }; | |
| 1838 | static const unsigned int drif2_ctrl_a_mux[] = { | |
| 1839 | RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, | |
| 1840 | }; | |
| 1841 | static const unsigned int drif2_data0_a_pins[] = { | |
| 1842 | /* D0 */ | |
| 1843 | RCAR_GP_PIN(6, 7), | |
| 1844 | }; | |
| 1845 | static const unsigned int drif2_data0_a_mux[] = { | |
| 1846 | RIF2_D0_A_MARK, | |
| 1847 | }; | |
| 1848 | static const unsigned int drif2_data1_a_pins[] = { | |
| 1849 | /* D1 */ | |
| 1850 | RCAR_GP_PIN(6, 10), | |
| 1851 | }; | |
| 1852 | static const unsigned int drif2_data1_a_mux[] = { | |
| 1853 | RIF2_D1_A_MARK, | |
| 1854 | }; | |
| 1855 | static const unsigned int drif2_ctrl_b_pins[] = { | |
| 1856 | /* CLK, SYNC */ | |
| 1857 | RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), | |
| 1858 | }; | |
| 1859 | static const unsigned int drif2_ctrl_b_mux[] = { | |
| 1860 | RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, | |
| 1861 | }; | |
| 1862 | static const unsigned int drif2_data0_b_pins[] = { | |
| 1863 | /* D0 */ | |
| 1864 | RCAR_GP_PIN(6, 30), | |
| 1865 | }; | |
| 1866 | static const unsigned int drif2_data0_b_mux[] = { | |
| 1867 | RIF2_D0_B_MARK, | |
| 1868 | }; | |
| 1869 | static const unsigned int drif2_data1_b_pins[] = { | |
| 1870 | /* D1 */ | |
| 1871 | RCAR_GP_PIN(6, 31), | |
| 1872 | }; | |
| 1873 | static const unsigned int drif2_data1_b_mux[] = { | |
| 1874 | RIF2_D1_B_MARK, | |
| 1875 | }; | |
| 1876 | /* - DRIF3 --------------------------------------------------------------- */ | |
| 1877 | static const unsigned int drif3_ctrl_a_pins[] = { | |
| 1878 | /* CLK, SYNC */ | |
| 1879 | RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), | |
| 1880 | }; | |
| 1881 | static const unsigned int drif3_ctrl_a_mux[] = { | |
| 1882 | RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, | |
| 1883 | }; | |
| 1884 | static const unsigned int drif3_data0_a_pins[] = { | |
| 1885 | /* D0 */ | |
| 1886 | RCAR_GP_PIN(6, 19), | |
| 1887 | }; | |
| 1888 | static const unsigned int drif3_data0_a_mux[] = { | |
| 1889 | RIF3_D0_A_MARK, | |
| 1890 | }; | |
| 1891 | static const unsigned int drif3_data1_a_pins[] = { | |
| 1892 | /* D1 */ | |
| 1893 | RCAR_GP_PIN(6, 20), | |
| 1894 | }; | |
| 1895 | static const unsigned int drif3_data1_a_mux[] = { | |
| 1896 | RIF3_D1_A_MARK, | |
| 1897 | }; | |
| 1898 | static const unsigned int drif3_ctrl_b_pins[] = { | |
| 1899 | /* CLK, SYNC */ | |
| 1900 | RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), | |
| 1901 | }; | |
| 1902 | static const unsigned int drif3_ctrl_b_mux[] = { | |
| 1903 | RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, | |
| 1904 | }; | |
| 1905 | static const unsigned int drif3_data0_b_pins[] = { | |
| 1906 | /* D0 */ | |
| 1907 | RCAR_GP_PIN(6, 28), | |
| 1908 | }; | |
| 1909 | static const unsigned int drif3_data0_b_mux[] = { | |
| 1910 | RIF3_D0_B_MARK, | |
| 1911 | }; | |
| 1912 | static const unsigned int drif3_data1_b_pins[] = { | |
| 1913 | /* D1 */ | |
| 1914 | RCAR_GP_PIN(6, 29), | |
| 1915 | }; | |
| 1916 | static const unsigned int drif3_data1_b_mux[] = { | |
| 1917 | RIF3_D1_B_MARK, | |
| 1918 | }; | |
| 1919 | ||
| cccc618a NS |
1920 | /* - DU --------------------------------------------------------------------- */ |
| 1921 | static const unsigned int du_rgb666_pins[] = { | |
| 1922 | /* R[7:2], G[7:2], B[7:2] */ | |
| 1923 | RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), | |
| 1924 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), | |
| 1925 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), | |
| 1926 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), | |
| 1927 | RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), | |
| 1928 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), | |
| 1929 | }; | |
| 1930 | static const unsigned int du_rgb666_mux[] = { | |
| 1931 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, | |
| 1932 | DU_DR3_MARK, DU_DR2_MARK, | |
| 1933 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, | |
| 1934 | DU_DG3_MARK, DU_DG2_MARK, | |
| 1935 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, | |
| 1936 | DU_DB3_MARK, DU_DB2_MARK, | |
| 1937 | }; | |
| 1938 | static const unsigned int du_rgb888_pins[] = { | |
| 1939 | /* R[7:0], G[7:0], B[7:0] */ | |
| 1940 | RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), | |
| 1941 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), | |
| 1942 | RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), | |
| 1943 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), | |
| 1944 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), | |
| 1945 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), | |
| 1946 | RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), | |
| 1947 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), | |
| 1948 | RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), | |
| 1949 | }; | |
| 1950 | static const unsigned int du_rgb888_mux[] = { | |
| 1951 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, | |
| 1952 | DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, | |
| 1953 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, | |
| 1954 | DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, | |
| 1955 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, | |
| 1956 | DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, | |
| 1957 | }; | |
| 1958 | static const unsigned int du_clk_out_0_pins[] = { | |
| 1959 | /* CLKOUT */ | |
| 1960 | RCAR_GP_PIN(1, 27), | |
| 1961 | }; | |
| 1962 | static const unsigned int du_clk_out_0_mux[] = { | |
| 1963 | DU_DOTCLKOUT0_MARK | |
| 1964 | }; | |
| 1965 | static const unsigned int du_clk_out_1_pins[] = { | |
| 1966 | /* CLKOUT */ | |
| 1967 | RCAR_GP_PIN(2, 3), | |
| 1968 | }; | |
| 1969 | static const unsigned int du_clk_out_1_mux[] = { | |
| 1970 | DU_DOTCLKOUT1_MARK | |
| 1971 | }; | |
| 1972 | static const unsigned int du_sync_pins[] = { | |
| 1973 | /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ | |
| 1974 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), | |
| 1975 | }; | |
| 1976 | static const unsigned int du_sync_mux[] = { | |
| 1977 | DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK | |
| 1978 | }; | |
| 1979 | static const unsigned int du_oddf_pins[] = { | |
| 1980 | /* EXDISP/EXODDF/EXCDE */ | |
| 1981 | RCAR_GP_PIN(2, 2), | |
| 1982 | }; | |
| 1983 | static const unsigned int du_oddf_mux[] = { | |
| 1984 | DU_EXODDF_DU_ODDF_DISP_CDE_MARK, | |
| 1985 | }; | |
| 1986 | static const unsigned int du_cde_pins[] = { | |
| 1987 | /* CDE */ | |
| 1988 | RCAR_GP_PIN(2, 0), | |
| 1989 | }; | |
| 1990 | static const unsigned int du_cde_mux[] = { | |
| 1991 | DU_CDE_MARK, | |
| 1992 | }; | |
| 1993 | static const unsigned int du_disp_pins[] = { | |
| 1994 | /* DISP */ | |
| 1995 | RCAR_GP_PIN(2, 1), | |
| 1996 | }; | |
| 1997 | static const unsigned int du_disp_mux[] = { | |
| 1998 | DU_DISP_MARK, | |
| 1999 | }; | |
| 2000 | ||
| 0e4e4999 UH |
2001 | /* - HSCIF0 ----------------------------------------------------------------- */ |
| 2002 | static const unsigned int hscif0_data_pins[] = { | |
| 2003 | /* RX, TX */ | |
| 2004 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), | |
| 2005 | }; | |
| 2006 | static const unsigned int hscif0_data_mux[] = { | |
| 2007 | HRX0_MARK, HTX0_MARK, | |
| 2008 | }; | |
| 2009 | static const unsigned int hscif0_clk_pins[] = { | |
| 2010 | /* SCK */ | |
| 2011 | RCAR_GP_PIN(5, 12), | |
| 2012 | }; | |
| 2013 | static const unsigned int hscif0_clk_mux[] = { | |
| 2014 | HSCK0_MARK, | |
| 2015 | }; | |
| 2016 | static const unsigned int hscif0_ctrl_pins[] = { | |
| 2017 | /* RTS, CTS */ | |
| 2018 | RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), | |
| 2019 | }; | |
| 2020 | static const unsigned int hscif0_ctrl_mux[] = { | |
| 2021 | HRTS0_N_MARK, HCTS0_N_MARK, | |
| 2022 | }; | |
| 2023 | /* - HSCIF1 ----------------------------------------------------------------- */ | |
| 2024 | static const unsigned int hscif1_data_a_pins[] = { | |
| 2025 | /* RX, TX */ | |
| 2026 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
| 2027 | }; | |
| 2028 | static const unsigned int hscif1_data_a_mux[] = { | |
| 2029 | HRX1_A_MARK, HTX1_A_MARK, | |
| 2030 | }; | |
| 2031 | static const unsigned int hscif1_clk_a_pins[] = { | |
| 2032 | /* SCK */ | |
| 2033 | RCAR_GP_PIN(6, 21), | |
| 2034 | }; | |
| 2035 | static const unsigned int hscif1_clk_a_mux[] = { | |
| 2036 | HSCK1_A_MARK, | |
| 2037 | }; | |
| 2038 | static const unsigned int hscif1_ctrl_a_pins[] = { | |
| 2039 | /* RTS, CTS */ | |
| 2040 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), | |
| 2041 | }; | |
| 2042 | static const unsigned int hscif1_ctrl_a_mux[] = { | |
| 2043 | HRTS1_N_A_MARK, HCTS1_N_A_MARK, | |
| 2044 | }; | |
| 2045 | ||
| 2046 | static const unsigned int hscif1_data_b_pins[] = { | |
| 2047 | /* RX, TX */ | |
| 2048 | RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), | |
| 2049 | }; | |
| 2050 | static const unsigned int hscif1_data_b_mux[] = { | |
| 2051 | HRX1_B_MARK, HTX1_B_MARK, | |
| 2052 | }; | |
| 2053 | static const unsigned int hscif1_clk_b_pins[] = { | |
| 2054 | /* SCK */ | |
| 2055 | RCAR_GP_PIN(5, 0), | |
| 2056 | }; | |
| 2057 | static const unsigned int hscif1_clk_b_mux[] = { | |
| 2058 | HSCK1_B_MARK, | |
| 2059 | }; | |
| 2060 | static const unsigned int hscif1_ctrl_b_pins[] = { | |
| 2061 | /* RTS, CTS */ | |
| 2062 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), | |
| 2063 | }; | |
| 2064 | static const unsigned int hscif1_ctrl_b_mux[] = { | |
| 2065 | HRTS1_N_B_MARK, HCTS1_N_B_MARK, | |
| 2066 | }; | |
| 2067 | /* - HSCIF2 ----------------------------------------------------------------- */ | |
| 2068 | static const unsigned int hscif2_data_a_pins[] = { | |
| 2069 | /* RX, TX */ | |
| 2070 | RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), | |
| 2071 | }; | |
| 2072 | static const unsigned int hscif2_data_a_mux[] = { | |
| 2073 | HRX2_A_MARK, HTX2_A_MARK, | |
| 2074 | }; | |
| 2075 | static const unsigned int hscif2_clk_a_pins[] = { | |
| 2076 | /* SCK */ | |
| 2077 | RCAR_GP_PIN(6, 10), | |
| 2078 | }; | |
| 2079 | static const unsigned int hscif2_clk_a_mux[] = { | |
| 2080 | HSCK2_A_MARK, | |
| 2081 | }; | |
| 2082 | static const unsigned int hscif2_ctrl_a_pins[] = { | |
| 2083 | /* RTS, CTS */ | |
| 2084 | RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), | |
| 2085 | }; | |
| 2086 | static const unsigned int hscif2_ctrl_a_mux[] = { | |
| 2087 | HRTS2_N_A_MARK, HCTS2_N_A_MARK, | |
| 2088 | }; | |
| 2089 | ||
| 2090 | static const unsigned int hscif2_data_b_pins[] = { | |
| 2091 | /* RX, TX */ | |
| 2092 | RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), | |
| 2093 | }; | |
| 2094 | static const unsigned int hscif2_data_b_mux[] = { | |
| 2095 | HRX2_B_MARK, HTX2_B_MARK, | |
| 2096 | }; | |
| 2097 | static const unsigned int hscif2_clk_b_pins[] = { | |
| 2098 | /* SCK */ | |
| 2099 | RCAR_GP_PIN(6, 21), | |
| 2100 | }; | |
| 2101 | static const unsigned int hscif2_clk_b_mux[] = { | |
| 2102 | HSCK2_B_MARK, | |
| 2103 | }; | |
| 2104 | static const unsigned int hscif2_ctrl_b_pins[] = { | |
| 2105 | /* RTS, CTS */ | |
| 2106 | RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), | |
| 2107 | }; | |
| 2108 | static const unsigned int hscif2_ctrl_b_mux[] = { | |
| 2109 | HRTS2_N_B_MARK, HCTS2_N_B_MARK, | |
| 2110 | }; | |
| 2111 | ||
| 2112 | static const unsigned int hscif2_data_c_pins[] = { | |
| 2113 | /* RX, TX */ | |
| 2114 | RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), | |
| 2115 | }; | |
| 2116 | static const unsigned int hscif2_data_c_mux[] = { | |
| 2117 | HRX2_C_MARK, HTX2_C_MARK, | |
| 2118 | }; | |
| 2119 | static const unsigned int hscif2_clk_c_pins[] = { | |
| 2120 | /* SCK */ | |
| 2121 | RCAR_GP_PIN(6, 24), | |
| 2122 | }; | |
| 2123 | static const unsigned int hscif2_clk_c_mux[] = { | |
| 2124 | HSCK2_C_MARK, | |
| 2125 | }; | |
| 2126 | static const unsigned int hscif2_ctrl_c_pins[] = { | |
| 2127 | /* RTS, CTS */ | |
| 2128 | RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), | |
| 2129 | }; | |
| 2130 | static const unsigned int hscif2_ctrl_c_mux[] = { | |
| 2131 | HRTS2_N_C_MARK, HCTS2_N_C_MARK, | |
| 2132 | }; | |
| 2133 | /* - HSCIF3 ----------------------------------------------------------------- */ | |
| 2134 | static const unsigned int hscif3_data_a_pins[] = { | |
| 2135 | /* RX, TX */ | |
| 2136 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), | |
| 2137 | }; | |
| 2138 | static const unsigned int hscif3_data_a_mux[] = { | |
| 2139 | HRX3_A_MARK, HTX3_A_MARK, | |
| 2140 | }; | |
| 2141 | static const unsigned int hscif3_clk_pins[] = { | |
| 2142 | /* SCK */ | |
| 2143 | RCAR_GP_PIN(1, 22), | |
| 2144 | }; | |
| 2145 | static const unsigned int hscif3_clk_mux[] = { | |
| 2146 | HSCK3_MARK, | |
| 2147 | }; | |
| 2148 | static const unsigned int hscif3_ctrl_pins[] = { | |
| 2149 | /* RTS, CTS */ | |
| 2150 | RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), | |
| 2151 | }; | |
| 2152 | static const unsigned int hscif3_ctrl_mux[] = { | |
| 2153 | HRTS3_N_MARK, HCTS3_N_MARK, | |
| 2154 | }; | |
| 2155 | ||
| 2156 | static const unsigned int hscif3_data_b_pins[] = { | |
| 2157 | /* RX, TX */ | |
| 2158 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | |
| 2159 | }; | |
| 2160 | static const unsigned int hscif3_data_b_mux[] = { | |
| 2161 | HRX3_B_MARK, HTX3_B_MARK, | |
| 2162 | }; | |
| 2163 | static const unsigned int hscif3_data_c_pins[] = { | |
| 2164 | /* RX, TX */ | |
| 2165 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
| 2166 | }; | |
| 2167 | static const unsigned int hscif3_data_c_mux[] = { | |
| 2168 | HRX3_C_MARK, HTX3_C_MARK, | |
| 2169 | }; | |
| 2170 | static const unsigned int hscif3_data_d_pins[] = { | |
| 2171 | /* RX, TX */ | |
| 2172 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), | |
| 2173 | }; | |
| 2174 | static const unsigned int hscif3_data_d_mux[] = { | |
| 2175 | HRX3_D_MARK, HTX3_D_MARK, | |
| 2176 | }; | |
| 2177 | /* - HSCIF4 ----------------------------------------------------------------- */ | |
| 2178 | static const unsigned int hscif4_data_a_pins[] = { | |
| 2179 | /* RX, TX */ | |
| 2180 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | |
| 2181 | }; | |
| 2182 | static const unsigned int hscif4_data_a_mux[] = { | |
| 2183 | HRX4_A_MARK, HTX4_A_MARK, | |
| 2184 | }; | |
| 2185 | static const unsigned int hscif4_clk_pins[] = { | |
| 2186 | /* SCK */ | |
| 2187 | RCAR_GP_PIN(1, 11), | |
| 2188 | }; | |
| 2189 | static const unsigned int hscif4_clk_mux[] = { | |
| 2190 | HSCK4_MARK, | |
| 2191 | }; | |
| 2192 | static const unsigned int hscif4_ctrl_pins[] = { | |
| 2193 | /* RTS, CTS */ | |
| 2194 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), | |
| 2195 | }; | |
| 2196 | static const unsigned int hscif4_ctrl_mux[] = { | |
| 2197 | HRTS4_N_MARK, HCTS4_N_MARK, | |
| 2198 | }; | |
| 2199 | ||
| 2200 | static const unsigned int hscif4_data_b_pins[] = { | |
| 2201 | /* RX, TX */ | |
| 2202 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), | |
| 2203 | }; | |
| 2204 | static const unsigned int hscif4_data_b_mux[] = { | |
| 2205 | HRX4_B_MARK, HTX4_B_MARK, | |
| 2206 | }; | |
| 2207 | ||
| 02609a23 UH |
2208 | /* - I2C -------------------------------------------------------------------- */ |
| 2209 | static const unsigned int i2c1_a_pins[] = { | |
| 2210 | /* SDA, SCL */ | |
| 2211 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), | |
| 2212 | }; | |
| 2213 | static const unsigned int i2c1_a_mux[] = { | |
| 2214 | SDA1_A_MARK, SCL1_A_MARK, | |
| 2215 | }; | |
| 2216 | static const unsigned int i2c1_b_pins[] = { | |
| 2217 | /* SDA, SCL */ | |
| 2218 | RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), | |
| 2219 | }; | |
| 2220 | static const unsigned int i2c1_b_mux[] = { | |
| 2221 | SDA1_B_MARK, SCL1_B_MARK, | |
| 2222 | }; | |
| 2223 | static const unsigned int i2c2_a_pins[] = { | |
| 2224 | /* SDA, SCL */ | |
| 2225 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), | |
| 2226 | }; | |
| 2227 | static const unsigned int i2c2_a_mux[] = { | |
| 2228 | SDA2_A_MARK, SCL2_A_MARK, | |
| 2229 | }; | |
| 2230 | static const unsigned int i2c2_b_pins[] = { | |
| 2231 | /* SDA, SCL */ | |
| 2232 | RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), | |
| 2233 | }; | |
| 2234 | static const unsigned int i2c2_b_mux[] = { | |
| 2235 | SDA2_B_MARK, SCL2_B_MARK, | |
| 2236 | }; | |
| 2237 | static const unsigned int i2c6_a_pins[] = { | |
| 2238 | /* SDA, SCL */ | |
| 2239 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), | |
| 2240 | }; | |
| 2241 | static const unsigned int i2c6_a_mux[] = { | |
| 2242 | SDA6_A_MARK, SCL6_A_MARK, | |
| 2243 | }; | |
| 2244 | static const unsigned int i2c6_b_pins[] = { | |
| 2245 | /* SDA, SCL */ | |
| 2246 | RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), | |
| 2247 | }; | |
| 2248 | static const unsigned int i2c6_b_mux[] = { | |
| 2249 | SDA6_B_MARK, SCL6_B_MARK, | |
| 2250 | }; | |
| 2251 | static const unsigned int i2c6_c_pins[] = { | |
| 2252 | /* SDA, SCL */ | |
| 2253 | RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), | |
| 2254 | }; | |
| 2255 | static const unsigned int i2c6_c_mux[] = { | |
| 2256 | SDA6_C_MARK, SCL6_C_MARK, | |
| 2257 | }; | |
| 2258 | ||
| 4753231c TK |
2259 | /* - MSIOF0 ----------------------------------------------------------------- */ |
| 2260 | static const unsigned int msiof0_clk_pins[] = { | |
| 2261 | /* SCK */ | |
| 2262 | RCAR_GP_PIN(5, 17), | |
| 2263 | }; | |
| 2264 | static const unsigned int msiof0_clk_mux[] = { | |
| 2265 | MSIOF0_SCK_MARK, | |
| 2266 | }; | |
| 2267 | static const unsigned int msiof0_sync_pins[] = { | |
| 2268 | /* SYNC */ | |
| 2269 | RCAR_GP_PIN(5, 18), | |
| 2270 | }; | |
| 2271 | static const unsigned int msiof0_sync_mux[] = { | |
| 2272 | MSIOF0_SYNC_MARK, | |
| 2273 | }; | |
| 2274 | static const unsigned int msiof0_ss1_pins[] = { | |
| 2275 | /* SS1 */ | |
| 2276 | RCAR_GP_PIN(5, 19), | |
| 2277 | }; | |
| 2278 | static const unsigned int msiof0_ss1_mux[] = { | |
| 2279 | MSIOF0_SS1_MARK, | |
| 2280 | }; | |
| 2281 | static const unsigned int msiof0_ss2_pins[] = { | |
| 2282 | /* SS2 */ | |
| 2283 | RCAR_GP_PIN(5, 21), | |
| 2284 | }; | |
| 2285 | static const unsigned int msiof0_ss2_mux[] = { | |
| 2286 | MSIOF0_SS2_MARK, | |
| 2287 | }; | |
| 2288 | static const unsigned int msiof0_txd_pins[] = { | |
| 2289 | /* TXD */ | |
| 2290 | RCAR_GP_PIN(5, 20), | |
| 2291 | }; | |
| 2292 | static const unsigned int msiof0_txd_mux[] = { | |
| 2293 | MSIOF0_TXD_MARK, | |
| 2294 | }; | |
| 2295 | static const unsigned int msiof0_rxd_pins[] = { | |
| 2296 | /* RXD */ | |
| 2297 | RCAR_GP_PIN(5, 22), | |
| 2298 | }; | |
| 2299 | static const unsigned int msiof0_rxd_mux[] = { | |
| 2300 | MSIOF0_RXD_MARK, | |
| 2301 | }; | |
| 2302 | /* - MSIOF1 ----------------------------------------------------------------- */ | |
| 2303 | static const unsigned int msiof1_clk_a_pins[] = { | |
| 2304 | /* SCK */ | |
| 2305 | RCAR_GP_PIN(6, 8), | |
| 2306 | }; | |
| 2307 | static const unsigned int msiof1_clk_a_mux[] = { | |
| 2308 | MSIOF1_SCK_A_MARK, | |
| 2309 | }; | |
| 2310 | static const unsigned int msiof1_sync_a_pins[] = { | |
| 2311 | /* SYNC */ | |
| 2312 | RCAR_GP_PIN(6, 9), | |
| 2313 | }; | |
| 2314 | static const unsigned int msiof1_sync_a_mux[] = { | |
| 2315 | MSIOF1_SYNC_A_MARK, | |
| 2316 | }; | |
| 2317 | static const unsigned int msiof1_ss1_a_pins[] = { | |
| 2318 | /* SS1 */ | |
| 2319 | RCAR_GP_PIN(6, 5), | |
| 2320 | }; | |
| 2321 | static const unsigned int msiof1_ss1_a_mux[] = { | |
| 2322 | MSIOF1_SS1_A_MARK, | |
| 2323 | }; | |
| 2324 | static const unsigned int msiof1_ss2_a_pins[] = { | |
| 2325 | /* SS2 */ | |
| 2326 | RCAR_GP_PIN(6, 6), | |
| 2327 | }; | |
| 2328 | static const unsigned int msiof1_ss2_a_mux[] = { | |
| 2329 | MSIOF1_SS2_A_MARK, | |
| 2330 | }; | |
| 2331 | static const unsigned int msiof1_txd_a_pins[] = { | |
| 2332 | /* TXD */ | |
| 2333 | RCAR_GP_PIN(6, 7), | |
| 2334 | }; | |
| 2335 | static const unsigned int msiof1_txd_a_mux[] = { | |
| 2336 | MSIOF1_TXD_A_MARK, | |
| 2337 | }; | |
| 2338 | static const unsigned int msiof1_rxd_a_pins[] = { | |
| 2339 | /* RXD */ | |
| 2340 | RCAR_GP_PIN(6, 10), | |
| 2341 | }; | |
| 2342 | static const unsigned int msiof1_rxd_a_mux[] = { | |
| 2343 | MSIOF1_RXD_A_MARK, | |
| 2344 | }; | |
| 2345 | static const unsigned int msiof1_clk_b_pins[] = { | |
| 2346 | /* SCK */ | |
| 2347 | RCAR_GP_PIN(5, 9), | |
| 2348 | }; | |
| 2349 | static const unsigned int msiof1_clk_b_mux[] = { | |
| 2350 | MSIOF1_SCK_B_MARK, | |
| 2351 | }; | |
| 2352 | static const unsigned int msiof1_sync_b_pins[] = { | |
| 2353 | /* SYNC */ | |
| 2354 | RCAR_GP_PIN(5, 3), | |
| 2355 | }; | |
| 2356 | static const unsigned int msiof1_sync_b_mux[] = { | |
| 2357 | MSIOF1_SYNC_B_MARK, | |
| 2358 | }; | |
| 2359 | static const unsigned int msiof1_ss1_b_pins[] = { | |
| 2360 | /* SS1 */ | |
| 2361 | RCAR_GP_PIN(5, 4), | |
| 2362 | }; | |
| 2363 | static const unsigned int msiof1_ss1_b_mux[] = { | |
| 2364 | MSIOF1_SS1_B_MARK, | |
| 2365 | }; | |
| 2366 | static const unsigned int msiof1_ss2_b_pins[] = { | |
| 2367 | /* SS2 */ | |
| 2368 | RCAR_GP_PIN(5, 0), | |
| 2369 | }; | |
| 2370 | static const unsigned int msiof1_ss2_b_mux[] = { | |
| 2371 | MSIOF1_SS2_B_MARK, | |
| 2372 | }; | |
| 2373 | static const unsigned int msiof1_txd_b_pins[] = { | |
| 2374 | /* TXD */ | |
| 2375 | RCAR_GP_PIN(5, 8), | |
| 2376 | }; | |
| 2377 | static const unsigned int msiof1_txd_b_mux[] = { | |
| 2378 | MSIOF1_TXD_B_MARK, | |
| 2379 | }; | |
| 2380 | static const unsigned int msiof1_rxd_b_pins[] = { | |
| 2381 | /* RXD */ | |
| 2382 | RCAR_GP_PIN(5, 7), | |
| 2383 | }; | |
| 2384 | static const unsigned int msiof1_rxd_b_mux[] = { | |
| 2385 | MSIOF1_RXD_B_MARK, | |
| 2386 | }; | |
| 2387 | static const unsigned int msiof1_clk_c_pins[] = { | |
| 2388 | /* SCK */ | |
| 2389 | RCAR_GP_PIN(6, 17), | |
| 2390 | }; | |
| 2391 | static const unsigned int msiof1_clk_c_mux[] = { | |
| 2392 | MSIOF1_SCK_C_MARK, | |
| 2393 | }; | |
| 2394 | static const unsigned int msiof1_sync_c_pins[] = { | |
| 2395 | /* SYNC */ | |
| 2396 | RCAR_GP_PIN(6, 18), | |
| 2397 | }; | |
| 2398 | static const unsigned int msiof1_sync_c_mux[] = { | |
| 2399 | MSIOF1_SYNC_C_MARK, | |
| 2400 | }; | |
| 2401 | static const unsigned int msiof1_ss1_c_pins[] = { | |
| 2402 | /* SS1 */ | |
| 2403 | RCAR_GP_PIN(6, 21), | |
| 2404 | }; | |
| 2405 | static const unsigned int msiof1_ss1_c_mux[] = { | |
| 2406 | MSIOF1_SS1_C_MARK, | |
| 2407 | }; | |
| 2408 | static const unsigned int msiof1_ss2_c_pins[] = { | |
| 2409 | /* SS2 */ | |
| 2410 | RCAR_GP_PIN(6, 27), | |
| 2411 | }; | |
| 2412 | static const unsigned int msiof1_ss2_c_mux[] = { | |
| 2413 | MSIOF1_SS2_C_MARK, | |
| 2414 | }; | |
| 2415 | static const unsigned int msiof1_txd_c_pins[] = { | |
| 2416 | /* TXD */ | |
| 2417 | RCAR_GP_PIN(6, 20), | |
| 2418 | }; | |
| 2419 | static const unsigned int msiof1_txd_c_mux[] = { | |
| 2420 | MSIOF1_TXD_C_MARK, | |
| 2421 | }; | |
| 2422 | static const unsigned int msiof1_rxd_c_pins[] = { | |
| 2423 | /* RXD */ | |
| 2424 | RCAR_GP_PIN(6, 19), | |
| 2425 | }; | |
| 2426 | static const unsigned int msiof1_rxd_c_mux[] = { | |
| 2427 | MSIOF1_RXD_C_MARK, | |
| 2428 | }; | |
| 2429 | static const unsigned int msiof1_clk_d_pins[] = { | |
| 2430 | /* SCK */ | |
| 2431 | RCAR_GP_PIN(5, 12), | |
| 2432 | }; | |
| 2433 | static const unsigned int msiof1_clk_d_mux[] = { | |
| 2434 | MSIOF1_SCK_D_MARK, | |
| 2435 | }; | |
| 2436 | static const unsigned int msiof1_sync_d_pins[] = { | |
| 2437 | /* SYNC */ | |
| 2438 | RCAR_GP_PIN(5, 15), | |
| 2439 | }; | |
| 2440 | static const unsigned int msiof1_sync_d_mux[] = { | |
| 2441 | MSIOF1_SYNC_D_MARK, | |
| 2442 | }; | |
| 2443 | static const unsigned int msiof1_ss1_d_pins[] = { | |
| 2444 | /* SS1 */ | |
| 2445 | RCAR_GP_PIN(5, 16), | |
| 2446 | }; | |
| 2447 | static const unsigned int msiof1_ss1_d_mux[] = { | |
| 2448 | MSIOF1_SS1_D_MARK, | |
| 2449 | }; | |
| 2450 | static const unsigned int msiof1_ss2_d_pins[] = { | |
| 2451 | /* SS2 */ | |
| 2452 | RCAR_GP_PIN(5, 21), | |
| 2453 | }; | |
| 2454 | static const unsigned int msiof1_ss2_d_mux[] = { | |
| 2455 | MSIOF1_SS2_D_MARK, | |
| 2456 | }; | |
| 2457 | static const unsigned int msiof1_txd_d_pins[] = { | |
| 2458 | /* TXD */ | |
| 2459 | RCAR_GP_PIN(5, 14), | |
| 2460 | }; | |
| 2461 | static const unsigned int msiof1_txd_d_mux[] = { | |
| 2462 | MSIOF1_TXD_D_MARK, | |
| 2463 | }; | |
| 2464 | static const unsigned int msiof1_rxd_d_pins[] = { | |
| 2465 | /* RXD */ | |
| 2466 | RCAR_GP_PIN(5, 13), | |
| 2467 | }; | |
| 2468 | static const unsigned int msiof1_rxd_d_mux[] = { | |
| 2469 | MSIOF1_RXD_D_MARK, | |
| 2470 | }; | |
| 2471 | static const unsigned int msiof1_clk_e_pins[] = { | |
| 2472 | /* SCK */ | |
| 2473 | RCAR_GP_PIN(3, 0), | |
| 2474 | }; | |
| 2475 | static const unsigned int msiof1_clk_e_mux[] = { | |
| 2476 | MSIOF1_SCK_E_MARK, | |
| 2477 | }; | |
| 2478 | static const unsigned int msiof1_sync_e_pins[] = { | |
| 2479 | /* SYNC */ | |
| 2480 | RCAR_GP_PIN(3, 1), | |
| 2481 | }; | |
| 2482 | static const unsigned int msiof1_sync_e_mux[] = { | |
| 2483 | MSIOF1_SYNC_E_MARK, | |
| 2484 | }; | |
| 2485 | static const unsigned int msiof1_ss1_e_pins[] = { | |
| 2486 | /* SS1 */ | |
| 2487 | RCAR_GP_PIN(3, 4), | |
| 2488 | }; | |
| 2489 | static const unsigned int msiof1_ss1_e_mux[] = { | |
| 2490 | MSIOF1_SS1_E_MARK, | |
| 2491 | }; | |
| 2492 | static const unsigned int msiof1_ss2_e_pins[] = { | |
| 2493 | /* SS2 */ | |
| 2494 | RCAR_GP_PIN(3, 5), | |
| 2495 | }; | |
| 2496 | static const unsigned int msiof1_ss2_e_mux[] = { | |
| 2497 | MSIOF1_SS2_E_MARK, | |
| 2498 | }; | |
| 2499 | static const unsigned int msiof1_txd_e_pins[] = { | |
| 2500 | /* TXD */ | |
| 2501 | RCAR_GP_PIN(3, 3), | |
| 2502 | }; | |
| 2503 | static const unsigned int msiof1_txd_e_mux[] = { | |
| 2504 | MSIOF1_TXD_E_MARK, | |
| 2505 | }; | |
| 2506 | static const unsigned int msiof1_rxd_e_pins[] = { | |
| 2507 | /* RXD */ | |
| 2508 | RCAR_GP_PIN(3, 2), | |
| 2509 | }; | |
| 2510 | static const unsigned int msiof1_rxd_e_mux[] = { | |
| 2511 | MSIOF1_RXD_E_MARK, | |
| 2512 | }; | |
| 2513 | static const unsigned int msiof1_clk_f_pins[] = { | |
| 2514 | /* SCK */ | |
| 2515 | RCAR_GP_PIN(5, 23), | |
| 2516 | }; | |
| 2517 | static const unsigned int msiof1_clk_f_mux[] = { | |
| 2518 | MSIOF1_SCK_F_MARK, | |
| 2519 | }; | |
| 2520 | static const unsigned int msiof1_sync_f_pins[] = { | |
| 2521 | /* SYNC */ | |
| 2522 | RCAR_GP_PIN(5, 24), | |
| 2523 | }; | |
| 2524 | static const unsigned int msiof1_sync_f_mux[] = { | |
| 2525 | MSIOF1_SYNC_F_MARK, | |
| 2526 | }; | |
| 2527 | static const unsigned int msiof1_ss1_f_pins[] = { | |
| 2528 | /* SS1 */ | |
| 2529 | RCAR_GP_PIN(6, 1), | |
| 2530 | }; | |
| 2531 | static const unsigned int msiof1_ss1_f_mux[] = { | |
| 2532 | MSIOF1_SS1_F_MARK, | |
| 2533 | }; | |
| 2534 | static const unsigned int msiof1_ss2_f_pins[] = { | |
| 2535 | /* SS2 */ | |
| 2536 | RCAR_GP_PIN(6, 2), | |
| 2537 | }; | |
| 2538 | static const unsigned int msiof1_ss2_f_mux[] = { | |
| 2539 | MSIOF1_SS2_F_MARK, | |
| 2540 | }; | |
| 2541 | static const unsigned int msiof1_txd_f_pins[] = { | |
| 2542 | /* TXD */ | |
| 2543 | RCAR_GP_PIN(6, 0), | |
| 2544 | }; | |
| 2545 | static const unsigned int msiof1_txd_f_mux[] = { | |
| 2546 | MSIOF1_TXD_F_MARK, | |
| 2547 | }; | |
| 2548 | static const unsigned int msiof1_rxd_f_pins[] = { | |
| 2549 | /* RXD */ | |
| 2550 | RCAR_GP_PIN(5, 25), | |
| 2551 | }; | |
| 2552 | static const unsigned int msiof1_rxd_f_mux[] = { | |
| 2553 | MSIOF1_RXD_F_MARK, | |
| 2554 | }; | |
| 2555 | static const unsigned int msiof1_clk_g_pins[] = { | |
| 2556 | /* SCK */ | |
| 2557 | RCAR_GP_PIN(3, 6), | |
| 2558 | }; | |
| 2559 | static const unsigned int msiof1_clk_g_mux[] = { | |
| 2560 | MSIOF1_SCK_G_MARK, | |
| 2561 | }; | |
| 2562 | static const unsigned int msiof1_sync_g_pins[] = { | |
| 2563 | /* SYNC */ | |
| 2564 | RCAR_GP_PIN(3, 7), | |
| 2565 | }; | |
| 2566 | static const unsigned int msiof1_sync_g_mux[] = { | |
| 2567 | MSIOF1_SYNC_G_MARK, | |
| 2568 | }; | |
| 2569 | static const unsigned int msiof1_ss1_g_pins[] = { | |
| 2570 | /* SS1 */ | |
| 2571 | RCAR_GP_PIN(3, 10), | |
| 2572 | }; | |
| 2573 | static const unsigned int msiof1_ss1_g_mux[] = { | |
| 2574 | MSIOF1_SS1_G_MARK, | |
| 2575 | }; | |
| 2576 | static const unsigned int msiof1_ss2_g_pins[] = { | |
| 2577 | /* SS2 */ | |
| 2578 | RCAR_GP_PIN(3, 11), | |
| 2579 | }; | |
| 2580 | static const unsigned int msiof1_ss2_g_mux[] = { | |
| 2581 | MSIOF1_SS2_G_MARK, | |
| 2582 | }; | |
| 2583 | static const unsigned int msiof1_txd_g_pins[] = { | |
| 2584 | /* TXD */ | |
| 2585 | RCAR_GP_PIN(3, 9), | |
| 2586 | }; | |
| 2587 | static const unsigned int msiof1_txd_g_mux[] = { | |
| 2588 | MSIOF1_TXD_G_MARK, | |
| 2589 | }; | |
| 2590 | static const unsigned int msiof1_rxd_g_pins[] = { | |
| 2591 | /* RXD */ | |
| 2592 | RCAR_GP_PIN(3, 8), | |
| 2593 | }; | |
| 2594 | static const unsigned int msiof1_rxd_g_mux[] = { | |
| 2595 | MSIOF1_RXD_G_MARK, | |
| 2596 | }; | |
| 2597 | /* - MSIOF2 ----------------------------------------------------------------- */ | |
| 2598 | static const unsigned int msiof2_clk_a_pins[] = { | |
| 2599 | /* SCK */ | |
| 2600 | RCAR_GP_PIN(1, 9), | |
| 2601 | }; | |
| 2602 | static const unsigned int msiof2_clk_a_mux[] = { | |
| 2603 | MSIOF2_SCK_A_MARK, | |
| 2604 | }; | |
| 2605 | static const unsigned int msiof2_sync_a_pins[] = { | |
| 2606 | /* SYNC */ | |
| 2607 | RCAR_GP_PIN(1, 8), | |
| 2608 | }; | |
| 2609 | static const unsigned int msiof2_sync_a_mux[] = { | |
| 2610 | MSIOF2_SYNC_A_MARK, | |
| 2611 | }; | |
| 2612 | static const unsigned int msiof2_ss1_a_pins[] = { | |
| 2613 | /* SS1 */ | |
| 2614 | RCAR_GP_PIN(1, 6), | |
| 2615 | }; | |
| 2616 | static const unsigned int msiof2_ss1_a_mux[] = { | |
| 2617 | MSIOF2_SS1_A_MARK, | |
| 2618 | }; | |
| 2619 | static const unsigned int msiof2_ss2_a_pins[] = { | |
| 2620 | /* SS2 */ | |
| 2621 | RCAR_GP_PIN(1, 7), | |
| 2622 | }; | |
| 2623 | static const unsigned int msiof2_ss2_a_mux[] = { | |
| 2624 | MSIOF2_SS2_A_MARK, | |
| 2625 | }; | |
| 2626 | static const unsigned int msiof2_txd_a_pins[] = { | |
| 2627 | /* TXD */ | |
| 2628 | RCAR_GP_PIN(1, 11), | |
| 2629 | }; | |
| 2630 | static const unsigned int msiof2_txd_a_mux[] = { | |
| 2631 | MSIOF2_TXD_A_MARK, | |
| 2632 | }; | |
| 2633 | static const unsigned int msiof2_rxd_a_pins[] = { | |
| 2634 | /* RXD */ | |
| 2635 | RCAR_GP_PIN(1, 10), | |
| 2636 | }; | |
| 2637 | static const unsigned int msiof2_rxd_a_mux[] = { | |
| 2638 | MSIOF2_RXD_A_MARK, | |
| 2639 | }; | |
| 2640 | static const unsigned int msiof2_clk_b_pins[] = { | |
| 2641 | /* SCK */ | |
| 2642 | RCAR_GP_PIN(0, 4), | |
| 2643 | }; | |
| 2644 | static const unsigned int msiof2_clk_b_mux[] = { | |
| 2645 | MSIOF2_SCK_B_MARK, | |
| 2646 | }; | |
| 2647 | static const unsigned int msiof2_sync_b_pins[] = { | |
| 2648 | /* SYNC */ | |
| 2649 | RCAR_GP_PIN(0, 5), | |
| 2650 | }; | |
| 2651 | static const unsigned int msiof2_sync_b_mux[] = { | |
| 2652 | MSIOF2_SYNC_B_MARK, | |
| 2653 | }; | |
| 2654 | static const unsigned int msiof2_ss1_b_pins[] = { | |
| 2655 | /* SS1 */ | |
| 2656 | RCAR_GP_PIN(0, 0), | |
| 2657 | }; | |
| 2658 | static const unsigned int msiof2_ss1_b_mux[] = { | |
| 2659 | MSIOF2_SS1_B_MARK, | |
| 2660 | }; | |
| 2661 | static const unsigned int msiof2_ss2_b_pins[] = { | |
| 2662 | /* SS2 */ | |
| 2663 | RCAR_GP_PIN(0, 1), | |
| 2664 | }; | |
| 2665 | static const unsigned int msiof2_ss2_b_mux[] = { | |
| 2666 | MSIOF2_SS2_B_MARK, | |
| 2667 | }; | |
| 2668 | static const unsigned int msiof2_txd_b_pins[] = { | |
| 2669 | /* TXD */ | |
| 2670 | RCAR_GP_PIN(0, 7), | |
| 2671 | }; | |
| 2672 | static const unsigned int msiof2_txd_b_mux[] = { | |
| 2673 | MSIOF2_TXD_B_MARK, | |
| 2674 | }; | |
| 2675 | static const unsigned int msiof2_rxd_b_pins[] = { | |
| 2676 | /* RXD */ | |
| 2677 | RCAR_GP_PIN(0, 6), | |
| 2678 | }; | |
| 2679 | static const unsigned int msiof2_rxd_b_mux[] = { | |
| 2680 | MSIOF2_RXD_B_MARK, | |
| 2681 | }; | |
| 2682 | static const unsigned int msiof2_clk_c_pins[] = { | |
| 2683 | /* SCK */ | |
| 2684 | RCAR_GP_PIN(2, 12), | |
| 2685 | }; | |
| 2686 | static const unsigned int msiof2_clk_c_mux[] = { | |
| 2687 | MSIOF2_SCK_C_MARK, | |
| 2688 | }; | |
| 2689 | static const unsigned int msiof2_sync_c_pins[] = { | |
| 2690 | /* SYNC */ | |
| 2691 | RCAR_GP_PIN(2, 11), | |
| 2692 | }; | |
| 2693 | static const unsigned int msiof2_sync_c_mux[] = { | |
| 2694 | MSIOF2_SYNC_C_MARK, | |
| 2695 | }; | |
| 2696 | static const unsigned int msiof2_ss1_c_pins[] = { | |
| 2697 | /* SS1 */ | |
| 2698 | RCAR_GP_PIN(2, 10), | |
| 2699 | }; | |
| 2700 | static const unsigned int msiof2_ss1_c_mux[] = { | |
| 2701 | MSIOF2_SS1_C_MARK, | |
| 2702 | }; | |
| 2703 | static const unsigned int msiof2_ss2_c_pins[] = { | |
| 2704 | /* SS2 */ | |
| 2705 | RCAR_GP_PIN(2, 9), | |
| 2706 | }; | |
| 2707 | static const unsigned int msiof2_ss2_c_mux[] = { | |
| 2708 | MSIOF2_SS2_C_MARK, | |
| 2709 | }; | |
| 2710 | static const unsigned int msiof2_txd_c_pins[] = { | |
| 2711 | /* TXD */ | |
| 2712 | RCAR_GP_PIN(2, 14), | |
| 2713 | }; | |
| 2714 | static const unsigned int msiof2_txd_c_mux[] = { | |
| 2715 | MSIOF2_TXD_C_MARK, | |
| 2716 | }; | |
| 2717 | static const unsigned int msiof2_rxd_c_pins[] = { | |
| 2718 | /* RXD */ | |
| 2719 | RCAR_GP_PIN(2, 13), | |
| 2720 | }; | |
| 2721 | static const unsigned int msiof2_rxd_c_mux[] = { | |
| 2722 | MSIOF2_RXD_C_MARK, | |
| 2723 | }; | |
| 2724 | static const unsigned int msiof2_clk_d_pins[] = { | |
| 2725 | /* SCK */ | |
| 2726 | RCAR_GP_PIN(0, 8), | |
| 2727 | }; | |
| 2728 | static const unsigned int msiof2_clk_d_mux[] = { | |
| 2729 | MSIOF2_SCK_D_MARK, | |
| 2730 | }; | |
| 2731 | static const unsigned int msiof2_sync_d_pins[] = { | |
| 2732 | /* SYNC */ | |
| 2733 | RCAR_GP_PIN(0, 9), | |
| 2734 | }; | |
| 2735 | static const unsigned int msiof2_sync_d_mux[] = { | |
| 2736 | MSIOF2_SYNC_D_MARK, | |
| 2737 | }; | |
| 2738 | static const unsigned int msiof2_ss1_d_pins[] = { | |
| 2739 | /* SS1 */ | |
| 2740 | RCAR_GP_PIN(0, 12), | |
| 2741 | }; | |
| 2742 | static const unsigned int msiof2_ss1_d_mux[] = { | |
| 2743 | MSIOF2_SS1_D_MARK, | |
| 2744 | }; | |
| 2745 | static const unsigned int msiof2_ss2_d_pins[] = { | |
| 2746 | /* SS2 */ | |
| 2747 | RCAR_GP_PIN(0, 13), | |
| 2748 | }; | |
| 2749 | static const unsigned int msiof2_ss2_d_mux[] = { | |
| 2750 | MSIOF2_SS2_D_MARK, | |
| 2751 | }; | |
| 2752 | static const unsigned int msiof2_txd_d_pins[] = { | |
| 2753 | /* TXD */ | |
| 2754 | RCAR_GP_PIN(0, 11), | |
| 2755 | }; | |
| 2756 | static const unsigned int msiof2_txd_d_mux[] = { | |
| 2757 | MSIOF2_TXD_D_MARK, | |
| 2758 | }; | |
| 2759 | static const unsigned int msiof2_rxd_d_pins[] = { | |
| 2760 | /* RXD */ | |
| 2761 | RCAR_GP_PIN(0, 10), | |
| 2762 | }; | |
| 2763 | static const unsigned int msiof2_rxd_d_mux[] = { | |
| 2764 | MSIOF2_RXD_D_MARK, | |
| 2765 | }; | |
| 2766 | /* - MSIOF3 ----------------------------------------------------------------- */ | |
| 2767 | static const unsigned int msiof3_clk_a_pins[] = { | |
| 2768 | /* SCK */ | |
| 2769 | RCAR_GP_PIN(0, 0), | |
| 2770 | }; | |
| 2771 | static const unsigned int msiof3_clk_a_mux[] = { | |
| 2772 | MSIOF3_SCK_A_MARK, | |
| 2773 | }; | |
| 2774 | static const unsigned int msiof3_sync_a_pins[] = { | |
| 2775 | /* SYNC */ | |
| 2776 | RCAR_GP_PIN(0, 1), | |
| 2777 | }; | |
| 2778 | static const unsigned int msiof3_sync_a_mux[] = { | |
| 2779 | MSIOF3_SYNC_A_MARK, | |
| 2780 | }; | |
| 2781 | static const unsigned int msiof3_ss1_a_pins[] = { | |
| 2782 | /* SS1 */ | |
| 2783 | RCAR_GP_PIN(0, 14), | |
| 2784 | }; | |
| 2785 | static const unsigned int msiof3_ss1_a_mux[] = { | |
| 2786 | MSIOF3_SS1_A_MARK, | |
| 2787 | }; | |
| 2788 | static const unsigned int msiof3_ss2_a_pins[] = { | |
| 2789 | /* SS2 */ | |
| 2790 | RCAR_GP_PIN(0, 15), | |
| 2791 | }; | |
| 2792 | static const unsigned int msiof3_ss2_a_mux[] = { | |
| 2793 | MSIOF3_SS2_A_MARK, | |
| 2794 | }; | |
| 2795 | static const unsigned int msiof3_txd_a_pins[] = { | |
| 2796 | /* TXD */ | |
| 2797 | RCAR_GP_PIN(0, 3), | |
| 2798 | }; | |
| 2799 | static const unsigned int msiof3_txd_a_mux[] = { | |
| 2800 | MSIOF3_TXD_A_MARK, | |
| 2801 | }; | |
| 2802 | static const unsigned int msiof3_rxd_a_pins[] = { | |
| 2803 | /* RXD */ | |
| 2804 | RCAR_GP_PIN(0, 2), | |
| 2805 | }; | |
| 2806 | static const unsigned int msiof3_rxd_a_mux[] = { | |
| 2807 | MSIOF3_RXD_A_MARK, | |
| 2808 | }; | |
| 2809 | static const unsigned int msiof3_clk_b_pins[] = { | |
| 2810 | /* SCK */ | |
| 2811 | RCAR_GP_PIN(1, 2), | |
| 2812 | }; | |
| 2813 | static const unsigned int msiof3_clk_b_mux[] = { | |
| 2814 | MSIOF3_SCK_B_MARK, | |
| 2815 | }; | |
| 2816 | static const unsigned int msiof3_sync_b_pins[] = { | |
| 2817 | /* SYNC */ | |
| 2818 | RCAR_GP_PIN(1, 0), | |
| 2819 | }; | |
| 2820 | static const unsigned int msiof3_sync_b_mux[] = { | |
| 2821 | MSIOF3_SYNC_B_MARK, | |
| 2822 | }; | |
| 2823 | static const unsigned int msiof3_ss1_b_pins[] = { | |
| 2824 | /* SS1 */ | |
| 2825 | RCAR_GP_PIN(1, 4), | |
| 2826 | }; | |
| 2827 | static const unsigned int msiof3_ss1_b_mux[] = { | |
| 2828 | MSIOF3_SS1_B_MARK, | |
| 2829 | }; | |
| 2830 | static const unsigned int msiof3_ss2_b_pins[] = { | |
| 2831 | /* SS2 */ | |
| 2832 | RCAR_GP_PIN(1, 5), | |
| 2833 | }; | |
| 2834 | static const unsigned int msiof3_ss2_b_mux[] = { | |
| 2835 | MSIOF3_SS2_B_MARK, | |
| 2836 | }; | |
| 2837 | static const unsigned int msiof3_txd_b_pins[] = { | |
| 2838 | /* TXD */ | |
| 2839 | RCAR_GP_PIN(1, 1), | |
| 2840 | }; | |
| 2841 | static const unsigned int msiof3_txd_b_mux[] = { | |
| 2842 | MSIOF3_TXD_B_MARK, | |
| 2843 | }; | |
| 2844 | static const unsigned int msiof3_rxd_b_pins[] = { | |
| 2845 | /* RXD */ | |
| 2846 | RCAR_GP_PIN(1, 3), | |
| 2847 | }; | |
| 2848 | static const unsigned int msiof3_rxd_b_mux[] = { | |
| 2849 | MSIOF3_RXD_B_MARK, | |
| 2850 | }; | |
| 2851 | static const unsigned int msiof3_clk_c_pins[] = { | |
| 2852 | /* SCK */ | |
| 2853 | RCAR_GP_PIN(1, 12), | |
| 2854 | }; | |
| 2855 | static const unsigned int msiof3_clk_c_mux[] = { | |
| 2856 | MSIOF3_SCK_C_MARK, | |
| 2857 | }; | |
| 2858 | static const unsigned int msiof3_sync_c_pins[] = { | |
| 2859 | /* SYNC */ | |
| 2860 | RCAR_GP_PIN(1, 13), | |
| 2861 | }; | |
| 2862 | static const unsigned int msiof3_sync_c_mux[] = { | |
| 2863 | MSIOF3_SYNC_C_MARK, | |
| 2864 | }; | |
| 2865 | static const unsigned int msiof3_txd_c_pins[] = { | |
| 2866 | /* TXD */ | |
| 2867 | RCAR_GP_PIN(1, 15), | |
| 2868 | }; | |
| 2869 | static const unsigned int msiof3_txd_c_mux[] = { | |
| 2870 | MSIOF3_TXD_C_MARK, | |
| 2871 | }; | |
| 2872 | static const unsigned int msiof3_rxd_c_pins[] = { | |
| 2873 | /* RXD */ | |
| 2874 | RCAR_GP_PIN(1, 14), | |
| 2875 | }; | |
| 2876 | static const unsigned int msiof3_rxd_c_mux[] = { | |
| 2877 | MSIOF3_RXD_C_MARK, | |
| 2878 | }; | |
| 2879 | static const unsigned int msiof3_clk_d_pins[] = { | |
| 2880 | /* SCK */ | |
| 2881 | RCAR_GP_PIN(1, 22), | |
| 2882 | }; | |
| 2883 | static const unsigned int msiof3_clk_d_mux[] = { | |
| 2884 | MSIOF3_SCK_D_MARK, | |
| 2885 | }; | |
| 2886 | static const unsigned int msiof3_sync_d_pins[] = { | |
| 2887 | /* SYNC */ | |
| 2888 | RCAR_GP_PIN(1, 23), | |
| 2889 | }; | |
| 2890 | static const unsigned int msiof3_sync_d_mux[] = { | |
| 2891 | MSIOF3_SYNC_D_MARK, | |
| 2892 | }; | |
| 2893 | static const unsigned int msiof3_ss1_d_pins[] = { | |
| 2894 | /* SS1 */ | |
| 2895 | RCAR_GP_PIN(1, 26), | |
| 2896 | }; | |
| 2897 | static const unsigned int msiof3_ss1_d_mux[] = { | |
| 2898 | MSIOF3_SS1_D_MARK, | |
| 2899 | }; | |
| 2900 | static const unsigned int msiof3_txd_d_pins[] = { | |
| 2901 | /* TXD */ | |
| 2902 | RCAR_GP_PIN(1, 25), | |
| 2903 | }; | |
| 2904 | static const unsigned int msiof3_txd_d_mux[] = { | |
| 2905 | MSIOF3_TXD_D_MARK, | |
| 2906 | }; | |
| 2907 | static const unsigned int msiof3_rxd_d_pins[] = { | |
| 2908 | /* RXD */ | |
| 2909 | RCAR_GP_PIN(1, 24), | |
| 2910 | }; | |
| 2911 | static const unsigned int msiof3_rxd_d_mux[] = { | |
| 2912 | MSIOF3_RXD_D_MARK, | |
| 2913 | }; | |
| 2914 | ||
| 2915 | static const unsigned int msiof3_clk_e_pins[] = { | |
| 2916 | /* SCK */ | |
| 2917 | RCAR_GP_PIN(2, 3), | |
| 2918 | }; | |
| 2919 | static const unsigned int msiof3_clk_e_mux[] = { | |
| 2920 | MSIOF3_SCK_E_MARK, | |
| 2921 | }; | |
| 2922 | static const unsigned int msiof3_sync_e_pins[] = { | |
| 2923 | /* SYNC */ | |
| 2924 | RCAR_GP_PIN(2, 2), | |
| 2925 | }; | |
| 2926 | static const unsigned int msiof3_sync_e_mux[] = { | |
| 2927 | MSIOF3_SYNC_E_MARK, | |
| 2928 | }; | |
| 2929 | static const unsigned int msiof3_ss1_e_pins[] = { | |
| 2930 | /* SS1 */ | |
| 2931 | RCAR_GP_PIN(2, 1), | |
| 2932 | }; | |
| 2933 | static const unsigned int msiof3_ss1_e_mux[] = { | |
| 2934 | MSIOF3_SS1_E_MARK, | |
| 2935 | }; | |
| 2936 | static const unsigned int msiof3_ss2_e_pins[] = { | |
| 2937 | /* SS1 */ | |
| 2938 | RCAR_GP_PIN(2, 0), | |
| 2939 | }; | |
| 2940 | static const unsigned int msiof3_ss2_e_mux[] = { | |
| 2941 | MSIOF3_SS1_E_MARK, | |
| 2942 | }; | |
| 2943 | static const unsigned int msiof3_txd_e_pins[] = { | |
| 2944 | /* TXD */ | |
| 2945 | RCAR_GP_PIN(2, 5), | |
| 2946 | }; | |
| 2947 | static const unsigned int msiof3_txd_e_mux[] = { | |
| 2948 | MSIOF3_TXD_E_MARK, | |
| 2949 | }; | |
| 2950 | static const unsigned int msiof3_rxd_e_pins[] = { | |
| 2951 | /* RXD */ | |
| 2952 | RCAR_GP_PIN(2, 4), | |
| 2953 | }; | |
| 2954 | static const unsigned int msiof3_rxd_e_mux[] = { | |
| 2955 | MSIOF3_RXD_E_MARK, | |
| 2956 | }; | |
| 2957 | ||
| 332cb226 TK |
2958 | /* - PWM0 --------------------------------------------------------------------*/ |
| 2959 | static const unsigned int pwm0_pins[] = { | |
| 2960 | /* PWM */ | |
| 2961 | RCAR_GP_PIN(2, 6), | |
| 2962 | }; | |
| 2963 | static const unsigned int pwm0_mux[] = { | |
| 2964 | PWM0_MARK, | |
| 2965 | }; | |
| 2966 | /* - PWM1 --------------------------------------------------------------------*/ | |
| 2967 | static const unsigned int pwm1_a_pins[] = { | |
| 2968 | /* PWM */ | |
| 2969 | RCAR_GP_PIN(2, 7), | |
| 2970 | }; | |
| 2971 | static const unsigned int pwm1_a_mux[] = { | |
| 2972 | PWM1_A_MARK, | |
| 2973 | }; | |
| 2974 | static const unsigned int pwm1_b_pins[] = { | |
| 2975 | /* PWM */ | |
| 2976 | RCAR_GP_PIN(1, 8), | |
| 2977 | }; | |
| 2978 | static const unsigned int pwm1_b_mux[] = { | |
| 2979 | PWM1_B_MARK, | |
| 2980 | }; | |
| 2981 | /* - PWM2 --------------------------------------------------------------------*/ | |
| 2982 | static const unsigned int pwm2_a_pins[] = { | |
| 2983 | /* PWM */ | |
| 2984 | RCAR_GP_PIN(2, 8), | |
| 2985 | }; | |
| 2986 | static const unsigned int pwm2_a_mux[] = { | |
| 2987 | PWM2_A_MARK, | |
| 2988 | }; | |
| 2989 | static const unsigned int pwm2_b_pins[] = { | |
| 2990 | /* PWM */ | |
| 2991 | RCAR_GP_PIN(1, 11), | |
| 2992 | }; | |
| 2993 | static const unsigned int pwm2_b_mux[] = { | |
| 2994 | PWM2_B_MARK, | |
| 2995 | }; | |
| 2996 | /* - PWM3 --------------------------------------------------------------------*/ | |
| 2997 | static const unsigned int pwm3_a_pins[] = { | |
| 2998 | /* PWM */ | |
| 2999 | RCAR_GP_PIN(1, 0), | |
| 3000 | }; | |
| 3001 | static const unsigned int pwm3_a_mux[] = { | |
| 3002 | PWM3_A_MARK, | |
| 3003 | }; | |
| 3004 | static const unsigned int pwm3_b_pins[] = { | |
| 3005 | /* PWM */ | |
| 3006 | RCAR_GP_PIN(2, 2), | |
| 3007 | }; | |
| 3008 | static const unsigned int pwm3_b_mux[] = { | |
| 3009 | PWM3_B_MARK, | |
| 3010 | }; | |
| 3011 | /* - PWM4 --------------------------------------------------------------------*/ | |
| 3012 | static const unsigned int pwm4_a_pins[] = { | |
| 3013 | /* PWM */ | |
| 3014 | RCAR_GP_PIN(1, 1), | |
| 3015 | }; | |
| 3016 | static const unsigned int pwm4_a_mux[] = { | |
| 3017 | PWM4_A_MARK, | |
| 3018 | }; | |
| 3019 | static const unsigned int pwm4_b_pins[] = { | |
| 3020 | /* PWM */ | |
| 3021 | RCAR_GP_PIN(2, 3), | |
| 3022 | }; | |
| 3023 | static const unsigned int pwm4_b_mux[] = { | |
| 3024 | PWM4_B_MARK, | |
| 3025 | }; | |
| 3026 | /* - PWM5 --------------------------------------------------------------------*/ | |
| 3027 | static const unsigned int pwm5_a_pins[] = { | |
| 3028 | /* PWM */ | |
| 3029 | RCAR_GP_PIN(1, 2), | |
| 3030 | }; | |
| 3031 | static const unsigned int pwm5_a_mux[] = { | |
| 3032 | PWM5_A_MARK, | |
| 3033 | }; | |
| 3034 | static const unsigned int pwm5_b_pins[] = { | |
| 3035 | /* PWM */ | |
| 3036 | RCAR_GP_PIN(2, 4), | |
| 3037 | }; | |
| 3038 | static const unsigned int pwm5_b_mux[] = { | |
| 3039 | PWM5_B_MARK, | |
| 3040 | }; | |
| 3041 | /* - PWM6 --------------------------------------------------------------------*/ | |
| 3042 | static const unsigned int pwm6_a_pins[] = { | |
| 3043 | /* PWM */ | |
| 3044 | RCAR_GP_PIN(1, 3), | |
| 3045 | }; | |
| 3046 | static const unsigned int pwm6_a_mux[] = { | |
| 3047 | PWM6_A_MARK, | |
| 3048 | }; | |
| 3049 | static const unsigned int pwm6_b_pins[] = { | |
| 3050 | /* PWM */ | |
| 3051 | RCAR_GP_PIN(2, 5), | |
| 3052 | }; | |
| 3053 | static const unsigned int pwm6_b_mux[] = { | |
| 3054 | PWM6_B_MARK, | |
| 3055 | }; | |
| 3056 | ||
| fc43d8b2 TK |
3057 | /* - SCIF0 ------------------------------------------------------------------ */ |
| 3058 | static const unsigned int scif0_data_pins[] = { | |
| 3059 | /* RX, TX */ | |
| 3060 | RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), | |
| 3061 | }; | |
| 3062 | static const unsigned int scif0_data_mux[] = { | |
| 3063 | RX0_MARK, TX0_MARK, | |
| 3064 | }; | |
| 3065 | static const unsigned int scif0_clk_pins[] = { | |
| 3066 | /* SCK */ | |
| 3067 | RCAR_GP_PIN(5, 0), | |
| 3068 | }; | |
| 3069 | static const unsigned int scif0_clk_mux[] = { | |
| 3070 | SCK0_MARK, | |
| 3071 | }; | |
| 3072 | static const unsigned int scif0_ctrl_pins[] = { | |
| 3073 | /* RTS, CTS */ | |
| 3074 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), | |
| 3075 | }; | |
| 3076 | static const unsigned int scif0_ctrl_mux[] = { | |
| 3077 | RTS0_N_TANS_MARK, CTS0_N_MARK, | |
| 3078 | }; | |
| 3079 | /* - SCIF1 ------------------------------------------------------------------ */ | |
| 3080 | static const unsigned int scif1_data_a_pins[] = { | |
| 3081 | /* RX, TX */ | |
| 3082 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
| 3083 | }; | |
| 3084 | static const unsigned int scif1_data_a_mux[] = { | |
| 3085 | RX1_A_MARK, TX1_A_MARK, | |
| 3086 | }; | |
| 3087 | static const unsigned int scif1_clk_pins[] = { | |
| 3088 | /* SCK */ | |
| 3089 | RCAR_GP_PIN(6, 21), | |
| 3090 | }; | |
| 3091 | static const unsigned int scif1_clk_mux[] = { | |
| 3092 | SCK1_MARK, | |
| 3093 | }; | |
| 3094 | static const unsigned int scif1_ctrl_pins[] = { | |
| 3095 | /* RTS, CTS */ | |
| 3096 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), | |
| 3097 | }; | |
| 3098 | static const unsigned int scif1_ctrl_mux[] = { | |
| 3099 | RTS1_N_TANS_MARK, CTS1_N_MARK, | |
| 3100 | }; | |
| 3101 | ||
| 3102 | static const unsigned int scif1_data_b_pins[] = { | |
| 3103 | /* RX, TX */ | |
| 3104 | RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), | |
| 3105 | }; | |
| 3106 | static const unsigned int scif1_data_b_mux[] = { | |
| 3107 | RX1_B_MARK, TX1_B_MARK, | |
| 3108 | }; | |
| 3109 | /* - SCIF2 ------------------------------------------------------------------ */ | |
| 3110 | static const unsigned int scif2_data_a_pins[] = { | |
| 3111 | /* RX, TX */ | |
| 3112 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), | |
| 3113 | }; | |
| 3114 | static const unsigned int scif2_data_a_mux[] = { | |
| 3115 | RX2_A_MARK, TX2_A_MARK, | |
| 3116 | }; | |
| 3117 | static const unsigned int scif2_clk_pins[] = { | |
| 3118 | /* SCK */ | |
| 3119 | RCAR_GP_PIN(5, 9), | |
| 3120 | }; | |
| 3121 | static const unsigned int scif2_clk_mux[] = { | |
| 3122 | SCK2_MARK, | |
| 3123 | }; | |
| 3124 | static const unsigned int scif2_data_b_pins[] = { | |
| 3125 | /* RX, TX */ | |
| 3126 | RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), | |
| 3127 | }; | |
| 3128 | static const unsigned int scif2_data_b_mux[] = { | |
| 3129 | RX2_B_MARK, TX2_B_MARK, | |
| 3130 | }; | |
| 3131 | /* - SCIF3 ------------------------------------------------------------------ */ | |
| 3132 | static const unsigned int scif3_data_a_pins[] = { | |
| 3133 | /* RX, TX */ | |
| 3134 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), | |
| 3135 | }; | |
| 3136 | static const unsigned int scif3_data_a_mux[] = { | |
| 3137 | RX3_A_MARK, TX3_A_MARK, | |
| 3138 | }; | |
| 3139 | static const unsigned int scif3_clk_pins[] = { | |
| 3140 | /* SCK */ | |
| 3141 | RCAR_GP_PIN(1, 22), | |
| 3142 | }; | |
| 3143 | static const unsigned int scif3_clk_mux[] = { | |
| 3144 | SCK3_MARK, | |
| 3145 | }; | |
| 3146 | static const unsigned int scif3_ctrl_pins[] = { | |
| 3147 | /* RTS, CTS */ | |
| 3148 | RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), | |
| 3149 | }; | |
| 3150 | static const unsigned int scif3_ctrl_mux[] = { | |
| 3151 | RTS3_N_TANS_MARK, CTS3_N_MARK, | |
| 3152 | }; | |
| 3153 | static const unsigned int scif3_data_b_pins[] = { | |
| 3154 | /* RX, TX */ | |
| 3155 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), | |
| 3156 | }; | |
| 3157 | static const unsigned int scif3_data_b_mux[] = { | |
| 3158 | RX3_B_MARK, TX3_B_MARK, | |
| 3159 | }; | |
| 3160 | /* - SCIF4 ------------------------------------------------------------------ */ | |
| 3161 | static const unsigned int scif4_data_a_pins[] = { | |
| 3162 | /* RX, TX */ | |
| 3163 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
| 3164 | }; | |
| 3165 | static const unsigned int scif4_data_a_mux[] = { | |
| 3166 | RX4_A_MARK, TX4_A_MARK, | |
| 3167 | }; | |
| 3168 | static const unsigned int scif4_clk_a_pins[] = { | |
| 3169 | /* SCK */ | |
| 3170 | RCAR_GP_PIN(2, 10), | |
| 3171 | }; | |
| 3172 | static const unsigned int scif4_clk_a_mux[] = { | |
| 3173 | SCK4_A_MARK, | |
| 3174 | }; | |
| 3175 | static const unsigned int scif4_ctrl_a_pins[] = { | |
| 3176 | /* RTS, CTS */ | |
| 3177 | RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), | |
| 3178 | }; | |
| 3179 | static const unsigned int scif4_ctrl_a_mux[] = { | |
| 3180 | RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, | |
| 3181 | }; | |
| 3182 | static const unsigned int scif4_data_b_pins[] = { | |
| 3183 | /* RX, TX */ | |
| 3184 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
| 3185 | }; | |
| 3186 | static const unsigned int scif4_data_b_mux[] = { | |
| 3187 | RX4_B_MARK, TX4_B_MARK, | |
| 3188 | }; | |
| 3189 | static const unsigned int scif4_clk_b_pins[] = { | |
| 3190 | /* SCK */ | |
| 3191 | RCAR_GP_PIN(1, 5), | |
| 3192 | }; | |
| 3193 | static const unsigned int scif4_clk_b_mux[] = { | |
| 3194 | SCK4_B_MARK, | |
| 3195 | }; | |
| 3196 | static const unsigned int scif4_ctrl_b_pins[] = { | |
| 3197 | /* RTS, CTS */ | |
| 3198 | RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), | |
| 3199 | }; | |
| 3200 | static const unsigned int scif4_ctrl_b_mux[] = { | |
| 3201 | RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, | |
| 3202 | }; | |
| 3203 | static const unsigned int scif4_data_c_pins[] = { | |
| 3204 | /* RX, TX */ | |
| 3205 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | |
| 3206 | }; | |
| 3207 | static const unsigned int scif4_data_c_mux[] = { | |
| 3208 | RX4_C_MARK, TX4_C_MARK, | |
| 3209 | }; | |
| 3210 | static const unsigned int scif4_clk_c_pins[] = { | |
| 3211 | /* SCK */ | |
| 3212 | RCAR_GP_PIN(0, 8), | |
| 3213 | }; | |
| 3214 | static const unsigned int scif4_clk_c_mux[] = { | |
| 3215 | SCK4_C_MARK, | |
| 3216 | }; | |
| 3217 | static const unsigned int scif4_ctrl_c_pins[] = { | |
| 3218 | /* RTS, CTS */ | |
| 3219 | RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), | |
| 3220 | }; | |
| 3221 | static const unsigned int scif4_ctrl_c_mux[] = { | |
| 3222 | RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, | |
| 3223 | }; | |
| 3224 | /* - SCIF5 ------------------------------------------------------------------ */ | |
| 3225 | static const unsigned int scif5_data_a_pins[] = { | |
| 3226 | /* RX, TX */ | |
| 3227 | RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), | |
| 3228 | }; | |
| 3229 | static const unsigned int scif5_data_a_mux[] = { | |
| 3230 | RX5_A_MARK, TX5_A_MARK, | |
| 3231 | }; | |
| 3232 | static const unsigned int scif5_clk_a_pins[] = { | |
| 3233 | /* SCK */ | |
| 3234 | RCAR_GP_PIN(6, 21), | |
| 3235 | }; | |
| 3236 | static const unsigned int scif5_clk_a_mux[] = { | |
| 3237 | SCK5_A_MARK, | |
| 3238 | }; | |
| 3239 | ||
| 3240 | static const unsigned int scif5_data_b_pins[] = { | |
| 3241 | /* RX, TX */ | |
| 3242 | RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), | |
| 3243 | }; | |
| 3244 | static const unsigned int scif5_data_b_mux[] = { | |
| 3245 | RX5_B_MARK, TX5_B_MARK, | |
| 3246 | }; | |
| 3247 | static const unsigned int scif5_clk_b_pins[] = { | |
| 3248 | /* SCK */ | |
| 3249 | RCAR_GP_PIN(5, 0), | |
| 3250 | }; | |
| 3251 | static const unsigned int scif5_clk_b_mux[] = { | |
| 3252 | SCK5_B_MARK, | |
| 3253 | }; | |
| 3254 | ||
| 3255 | /* - SCIF Clock ------------------------------------------------------------- */ | |
| 3256 | static const unsigned int scif_clk_a_pins[] = { | |
| 3257 | /* SCIF_CLK */ | |
| 3258 | RCAR_GP_PIN(6, 23), | |
| 3259 | }; | |
| 3260 | static const unsigned int scif_clk_a_mux[] = { | |
| 3261 | SCIF_CLK_A_MARK, | |
| 3262 | }; | |
| 3263 | static const unsigned int scif_clk_b_pins[] = { | |
| 3264 | /* SCIF_CLK */ | |
| 3265 | RCAR_GP_PIN(5, 9), | |
| 3266 | }; | |
| 3267 | static const unsigned int scif_clk_b_mux[] = { | |
| 3268 | SCIF_CLK_B_MARK, | |
| 3269 | }; | |
| 3270 | ||
| 374cf699 TK |
3271 | /* - SDHI0 ------------------------------------------------------------------ */ |
| 3272 | static const unsigned int sdhi0_data1_pins[] = { | |
| 3273 | /* D0 */ | |
| 3274 | RCAR_GP_PIN(3, 2), | |
| 3275 | }; | |
| 3276 | static const unsigned int sdhi0_data1_mux[] = { | |
| 3277 | SD0_DAT0_MARK, | |
| 3278 | }; | |
| 3279 | static const unsigned int sdhi0_data4_pins[] = { | |
| 3280 | /* D[0:3] */ | |
| 3281 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), | |
| 3282 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), | |
| 3283 | }; | |
| 3284 | static const unsigned int sdhi0_data4_mux[] = { | |
| 3285 | SD0_DAT0_MARK, SD0_DAT1_MARK, | |
| 3286 | SD0_DAT2_MARK, SD0_DAT3_MARK, | |
| 3287 | }; | |
| 3288 | static const unsigned int sdhi0_ctrl_pins[] = { | |
| 3289 | /* CLK, CMD */ | |
| 3290 | RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), | |
| 3291 | }; | |
| 3292 | static const unsigned int sdhi0_ctrl_mux[] = { | |
| 3293 | SD0_CLK_MARK, SD0_CMD_MARK, | |
| 3294 | }; | |
| 3295 | static const unsigned int sdhi0_cd_pins[] = { | |
| 3296 | /* CD */ | |
| 3297 | RCAR_GP_PIN(3, 12), | |
| 3298 | }; | |
| 3299 | static const unsigned int sdhi0_cd_mux[] = { | |
| 3300 | SD0_CD_MARK, | |
| 3301 | }; | |
| 3302 | static const unsigned int sdhi0_wp_pins[] = { | |
| 3303 | /* WP */ | |
| 3304 | RCAR_GP_PIN(3, 13), | |
| 3305 | }; | |
| 3306 | static const unsigned int sdhi0_wp_mux[] = { | |
| 3307 | SD0_WP_MARK, | |
| 3308 | }; | |
| 3309 | /* - SDHI1 ------------------------------------------------------------------ */ | |
| 3310 | static const unsigned int sdhi1_data1_pins[] = { | |
| 3311 | /* D0 */ | |
| 3312 | RCAR_GP_PIN(3, 8), | |
| 3313 | }; | |
| 3314 | static const unsigned int sdhi1_data1_mux[] = { | |
| 3315 | SD1_DAT0_MARK, | |
| 3316 | }; | |
| 3317 | static const unsigned int sdhi1_data4_pins[] = { | |
| 3318 | /* D[0:3] */ | |
| 3319 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), | |
| 3320 | RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), | |
| 3321 | }; | |
| 3322 | static const unsigned int sdhi1_data4_mux[] = { | |
| 3323 | SD1_DAT0_MARK, SD1_DAT1_MARK, | |
| 3324 | SD1_DAT2_MARK, SD1_DAT3_MARK, | |
| 3325 | }; | |
| 3326 | static const unsigned int sdhi1_ctrl_pins[] = { | |
| 3327 | /* CLK, CMD */ | |
| 3328 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | |
| 3329 | }; | |
| 3330 | static const unsigned int sdhi1_ctrl_mux[] = { | |
| 3331 | SD1_CLK_MARK, SD1_CMD_MARK, | |
| 3332 | }; | |
| 3333 | static const unsigned int sdhi1_cd_pins[] = { | |
| 3334 | /* CD */ | |
| 3335 | RCAR_GP_PIN(3, 14), | |
| 3336 | }; | |
| 3337 | static const unsigned int sdhi1_cd_mux[] = { | |
| 3338 | SD1_CD_MARK, | |
| 3339 | }; | |
| 3340 | static const unsigned int sdhi1_wp_pins[] = { | |
| 3341 | /* WP */ | |
| 3342 | RCAR_GP_PIN(3, 15), | |
| 3343 | }; | |
| 3344 | static const unsigned int sdhi1_wp_mux[] = { | |
| 3345 | SD1_WP_MARK, | |
| 3346 | }; | |
| 3347 | /* - SDHI2 ------------------------------------------------------------------ */ | |
| 3348 | static const unsigned int sdhi2_data1_pins[] = { | |
| 3349 | /* D0 */ | |
| 3350 | RCAR_GP_PIN(4, 2), | |
| 3351 | }; | |
| 3352 | static const unsigned int sdhi2_data1_mux[] = { | |
| 3353 | SD2_DAT0_MARK, | |
| 3354 | }; | |
| 3355 | static const unsigned int sdhi2_data4_pins[] = { | |
| 3356 | /* D[0:3] */ | |
| 3357 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), | |
| 3358 | RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), | |
| 3359 | }; | |
| 3360 | static const unsigned int sdhi2_data4_mux[] = { | |
| 3361 | SD2_DAT0_MARK, SD2_DAT1_MARK, | |
| 3362 | SD2_DAT2_MARK, SD2_DAT3_MARK, | |
| 3363 | }; | |
| 3364 | static const unsigned int sdhi2_data8_pins[] = { | |
| 3365 | /* D[0:7] */ | |
| 3366 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), | |
| 3367 | RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), | |
| 3368 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), | |
| 3369 | RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), | |
| 3370 | }; | |
| 3371 | static const unsigned int sdhi2_data8_mux[] = { | |
| 3372 | SD2_DAT0_MARK, SD2_DAT1_MARK, | |
| 3373 | SD2_DAT2_MARK, SD2_DAT3_MARK, | |
| 3374 | SD2_DAT4_MARK, SD2_DAT5_MARK, | |
| 3375 | SD2_DAT6_MARK, SD2_DAT7_MARK, | |
| 3376 | }; | |
| 3377 | static const unsigned int sdhi2_ctrl_pins[] = { | |
| 3378 | /* CLK, CMD */ | |
| 3379 | RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), | |
| 3380 | }; | |
| 3381 | static const unsigned int sdhi2_ctrl_mux[] = { | |
| 3382 | SD2_CLK_MARK, SD2_CMD_MARK, | |
| 3383 | }; | |
| 3384 | static const unsigned int sdhi2_cd_a_pins[] = { | |
| 3385 | /* CD */ | |
| 3386 | RCAR_GP_PIN(4, 13), | |
| 3387 | }; | |
| 3388 | static const unsigned int sdhi2_cd_a_mux[] = { | |
| 3389 | SD2_CD_A_MARK, | |
| 3390 | }; | |
| 3391 | static const unsigned int sdhi2_cd_b_pins[] = { | |
| 3392 | /* CD */ | |
| 3393 | RCAR_GP_PIN(5, 10), | |
| 3394 | }; | |
| 3395 | static const unsigned int sdhi2_cd_b_mux[] = { | |
| 3396 | SD2_CD_B_MARK, | |
| 3397 | }; | |
| 3398 | static const unsigned int sdhi2_wp_a_pins[] = { | |
| 3399 | /* WP */ | |
| 3400 | RCAR_GP_PIN(4, 14), | |
| 3401 | }; | |
| 3402 | static const unsigned int sdhi2_wp_a_mux[] = { | |
| 3403 | SD2_WP_A_MARK, | |
| 3404 | }; | |
| 3405 | static const unsigned int sdhi2_wp_b_pins[] = { | |
| 3406 | /* WP */ | |
| 3407 | RCAR_GP_PIN(5, 11), | |
| 3408 | }; | |
| 3409 | static const unsigned int sdhi2_wp_b_mux[] = { | |
| 3410 | SD2_WP_B_MARK, | |
| 3411 | }; | |
| 3412 | static const unsigned int sdhi2_ds_pins[] = { | |
| 3413 | /* DS */ | |
| 3414 | RCAR_GP_PIN(4, 6), | |
| 3415 | }; | |
| 3416 | static const unsigned int sdhi2_ds_mux[] = { | |
| 3417 | SD2_DS_MARK, | |
| 3418 | }; | |
| 3419 | /* - SDHI3 ------------------------------------------------------------------ */ | |
| 3420 | static const unsigned int sdhi3_data1_pins[] = { | |
| 3421 | /* D0 */ | |
| 3422 | RCAR_GP_PIN(4, 9), | |
| 3423 | }; | |
| 3424 | static const unsigned int sdhi3_data1_mux[] = { | |
| 3425 | SD3_DAT0_MARK, | |
| 3426 | }; | |
| 3427 | static const unsigned int sdhi3_data4_pins[] = { | |
| 3428 | /* D[0:3] */ | |
| 3429 | RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), | |
| 3430 | RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), | |
| 3431 | }; | |
| 3432 | static const unsigned int sdhi3_data4_mux[] = { | |
| 3433 | SD3_DAT0_MARK, SD3_DAT1_MARK, | |
| 3434 | SD3_DAT2_MARK, SD3_DAT3_MARK, | |
| 3435 | }; | |
| 3436 | static const unsigned int sdhi3_data8_pins[] = { | |
| 3437 | /* D[0:7] */ | |
| 3438 | RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), | |
| 3439 | RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), | |
| 3440 | RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), | |
| 3441 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), | |
| 3442 | }; | |
| 3443 | static const unsigned int sdhi3_data8_mux[] = { | |
| 3444 | SD3_DAT0_MARK, SD3_DAT1_MARK, | |
| 3445 | SD3_DAT2_MARK, SD3_DAT3_MARK, | |
| 3446 | SD3_DAT4_MARK, SD3_DAT5_MARK, | |
| 3447 | SD3_DAT6_MARK, SD3_DAT7_MARK, | |
| 3448 | }; | |
| 3449 | static const unsigned int sdhi3_ctrl_pins[] = { | |
| 3450 | /* CLK, CMD */ | |
| 3451 | RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), | |
| 3452 | }; | |
| 3453 | static const unsigned int sdhi3_ctrl_mux[] = { | |
| 3454 | SD3_CLK_MARK, SD3_CMD_MARK, | |
| 3455 | }; | |
| 3456 | static const unsigned int sdhi3_cd_pins[] = { | |
| 3457 | /* CD */ | |
| 3458 | RCAR_GP_PIN(4, 15), | |
| 3459 | }; | |
| 3460 | static const unsigned int sdhi3_cd_mux[] = { | |
| 3461 | SD3_CD_MARK, | |
| 3462 | }; | |
| 3463 | static const unsigned int sdhi3_wp_pins[] = { | |
| 3464 | /* WP */ | |
| 3465 | RCAR_GP_PIN(4, 16), | |
| 3466 | }; | |
| 3467 | static const unsigned int sdhi3_wp_mux[] = { | |
| 3468 | SD3_WP_MARK, | |
| 3469 | }; | |
| 3470 | static const unsigned int sdhi3_ds_pins[] = { | |
| 3471 | /* DS */ | |
| 3472 | RCAR_GP_PIN(4, 17), | |
| 3473 | }; | |
| 3474 | static const unsigned int sdhi3_ds_mux[] = { | |
| 3475 | SD3_DS_MARK, | |
| 3476 | }; | |
| 3477 | ||
| f9aece73 | 3478 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
| 9c99a63e TK |
3479 | SH_PFC_PIN_GROUP(avb_link), |
| 3480 | SH_PFC_PIN_GROUP(avb_magic), | |
| 3481 | SH_PFC_PIN_GROUP(avb_phy_int), | |
| 3482 | SH_PFC_PIN_GROUP(avb_mdc), | |
| 3483 | SH_PFC_PIN_GROUP(avb_avtp_pps), | |
| 3484 | SH_PFC_PIN_GROUP(avb_avtp_match_a), | |
| 3485 | SH_PFC_PIN_GROUP(avb_avtp_capture_a), | |
| 3486 | SH_PFC_PIN_GROUP(avb_avtp_match_b), | |
| 3487 | SH_PFC_PIN_GROUP(avb_avtp_capture_b), | |
| cf75341a CP |
3488 | SH_PFC_PIN_GROUP(can0_data_a), |
| 3489 | SH_PFC_PIN_GROUP(can0_data_b), | |
| 3490 | SH_PFC_PIN_GROUP(can1_data), | |
| 3491 | SH_PFC_PIN_GROUP(can_clk), | |
| 3dc93dce CP |
3492 | SH_PFC_PIN_GROUP(canfd0_data_a), |
| 3493 | SH_PFC_PIN_GROUP(canfd0_data_b), | |
| 3494 | SH_PFC_PIN_GROUP(canfd1_data), | |
| fb082831 RS |
3495 | SH_PFC_PIN_GROUP(drif0_ctrl_a), |
| 3496 | SH_PFC_PIN_GROUP(drif0_data0_a), | |
| 3497 | SH_PFC_PIN_GROUP(drif0_data1_a), | |
| 3498 | SH_PFC_PIN_GROUP(drif0_ctrl_b), | |
| 3499 | SH_PFC_PIN_GROUP(drif0_data0_b), | |
| 3500 | SH_PFC_PIN_GROUP(drif0_data1_b), | |
| 3501 | SH_PFC_PIN_GROUP(drif0_ctrl_c), | |
| 3502 | SH_PFC_PIN_GROUP(drif0_data0_c), | |
| 3503 | SH_PFC_PIN_GROUP(drif0_data1_c), | |
| 3504 | SH_PFC_PIN_GROUP(drif1_ctrl_a), | |
| 3505 | SH_PFC_PIN_GROUP(drif1_data0_a), | |
| 3506 | SH_PFC_PIN_GROUP(drif1_data1_a), | |
| 3507 | SH_PFC_PIN_GROUP(drif1_ctrl_b), | |
| 3508 | SH_PFC_PIN_GROUP(drif1_data0_b), | |
| 3509 | SH_PFC_PIN_GROUP(drif1_data1_b), | |
| 3510 | SH_PFC_PIN_GROUP(drif1_ctrl_c), | |
| 3511 | SH_PFC_PIN_GROUP(drif1_data0_c), | |
| 3512 | SH_PFC_PIN_GROUP(drif1_data1_c), | |
| 3513 | SH_PFC_PIN_GROUP(drif2_ctrl_a), | |
| 3514 | SH_PFC_PIN_GROUP(drif2_data0_a), | |
| 3515 | SH_PFC_PIN_GROUP(drif2_data1_a), | |
| 3516 | SH_PFC_PIN_GROUP(drif2_ctrl_b), | |
| 3517 | SH_PFC_PIN_GROUP(drif2_data0_b), | |
| 3518 | SH_PFC_PIN_GROUP(drif2_data1_b), | |
| 3519 | SH_PFC_PIN_GROUP(drif3_ctrl_a), | |
| 3520 | SH_PFC_PIN_GROUP(drif3_data0_a), | |
| 3521 | SH_PFC_PIN_GROUP(drif3_data1_a), | |
| 3522 | SH_PFC_PIN_GROUP(drif3_ctrl_b), | |
| 3523 | SH_PFC_PIN_GROUP(drif3_data0_b), | |
| 3524 | SH_PFC_PIN_GROUP(drif3_data1_b), | |
| cccc618a NS |
3525 | SH_PFC_PIN_GROUP(du_rgb666), |
| 3526 | SH_PFC_PIN_GROUP(du_rgb888), | |
| 3527 | SH_PFC_PIN_GROUP(du_clk_out_0), | |
| 3528 | SH_PFC_PIN_GROUP(du_clk_out_1), | |
| 3529 | SH_PFC_PIN_GROUP(du_sync), | |
| 3530 | SH_PFC_PIN_GROUP(du_oddf), | |
| 3531 | SH_PFC_PIN_GROUP(du_cde), | |
| 3532 | SH_PFC_PIN_GROUP(du_disp), | |
| 0e4e4999 UH |
3533 | SH_PFC_PIN_GROUP(hscif0_data), |
| 3534 | SH_PFC_PIN_GROUP(hscif0_clk), | |
| 3535 | SH_PFC_PIN_GROUP(hscif0_ctrl), | |
| 3536 | SH_PFC_PIN_GROUP(hscif1_data_a), | |
| 3537 | SH_PFC_PIN_GROUP(hscif1_clk_a), | |
| 3538 | SH_PFC_PIN_GROUP(hscif1_ctrl_a), | |
| 3539 | SH_PFC_PIN_GROUP(hscif1_data_b), | |
| 3540 | SH_PFC_PIN_GROUP(hscif1_clk_b), | |
| 3541 | SH_PFC_PIN_GROUP(hscif1_ctrl_b), | |
| 3542 | SH_PFC_PIN_GROUP(hscif2_data_a), | |
| 3543 | SH_PFC_PIN_GROUP(hscif2_clk_a), | |
| 3544 | SH_PFC_PIN_GROUP(hscif2_ctrl_a), | |
| 3545 | SH_PFC_PIN_GROUP(hscif2_data_b), | |
| 3546 | SH_PFC_PIN_GROUP(hscif2_clk_b), | |
| 3547 | SH_PFC_PIN_GROUP(hscif2_ctrl_b), | |
| 3548 | SH_PFC_PIN_GROUP(hscif2_data_c), | |
| 3549 | SH_PFC_PIN_GROUP(hscif2_clk_c), | |
| 3550 | SH_PFC_PIN_GROUP(hscif2_ctrl_c), | |
| 3551 | SH_PFC_PIN_GROUP(hscif3_data_a), | |
| 3552 | SH_PFC_PIN_GROUP(hscif3_clk), | |
| 3553 | SH_PFC_PIN_GROUP(hscif3_ctrl), | |
| 3554 | SH_PFC_PIN_GROUP(hscif3_data_b), | |
| 3555 | SH_PFC_PIN_GROUP(hscif3_data_c), | |
| 3556 | SH_PFC_PIN_GROUP(hscif3_data_d), | |
| 3557 | SH_PFC_PIN_GROUP(hscif4_data_a), | |
| 3558 | SH_PFC_PIN_GROUP(hscif4_clk), | |
| 3559 | SH_PFC_PIN_GROUP(hscif4_ctrl), | |
| 3560 | SH_PFC_PIN_GROUP(hscif4_data_b), | |
| 02609a23 UH |
3561 | SH_PFC_PIN_GROUP(i2c1_a), |
| 3562 | SH_PFC_PIN_GROUP(i2c1_b), | |
| 3563 | SH_PFC_PIN_GROUP(i2c2_a), | |
| 3564 | SH_PFC_PIN_GROUP(i2c2_b), | |
| 3565 | SH_PFC_PIN_GROUP(i2c6_a), | |
| 3566 | SH_PFC_PIN_GROUP(i2c6_b), | |
| 3567 | SH_PFC_PIN_GROUP(i2c6_c), | |
| 4753231c TK |
3568 | SH_PFC_PIN_GROUP(msiof0_clk), |
| 3569 | SH_PFC_PIN_GROUP(msiof0_sync), | |
| 3570 | SH_PFC_PIN_GROUP(msiof0_ss1), | |
| 3571 | SH_PFC_PIN_GROUP(msiof0_ss2), | |
| 3572 | SH_PFC_PIN_GROUP(msiof0_txd), | |
| 3573 | SH_PFC_PIN_GROUP(msiof0_rxd), | |
| 3574 | SH_PFC_PIN_GROUP(msiof1_clk_a), | |
| 3575 | SH_PFC_PIN_GROUP(msiof1_sync_a), | |
| 3576 | SH_PFC_PIN_GROUP(msiof1_ss1_a), | |
| 3577 | SH_PFC_PIN_GROUP(msiof1_ss2_a), | |
| 3578 | SH_PFC_PIN_GROUP(msiof1_txd_a), | |
| 3579 | SH_PFC_PIN_GROUP(msiof1_rxd_a), | |
| 3580 | SH_PFC_PIN_GROUP(msiof1_clk_b), | |
| 3581 | SH_PFC_PIN_GROUP(msiof1_sync_b), | |
| 3582 | SH_PFC_PIN_GROUP(msiof1_ss1_b), | |
| 3583 | SH_PFC_PIN_GROUP(msiof1_ss2_b), | |
| 3584 | SH_PFC_PIN_GROUP(msiof1_txd_b), | |
| 3585 | SH_PFC_PIN_GROUP(msiof1_rxd_b), | |
| 3586 | SH_PFC_PIN_GROUP(msiof1_clk_c), | |
| 3587 | SH_PFC_PIN_GROUP(msiof1_sync_c), | |
| 3588 | SH_PFC_PIN_GROUP(msiof1_ss1_c), | |
| 3589 | SH_PFC_PIN_GROUP(msiof1_ss2_c), | |
| 3590 | SH_PFC_PIN_GROUP(msiof1_txd_c), | |
| 3591 | SH_PFC_PIN_GROUP(msiof1_rxd_c), | |
| 3592 | SH_PFC_PIN_GROUP(msiof1_clk_d), | |
| 3593 | SH_PFC_PIN_GROUP(msiof1_sync_d), | |
| 3594 | SH_PFC_PIN_GROUP(msiof1_ss1_d), | |
| 3595 | SH_PFC_PIN_GROUP(msiof1_ss2_d), | |
| 3596 | SH_PFC_PIN_GROUP(msiof1_txd_d), | |
| 3597 | SH_PFC_PIN_GROUP(msiof1_rxd_d), | |
| 3598 | SH_PFC_PIN_GROUP(msiof1_clk_e), | |
| 3599 | SH_PFC_PIN_GROUP(msiof1_sync_e), | |
| 3600 | SH_PFC_PIN_GROUP(msiof1_ss1_e), | |
| 3601 | SH_PFC_PIN_GROUP(msiof1_ss2_e), | |
| 3602 | SH_PFC_PIN_GROUP(msiof1_txd_e), | |
| 3603 | SH_PFC_PIN_GROUP(msiof1_rxd_e), | |
| 3604 | SH_PFC_PIN_GROUP(msiof1_clk_f), | |
| 3605 | SH_PFC_PIN_GROUP(msiof1_sync_f), | |
| 3606 | SH_PFC_PIN_GROUP(msiof1_ss1_f), | |
| 3607 | SH_PFC_PIN_GROUP(msiof1_ss2_f), | |
| 3608 | SH_PFC_PIN_GROUP(msiof1_txd_f), | |
| 3609 | SH_PFC_PIN_GROUP(msiof1_rxd_f), | |
| 3610 | SH_PFC_PIN_GROUP(msiof1_clk_g), | |
| 3611 | SH_PFC_PIN_GROUP(msiof1_sync_g), | |
| 3612 | SH_PFC_PIN_GROUP(msiof1_ss1_g), | |
| 3613 | SH_PFC_PIN_GROUP(msiof1_ss2_g), | |
| 3614 | SH_PFC_PIN_GROUP(msiof1_txd_g), | |
| 3615 | SH_PFC_PIN_GROUP(msiof1_rxd_g), | |
| 3616 | SH_PFC_PIN_GROUP(msiof2_clk_a), | |
| 3617 | SH_PFC_PIN_GROUP(msiof2_sync_a), | |
| 3618 | SH_PFC_PIN_GROUP(msiof2_ss1_a), | |
| 3619 | SH_PFC_PIN_GROUP(msiof2_ss2_a), | |
| 3620 | SH_PFC_PIN_GROUP(msiof2_txd_a), | |
| 3621 | SH_PFC_PIN_GROUP(msiof2_rxd_a), | |
| 3622 | SH_PFC_PIN_GROUP(msiof2_clk_b), | |
| 3623 | SH_PFC_PIN_GROUP(msiof2_sync_b), | |
| 3624 | SH_PFC_PIN_GROUP(msiof2_ss1_b), | |
| 3625 | SH_PFC_PIN_GROUP(msiof2_ss2_b), | |
| 3626 | SH_PFC_PIN_GROUP(msiof2_txd_b), | |
| 3627 | SH_PFC_PIN_GROUP(msiof2_rxd_b), | |
| 3628 | SH_PFC_PIN_GROUP(msiof2_clk_c), | |
| 3629 | SH_PFC_PIN_GROUP(msiof2_sync_c), | |
| 3630 | SH_PFC_PIN_GROUP(msiof2_ss1_c), | |
| 3631 | SH_PFC_PIN_GROUP(msiof2_ss2_c), | |
| 3632 | SH_PFC_PIN_GROUP(msiof2_txd_c), | |
| 3633 | SH_PFC_PIN_GROUP(msiof2_rxd_c), | |
| 3634 | SH_PFC_PIN_GROUP(msiof2_clk_d), | |
| 3635 | SH_PFC_PIN_GROUP(msiof2_sync_d), | |
| 3636 | SH_PFC_PIN_GROUP(msiof2_ss1_d), | |
| 3637 | SH_PFC_PIN_GROUP(msiof2_ss2_d), | |
| 3638 | SH_PFC_PIN_GROUP(msiof2_txd_d), | |
| 3639 | SH_PFC_PIN_GROUP(msiof2_rxd_d), | |
| 3640 | SH_PFC_PIN_GROUP(msiof3_clk_a), | |
| 3641 | SH_PFC_PIN_GROUP(msiof3_sync_a), | |
| 3642 | SH_PFC_PIN_GROUP(msiof3_ss1_a), | |
| 3643 | SH_PFC_PIN_GROUP(msiof3_ss2_a), | |
| 3644 | SH_PFC_PIN_GROUP(msiof3_txd_a), | |
| 3645 | SH_PFC_PIN_GROUP(msiof3_rxd_a), | |
| 3646 | SH_PFC_PIN_GROUP(msiof3_clk_b), | |
| 3647 | SH_PFC_PIN_GROUP(msiof3_sync_b), | |
| 3648 | SH_PFC_PIN_GROUP(msiof3_ss1_b), | |
| 3649 | SH_PFC_PIN_GROUP(msiof3_ss2_b), | |
| 3650 | SH_PFC_PIN_GROUP(msiof3_txd_b), | |
| 3651 | SH_PFC_PIN_GROUP(msiof3_rxd_b), | |
| 3652 | SH_PFC_PIN_GROUP(msiof3_clk_c), | |
| 3653 | SH_PFC_PIN_GROUP(msiof3_sync_c), | |
| 3654 | SH_PFC_PIN_GROUP(msiof3_txd_c), | |
| 3655 | SH_PFC_PIN_GROUP(msiof3_rxd_c), | |
| 3656 | SH_PFC_PIN_GROUP(msiof3_clk_d), | |
| 3657 | SH_PFC_PIN_GROUP(msiof3_sync_d), | |
| 3658 | SH_PFC_PIN_GROUP(msiof3_ss1_d), | |
| 3659 | SH_PFC_PIN_GROUP(msiof3_txd_d), | |
| 3660 | SH_PFC_PIN_GROUP(msiof3_rxd_d), | |
| 3661 | SH_PFC_PIN_GROUP(msiof3_clk_e), | |
| 3662 | SH_PFC_PIN_GROUP(msiof3_sync_e), | |
| 3663 | SH_PFC_PIN_GROUP(msiof3_ss1_e), | |
| 3664 | SH_PFC_PIN_GROUP(msiof3_ss2_e), | |
| 3665 | SH_PFC_PIN_GROUP(msiof3_txd_e), | |
| 3666 | SH_PFC_PIN_GROUP(msiof3_rxd_e), | |
| 332cb226 TK |
3667 | SH_PFC_PIN_GROUP(pwm0), |
| 3668 | SH_PFC_PIN_GROUP(pwm1_a), | |
| 3669 | SH_PFC_PIN_GROUP(pwm1_b), | |
| 3670 | SH_PFC_PIN_GROUP(pwm2_a), | |
| 3671 | SH_PFC_PIN_GROUP(pwm2_b), | |
| 3672 | SH_PFC_PIN_GROUP(pwm3_a), | |
| 3673 | SH_PFC_PIN_GROUP(pwm3_b), | |
| 3674 | SH_PFC_PIN_GROUP(pwm4_a), | |
| 3675 | SH_PFC_PIN_GROUP(pwm4_b), | |
| 3676 | SH_PFC_PIN_GROUP(pwm5_a), | |
| 3677 | SH_PFC_PIN_GROUP(pwm5_b), | |
| 3678 | SH_PFC_PIN_GROUP(pwm6_a), | |
| 3679 | SH_PFC_PIN_GROUP(pwm6_b), | |
| fc43d8b2 TK |
3680 | SH_PFC_PIN_GROUP(scif0_data), |
| 3681 | SH_PFC_PIN_GROUP(scif0_clk), | |
| 3682 | SH_PFC_PIN_GROUP(scif0_ctrl), | |
| 3683 | SH_PFC_PIN_GROUP(scif1_data_a), | |
| 3684 | SH_PFC_PIN_GROUP(scif1_clk), | |
| 3685 | SH_PFC_PIN_GROUP(scif1_ctrl), | |
| 3686 | SH_PFC_PIN_GROUP(scif1_data_b), | |
| 3687 | SH_PFC_PIN_GROUP(scif2_data_a), | |
| 3688 | SH_PFC_PIN_GROUP(scif2_clk), | |
| 3689 | SH_PFC_PIN_GROUP(scif2_data_b), | |
| 3690 | SH_PFC_PIN_GROUP(scif3_data_a), | |
| 3691 | SH_PFC_PIN_GROUP(scif3_clk), | |
| 3692 | SH_PFC_PIN_GROUP(scif3_ctrl), | |
| 3693 | SH_PFC_PIN_GROUP(scif3_data_b), | |
| 3694 | SH_PFC_PIN_GROUP(scif4_data_a), | |
| 3695 | SH_PFC_PIN_GROUP(scif4_clk_a), | |
| 3696 | SH_PFC_PIN_GROUP(scif4_ctrl_a), | |
| 3697 | SH_PFC_PIN_GROUP(scif4_data_b), | |
| 3698 | SH_PFC_PIN_GROUP(scif4_clk_b), | |
| 3699 | SH_PFC_PIN_GROUP(scif4_ctrl_b), | |
| 3700 | SH_PFC_PIN_GROUP(scif4_data_c), | |
| 3701 | SH_PFC_PIN_GROUP(scif4_clk_c), | |
| 3702 | SH_PFC_PIN_GROUP(scif4_ctrl_c), | |
| 3703 | SH_PFC_PIN_GROUP(scif5_data_a), | |
| 3704 | SH_PFC_PIN_GROUP(scif5_clk_a), | |
| 3705 | SH_PFC_PIN_GROUP(scif5_data_b), | |
| 3706 | SH_PFC_PIN_GROUP(scif5_clk_b), | |
| 3707 | SH_PFC_PIN_GROUP(scif_clk_a), | |
| 3708 | SH_PFC_PIN_GROUP(scif_clk_b), | |
| 374cf699 TK |
3709 | SH_PFC_PIN_GROUP(sdhi0_data1), |
| 3710 | SH_PFC_PIN_GROUP(sdhi0_data4), | |
| 3711 | SH_PFC_PIN_GROUP(sdhi0_ctrl), | |
| 3712 | SH_PFC_PIN_GROUP(sdhi0_cd), | |
| 3713 | SH_PFC_PIN_GROUP(sdhi0_wp), | |
| 3714 | SH_PFC_PIN_GROUP(sdhi1_data1), | |
| 3715 | SH_PFC_PIN_GROUP(sdhi1_data4), | |
| 3716 | SH_PFC_PIN_GROUP(sdhi1_ctrl), | |
| 3717 | SH_PFC_PIN_GROUP(sdhi1_cd), | |
| 3718 | SH_PFC_PIN_GROUP(sdhi1_wp), | |
| 3719 | SH_PFC_PIN_GROUP(sdhi2_data1), | |
| 3720 | SH_PFC_PIN_GROUP(sdhi2_data4), | |
| 3721 | SH_PFC_PIN_GROUP(sdhi2_data8), | |
| 3722 | SH_PFC_PIN_GROUP(sdhi2_ctrl), | |
| 3723 | SH_PFC_PIN_GROUP(sdhi2_cd_a), | |
| 3724 | SH_PFC_PIN_GROUP(sdhi2_wp_a), | |
| 3725 | SH_PFC_PIN_GROUP(sdhi2_cd_b), | |
| 3726 | SH_PFC_PIN_GROUP(sdhi2_wp_b), | |
| 3727 | SH_PFC_PIN_GROUP(sdhi2_ds), | |
| 3728 | SH_PFC_PIN_GROUP(sdhi3_data1), | |
| 3729 | SH_PFC_PIN_GROUP(sdhi3_data4), | |
| 3730 | SH_PFC_PIN_GROUP(sdhi3_data8), | |
| 3731 | SH_PFC_PIN_GROUP(sdhi3_ctrl), | |
| 3732 | SH_PFC_PIN_GROUP(sdhi3_cd), | |
| 3733 | SH_PFC_PIN_GROUP(sdhi3_wp), | |
| 3734 | SH_PFC_PIN_GROUP(sdhi3_ds), | |
| fc43d8b2 TK |
3735 | }; |
| 3736 | ||
| 9c99a63e TK |
3737 | static const char * const avb_groups[] = { |
| 3738 | "avb_link", | |
| 3739 | "avb_magic", | |
| 3740 | "avb_phy_int", | |
| 3741 | "avb_mdc", | |
| 3742 | "avb_avtp_pps", | |
| 3743 | "avb_avtp_match_a", | |
| 3744 | "avb_avtp_capture_a", | |
| 3745 | "avb_avtp_match_b", | |
| 3746 | "avb_avtp_capture_b", | |
| 3747 | }; | |
| 3748 | ||
| cf75341a CP |
3749 | static const char * const can0_groups[] = { |
| 3750 | "can0_data_a", | |
| 3751 | "can0_data_b", | |
| 3752 | }; | |
| 3753 | ||
| 3754 | static const char * const can1_groups[] = { | |
| 3755 | "can1_data", | |
| 3756 | }; | |
| 3757 | ||
| 3758 | static const char * const can_clk_groups[] = { | |
| 3759 | "can_clk", | |
| 3760 | }; | |
| 3761 | ||
| 3dc93dce CP |
3762 | static const char * const canfd0_groups[] = { |
| 3763 | "canfd0_data_a", | |
| 3764 | "canfd0_data_b", | |
| 3765 | }; | |
| 3766 | ||
| 3767 | static const char * const canfd1_groups[] = { | |
| 3768 | "canfd1_data", | |
| 3769 | }; | |
| 3770 | ||
| fb082831 RS |
3771 | static const char * const drif0_groups[] = { |
| 3772 | "drif0_ctrl_a", | |
| 3773 | "drif0_data0_a", | |
| 3774 | "drif0_data1_a", | |
| 3775 | "drif0_ctrl_b", | |
| 3776 | "drif0_data0_b", | |
| 3777 | "drif0_data1_b", | |
| 3778 | "drif0_ctrl_c", | |
| 3779 | "drif0_data0_c", | |
| 3780 | "drif0_data1_c", | |
| 3781 | }; | |
| 3782 | ||
| 3783 | static const char * const drif1_groups[] = { | |
| 3784 | "drif1_ctrl_a", | |
| 3785 | "drif1_data0_a", | |
| 3786 | "drif1_data1_a", | |
| 3787 | "drif1_ctrl_b", | |
| 3788 | "drif1_data0_b", | |
| 3789 | "drif1_data1_b", | |
| 3790 | "drif1_ctrl_c", | |
| 3791 | "drif1_data0_c", | |
| 3792 | "drif1_data1_c", | |
| 3793 | }; | |
| 3794 | ||
| 3795 | static const char * const drif2_groups[] = { | |
| 3796 | "drif2_ctrl_a", | |
| 3797 | "drif2_data0_a", | |
| 3798 | "drif2_data1_a", | |
| 3799 | "drif2_ctrl_b", | |
| 3800 | "drif2_data0_b", | |
| 3801 | "drif2_data1_b", | |
| 3802 | }; | |
| 3803 | ||
| 3804 | static const char * const drif3_groups[] = { | |
| 3805 | "drif3_ctrl_a", | |
| 3806 | "drif3_data0_a", | |
| 3807 | "drif3_data1_a", | |
| 3808 | "drif3_ctrl_b", | |
| 3809 | "drif3_data0_b", | |
| 3810 | "drif3_data1_b", | |
| 3811 | }; | |
| 3812 | ||
| cccc618a NS |
3813 | static const char * const du_groups[] = { |
| 3814 | "du_rgb666", | |
| 3815 | "du_rgb888", | |
| 3816 | "du_clk_out_0", | |
| 3817 | "du_clk_out_1", | |
| 3818 | "du_sync", | |
| 3819 | "du_oddf", | |
| 3820 | "du_cde", | |
| 3821 | "du_disp", | |
| 3822 | }; | |
| 3823 | ||
| 0e4e4999 UH |
3824 | static const char * const hscif0_groups[] = { |
| 3825 | "hscif0_data", | |
| 3826 | "hscif0_clk", | |
| 3827 | "hscif0_ctrl", | |
| 3828 | }; | |
| 3829 | ||
| 3830 | static const char * const hscif1_groups[] = { | |
| 3831 | "hscif1_data_a", | |
| 3832 | "hscif1_clk_a", | |
| 3833 | "hscif1_ctrl_a", | |
| 3834 | "hscif1_data_b", | |
| 3835 | "hscif1_clk_b", | |
| 3836 | "hscif1_ctrl_b", | |
| 3837 | }; | |
| 3838 | ||
| 3839 | static const char * const hscif2_groups[] = { | |
| 3840 | "hscif2_data_a", | |
| 3841 | "hscif2_clk_a", | |
| 3842 | "hscif2_ctrl_a", | |
| 3843 | "hscif2_data_b", | |
| 3844 | "hscif2_clk_b", | |
| 3845 | "hscif2_ctrl_b", | |
| 3846 | "hscif2_data_c", | |
| 3847 | "hscif2_clk_c", | |
| 3848 | "hscif2_ctrl_c", | |
| 3849 | }; | |
| 3850 | ||
| 3851 | static const char * const hscif3_groups[] = { | |
| 3852 | "hscif3_data_a", | |
| 3853 | "hscif3_clk", | |
| 3854 | "hscif3_ctrl", | |
| 3855 | "hscif3_data_b", | |
| 3856 | "hscif3_data_c", | |
| 3857 | "hscif3_data_d", | |
| 3858 | }; | |
| 3859 | ||
| 3860 | static const char * const hscif4_groups[] = { | |
| 3861 | "hscif4_data_a", | |
| 3862 | "hscif4_clk", | |
| 3863 | "hscif4_ctrl", | |
| 3864 | "hscif4_data_b", | |
| 3865 | }; | |
| 3866 | ||
| 02609a23 UH |
3867 | static const char * const i2c1_groups[] = { |
| 3868 | "i2c1_a", | |
| 3869 | "i2c1_b", | |
| 3870 | }; | |
| 3871 | ||
| 3872 | static const char * const i2c2_groups[] = { | |
| 3873 | "i2c2_a", | |
| 3874 | "i2c2_b", | |
| 3875 | }; | |
| 3876 | ||
| 3877 | static const char * const i2c6_groups[] = { | |
| 3878 | "i2c6_a", | |
| 3879 | "i2c6_b", | |
| 3880 | "i2c6_c", | |
| 3881 | }; | |
| 3882 | ||
| 4753231c TK |
3883 | static const char * const msiof0_groups[] = { |
| 3884 | "msiof0_clk", | |
| 3885 | "msiof0_sync", | |
| 3886 | "msiof0_ss1", | |
| 3887 | "msiof0_ss2", | |
| 3888 | "msiof0_txd", | |
| 3889 | "msiof0_rxd", | |
| 3890 | }; | |
| 3891 | ||
| 3892 | static const char * const msiof1_groups[] = { | |
| 3893 | "msiof1_clk_a", | |
| 3894 | "msiof1_sync_a", | |
| 3895 | "msiof1_ss1_a", | |
| 3896 | "msiof1_ss2_a", | |
| 3897 | "msiof1_txd_a", | |
| 3898 | "msiof1_rxd_a", | |
| 3899 | "msiof1_clk_b", | |
| 3900 | "msiof1_sync_b", | |
| 3901 | "msiof1_ss1_b", | |
| 3902 | "msiof1_ss2_b", | |
| 3903 | "msiof1_txd_b", | |
| 3904 | "msiof1_rxd_b", | |
| 3905 | "msiof1_clk_c", | |
| 3906 | "msiof1_sync_c", | |
| 3907 | "msiof1_ss1_c", | |
| 3908 | "msiof1_ss2_c", | |
| 3909 | "msiof1_txd_c", | |
| 3910 | "msiof1_rxd_c", | |
| 3911 | "msiof1_clk_d", | |
| 3912 | "msiof1_sync_d", | |
| 3913 | "msiof1_ss1_d", | |
| 3914 | "msiof1_ss2_d", | |
| 3915 | "msiof1_txd_d", | |
| 3916 | "msiof1_rxd_d", | |
| 3917 | "msiof1_clk_e", | |
| 3918 | "msiof1_sync_e", | |
| 3919 | "msiof1_ss1_e", | |
| 3920 | "msiof1_ss2_e", | |
| 3921 | "msiof1_txd_e", | |
| 3922 | "msiof1_rxd_e", | |
| 3923 | "msiof1_clk_f", | |
| 3924 | "msiof1_sync_f", | |
| 3925 | "msiof1_ss1_f", | |
| 3926 | "msiof1_ss2_f", | |
| 3927 | "msiof1_txd_f", | |
| 3928 | "msiof1_rxd_f", | |
| 3929 | "msiof1_clk_g", | |
| 3930 | "msiof1_sync_g", | |
| 3931 | "msiof1_ss1_g", | |
| 3932 | "msiof1_ss2_g", | |
| 3933 | "msiof1_txd_g", | |
| 3934 | "msiof1_rxd_g", | |
| 3935 | }; | |
| 3936 | ||
| 3937 | static const char * const msiof2_groups[] = { | |
| 3938 | "msiof2_clk_a", | |
| 3939 | "msiof2_sync_a", | |
| 3940 | "msiof2_ss1_a", | |
| 3941 | "msiof2_ss2_a", | |
| 3942 | "msiof2_txd_a", | |
| 3943 | "msiof2_rxd_a", | |
| 3944 | "msiof2_clk_b", | |
| 3945 | "msiof2_sync_b", | |
| 3946 | "msiof2_ss1_b", | |
| 3947 | "msiof2_ss2_b", | |
| 3948 | "msiof2_txd_b", | |
| 3949 | "msiof2_rxd_b", | |
| 3950 | "msiof2_clk_c", | |
| 3951 | "msiof2_sync_c", | |
| 3952 | "msiof2_ss1_c", | |
| 3953 | "msiof2_ss2_c", | |
| 3954 | "msiof2_txd_c", | |
| 3955 | "msiof2_rxd_c", | |
| 3956 | "msiof2_clk_d", | |
| 3957 | "msiof2_sync_d", | |
| 3958 | "msiof2_ss1_d", | |
| 3959 | "msiof2_ss2_d", | |
| 3960 | "msiof2_txd_d", | |
| 3961 | "msiof2_rxd_d", | |
| 3962 | }; | |
| 3963 | ||
| 3964 | static const char * const msiof3_groups[] = { | |
| 3965 | "msiof3_clk_a", | |
| 3966 | "msiof3_sync_a", | |
| 3967 | "msiof3_ss1_a", | |
| 3968 | "msiof3_ss2_a", | |
| 3969 | "msiof3_txd_a", | |
| 3970 | "msiof3_rxd_a", | |
| 3971 | "msiof3_clk_b", | |
| 3972 | "msiof3_sync_b", | |
| 3973 | "msiof3_ss1_b", | |
| 3974 | "msiof3_ss2_b", | |
| 3975 | "msiof3_txd_b", | |
| 3976 | "msiof3_rxd_b", | |
| 3977 | "msiof3_clk_c", | |
| 3978 | "msiof3_sync_c", | |
| 3979 | "msiof3_txd_c", | |
| 3980 | "msiof3_rxd_c", | |
| 3981 | "msiof3_clk_d", | |
| 3982 | "msiof3_sync_d", | |
| 3983 | "msiof3_ss1_d", | |
| 3984 | "msiof3_txd_d", | |
| 3985 | "msiof3_rxd_d", | |
| 3986 | "msiof3_clk_e", | |
| 3987 | "msiof3_sync_e", | |
| 3988 | "msiof3_ss1_e", | |
| 3989 | "msiof3_ss2_e", | |
| 3990 | "msiof3_txd_e", | |
| 3991 | "msiof3_rxd_e", | |
| 3992 | }; | |
| 3993 | ||
| 332cb226 TK |
3994 | static const char * const pwm0_groups[] = { |
| 3995 | "pwm0", | |
| 3996 | }; | |
| 3997 | ||
| 3998 | static const char * const pwm1_groups[] = { | |
| 3999 | "pwm1_a", | |
| 4000 | "pwm1_b", | |
| 4001 | }; | |
| 4002 | ||
| 4003 | static const char * const pwm2_groups[] = { | |
| 4004 | "pwm2_a", | |
| 4005 | "pwm2_b", | |
| 4006 | }; | |
| 4007 | ||
| 4008 | static const char * const pwm3_groups[] = { | |
| 4009 | "pwm3_a", | |
| 4010 | "pwm3_b", | |
| 4011 | }; | |
| 4012 | ||
| 4013 | static const char * const pwm4_groups[] = { | |
| 4014 | "pwm4_a", | |
| 4015 | "pwm4_b", | |
| 4016 | }; | |
| 4017 | ||
| 4018 | static const char * const pwm5_groups[] = { | |
| 4019 | "pwm5_a", | |
| 4020 | "pwm5_b", | |
| 4021 | }; | |
| 4022 | ||
| 4023 | static const char * const pwm6_groups[] = { | |
| 4024 | "pwm6_a", | |
| 4025 | "pwm6_b", | |
| 4026 | }; | |
| 4027 | ||
| fc43d8b2 TK |
4028 | static const char * const scif0_groups[] = { |
| 4029 | "scif0_data", | |
| 4030 | "scif0_clk", | |
| 4031 | "scif0_ctrl", | |
| 4032 | }; | |
| 4033 | ||
| 4034 | static const char * const scif1_groups[] = { | |
| 4035 | "scif1_data_a", | |
| 4036 | "scif1_clk", | |
| 4037 | "scif1_ctrl", | |
| 4038 | "scif1_data_b", | |
| 4039 | }; | |
| 4040 | ||
| 4041 | static const char * const scif2_groups[] = { | |
| 4042 | "scif2_data_a", | |
| 4043 | "scif2_clk", | |
| 4044 | "scif2_data_b", | |
| 4045 | }; | |
| 4046 | ||
| 4047 | static const char * const scif3_groups[] = { | |
| 4048 | "scif3_data_a", | |
| 4049 | "scif3_clk", | |
| 4050 | "scif3_ctrl", | |
| 4051 | "scif3_data_b", | |
| 4052 | }; | |
| 4053 | ||
| 4054 | static const char * const scif4_groups[] = { | |
| 4055 | "scif4_data_a", | |
| 4056 | "scif4_clk_a", | |
| 4057 | "scif4_ctrl_a", | |
| 4058 | "scif4_data_b", | |
| 4059 | "scif4_clk_b", | |
| 4060 | "scif4_ctrl_b", | |
| 4061 | "scif4_data_c", | |
| 4062 | "scif4_clk_c", | |
| 4063 | "scif4_ctrl_c", | |
| 4064 | }; | |
| 4065 | ||
| 4066 | static const char * const scif5_groups[] = { | |
| 4067 | "scif5_data_a", | |
| 4068 | "scif5_clk_a", | |
| 4069 | "scif5_data_b", | |
| 4070 | "scif5_clk_b", | |
| 4071 | }; | |
| 4072 | ||
| 4073 | static const char * const scif_clk_groups[] = { | |
| 4074 | "scif_clk_a", | |
| 4075 | "scif_clk_b", | |
| f9aece73 TK |
4076 | }; |
| 4077 | ||
| 374cf699 TK |
4078 | static const char * const sdhi0_groups[] = { |
| 4079 | "sdhi0_data1", | |
| 4080 | "sdhi0_data4", | |
| 4081 | "sdhi0_ctrl", | |
| 4082 | "sdhi0_cd", | |
| 4083 | "sdhi0_wp", | |
| 4084 | }; | |
| 4085 | ||
| 4086 | static const char * const sdhi1_groups[] = { | |
| 4087 | "sdhi1_data1", | |
| 4088 | "sdhi1_data4", | |
| 4089 | "sdhi1_ctrl", | |
| 4090 | "sdhi1_cd", | |
| 4091 | "sdhi1_wp", | |
| 4092 | }; | |
| 4093 | ||
| 4094 | static const char * const sdhi2_groups[] = { | |
| 4095 | "sdhi2_data1", | |
| 4096 | "sdhi2_data4", | |
| 4097 | "sdhi2_data8", | |
| 4098 | "sdhi2_ctrl", | |
| 4099 | "sdhi2_cd_a", | |
| 4100 | "sdhi2_wp_a", | |
| 4101 | "sdhi2_cd_b", | |
| 4102 | "sdhi2_wp_b", | |
| 4103 | "sdhi2_ds", | |
| 4104 | }; | |
| 4105 | ||
| 4106 | static const char * const sdhi3_groups[] = { | |
| 4107 | "sdhi3_data1", | |
| 4108 | "sdhi3_data4", | |
| 4109 | "sdhi3_data8", | |
| 4110 | "sdhi3_ctrl", | |
| 4111 | "sdhi3_cd", | |
| 4112 | "sdhi3_wp", | |
| 4113 | "sdhi3_ds", | |
| 4114 | }; | |
| 4115 | ||
| f9aece73 | 4116 | static const struct sh_pfc_function pinmux_functions[] = { |
| 9c99a63e | 4117 | SH_PFC_FUNCTION(avb), |
| cf75341a CP |
4118 | SH_PFC_FUNCTION(can0), |
| 4119 | SH_PFC_FUNCTION(can1), | |
| 4120 | SH_PFC_FUNCTION(can_clk), | |
| 3dc93dce CP |
4121 | SH_PFC_FUNCTION(canfd0), |
| 4122 | SH_PFC_FUNCTION(canfd1), | |
| fb082831 RS |
4123 | SH_PFC_FUNCTION(drif0), |
| 4124 | SH_PFC_FUNCTION(drif1), | |
| 4125 | SH_PFC_FUNCTION(drif2), | |
| 4126 | SH_PFC_FUNCTION(drif3), | |
| cccc618a | 4127 | SH_PFC_FUNCTION(du), |
| 0e4e4999 UH |
4128 | SH_PFC_FUNCTION(hscif0), |
| 4129 | SH_PFC_FUNCTION(hscif1), | |
| 4130 | SH_PFC_FUNCTION(hscif2), | |
| 4131 | SH_PFC_FUNCTION(hscif3), | |
| 4132 | SH_PFC_FUNCTION(hscif4), | |
| 02609a23 UH |
4133 | SH_PFC_FUNCTION(i2c1), |
| 4134 | SH_PFC_FUNCTION(i2c2), | |
| 4135 | SH_PFC_FUNCTION(i2c6), | |
| 4753231c TK |
4136 | SH_PFC_FUNCTION(msiof0), |
| 4137 | SH_PFC_FUNCTION(msiof1), | |
| 4138 | SH_PFC_FUNCTION(msiof2), | |
| 4139 | SH_PFC_FUNCTION(msiof3), | |
| 332cb226 TK |
4140 | SH_PFC_FUNCTION(pwm0), |
| 4141 | SH_PFC_FUNCTION(pwm1), | |
| 4142 | SH_PFC_FUNCTION(pwm2), | |
| 4143 | SH_PFC_FUNCTION(pwm3), | |
| 4144 | SH_PFC_FUNCTION(pwm4), | |
| 4145 | SH_PFC_FUNCTION(pwm5), | |
| 4146 | SH_PFC_FUNCTION(pwm6), | |
| fc43d8b2 TK |
4147 | SH_PFC_FUNCTION(scif0), |
| 4148 | SH_PFC_FUNCTION(scif1), | |
| 4149 | SH_PFC_FUNCTION(scif2), | |
| 4150 | SH_PFC_FUNCTION(scif3), | |
| 4151 | SH_PFC_FUNCTION(scif4), | |
| 4152 | SH_PFC_FUNCTION(scif5), | |
| 4153 | SH_PFC_FUNCTION(scif_clk), | |
| 374cf699 TK |
4154 | SH_PFC_FUNCTION(sdhi0), |
| 4155 | SH_PFC_FUNCTION(sdhi1), | |
| 4156 | SH_PFC_FUNCTION(sdhi2), | |
| 4157 | SH_PFC_FUNCTION(sdhi3), | |
| f9aece73 TK |
4158 | }; |
| 4159 | ||
| 4160 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | |
| 4161 | #define F_(x, y) FN_##y | |
| 4162 | #define FM(x) FN_##x | |
| 4163 | { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { | |
| 4164 | 0, 0, | |
| 4165 | 0, 0, | |
| 4166 | 0, 0, | |
| 4167 | 0, 0, | |
| 4168 | 0, 0, | |
| 4169 | 0, 0, | |
| 4170 | 0, 0, | |
| 4171 | 0, 0, | |
| 4172 | 0, 0, | |
| 4173 | 0, 0, | |
| 4174 | 0, 0, | |
| 4175 | 0, 0, | |
| 4176 | 0, 0, | |
| 4177 | 0, 0, | |
| 4178 | 0, 0, | |
| 4179 | 0, 0, | |
| 4180 | GP_0_15_FN, GPSR0_15, | |
| 4181 | GP_0_14_FN, GPSR0_14, | |
| 4182 | GP_0_13_FN, GPSR0_13, | |
| 4183 | GP_0_12_FN, GPSR0_12, | |
| 4184 | GP_0_11_FN, GPSR0_11, | |
| 4185 | GP_0_10_FN, GPSR0_10, | |
| 4186 | GP_0_9_FN, GPSR0_9, | |
| 4187 | GP_0_8_FN, GPSR0_8, | |
| 4188 | GP_0_7_FN, GPSR0_7, | |
| 4189 | GP_0_6_FN, GPSR0_6, | |
| 4190 | GP_0_5_FN, GPSR0_5, | |
| 4191 | GP_0_4_FN, GPSR0_4, | |
| 4192 | GP_0_3_FN, GPSR0_3, | |
| 4193 | GP_0_2_FN, GPSR0_2, | |
| 4194 | GP_0_1_FN, GPSR0_1, | |
| 4195 | GP_0_0_FN, GPSR0_0, } | |
| 4196 | }, | |
| 4197 | { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { | |
| 4198 | 0, 0, | |
| 4199 | 0, 0, | |
| 4200 | 0, 0, | |
| 4201 | GP_1_28_FN, GPSR1_28, | |
| 4202 | GP_1_27_FN, GPSR1_27, | |
| 4203 | GP_1_26_FN, GPSR1_26, | |
| 4204 | GP_1_25_FN, GPSR1_25, | |
| 4205 | GP_1_24_FN, GPSR1_24, | |
| 4206 | GP_1_23_FN, GPSR1_23, | |
| 4207 | GP_1_22_FN, GPSR1_22, | |
| 4208 | GP_1_21_FN, GPSR1_21, | |
| 4209 | GP_1_20_FN, GPSR1_20, | |
| 4210 | GP_1_19_FN, GPSR1_19, | |
| 4211 | GP_1_18_FN, GPSR1_18, | |
| 4212 | GP_1_17_FN, GPSR1_17, | |
| 4213 | GP_1_16_FN, GPSR1_16, | |
| 4214 | GP_1_15_FN, GPSR1_15, | |
| 4215 | GP_1_14_FN, GPSR1_14, | |
| 4216 | GP_1_13_FN, GPSR1_13, | |
| 4217 | GP_1_12_FN, GPSR1_12, | |
| 4218 | GP_1_11_FN, GPSR1_11, | |
| 4219 | GP_1_10_FN, GPSR1_10, | |
| 4220 | GP_1_9_FN, GPSR1_9, | |
| 4221 | GP_1_8_FN, GPSR1_8, | |
| 4222 | GP_1_7_FN, GPSR1_7, | |
| 4223 | GP_1_6_FN, GPSR1_6, | |
| 4224 | GP_1_5_FN, GPSR1_5, | |
| 4225 | GP_1_4_FN, GPSR1_4, | |
| 4226 | GP_1_3_FN, GPSR1_3, | |
| 4227 | GP_1_2_FN, GPSR1_2, | |
| 4228 | GP_1_1_FN, GPSR1_1, | |
| 4229 | GP_1_0_FN, GPSR1_0, } | |
| 4230 | }, | |
| 4231 | { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { | |
| 4232 | 0, 0, | |
| 4233 | 0, 0, | |
| 4234 | 0, 0, | |
| 4235 | 0, 0, | |
| 4236 | 0, 0, | |
| 4237 | 0, 0, | |
| 4238 | 0, 0, | |
| 4239 | 0, 0, | |
| 4240 | 0, 0, | |
| 4241 | 0, 0, | |
| 4242 | 0, 0, | |
| 4243 | 0, 0, | |
| 4244 | 0, 0, | |
| 4245 | 0, 0, | |
| 4246 | 0, 0, | |
| 4247 | 0, 0, | |
| 4248 | 0, 0, | |
| 4249 | GP_2_14_FN, GPSR2_14, | |
| 4250 | GP_2_13_FN, GPSR2_13, | |
| 4251 | GP_2_12_FN, GPSR2_12, | |
| 4252 | GP_2_11_FN, GPSR2_11, | |
| 4253 | GP_2_10_FN, GPSR2_10, | |
| 4254 | GP_2_9_FN, GPSR2_9, | |
| 4255 | GP_2_8_FN, GPSR2_8, | |
| 4256 | GP_2_7_FN, GPSR2_7, | |
| 4257 | GP_2_6_FN, GPSR2_6, | |
| 4258 | GP_2_5_FN, GPSR2_5, | |
| 4259 | GP_2_4_FN, GPSR2_4, | |
| 4260 | GP_2_3_FN, GPSR2_3, | |
| 4261 | GP_2_2_FN, GPSR2_2, | |
| 4262 | GP_2_1_FN, GPSR2_1, | |
| 4263 | GP_2_0_FN, GPSR2_0, } | |
| 4264 | }, | |
| 4265 | { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { | |
| 4266 | 0, 0, | |
| 4267 | 0, 0, | |
| 4268 | 0, 0, | |
| 4269 | 0, 0, | |
| 4270 | 0, 0, | |
| 4271 | 0, 0, | |
| 4272 | 0, 0, | |
| 4273 | 0, 0, | |
| 4274 | 0, 0, | |
| 4275 | 0, 0, | |
| 4276 | 0, 0, | |
| 4277 | 0, 0, | |
| 4278 | 0, 0, | |
| 4279 | 0, 0, | |
| 4280 | 0, 0, | |
| 4281 | 0, 0, | |
| 4282 | GP_3_15_FN, GPSR3_15, | |
| 4283 | GP_3_14_FN, GPSR3_14, | |
| 4284 | GP_3_13_FN, GPSR3_13, | |
| 4285 | GP_3_12_FN, GPSR3_12, | |
| 4286 | GP_3_11_FN, GPSR3_11, | |
| 4287 | GP_3_10_FN, GPSR3_10, | |
| 4288 | GP_3_9_FN, GPSR3_9, | |
| 4289 | GP_3_8_FN, GPSR3_8, | |
| 4290 | GP_3_7_FN, GPSR3_7, | |
| 4291 | GP_3_6_FN, GPSR3_6, | |
| 4292 | GP_3_5_FN, GPSR3_5, | |
| 4293 | GP_3_4_FN, GPSR3_4, | |
| 4294 | GP_3_3_FN, GPSR3_3, | |
| 4295 | GP_3_2_FN, GPSR3_2, | |
| 4296 | GP_3_1_FN, GPSR3_1, | |
| 4297 | GP_3_0_FN, GPSR3_0, } | |
| 4298 | }, | |
| 4299 | { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { | |
| 4300 | 0, 0, | |
| 4301 | 0, 0, | |
| 4302 | 0, 0, | |
| 4303 | 0, 0, | |
| 4304 | 0, 0, | |
| 4305 | 0, 0, | |
| 4306 | 0, 0, | |
| 4307 | 0, 0, | |
| 4308 | 0, 0, | |
| 4309 | 0, 0, | |
| 4310 | 0, 0, | |
| 4311 | 0, 0, | |
| 4312 | 0, 0, | |
| 4313 | 0, 0, | |
| 4314 | GP_4_17_FN, GPSR4_17, | |
| 4315 | GP_4_16_FN, GPSR4_16, | |
| 4316 | GP_4_15_FN, GPSR4_15, | |
| 4317 | GP_4_14_FN, GPSR4_14, | |
| 4318 | GP_4_13_FN, GPSR4_13, | |
| 4319 | GP_4_12_FN, GPSR4_12, | |
| 4320 | GP_4_11_FN, GPSR4_11, | |
| 4321 | GP_4_10_FN, GPSR4_10, | |
| 4322 | GP_4_9_FN, GPSR4_9, | |
| 4323 | GP_4_8_FN, GPSR4_8, | |
| 4324 | GP_4_7_FN, GPSR4_7, | |
| 4325 | GP_4_6_FN, GPSR4_6, | |
| 4326 | GP_4_5_FN, GPSR4_5, | |
| 4327 | GP_4_4_FN, GPSR4_4, | |
| 4328 | GP_4_3_FN, GPSR4_3, | |
| 4329 | GP_4_2_FN, GPSR4_2, | |
| 4330 | GP_4_1_FN, GPSR4_1, | |
| 4331 | GP_4_0_FN, GPSR4_0, } | |
| 4332 | }, | |
| 4333 | { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { | |
| 4334 | 0, 0, | |
| 4335 | 0, 0, | |
| 4336 | 0, 0, | |
| 4337 | 0, 0, | |
| 4338 | 0, 0, | |
| 4339 | 0, 0, | |
| 4340 | GP_5_25_FN, GPSR5_25, | |
| 4341 | GP_5_24_FN, GPSR5_24, | |
| 4342 | GP_5_23_FN, GPSR5_23, | |
| 4343 | GP_5_22_FN, GPSR5_22, | |
| 4344 | GP_5_21_FN, GPSR5_21, | |
| 4345 | GP_5_20_FN, GPSR5_20, | |
| 4346 | GP_5_19_FN, GPSR5_19, | |
| 4347 | GP_5_18_FN, GPSR5_18, | |
| 4348 | GP_5_17_FN, GPSR5_17, | |
| 4349 | GP_5_16_FN, GPSR5_16, | |
| 4350 | GP_5_15_FN, GPSR5_15, | |
| 4351 | GP_5_14_FN, GPSR5_14, | |
| 4352 | GP_5_13_FN, GPSR5_13, | |
| 4353 | GP_5_12_FN, GPSR5_12, | |
| 4354 | GP_5_11_FN, GPSR5_11, | |
| 4355 | GP_5_10_FN, GPSR5_10, | |
| 4356 | GP_5_9_FN, GPSR5_9, | |
| 4357 | GP_5_8_FN, GPSR5_8, | |
| 4358 | GP_5_7_FN, GPSR5_7, | |
| 4359 | GP_5_6_FN, GPSR5_6, | |
| 4360 | GP_5_5_FN, GPSR5_5, | |
| 4361 | GP_5_4_FN, GPSR5_4, | |
| 4362 | GP_5_3_FN, GPSR5_3, | |
| 4363 | GP_5_2_FN, GPSR5_2, | |
| 4364 | GP_5_1_FN, GPSR5_1, | |
| 4365 | GP_5_0_FN, GPSR5_0, } | |
| 4366 | }, | |
| 4367 | { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { | |
| 4368 | GP_6_31_FN, GPSR6_31, | |
| 4369 | GP_6_30_FN, GPSR6_30, | |
| 4370 | GP_6_29_FN, GPSR6_29, | |
| 4371 | GP_6_28_FN, GPSR6_28, | |
| 4372 | GP_6_27_FN, GPSR6_27, | |
| 4373 | GP_6_26_FN, GPSR6_26, | |
| 4374 | GP_6_25_FN, GPSR6_25, | |
| 4375 | GP_6_24_FN, GPSR6_24, | |
| 4376 | GP_6_23_FN, GPSR6_23, | |
| 4377 | GP_6_22_FN, GPSR6_22, | |
| 4378 | GP_6_21_FN, GPSR6_21, | |
| 4379 | GP_6_20_FN, GPSR6_20, | |
| 4380 | GP_6_19_FN, GPSR6_19, | |
| 4381 | GP_6_18_FN, GPSR6_18, | |
| 4382 | GP_6_17_FN, GPSR6_17, | |
| 4383 | GP_6_16_FN, GPSR6_16, | |
| 4384 | GP_6_15_FN, GPSR6_15, | |
| 4385 | GP_6_14_FN, GPSR6_14, | |
| 4386 | GP_6_13_FN, GPSR6_13, | |
| 4387 | GP_6_12_FN, GPSR6_12, | |
| 4388 | GP_6_11_FN, GPSR6_11, | |
| 4389 | GP_6_10_FN, GPSR6_10, | |
| 4390 | GP_6_9_FN, GPSR6_9, | |
| 4391 | GP_6_8_FN, GPSR6_8, | |
| 4392 | GP_6_7_FN, GPSR6_7, | |
| 4393 | GP_6_6_FN, GPSR6_6, | |
| 4394 | GP_6_5_FN, GPSR6_5, | |
| 4395 | GP_6_4_FN, GPSR6_4, | |
| 4396 | GP_6_3_FN, GPSR6_3, | |
| 4397 | GP_6_2_FN, GPSR6_2, | |
| 4398 | GP_6_1_FN, GPSR6_1, | |
| 4399 | GP_6_0_FN, GPSR6_0, } | |
| 4400 | }, | |
| 4401 | { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { | |
| 4402 | 0, 0, | |
| 4403 | 0, 0, | |
| 4404 | 0, 0, | |
| 4405 | 0, 0, | |
| 4406 | 0, 0, | |
| 4407 | 0, 0, | |
| 4408 | 0, 0, | |
| 4409 | 0, 0, | |
| 4410 | 0, 0, | |
| 4411 | 0, 0, | |
| 4412 | 0, 0, | |
| 4413 | 0, 0, | |
| 4414 | 0, 0, | |
| 4415 | 0, 0, | |
| 4416 | 0, 0, | |
| 4417 | 0, 0, | |
| 4418 | 0, 0, | |
| 4419 | 0, 0, | |
| 4420 | 0, 0, | |
| 4421 | 0, 0, | |
| 4422 | 0, 0, | |
| 4423 | 0, 0, | |
| 4424 | 0, 0, | |
| 4425 | 0, 0, | |
| 4426 | 0, 0, | |
| 4427 | 0, 0, | |
| 4428 | 0, 0, | |
| 4429 | 0, 0, | |
| 4430 | GP_7_3_FN, GPSR7_3, | |
| 4431 | GP_7_2_FN, GPSR7_2, | |
| 4432 | GP_7_1_FN, GPSR7_1, | |
| 4433 | GP_7_0_FN, GPSR7_0, } | |
| 4434 | }, | |
| 4435 | #undef F_ | |
| 4436 | #undef FM | |
| 4437 | ||
| 4438 | #define F_(x, y) x, | |
| 4439 | #define FM(x) FN_##x, | |
| 4440 | { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { | |
| 4441 | IP0_31_28 | |
| 4442 | IP0_27_24 | |
| 4443 | IP0_23_20 | |
| 4444 | IP0_19_16 | |
| 4445 | IP0_15_12 | |
| 4446 | IP0_11_8 | |
| 4447 | IP0_7_4 | |
| 4448 | IP0_3_0 } | |
| 4449 | }, | |
| 4450 | { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { | |
| 4451 | IP1_31_28 | |
| 4452 | IP1_27_24 | |
| 4453 | IP1_23_20 | |
| 4454 | IP1_19_16 | |
| 4455 | IP1_15_12 | |
| 4456 | IP1_11_8 | |
| 4457 | IP1_7_4 | |
| 4458 | IP1_3_0 } | |
| 4459 | }, | |
| 4460 | { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { | |
| 4461 | IP2_31_28 | |
| 4462 | IP2_27_24 | |
| 4463 | IP2_23_20 | |
| 4464 | IP2_19_16 | |
| 4465 | IP2_15_12 | |
| 4466 | IP2_11_8 | |
| 4467 | IP2_7_4 | |
| 4468 | IP2_3_0 } | |
| 4469 | }, | |
| 4470 | { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { | |
| 4471 | IP3_31_28 | |
| 4472 | IP3_27_24 | |
| 4473 | IP3_23_20 | |
| 4474 | IP3_19_16 | |
| 4475 | IP3_15_12 | |
| 4476 | IP3_11_8 | |
| 4477 | IP3_7_4 | |
| 4478 | IP3_3_0 } | |
| 4479 | }, | |
| 4480 | { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { | |
| 4481 | IP4_31_28 | |
| 4482 | IP4_27_24 | |
| 4483 | IP4_23_20 | |
| 4484 | IP4_19_16 | |
| 4485 | IP4_15_12 | |
| 4486 | IP4_11_8 | |
| 4487 | IP4_7_4 | |
| 4488 | IP4_3_0 } | |
| 4489 | }, | |
| 4490 | { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { | |
| 4491 | IP5_31_28 | |
| 4492 | IP5_27_24 | |
| 4493 | IP5_23_20 | |
| 4494 | IP5_19_16 | |
| 4495 | IP5_15_12 | |
| 4496 | IP5_11_8 | |
| 4497 | IP5_7_4 | |
| 4498 | IP5_3_0 } | |
| 4499 | }, | |
| 4500 | { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { | |
| 4501 | IP6_31_28 | |
| 4502 | IP6_27_24 | |
| 4503 | IP6_23_20 | |
| 4504 | IP6_19_16 | |
| 4505 | IP6_15_12 | |
| 4506 | IP6_11_8 | |
| 4507 | IP6_7_4 | |
| 4508 | IP6_3_0 } | |
| 4509 | }, | |
| 4510 | { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { | |
| 4511 | IP7_31_28 | |
| 4512 | IP7_27_24 | |
| 4513 | IP7_23_20 | |
| 4514 | IP7_19_16 | |
| 4515 | IP7_15_12 | |
| 4516 | IP7_11_8 | |
| 4517 | IP7_7_4 | |
| 4518 | IP7_3_0 } | |
| 4519 | }, | |
| 4520 | { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { | |
| 4521 | IP8_31_28 | |
| 4522 | IP8_27_24 | |
| 4523 | IP8_23_20 | |
| 4524 | IP8_19_16 | |
| 4525 | IP8_15_12 | |
| 4526 | IP8_11_8 | |
| 4527 | IP8_7_4 | |
| 4528 | IP8_3_0 } | |
| 4529 | }, | |
| 4530 | { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { | |
| 4531 | IP9_31_28 | |
| 4532 | IP9_27_24 | |
| 4533 | IP9_23_20 | |
| 4534 | IP9_19_16 | |
| 4535 | IP9_15_12 | |
| 4536 | IP9_11_8 | |
| 4537 | IP9_7_4 | |
| 4538 | IP9_3_0 } | |
| 4539 | }, | |
| 4540 | { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { | |
| 4541 | IP10_31_28 | |
| 4542 | IP10_27_24 | |
| 4543 | IP10_23_20 | |
| 4544 | IP10_19_16 | |
| 4545 | IP10_15_12 | |
| 4546 | IP10_11_8 | |
| 4547 | IP10_7_4 | |
| 4548 | IP10_3_0 } | |
| 4549 | }, | |
| 4550 | { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { | |
| 4551 | IP11_31_28 | |
| 4552 | IP11_27_24 | |
| 4553 | IP11_23_20 | |
| 4554 | IP11_19_16 | |
| 4555 | IP11_15_12 | |
| 4556 | IP11_11_8 | |
| 4557 | IP11_7_4 | |
| 4558 | IP11_3_0 } | |
| 4559 | }, | |
| 4560 | { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { | |
| 4561 | IP12_31_28 | |
| 4562 | IP12_27_24 | |
| 4563 | IP12_23_20 | |
| 4564 | IP12_19_16 | |
| 4565 | IP12_15_12 | |
| 4566 | IP12_11_8 | |
| 4567 | IP12_7_4 | |
| 4568 | IP12_3_0 } | |
| 4569 | }, | |
| 4570 | { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { | |
| 4571 | IP13_31_28 | |
| 4572 | IP13_27_24 | |
| 4573 | IP13_23_20 | |
| 4574 | IP13_19_16 | |
| 4575 | IP13_15_12 | |
| 4576 | IP13_11_8 | |
| 4577 | IP13_7_4 | |
| 4578 | IP13_3_0 } | |
| 4579 | }, | |
| 4580 | { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { | |
| 4581 | IP14_31_28 | |
| 4582 | IP14_27_24 | |
| 4583 | IP14_23_20 | |
| 4584 | IP14_19_16 | |
| 4585 | IP14_15_12 | |
| 4586 | IP14_11_8 | |
| 4587 | IP14_7_4 | |
| 4588 | IP14_3_0 } | |
| 4589 | }, | |
| 4590 | { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { | |
| 4591 | IP15_31_28 | |
| 4592 | IP15_27_24 | |
| 4593 | IP15_23_20 | |
| 4594 | IP15_19_16 | |
| 4595 | IP15_15_12 | |
| 4596 | IP15_11_8 | |
| 4597 | IP15_7_4 | |
| 4598 | IP15_3_0 } | |
| 4599 | }, | |
| 4600 | { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { | |
| 4601 | IP16_31_28 | |
| 4602 | IP16_27_24 | |
| 4603 | IP16_23_20 | |
| 4604 | IP16_19_16 | |
| 4605 | IP16_15_12 | |
| 4606 | IP16_11_8 | |
| 4607 | IP16_7_4 | |
| 4608 | IP16_3_0 } | |
| 4609 | }, | |
| 4610 | { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { | |
| 4611 | IP17_31_28 | |
| 4612 | IP17_27_24 | |
| 4613 | IP17_23_20 | |
| 4614 | IP17_19_16 | |
| 4615 | IP17_15_12 | |
| 4616 | IP17_11_8 | |
| 4617 | IP17_7_4 | |
| 4618 | IP17_3_0 } | |
| 4619 | }, | |
| 4620 | { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { | |
| 4621 | /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4622 | /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4623 | /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4624 | /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4625 | /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4626 | /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4627 | IP18_7_4 | |
| 4628 | IP18_3_0 } | |
| 4629 | }, | |
| 4630 | #undef F_ | |
| 4631 | #undef FM | |
| 4632 | ||
| 4633 | #define F_(x, y) x, | |
| 4634 | #define FM(x) FN_##x, | |
| 4635 | { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, | |
| 4636 | 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, | |
| 4637 | 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { | |
| 4638 | MOD_SEL0_31_30_29 | |
| 4639 | MOD_SEL0_28_27 | |
| 4640 | MOD_SEL0_26_25_24 | |
| 4641 | MOD_SEL0_23 | |
| 4642 | MOD_SEL0_22 | |
| 4643 | MOD_SEL0_21 | |
| 4644 | MOD_SEL0_20 | |
| 4645 | MOD_SEL0_19 | |
| 4646 | MOD_SEL0_18_17 | |
| 4647 | MOD_SEL0_16 | |
| 4648 | MOD_SEL0_15 | |
| 4649 | MOD_SEL0_14_13 | |
| 4650 | MOD_SEL0_12 | |
| 4651 | MOD_SEL0_11 | |
| 4652 | MOD_SEL0_10 | |
| 4653 | MOD_SEL0_9_8 | |
| 4654 | MOD_SEL0_7_6 | |
| 4655 | MOD_SEL0_5 | |
| 4656 | MOD_SEL0_4_3 | |
| 4657 | /* RESERVED 2, 1, 0 */ | |
| 4658 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
| 4659 | }, | |
| 4660 | { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, | |
| 4661 | 2, 3, 1, 2, 3, 1, 1, 2, 1, | |
| 4662 | 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { | |
| 4663 | MOD_SEL1_31_30 | |
| 4664 | MOD_SEL1_29_28_27 | |
| 4665 | MOD_SEL1_26 | |
| 4666 | MOD_SEL1_25_24 | |
| 4667 | MOD_SEL1_23_22_21 | |
| 4668 | MOD_SEL1_20 | |
| 4669 | MOD_SEL1_19 | |
| 4670 | MOD_SEL1_18_17 | |
| 4671 | MOD_SEL1_16 | |
| 4672 | MOD_SEL1_15_14 | |
| 4673 | MOD_SEL1_13 | |
| 4674 | MOD_SEL1_12 | |
| 4675 | MOD_SEL1_11 | |
| 4676 | MOD_SEL1_10 | |
| 4677 | MOD_SEL1_9 | |
| 4678 | 0, 0, 0, 0, /* RESERVED 8, 7 */ | |
| 4679 | MOD_SEL1_6 | |
| 4680 | MOD_SEL1_5 | |
| 4681 | MOD_SEL1_4 | |
| 4682 | MOD_SEL1_3 | |
| 4683 | MOD_SEL1_2 | |
| 4684 | MOD_SEL1_1 | |
| 4685 | MOD_SEL1_0 } | |
| 4686 | }, | |
| 4687 | { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, | |
| 4688 | 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, | |
| 4689 | 4, 4, 4, 3, 1) { | |
| 4690 | MOD_SEL2_31 | |
| 4691 | MOD_SEL2_30 | |
| 4692 | MOD_SEL2_29 | |
| 4693 | MOD_SEL2_28_27 | |
| 4694 | MOD_SEL2_26 | |
| 4695 | MOD_SEL2_25_24_23 | |
| 4696 | MOD_SEL2_22 | |
| 4697 | MOD_SEL2_21 | |
| 4698 | MOD_SEL2_20 | |
| 4699 | MOD_SEL2_19 | |
| 4700 | MOD_SEL2_18 | |
| 4701 | MOD_SEL2_17 | |
| 4702 | /* RESERVED 16 */ | |
| 4703 | 0, 0, | |
| 4704 | /* RESERVED 15, 14, 13, 12 */ | |
| 4705 | 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4706 | 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4707 | /* RESERVED 11, 10, 9, 8 */ | |
| 4708 | 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4709 | 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4710 | /* RESERVED 7, 6, 5, 4 */ | |
| 4711 | 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4712 | 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4713 | /* RESERVED 3, 2, 1 */ | |
| 4714 | 0, 0, 0, 0, 0, 0, 0, 0, | |
| 4715 | MOD_SEL2_0 } | |
| 4716 | }, | |
| 4717 | { }, | |
| 4718 | }; | |
| 4719 | ||
| 9e35d6fa NS |
4720 | static const struct pinmux_drive_reg pinmux_drive_regs[] = { |
| 4721 | { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { | |
| 4722 | { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ | |
| 4723 | { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ | |
| 4724 | { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ | |
| 4725 | { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ | |
| 4726 | { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ | |
| 4727 | { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ | |
| 4728 | { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ | |
| 4729 | { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ | |
| 4730 | } }, | |
| 4731 | { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { | |
| 4732 | { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ | |
| 4733 | { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ | |
| 4734 | { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ | |
| 4735 | { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ | |
| 4736 | { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ | |
| 4737 | { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ | |
| 4738 | { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ | |
| 4739 | { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ | |
| 4740 | } }, | |
| 4741 | { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { | |
| 4742 | { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ | |
| 4743 | { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ | |
| 4744 | { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ | |
| 4745 | { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ | |
| 4746 | { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ | |
| 4747 | { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ | |
| 4748 | { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ | |
| 4749 | { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ | |
| 4750 | } }, | |
| 4751 | { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { | |
| 4752 | { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ | |
| 4753 | { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ | |
| 4754 | { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ | |
| 4755 | { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ | |
| 4756 | { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ | |
| 4757 | { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ | |
| 4758 | { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ | |
| 4759 | { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ | |
| 4760 | } }, | |
| 4761 | { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { | |
| 4762 | { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ | |
| 4763 | { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ | |
| 4764 | { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ | |
| 4765 | { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ | |
| 4766 | { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ | |
| 4767 | { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ | |
| 4768 | { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ | |
| 4769 | { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ | |
| 4770 | } }, | |
| 4771 | { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { | |
| 4772 | { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ | |
| 4773 | { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ | |
| 4774 | { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ | |
| 4775 | { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ | |
| 4776 | { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ | |
| 4777 | { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ | |
| 4778 | { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ | |
| 4779 | { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ | |
| 4780 | } }, | |
| 4781 | { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { | |
| 4782 | { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ | |
| 4783 | { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ | |
| 4784 | { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ | |
| 4785 | { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ | |
| 4786 | { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ | |
| 4787 | { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ | |
| 4788 | { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ | |
| 4789 | { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ | |
| 4790 | } }, | |
| 4791 | { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { | |
| 4792 | { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ | |
| 4793 | { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ | |
| 4794 | { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ | |
| 4795 | { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ | |
| 4796 | { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ | |
| 4797 | { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ | |
| 4798 | { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ | |
| 4799 | { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ | |
| 4800 | } }, | |
| 4801 | { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { | |
| 4802 | { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ | |
| 4803 | { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ | |
| 4804 | { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ | |
| 4805 | { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ | |
| 4806 | { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ | |
| 4807 | { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ | |
| 4808 | { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ | |
| 4809 | { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ | |
| 4810 | } }, | |
| 4811 | { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { | |
| 4812 | { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ | |
| 4813 | { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ | |
| 4814 | { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ | |
| 4815 | { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ | |
| 4816 | { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ | |
| 4817 | { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ | |
| 4818 | { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ | |
| 4819 | { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ | |
| 4820 | } }, | |
| 4821 | { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { | |
| 4822 | { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ | |
| 4823 | { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ | |
| 4824 | { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ | |
| 4825 | { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ | |
| 4826 | { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ | |
| 4827 | { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ | |
| 4828 | { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ | |
| 4829 | { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ | |
| 4830 | } }, | |
| 4831 | { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { | |
| 4832 | { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ | |
| 4833 | { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ | |
| 4834 | { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ | |
| 4835 | { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ | |
| 4836 | { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ | |
| 4837 | { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ | |
| 4838 | { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ | |
| 4839 | { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ | |
| 4840 | } }, | |
| 4841 | { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { | |
| 4842 | { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */ | |
| 4843 | { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */ | |
| 4844 | { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ | |
| 4845 | } }, | |
| 4846 | { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { | |
| 4847 | { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ | |
| 4848 | { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ | |
| 4849 | { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ | |
| 4850 | { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ | |
| 4851 | { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ | |
| 4852 | { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ | |
| 4853 | { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ | |
| 4854 | { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ | |
| 4855 | } }, | |
| 4856 | { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { | |
| 4857 | { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ | |
| 4858 | { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ | |
| 4859 | { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ | |
| 4860 | { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ | |
| 4861 | { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ | |
| 4862 | { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ | |
| 4863 | { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ | |
| 4864 | { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ | |
| 4865 | } }, | |
| 4866 | { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { | |
| 4867 | { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ | |
| 4868 | { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ | |
| 4869 | { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ | |
| 4870 | { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ | |
| 4871 | { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ | |
| 4872 | { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ | |
| 4873 | { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ | |
| 4874 | { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ | |
| 4875 | } }, | |
| 4876 | { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { | |
| 4877 | { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ | |
| 4878 | { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ | |
| 4879 | { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ | |
| 4880 | { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ | |
| 4881 | { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ | |
| 4882 | { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ | |
| 4883 | { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ | |
| 4884 | { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ | |
| 4885 | } }, | |
| 4886 | { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { | |
| 4887 | { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ | |
| 4888 | { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ | |
| 4889 | { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ | |
| 4890 | { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ | |
| 4891 | { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ | |
| 4892 | { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ | |
| 4893 | { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ | |
| 4894 | { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ | |
| 4895 | } }, | |
| 4896 | { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { | |
| 4897 | { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ | |
| 4898 | { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ | |
| 4899 | { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ | |
| 4900 | { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ | |
| 4901 | { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ | |
| 4902 | { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ | |
| 4903 | { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ | |
| 4904 | { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ | |
| 4905 | } }, | |
| 4906 | { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { | |
| 4907 | { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ | |
| 4908 | { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ | |
| 4909 | { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ | |
| 4910 | { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ | |
| 4911 | { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ | |
| 4912 | { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ | |
| 4913 | { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ | |
| 4914 | { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ | |
| 4915 | } }, | |
| 4916 | { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { | |
| 4917 | { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ | |
| 4918 | { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ | |
| 4919 | { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ | |
| 4920 | { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ | |
| 4921 | { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ | |
| 4922 | { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ | |
| 4923 | { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ | |
| 4924 | { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ | |
| 4925 | } }, | |
| 4926 | { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { | |
| 4927 | { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ | |
| 4928 | { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ | |
| 4929 | { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ | |
| 4930 | { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ | |
| 4931 | { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */ | |
| 4932 | { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */ | |
| 4933 | { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ | |
| 4934 | { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ | |
| 4935 | } }, | |
| 4936 | { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { | |
| 4937 | { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ | |
| 4938 | { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ | |
| 4939 | { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ | |
| 4940 | { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ | |
| 4941 | { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ | |
| 4942 | { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ | |
| 4943 | { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ | |
| 4944 | { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ | |
| 4945 | } }, | |
| 4946 | { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { | |
| 4947 | { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ | |
| 4948 | { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ | |
| 4949 | { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ | |
| 4950 | { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ | |
| 4951 | { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ | |
| 4952 | { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ | |
| 4953 | { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ | |
| 4954 | { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ | |
| 4955 | } }, | |
| 4956 | { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { | |
| 4957 | { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ | |
| 4958 | { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ | |
| 4959 | { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ | |
| 4960 | { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ | |
| 4961 | { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ | |
| 4962 | { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ | |
| 4963 | { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ | |
| 4964 | } }, | |
| 4965 | { }, | |
| 4966 | }; | |
| 4967 | ||
| c5901bdc SH |
4968 | static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) |
| 4969 | { | |
| 4970 | int bit = -EINVAL; | |
| 4971 | ||
| 4972 | *pocctrl = 0xe6060380; | |
| 4973 | ||
| 4974 | if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) | |
| 4975 | bit = pin & 0x1f; | |
| 4976 | ||
| 4977 | if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) | |
| 4978 | bit = (pin & 0x1f) + 12; | |
| 4979 | ||
| 4980 | return bit; | |
| 4981 | } | |
| 4982 | ||
| 2d40bd24 NS |
4983 | #define PUEN 0xe6060400 |
| 4984 | #define PUD 0xe6060440 | |
| 4985 | ||
| 4986 | #define PU0 0x00 | |
| 4987 | #define PU1 0x04 | |
| 4988 | #define PU2 0x08 | |
| 4989 | #define PU3 0x0c | |
| 4990 | #define PU4 0x10 | |
| 4991 | #define PU5 0x14 | |
| 4992 | #define PU6 0x18 | |
| 4993 | ||
| 4994 | static const struct sh_pfc_bias_info bias_info[] = { | |
| 4995 | { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ | |
| 4996 | { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ | |
| 4997 | { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ | |
| 4998 | { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ | |
| 4999 | { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ | |
| 5000 | { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ | |
| 5001 | { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ | |
| 5002 | { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ | |
| 5003 | { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ | |
| 5004 | { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ | |
| 5005 | { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ | |
| 5006 | { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ | |
| 5007 | { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ | |
| 5008 | { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ | |
| 5009 | { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ | |
| 5010 | { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ | |
| 5011 | { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ | |
| 5012 | { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ | |
| 5013 | { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ | |
| 5014 | { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ | |
| 5015 | { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ | |
| 5016 | { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ | |
| 5017 | { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ | |
| 5018 | { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ | |
| 5019 | { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ | |
| 5020 | { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ | |
| 5021 | { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ | |
| 5022 | { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ | |
| 5023 | { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ | |
| 5024 | { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ | |
| 5025 | { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ | |
| 5026 | { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ | |
| 5027 | ||
| 5028 | { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ | |
| 5029 | { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ | |
| 5030 | { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ | |
| 5031 | { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ | |
| 5032 | { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ | |
| 5033 | { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ | |
| 5034 | { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ | |
| 5035 | { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ | |
| 5036 | { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ | |
| 5037 | { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ | |
| 5038 | { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ | |
| 5039 | { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ | |
| 5040 | { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ | |
| 5041 | { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ | |
| 5042 | { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ | |
| 5043 | { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ | |
| 5044 | { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ | |
| 5045 | { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ | |
| 5046 | { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ | |
| 5047 | { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ | |
| 5048 | { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ | |
| 5049 | { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ | |
| 5050 | { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ | |
| 5051 | { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ | |
| 5052 | { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ | |
| 5053 | { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ | |
| 5054 | { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ | |
| 5055 | { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ | |
| 5056 | { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ | |
| 5057 | { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ | |
| 5058 | { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ | |
| 5059 | { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ | |
| 5060 | ||
| 5061 | { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ | |
| 5062 | { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ | |
| 5063 | { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */ | |
| 5064 | { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ | |
| 5065 | { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ | |
| 5066 | { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ | |
| 5067 | { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ | |
| 5068 | { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ | |
| 5069 | { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ | |
| 5070 | { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ | |
| 5071 | { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ | |
| 5072 | { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ | |
| 5073 | { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ | |
| 5074 | { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ | |
| 5075 | { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ | |
| 5076 | { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ | |
| 5077 | { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ | |
| 5078 | { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ | |
| 5079 | { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ | |
| 5080 | { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ | |
| 5081 | { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ | |
| 5082 | { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ | |
| 5083 | { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ | |
| 5084 | { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ | |
| 5085 | { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ | |
| 5086 | { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ | |
| 5087 | { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ | |
| 5088 | { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ | |
| 5089 | { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ | |
| 5090 | { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ | |
| 5091 | { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ | |
| 5092 | { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */ | |
| 5093 | ||
| 5094 | { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ | |
| 5095 | { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ | |
| 5096 | { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ | |
| 5097 | { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ | |
| 5098 | { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ | |
| 5099 | { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ | |
| 5100 | { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ | |
| 5101 | { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ | |
| 5102 | { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ | |
| 5103 | { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ | |
| 5104 | { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ | |
| 5105 | { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ | |
| 5106 | { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ | |
| 5107 | { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ | |
| 5108 | { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ | |
| 5109 | { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ | |
| 5110 | { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ | |
| 5111 | { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ | |
| 5112 | { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ | |
| 5113 | { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ | |
| 5114 | { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ | |
| 5115 | { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ | |
| 5116 | { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ | |
| 5117 | /* bit 8 n/a */ | |
| 5118 | { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ | |
| 5119 | { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ | |
| 5120 | { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ | |
| 5121 | { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ | |
| 5122 | { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ | |
| 5123 | { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */ | |
| 5124 | /* bit 1 n/a on M3*/ | |
| 5125 | { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */ | |
| 5126 | ||
| 5127 | { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ | |
| 5128 | { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ | |
| 5129 | { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ | |
| 5130 | { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ | |
| 5131 | { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ | |
| 5132 | { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ | |
| 5133 | { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ | |
| 5134 | { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ | |
| 5135 | { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ | |
| 5136 | { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ | |
| 5137 | { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ | |
| 5138 | { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ | |
| 5139 | { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ | |
| 5140 | { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ | |
| 5141 | { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ | |
| 5142 | { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ | |
| 5143 | { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ | |
| 5144 | { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ | |
| 5145 | { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ | |
| 5146 | { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ | |
| 5147 | { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ | |
| 5148 | { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ | |
| 5149 | { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ | |
| 5150 | { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ | |
| 5151 | { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ | |
| 5152 | { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ | |
| 5153 | { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ | |
| 5154 | { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ | |
| 5155 | { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ | |
| 5156 | { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ | |
| 5157 | { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ | |
| 5158 | { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ | |
| 5159 | ||
| 5160 | { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ | |
| 5161 | { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ | |
| 5162 | { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ | |
| 5163 | { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ | |
| 5164 | { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ | |
| 5165 | { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ | |
| 5166 | { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ | |
| 5167 | { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ | |
| 5168 | { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ | |
| 5169 | { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ | |
| 5170 | { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ | |
| 5171 | { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ | |
| 5172 | { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ | |
| 5173 | { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ | |
| 5174 | { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ | |
| 5175 | { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ | |
| 5176 | { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ | |
| 5177 | { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ | |
| 5178 | { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ | |
| 5179 | { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ | |
| 5180 | { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ | |
| 5181 | { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ | |
| 5182 | { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ | |
| 5183 | { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ | |
| 5184 | { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ | |
| 5185 | { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ | |
| 5186 | { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ | |
| 5187 | { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ | |
| 5188 | { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ | |
| 5189 | { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ | |
| 5190 | { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ | |
| 5191 | { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ | |
| 5192 | ||
| 5193 | { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */ | |
| 5194 | { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */ | |
| 5195 | { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ | |
| 5196 | { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ | |
| 5197 | { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ | |
| 5198 | { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ | |
| 5199 | { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ | |
| 5200 | }; | |
| 5201 | ||
| 5202 | static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, | |
| 5203 | unsigned int pin) | |
| 5204 | { | |
| 5205 | const struct sh_pfc_bias_info *info; | |
| 5206 | u32 reg; | |
| 5207 | u32 bit; | |
| 5208 | ||
| 5209 | info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); | |
| 5210 | if (!info) | |
| 5211 | return PIN_CONFIG_BIAS_DISABLE; | |
| 5212 | ||
| 5213 | reg = info->reg; | |
| 5214 | bit = BIT(info->bit); | |
| 5215 | ||
| 5216 | if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) | |
| 5217 | return PIN_CONFIG_BIAS_DISABLE; | |
| 5218 | else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) | |
| 5219 | return PIN_CONFIG_BIAS_PULL_UP; | |
| 5220 | else | |
| 5221 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
| 5222 | } | |
| 5223 | ||
| 5224 | static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, | |
| 5225 | unsigned int bias) | |
| 5226 | { | |
| 5227 | const struct sh_pfc_bias_info *info; | |
| 5228 | u32 enable, updown; | |
| 5229 | u32 reg; | |
| 5230 | u32 bit; | |
| 5231 | ||
| 5232 | info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); | |
| 5233 | if (!info) | |
| 5234 | return; | |
| 5235 | ||
| 5236 | reg = info->reg; | |
| 5237 | bit = BIT(info->bit); | |
| 5238 | ||
| 5239 | enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; | |
| 5240 | if (bias != PIN_CONFIG_BIAS_DISABLE) | |
| 5241 | enable |= bit; | |
| 5242 | ||
| 5243 | updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; | |
| 5244 | if (bias == PIN_CONFIG_BIAS_PULL_UP) | |
| 5245 | updown |= bit; | |
| 5246 | ||
| 5247 | sh_pfc_write_reg(pfc, PUD + reg, 32, updown); | |
| 5248 | sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); | |
| 5249 | } | |
| 5250 | ||
| c5901bdc SH |
5251 | static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { |
| 5252 | .pin_to_pocctrl = r8a7796_pin_to_pocctrl, | |
| 2d40bd24 NS |
5253 | .get_bias = r8a7796_pinmux_get_bias, |
| 5254 | .set_bias = r8a7796_pinmux_set_bias, | |
| c5901bdc SH |
5255 | }; |
| 5256 | ||
| f9aece73 TK |
5257 | const struct sh_pfc_soc_info r8a7796_pinmux_info = { |
| 5258 | .name = "r8a77960_pfc", | |
| c5901bdc | 5259 | .ops = &r8a7796_pinmux_ops, |
| f9aece73 TK |
5260 | .unlock_reg = 0xe6060000, /* PMMR */ |
| 5261 | ||
| 5262 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
| 5263 | ||
| 5264 | .pins = pinmux_pins, | |
| 5265 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
| 5266 | .groups = pinmux_groups, | |
| 5267 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
| 5268 | .functions = pinmux_functions, | |
| 5269 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
| 5270 | ||
| 5271 | .cfg_regs = pinmux_config_regs, | |
| 9e35d6fa | 5272 | .drive_regs = pinmux_drive_regs, |
| f9aece73 TK |
5273 | |
| 5274 | .pinmux_data = pinmux_data, | |
| 5275 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
| 5276 | }; |