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518fb721 GG |
1 | /* |
2 | * tps65910.c -- TI tps65910 | |
3 | * | |
4 | * Copyright 2010 Texas Instruments Inc. | |
5 | * | |
6 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
7 | * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
518fb721 GG |
23 | #include <linux/slab.h> |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mfd/tps65910.h> | |
6790178f | 26 | #include <linux/regulator/of_regulator.h> |
518fb721 | 27 | |
518fb721 | 28 | #define TPS65910_SUPPLY_STATE_ENABLED 0x1 |
1e0c66f4 LD |
29 | #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \ |
30 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \ | |
f30b0716 LD |
31 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \ |
32 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
518fb721 GG |
33 | |
34 | /* supported VIO voltages in milivolts */ | |
35 | static const u16 VIO_VSEL_table[] = { | |
36 | 1500, 1800, 2500, 3300, | |
37 | }; | |
38 | ||
a320e3c3 JEC |
39 | /* VSEL tables for TPS65910 specific LDOs and dcdc's */ |
40 | ||
41 | /* supported VDD3 voltages in milivolts */ | |
518fb721 GG |
42 | static const u16 VDD3_VSEL_table[] = { |
43 | 5000, | |
44 | }; | |
45 | ||
46 | /* supported VDIG1 voltages in milivolts */ | |
47 | static const u16 VDIG1_VSEL_table[] = { | |
48 | 1200, 1500, 1800, 2700, | |
49 | }; | |
50 | ||
51 | /* supported VDIG2 voltages in milivolts */ | |
52 | static const u16 VDIG2_VSEL_table[] = { | |
53 | 1000, 1100, 1200, 1800, | |
54 | }; | |
55 | ||
56 | /* supported VPLL voltages in milivolts */ | |
57 | static const u16 VPLL_VSEL_table[] = { | |
58 | 1000, 1100, 1800, 2500, | |
59 | }; | |
60 | ||
61 | /* supported VDAC voltages in milivolts */ | |
62 | static const u16 VDAC_VSEL_table[] = { | |
63 | 1800, 2600, 2800, 2850, | |
64 | }; | |
65 | ||
66 | /* supported VAUX1 voltages in milivolts */ | |
67 | static const u16 VAUX1_VSEL_table[] = { | |
68 | 1800, 2500, 2800, 2850, | |
69 | }; | |
70 | ||
71 | /* supported VAUX2 voltages in milivolts */ | |
72 | static const u16 VAUX2_VSEL_table[] = { | |
73 | 1800, 2800, 2900, 3300, | |
74 | }; | |
75 | ||
76 | /* supported VAUX33 voltages in milivolts */ | |
77 | static const u16 VAUX33_VSEL_table[] = { | |
78 | 1800, 2000, 2800, 3300, | |
79 | }; | |
80 | ||
81 | /* supported VMMC voltages in milivolts */ | |
82 | static const u16 VMMC_VSEL_table[] = { | |
83 | 1800, 2800, 3000, 3300, | |
84 | }; | |
85 | ||
86 | struct tps_info { | |
87 | const char *name; | |
88 | unsigned min_uV; | |
89 | unsigned max_uV; | |
7d38a3cb LD |
90 | u8 n_voltages; |
91 | const u16 *voltage_table; | |
0651eed5 | 92 | int enable_time_us; |
518fb721 GG |
93 | }; |
94 | ||
95 | static struct tps_info tps65910_regs[] = { | |
96 | { | |
33a6943d | 97 | .name = "vrtc", |
0651eed5 | 98 | .enable_time_us = 2200, |
518fb721 GG |
99 | }, |
100 | { | |
33a6943d | 101 | .name = "vio", |
518fb721 GG |
102 | .min_uV = 1500000, |
103 | .max_uV = 3300000, | |
7d38a3cb LD |
104 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
105 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 106 | .enable_time_us = 350, |
518fb721 GG |
107 | }, |
108 | { | |
33a6943d | 109 | .name = "vdd1", |
518fb721 GG |
110 | .min_uV = 600000, |
111 | .max_uV = 4500000, | |
0651eed5 | 112 | .enable_time_us = 350, |
518fb721 GG |
113 | }, |
114 | { | |
33a6943d | 115 | .name = "vdd2", |
518fb721 GG |
116 | .min_uV = 600000, |
117 | .max_uV = 4500000, | |
0651eed5 | 118 | .enable_time_us = 350, |
518fb721 GG |
119 | }, |
120 | { | |
33a6943d | 121 | .name = "vdd3", |
518fb721 GG |
122 | .min_uV = 5000000, |
123 | .max_uV = 5000000, | |
7d38a3cb LD |
124 | .n_voltages = ARRAY_SIZE(VDD3_VSEL_table), |
125 | .voltage_table = VDD3_VSEL_table, | |
0651eed5 | 126 | .enable_time_us = 200, |
518fb721 GG |
127 | }, |
128 | { | |
33a6943d | 129 | .name = "vdig1", |
518fb721 GG |
130 | .min_uV = 1200000, |
131 | .max_uV = 2700000, | |
7d38a3cb LD |
132 | .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table), |
133 | .voltage_table = VDIG1_VSEL_table, | |
0651eed5 | 134 | .enable_time_us = 100, |
518fb721 GG |
135 | }, |
136 | { | |
33a6943d | 137 | .name = "vdig2", |
518fb721 GG |
138 | .min_uV = 1000000, |
139 | .max_uV = 1800000, | |
7d38a3cb LD |
140 | .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table), |
141 | .voltage_table = VDIG2_VSEL_table, | |
0651eed5 | 142 | .enable_time_us = 100, |
518fb721 GG |
143 | }, |
144 | { | |
33a6943d | 145 | .name = "vpll", |
518fb721 GG |
146 | .min_uV = 1000000, |
147 | .max_uV = 2500000, | |
7d38a3cb LD |
148 | .n_voltages = ARRAY_SIZE(VPLL_VSEL_table), |
149 | .voltage_table = VPLL_VSEL_table, | |
0651eed5 | 150 | .enable_time_us = 100, |
518fb721 GG |
151 | }, |
152 | { | |
33a6943d | 153 | .name = "vdac", |
518fb721 GG |
154 | .min_uV = 1800000, |
155 | .max_uV = 2850000, | |
7d38a3cb LD |
156 | .n_voltages = ARRAY_SIZE(VDAC_VSEL_table), |
157 | .voltage_table = VDAC_VSEL_table, | |
0651eed5 | 158 | .enable_time_us = 100, |
518fb721 GG |
159 | }, |
160 | { | |
33a6943d | 161 | .name = "vaux1", |
518fb721 GG |
162 | .min_uV = 1800000, |
163 | .max_uV = 2850000, | |
7d38a3cb LD |
164 | .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table), |
165 | .voltage_table = VAUX1_VSEL_table, | |
0651eed5 | 166 | .enable_time_us = 100, |
518fb721 GG |
167 | }, |
168 | { | |
33a6943d | 169 | .name = "vaux2", |
518fb721 GG |
170 | .min_uV = 1800000, |
171 | .max_uV = 3300000, | |
7d38a3cb LD |
172 | .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table), |
173 | .voltage_table = VAUX2_VSEL_table, | |
0651eed5 | 174 | .enable_time_us = 100, |
518fb721 GG |
175 | }, |
176 | { | |
33a6943d | 177 | .name = "vaux33", |
518fb721 GG |
178 | .min_uV = 1800000, |
179 | .max_uV = 3300000, | |
7d38a3cb LD |
180 | .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table), |
181 | .voltage_table = VAUX33_VSEL_table, | |
0651eed5 | 182 | .enable_time_us = 100, |
518fb721 GG |
183 | }, |
184 | { | |
33a6943d | 185 | .name = "vmmc", |
518fb721 GG |
186 | .min_uV = 1800000, |
187 | .max_uV = 3300000, | |
7d38a3cb LD |
188 | .n_voltages = ARRAY_SIZE(VMMC_VSEL_table), |
189 | .voltage_table = VMMC_VSEL_table, | |
0651eed5 | 190 | .enable_time_us = 100, |
518fb721 GG |
191 | }, |
192 | }; | |
193 | ||
a320e3c3 | 194 | static struct tps_info tps65911_regs[] = { |
c2f8efd7 | 195 | { |
33a6943d | 196 | .name = "vrtc", |
0651eed5 | 197 | .enable_time_us = 2200, |
c2f8efd7 | 198 | }, |
a320e3c3 | 199 | { |
33a6943d | 200 | .name = "vio", |
a320e3c3 JEC |
201 | .min_uV = 1500000, |
202 | .max_uV = 3300000, | |
7d38a3cb LD |
203 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
204 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 205 | .enable_time_us = 350, |
a320e3c3 JEC |
206 | }, |
207 | { | |
33a6943d | 208 | .name = "vdd1", |
a320e3c3 JEC |
209 | .min_uV = 600000, |
210 | .max_uV = 4500000, | |
7d38a3cb | 211 | .n_voltages = 73, |
0651eed5 | 212 | .enable_time_us = 350, |
a320e3c3 JEC |
213 | }, |
214 | { | |
33a6943d | 215 | .name = "vdd2", |
a320e3c3 JEC |
216 | .min_uV = 600000, |
217 | .max_uV = 4500000, | |
7d38a3cb | 218 | .n_voltages = 73, |
0651eed5 | 219 | .enable_time_us = 350, |
a320e3c3 JEC |
220 | }, |
221 | { | |
33a6943d | 222 | .name = "vddctrl", |
a320e3c3 JEC |
223 | .min_uV = 600000, |
224 | .max_uV = 1400000, | |
7d38a3cb | 225 | .n_voltages = 65, |
0651eed5 | 226 | .enable_time_us = 900, |
a320e3c3 JEC |
227 | }, |
228 | { | |
33a6943d | 229 | .name = "ldo1", |
a320e3c3 JEC |
230 | .min_uV = 1000000, |
231 | .max_uV = 3300000, | |
7d38a3cb | 232 | .n_voltages = 47, |
0651eed5 | 233 | .enable_time_us = 420, |
a320e3c3 JEC |
234 | }, |
235 | { | |
33a6943d | 236 | .name = "ldo2", |
a320e3c3 JEC |
237 | .min_uV = 1000000, |
238 | .max_uV = 3300000, | |
7d38a3cb | 239 | .n_voltages = 47, |
0651eed5 | 240 | .enable_time_us = 420, |
a320e3c3 JEC |
241 | }, |
242 | { | |
33a6943d | 243 | .name = "ldo3", |
a320e3c3 JEC |
244 | .min_uV = 1000000, |
245 | .max_uV = 3300000, | |
7d38a3cb | 246 | .n_voltages = 24, |
0651eed5 | 247 | .enable_time_us = 230, |
a320e3c3 JEC |
248 | }, |
249 | { | |
33a6943d | 250 | .name = "ldo4", |
a320e3c3 JEC |
251 | .min_uV = 1000000, |
252 | .max_uV = 3300000, | |
7d38a3cb | 253 | .n_voltages = 47, |
0651eed5 | 254 | .enable_time_us = 230, |
a320e3c3 JEC |
255 | }, |
256 | { | |
33a6943d | 257 | .name = "ldo5", |
a320e3c3 JEC |
258 | .min_uV = 1000000, |
259 | .max_uV = 3300000, | |
7d38a3cb | 260 | .n_voltages = 24, |
0651eed5 | 261 | .enable_time_us = 230, |
a320e3c3 JEC |
262 | }, |
263 | { | |
33a6943d | 264 | .name = "ldo6", |
a320e3c3 JEC |
265 | .min_uV = 1000000, |
266 | .max_uV = 3300000, | |
7d38a3cb | 267 | .n_voltages = 24, |
0651eed5 | 268 | .enable_time_us = 230, |
a320e3c3 JEC |
269 | }, |
270 | { | |
33a6943d | 271 | .name = "ldo7", |
a320e3c3 JEC |
272 | .min_uV = 1000000, |
273 | .max_uV = 3300000, | |
7d38a3cb | 274 | .n_voltages = 24, |
0651eed5 | 275 | .enable_time_us = 230, |
a320e3c3 JEC |
276 | }, |
277 | { | |
33a6943d | 278 | .name = "ldo8", |
a320e3c3 JEC |
279 | .min_uV = 1000000, |
280 | .max_uV = 3300000, | |
7d38a3cb | 281 | .n_voltages = 24, |
0651eed5 | 282 | .enable_time_us = 230, |
a320e3c3 JEC |
283 | }, |
284 | }; | |
285 | ||
1e0c66f4 LD |
286 | #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) |
287 | static unsigned int tps65910_ext_sleep_control[] = { | |
288 | 0, | |
289 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
290 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
291 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
292 | EXT_CONTROL_REG_BITS(VDD3, 1, 3), | |
293 | EXT_CONTROL_REG_BITS(VDIG1, 0, 1), | |
294 | EXT_CONTROL_REG_BITS(VDIG2, 0, 2), | |
295 | EXT_CONTROL_REG_BITS(VPLL, 0, 6), | |
296 | EXT_CONTROL_REG_BITS(VDAC, 0, 7), | |
297 | EXT_CONTROL_REG_BITS(VAUX1, 0, 3), | |
298 | EXT_CONTROL_REG_BITS(VAUX2, 0, 4), | |
299 | EXT_CONTROL_REG_BITS(VAUX33, 0, 5), | |
300 | EXT_CONTROL_REG_BITS(VMMC, 0, 0), | |
301 | }; | |
302 | ||
303 | static unsigned int tps65911_ext_sleep_control[] = { | |
304 | 0, | |
305 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
306 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
307 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
308 | EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3), | |
309 | EXT_CONTROL_REG_BITS(LDO1, 0, 1), | |
310 | EXT_CONTROL_REG_BITS(LDO2, 0, 2), | |
311 | EXT_CONTROL_REG_BITS(LDO3, 0, 7), | |
312 | EXT_CONTROL_REG_BITS(LDO4, 0, 6), | |
313 | EXT_CONTROL_REG_BITS(LDO5, 0, 3), | |
314 | EXT_CONTROL_REG_BITS(LDO6, 0, 0), | |
315 | EXT_CONTROL_REG_BITS(LDO7, 0, 5), | |
316 | EXT_CONTROL_REG_BITS(LDO8, 0, 4), | |
317 | }; | |
318 | ||
518fb721 | 319 | struct tps65910_reg { |
39aa9b6e | 320 | struct regulator_desc *desc; |
518fb721 | 321 | struct tps65910 *mfd; |
39aa9b6e AL |
322 | struct regulator_dev **rdev; |
323 | struct tps_info **info; | |
518fb721 | 324 | struct mutex mutex; |
39aa9b6e | 325 | int num_regulators; |
518fb721 | 326 | int mode; |
a320e3c3 | 327 | int (*get_ctrl_reg)(int); |
1e0c66f4 LD |
328 | unsigned int *ext_sleep_control; |
329 | unsigned int board_ext_control[TPS65910_NUM_REGS]; | |
518fb721 GG |
330 | }; |
331 | ||
332 | static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg) | |
333 | { | |
334 | u8 val; | |
335 | int err; | |
336 | ||
337 | err = pmic->mfd->read(pmic->mfd, reg, 1, &val); | |
338 | if (err) | |
339 | return err; | |
340 | ||
341 | return val; | |
342 | } | |
343 | ||
344 | static inline int tps65910_write(struct tps65910_reg *pmic, u8 reg, u8 val) | |
345 | { | |
346 | return pmic->mfd->write(pmic->mfd, reg, 1, &val); | |
347 | } | |
348 | ||
349 | static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, | |
350 | u8 set_mask, u8 clear_mask) | |
351 | { | |
352 | int err, data; | |
353 | ||
354 | mutex_lock(&pmic->mutex); | |
355 | ||
356 | data = tps65910_read(pmic, reg); | |
357 | if (data < 0) { | |
358 | dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
359 | err = data; | |
360 | goto out; | |
361 | } | |
362 | ||
363 | data &= ~clear_mask; | |
364 | data |= set_mask; | |
365 | err = tps65910_write(pmic, reg, data); | |
366 | if (err) | |
367 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
368 | ||
369 | out: | |
370 | mutex_unlock(&pmic->mutex); | |
371 | return err; | |
372 | } | |
373 | ||
374 | static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg) | |
375 | { | |
376 | int data; | |
377 | ||
378 | mutex_lock(&pmic->mutex); | |
379 | ||
380 | data = tps65910_read(pmic, reg); | |
381 | if (data < 0) | |
382 | dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
383 | ||
384 | mutex_unlock(&pmic->mutex); | |
385 | return data; | |
386 | } | |
387 | ||
388 | static int tps65910_reg_write(struct tps65910_reg *pmic, u8 reg, u8 val) | |
389 | { | |
390 | int err; | |
391 | ||
392 | mutex_lock(&pmic->mutex); | |
393 | ||
394 | err = tps65910_write(pmic, reg, val); | |
395 | if (err < 0) | |
396 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
397 | ||
398 | mutex_unlock(&pmic->mutex); | |
399 | return err; | |
400 | } | |
401 | ||
402 | static int tps65910_get_ctrl_register(int id) | |
403 | { | |
404 | switch (id) { | |
405 | case TPS65910_REG_VRTC: | |
406 | return TPS65910_VRTC; | |
407 | case TPS65910_REG_VIO: | |
408 | return TPS65910_VIO; | |
409 | case TPS65910_REG_VDD1: | |
410 | return TPS65910_VDD1; | |
411 | case TPS65910_REG_VDD2: | |
412 | return TPS65910_VDD2; | |
413 | case TPS65910_REG_VDD3: | |
414 | return TPS65910_VDD3; | |
415 | case TPS65910_REG_VDIG1: | |
416 | return TPS65910_VDIG1; | |
417 | case TPS65910_REG_VDIG2: | |
418 | return TPS65910_VDIG2; | |
419 | case TPS65910_REG_VPLL: | |
420 | return TPS65910_VPLL; | |
421 | case TPS65910_REG_VDAC: | |
422 | return TPS65910_VDAC; | |
423 | case TPS65910_REG_VAUX1: | |
424 | return TPS65910_VAUX1; | |
425 | case TPS65910_REG_VAUX2: | |
426 | return TPS65910_VAUX2; | |
427 | case TPS65910_REG_VAUX33: | |
428 | return TPS65910_VAUX33; | |
429 | case TPS65910_REG_VMMC: | |
430 | return TPS65910_VMMC; | |
431 | default: | |
432 | return -EINVAL; | |
433 | } | |
434 | } | |
435 | ||
a320e3c3 JEC |
436 | static int tps65911_get_ctrl_register(int id) |
437 | { | |
438 | switch (id) { | |
439 | case TPS65910_REG_VRTC: | |
440 | return TPS65910_VRTC; | |
441 | case TPS65910_REG_VIO: | |
442 | return TPS65910_VIO; | |
443 | case TPS65910_REG_VDD1: | |
444 | return TPS65910_VDD1; | |
445 | case TPS65910_REG_VDD2: | |
446 | return TPS65910_VDD2; | |
447 | case TPS65911_REG_VDDCTRL: | |
448 | return TPS65911_VDDCTRL; | |
449 | case TPS65911_REG_LDO1: | |
450 | return TPS65911_LDO1; | |
451 | case TPS65911_REG_LDO2: | |
452 | return TPS65911_LDO2; | |
453 | case TPS65911_REG_LDO3: | |
454 | return TPS65911_LDO3; | |
455 | case TPS65911_REG_LDO4: | |
456 | return TPS65911_LDO4; | |
457 | case TPS65911_REG_LDO5: | |
458 | return TPS65911_LDO5; | |
459 | case TPS65911_REG_LDO6: | |
460 | return TPS65911_LDO6; | |
461 | case TPS65911_REG_LDO7: | |
462 | return TPS65911_LDO7; | |
463 | case TPS65911_REG_LDO8: | |
464 | return TPS65911_LDO8; | |
465 | default: | |
466 | return -EINVAL; | |
467 | } | |
468 | } | |
469 | ||
0651eed5 LD |
470 | static int tps65910_enable_time(struct regulator_dev *dev) |
471 | { | |
472 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
473 | int id = rdev_get_id(dev); | |
474 | return pmic->info[id]->enable_time_us; | |
475 | } | |
518fb721 GG |
476 | |
477 | static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) | |
478 | { | |
479 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
480 | struct tps65910 *mfd = pmic->mfd; | |
481 | int reg, value, id = rdev_get_id(dev); | |
a320e3c3 JEC |
482 | |
483 | reg = pmic->get_ctrl_reg(id); | |
518fb721 GG |
484 | if (reg < 0) |
485 | return reg; | |
486 | ||
487 | switch (mode) { | |
488 | case REGULATOR_MODE_NORMAL: | |
489 | return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT, | |
490 | LDO_ST_MODE_BIT); | |
491 | case REGULATOR_MODE_IDLE: | |
492 | value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; | |
493 | return tps65910_set_bits(mfd, reg, value); | |
494 | case REGULATOR_MODE_STANDBY: | |
495 | return tps65910_clear_bits(mfd, reg, LDO_ST_ON_BIT); | |
496 | } | |
497 | ||
498 | return -EINVAL; | |
499 | } | |
500 | ||
501 | static unsigned int tps65910_get_mode(struct regulator_dev *dev) | |
502 | { | |
503 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
504 | int reg, value, id = rdev_get_id(dev); | |
505 | ||
a320e3c3 | 506 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
507 | if (reg < 0) |
508 | return reg; | |
509 | ||
510 | value = tps65910_reg_read(pmic, reg); | |
511 | if (value < 0) | |
512 | return value; | |
513 | ||
58599393 | 514 | if (!(value & LDO_ST_ON_BIT)) |
518fb721 GG |
515 | return REGULATOR_MODE_STANDBY; |
516 | else if (value & LDO_ST_MODE_BIT) | |
517 | return REGULATOR_MODE_IDLE; | |
518 | else | |
519 | return REGULATOR_MODE_NORMAL; | |
520 | } | |
521 | ||
18039e0f | 522 | static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) |
518fb721 GG |
523 | { |
524 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
18039e0f | 525 | int id = rdev_get_id(dev); |
a320e3c3 | 526 | int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; |
518fb721 GG |
527 | |
528 | switch (id) { | |
529 | case TPS65910_REG_VDD1: | |
530 | opvsel = tps65910_reg_read(pmic, TPS65910_VDD1_OP); | |
531 | mult = tps65910_reg_read(pmic, TPS65910_VDD1); | |
532 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; | |
533 | srvsel = tps65910_reg_read(pmic, TPS65910_VDD1_SR); | |
534 | sr = opvsel & VDD1_OP_CMD_MASK; | |
535 | opvsel &= VDD1_OP_SEL_MASK; | |
536 | srvsel &= VDD1_SR_SEL_MASK; | |
a320e3c3 | 537 | vselmax = 75; |
518fb721 GG |
538 | break; |
539 | case TPS65910_REG_VDD2: | |
540 | opvsel = tps65910_reg_read(pmic, TPS65910_VDD2_OP); | |
541 | mult = tps65910_reg_read(pmic, TPS65910_VDD2); | |
542 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; | |
543 | srvsel = tps65910_reg_read(pmic, TPS65910_VDD2_SR); | |
544 | sr = opvsel & VDD2_OP_CMD_MASK; | |
545 | opvsel &= VDD2_OP_SEL_MASK; | |
546 | srvsel &= VDD2_SR_SEL_MASK; | |
a320e3c3 JEC |
547 | vselmax = 75; |
548 | break; | |
549 | case TPS65911_REG_VDDCTRL: | |
550 | opvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_OP); | |
551 | srvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_SR); | |
552 | sr = opvsel & VDDCTRL_OP_CMD_MASK; | |
553 | opvsel &= VDDCTRL_OP_SEL_MASK; | |
554 | srvsel &= VDDCTRL_SR_SEL_MASK; | |
555 | vselmax = 64; | |
518fb721 GG |
556 | break; |
557 | } | |
558 | ||
559 | /* multiplier 0 == 1 but 2,3 normal */ | |
560 | if (!mult) | |
561 | mult=1; | |
562 | ||
563 | if (sr) { | |
a320e3c3 JEC |
564 | /* normalise to valid range */ |
565 | if (srvsel < 3) | |
566 | srvsel = 3; | |
567 | if (srvsel > vselmax) | |
568 | srvsel = vselmax; | |
18039e0f | 569 | return srvsel - 3; |
518fb721 GG |
570 | } else { |
571 | ||
a320e3c3 JEC |
572 | /* normalise to valid range*/ |
573 | if (opvsel < 3) | |
574 | opvsel = 3; | |
575 | if (opvsel > vselmax) | |
576 | opvsel = vselmax; | |
18039e0f | 577 | return opvsel - 3; |
518fb721 | 578 | } |
18039e0f | 579 | return -EINVAL; |
518fb721 GG |
580 | } |
581 | ||
1f904fd1 | 582 | static int tps65910_get_voltage_sel(struct regulator_dev *dev) |
518fb721 GG |
583 | { |
584 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
1f904fd1 | 585 | int reg, value, id = rdev_get_id(dev); |
518fb721 | 586 | |
a320e3c3 | 587 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
588 | if (reg < 0) |
589 | return reg; | |
590 | ||
591 | value = tps65910_reg_read(pmic, reg); | |
592 | if (value < 0) | |
593 | return value; | |
594 | ||
595 | switch (id) { | |
596 | case TPS65910_REG_VIO: | |
597 | case TPS65910_REG_VDIG1: | |
598 | case TPS65910_REG_VDIG2: | |
599 | case TPS65910_REG_VPLL: | |
600 | case TPS65910_REG_VDAC: | |
601 | case TPS65910_REG_VAUX1: | |
602 | case TPS65910_REG_VAUX2: | |
603 | case TPS65910_REG_VAUX33: | |
604 | case TPS65910_REG_VMMC: | |
605 | value &= LDO_SEL_MASK; | |
606 | value >>= LDO_SEL_SHIFT; | |
607 | break; | |
608 | default: | |
609 | return -EINVAL; | |
610 | } | |
611 | ||
1f904fd1 | 612 | return value; |
518fb721 GG |
613 | } |
614 | ||
615 | static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) | |
616 | { | |
617 | return 5 * 1000 * 1000; | |
618 | } | |
619 | ||
1f904fd1 | 620 | static int tps65911_get_voltage_sel(struct regulator_dev *dev) |
a320e3c3 JEC |
621 | { |
622 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
1f904fd1 | 623 | int id = rdev_get_id(dev); |
a320e3c3 JEC |
624 | u8 value, reg; |
625 | ||
626 | reg = pmic->get_ctrl_reg(id); | |
627 | ||
628 | value = tps65910_reg_read(pmic, reg); | |
629 | ||
630 | switch (id) { | |
631 | case TPS65911_REG_LDO1: | |
632 | case TPS65911_REG_LDO2: | |
633 | case TPS65911_REG_LDO4: | |
634 | value &= LDO1_SEL_MASK; | |
635 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
636 | break; |
637 | case TPS65911_REG_LDO3: | |
638 | case TPS65911_REG_LDO5: | |
639 | case TPS65911_REG_LDO6: | |
640 | case TPS65911_REG_LDO7: | |
641 | case TPS65911_REG_LDO8: | |
642 | value &= LDO3_SEL_MASK; | |
643 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
644 | break; |
645 | case TPS65910_REG_VIO: | |
e882eae8 LD |
646 | value &= LDO_SEL_MASK; |
647 | value >>= LDO_SEL_SHIFT; | |
1f904fd1 | 648 | break; |
a320e3c3 JEC |
649 | default: |
650 | return -EINVAL; | |
651 | } | |
652 | ||
1f904fd1 | 653 | return value; |
a320e3c3 JEC |
654 | } |
655 | ||
94732b97 AL |
656 | static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, |
657 | unsigned selector) | |
518fb721 GG |
658 | { |
659 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
660 | int id = rdev_get_id(dev), vsel; | |
a320e3c3 | 661 | int dcdc_mult = 0; |
518fb721 | 662 | |
a320e3c3 JEC |
663 | switch (id) { |
664 | case TPS65910_REG_VDD1: | |
780dc9ba | 665 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
666 | if (dcdc_mult == 1) |
667 | dcdc_mult--; | |
780dc9ba | 668 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
518fb721 | 669 | |
518fb721 GG |
670 | tps65910_modify_bits(pmic, TPS65910_VDD1, |
671 | (dcdc_mult << VDD1_VGAIN_SEL_SHIFT), | |
672 | VDD1_VGAIN_SEL_MASK); | |
673 | tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel); | |
a320e3c3 JEC |
674 | break; |
675 | case TPS65910_REG_VDD2: | |
780dc9ba | 676 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
677 | if (dcdc_mult == 1) |
678 | dcdc_mult--; | |
780dc9ba | 679 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
a320e3c3 | 680 | |
518fb721 GG |
681 | tps65910_modify_bits(pmic, TPS65910_VDD2, |
682 | (dcdc_mult << VDD2_VGAIN_SEL_SHIFT), | |
683 | VDD1_VGAIN_SEL_MASK); | |
684 | tps65910_reg_write(pmic, TPS65910_VDD2_OP, vsel); | |
a320e3c3 JEC |
685 | break; |
686 | case TPS65911_REG_VDDCTRL: | |
c4632aed | 687 | vsel = selector + 3; |
a320e3c3 | 688 | tps65910_reg_write(pmic, TPS65911_VDDCTRL_OP, vsel); |
518fb721 GG |
689 | } |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
94732b97 AL |
694 | static int tps65910_set_voltage_sel(struct regulator_dev *dev, |
695 | unsigned selector) | |
518fb721 GG |
696 | { |
697 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
698 | int reg, id = rdev_get_id(dev); | |
699 | ||
a320e3c3 | 700 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
701 | if (reg < 0) |
702 | return reg; | |
703 | ||
704 | switch (id) { | |
705 | case TPS65910_REG_VIO: | |
706 | case TPS65910_REG_VDIG1: | |
707 | case TPS65910_REG_VDIG2: | |
708 | case TPS65910_REG_VPLL: | |
709 | case TPS65910_REG_VDAC: | |
710 | case TPS65910_REG_VAUX1: | |
711 | case TPS65910_REG_VAUX2: | |
712 | case TPS65910_REG_VAUX33: | |
713 | case TPS65910_REG_VMMC: | |
714 | return tps65910_modify_bits(pmic, reg, | |
715 | (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); | |
716 | } | |
717 | ||
718 | return -EINVAL; | |
719 | } | |
720 | ||
94732b97 AL |
721 | static int tps65911_set_voltage_sel(struct regulator_dev *dev, |
722 | unsigned selector) | |
a320e3c3 JEC |
723 | { |
724 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
725 | int reg, id = rdev_get_id(dev); | |
726 | ||
727 | reg = pmic->get_ctrl_reg(id); | |
728 | if (reg < 0) | |
729 | return reg; | |
730 | ||
731 | switch (id) { | |
732 | case TPS65911_REG_LDO1: | |
733 | case TPS65911_REG_LDO2: | |
734 | case TPS65911_REG_LDO4: | |
735 | return tps65910_modify_bits(pmic, reg, | |
736 | (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK); | |
737 | case TPS65911_REG_LDO3: | |
738 | case TPS65911_REG_LDO5: | |
739 | case TPS65911_REG_LDO6: | |
740 | case TPS65911_REG_LDO7: | |
741 | case TPS65911_REG_LDO8: | |
a320e3c3 JEC |
742 | return tps65910_modify_bits(pmic, reg, |
743 | (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK); | |
e882eae8 LD |
744 | case TPS65910_REG_VIO: |
745 | return tps65910_modify_bits(pmic, reg, | |
746 | (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); | |
a320e3c3 JEC |
747 | } |
748 | ||
749 | return -EINVAL; | |
750 | } | |
751 | ||
752 | ||
518fb721 GG |
753 | static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, |
754 | unsigned selector) | |
755 | { | |
a320e3c3 | 756 | int volt, mult = 1, id = rdev_get_id(dev); |
518fb721 | 757 | |
a320e3c3 JEC |
758 | switch (id) { |
759 | case TPS65910_REG_VDD1: | |
760 | case TPS65910_REG_VDD2: | |
780dc9ba | 761 | mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 | 762 | volt = VDD1_2_MIN_VOLT + |
780dc9ba | 763 | (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET; |
d04156bc | 764 | break; |
a320e3c3 JEC |
765 | case TPS65911_REG_VDDCTRL: |
766 | volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); | |
d04156bc AL |
767 | break; |
768 | default: | |
769 | BUG(); | |
770 | return -EINVAL; | |
a320e3c3 | 771 | } |
518fb721 GG |
772 | |
773 | return volt * 100 * mult; | |
774 | } | |
775 | ||
776 | static int tps65910_list_voltage(struct regulator_dev *dev, | |
777 | unsigned selector) | |
778 | { | |
779 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
780 | int id = rdev_get_id(dev), voltage; | |
781 | ||
782 | if (id < TPS65910_REG_VIO || id > TPS65910_REG_VMMC) | |
783 | return -EINVAL; | |
784 | ||
7d38a3cb | 785 | if (selector >= pmic->info[id]->n_voltages) |
518fb721 GG |
786 | return -EINVAL; |
787 | else | |
7d38a3cb | 788 | voltage = pmic->info[id]->voltage_table[selector] * 1000; |
518fb721 GG |
789 | |
790 | return voltage; | |
791 | } | |
792 | ||
a320e3c3 JEC |
793 | static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) |
794 | { | |
795 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
796 | int step_mv = 0, id = rdev_get_id(dev); | |
797 | ||
798 | switch(id) { | |
799 | case TPS65911_REG_LDO1: | |
800 | case TPS65911_REG_LDO2: | |
801 | case TPS65911_REG_LDO4: | |
802 | /* The first 5 values of the selector correspond to 1V */ | |
803 | if (selector < 5) | |
804 | selector = 0; | |
805 | else | |
806 | selector -= 4; | |
807 | ||
808 | step_mv = 50; | |
809 | break; | |
810 | case TPS65911_REG_LDO3: | |
811 | case TPS65911_REG_LDO5: | |
812 | case TPS65911_REG_LDO6: | |
813 | case TPS65911_REG_LDO7: | |
814 | case TPS65911_REG_LDO8: | |
815 | /* The first 3 values of the selector correspond to 1V */ | |
816 | if (selector < 3) | |
817 | selector = 0; | |
818 | else | |
819 | selector -= 2; | |
820 | ||
821 | step_mv = 100; | |
822 | break; | |
823 | case TPS65910_REG_VIO: | |
7d38a3cb | 824 | return pmic->info[id]->voltage_table[selector] * 1000; |
a320e3c3 JEC |
825 | default: |
826 | return -EINVAL; | |
827 | } | |
828 | ||
829 | return (LDO_MIN_VOLT + selector * step_mv) * 1000; | |
830 | } | |
831 | ||
18039e0f LD |
832 | static int tps65910_set_voltage_dcdc_time_sel(struct regulator_dev *dev, |
833 | unsigned int old_selector, unsigned int new_selector) | |
834 | { | |
835 | int id = rdev_get_id(dev); | |
836 | int old_volt, new_volt; | |
837 | ||
838 | old_volt = tps65910_list_voltage_dcdc(dev, old_selector); | |
839 | if (old_volt < 0) | |
840 | return old_volt; | |
841 | ||
842 | new_volt = tps65910_list_voltage_dcdc(dev, new_selector); | |
843 | if (new_volt < 0) | |
844 | return new_volt; | |
845 | ||
846 | /* VDD1 and VDD2 are 12.5mV/us, VDDCTRL is 100mV/20us */ | |
847 | switch (id) { | |
848 | case TPS65910_REG_VDD1: | |
849 | case TPS65910_REG_VDD2: | |
850 | return DIV_ROUND_UP(abs(old_volt - new_volt), 12500); | |
851 | case TPS65911_REG_VDDCTRL: | |
852 | return DIV_ROUND_UP(abs(old_volt - new_volt), 5000); | |
853 | } | |
854 | return -EINVAL; | |
855 | } | |
856 | ||
518fb721 GG |
857 | /* Regulator ops (except VRTC) */ |
858 | static struct regulator_ops tps65910_ops_dcdc = { | |
a40a9c43 AL |
859 | .is_enabled = regulator_is_enabled_regmap, |
860 | .enable = regulator_enable_regmap, | |
861 | .disable = regulator_disable_regmap, | |
0651eed5 | 862 | .enable_time = tps65910_enable_time, |
518fb721 GG |
863 | .set_mode = tps65910_set_mode, |
864 | .get_mode = tps65910_get_mode, | |
18039e0f | 865 | .get_voltage_sel = tps65910_get_voltage_dcdc_sel, |
94732b97 | 866 | .set_voltage_sel = tps65910_set_voltage_dcdc_sel, |
18039e0f | 867 | .set_voltage_time_sel = tps65910_set_voltage_dcdc_time_sel, |
518fb721 GG |
868 | .list_voltage = tps65910_list_voltage_dcdc, |
869 | }; | |
870 | ||
871 | static struct regulator_ops tps65910_ops_vdd3 = { | |
a40a9c43 AL |
872 | .is_enabled = regulator_is_enabled_regmap, |
873 | .enable = regulator_enable_regmap, | |
874 | .disable = regulator_disable_regmap, | |
0651eed5 | 875 | .enable_time = tps65910_enable_time, |
518fb721 GG |
876 | .set_mode = tps65910_set_mode, |
877 | .get_mode = tps65910_get_mode, | |
878 | .get_voltage = tps65910_get_voltage_vdd3, | |
879 | .list_voltage = tps65910_list_voltage, | |
880 | }; | |
881 | ||
882 | static struct regulator_ops tps65910_ops = { | |
a40a9c43 AL |
883 | .is_enabled = regulator_is_enabled_regmap, |
884 | .enable = regulator_enable_regmap, | |
885 | .disable = regulator_disable_regmap, | |
0651eed5 | 886 | .enable_time = tps65910_enable_time, |
518fb721 GG |
887 | .set_mode = tps65910_set_mode, |
888 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 889 | .get_voltage_sel = tps65910_get_voltage_sel, |
94732b97 | 890 | .set_voltage_sel = tps65910_set_voltage_sel, |
518fb721 GG |
891 | .list_voltage = tps65910_list_voltage, |
892 | }; | |
893 | ||
a320e3c3 | 894 | static struct regulator_ops tps65911_ops = { |
a40a9c43 AL |
895 | .is_enabled = regulator_is_enabled_regmap, |
896 | .enable = regulator_enable_regmap, | |
897 | .disable = regulator_disable_regmap, | |
0651eed5 | 898 | .enable_time = tps65910_enable_time, |
a320e3c3 JEC |
899 | .set_mode = tps65910_set_mode, |
900 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 901 | .get_voltage_sel = tps65911_get_voltage_sel, |
94732b97 | 902 | .set_voltage_sel = tps65911_set_voltage_sel, |
a320e3c3 JEC |
903 | .list_voltage = tps65911_list_voltage, |
904 | }; | |
905 | ||
1e0c66f4 LD |
906 | static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, |
907 | int id, int ext_sleep_config) | |
908 | { | |
909 | struct tps65910 *mfd = pmic->mfd; | |
910 | u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF; | |
911 | u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF); | |
912 | int ret; | |
913 | ||
914 | /* | |
915 | * Regulator can not be control from multiple external input EN1, EN2 | |
916 | * and EN3 together. | |
917 | */ | |
918 | if (ext_sleep_config & EXT_SLEEP_CONTROL) { | |
919 | int en_count; | |
920 | en_count = ((ext_sleep_config & | |
921 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0); | |
922 | en_count += ((ext_sleep_config & | |
923 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0); | |
924 | en_count += ((ext_sleep_config & | |
925 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0); | |
f30b0716 LD |
926 | en_count += ((ext_sleep_config & |
927 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0); | |
1e0c66f4 LD |
928 | if (en_count > 1) { |
929 | dev_err(mfd->dev, | |
930 | "External sleep control flag is not proper\n"); | |
931 | return -EINVAL; | |
932 | } | |
933 | } | |
934 | ||
935 | pmic->board_ext_control[id] = ext_sleep_config; | |
936 | ||
937 | /* External EN1 control */ | |
938 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) | |
939 | ret = tps65910_set_bits(mfd, | |
940 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); | |
941 | else | |
942 | ret = tps65910_clear_bits(mfd, | |
943 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); | |
944 | if (ret < 0) { | |
945 | dev_err(mfd->dev, | |
946 | "Error in configuring external control EN1\n"); | |
947 | return ret; | |
948 | } | |
949 | ||
950 | /* External EN2 control */ | |
951 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) | |
952 | ret = tps65910_set_bits(mfd, | |
953 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); | |
954 | else | |
955 | ret = tps65910_clear_bits(mfd, | |
956 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); | |
957 | if (ret < 0) { | |
958 | dev_err(mfd->dev, | |
959 | "Error in configuring external control EN2\n"); | |
960 | return ret; | |
961 | } | |
962 | ||
963 | /* External EN3 control for TPS65910 LDO only */ | |
964 | if ((tps65910_chip_id(mfd) == TPS65910) && | |
965 | (id >= TPS65910_REG_VDIG1)) { | |
966 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) | |
967 | ret = tps65910_set_bits(mfd, | |
968 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); | |
969 | else | |
970 | ret = tps65910_clear_bits(mfd, | |
971 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); | |
972 | if (ret < 0) { | |
973 | dev_err(mfd->dev, | |
974 | "Error in configuring external control EN3\n"); | |
975 | return ret; | |
976 | } | |
977 | } | |
978 | ||
979 | /* Return if no external control is selected */ | |
980 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { | |
981 | /* Clear all sleep controls */ | |
982 | ret = tps65910_clear_bits(mfd, | |
983 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); | |
984 | if (!ret) | |
985 | ret = tps65910_clear_bits(mfd, | |
986 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); | |
987 | if (ret < 0) | |
988 | dev_err(mfd->dev, | |
989 | "Error in configuring SLEEP register\n"); | |
990 | return ret; | |
991 | } | |
992 | ||
993 | /* | |
994 | * For regulator that has separate operational and sleep register make | |
995 | * sure that operational is used and clear sleep register to turn | |
996 | * regulator off when external control is inactive | |
997 | */ | |
998 | if ((id == TPS65910_REG_VDD1) || | |
999 | (id == TPS65910_REG_VDD2) || | |
1000 | ((id == TPS65911_REG_VDDCTRL) && | |
1001 | (tps65910_chip_id(mfd) == TPS65911))) { | |
1002 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; | |
1003 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; | |
1004 | int opvsel = tps65910_reg_read(pmic, op_reg_add); | |
1005 | int srvsel = tps65910_reg_read(pmic, sr_reg_add); | |
1006 | if (opvsel & VDD1_OP_CMD_MASK) { | |
1007 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; | |
1008 | ret = tps65910_reg_write(pmic, op_reg_add, reg_val); | |
1009 | if (ret < 0) { | |
1010 | dev_err(mfd->dev, | |
1011 | "Error in configuring op register\n"); | |
1012 | return ret; | |
1013 | } | |
1014 | } | |
1015 | ret = tps65910_reg_write(pmic, sr_reg_add, 0); | |
1016 | if (ret < 0) { | |
1017 | dev_err(mfd->dev, "Error in settting sr register\n"); | |
1018 | return ret; | |
1019 | } | |
1020 | } | |
1021 | ||
1022 | ret = tps65910_clear_bits(mfd, | |
1023 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); | |
f30b0716 LD |
1024 | if (!ret) { |
1025 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
1026 | ret = tps65910_set_bits(mfd, | |
1027 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); | |
1028 | else | |
1029 | ret = tps65910_clear_bits(mfd, | |
1030 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); | |
1031 | } | |
1e0c66f4 LD |
1032 | if (ret < 0) |
1033 | dev_err(mfd->dev, | |
1034 | "Error in configuring SLEEP register\n"); | |
f30b0716 | 1035 | |
1e0c66f4 LD |
1036 | return ret; |
1037 | } | |
1038 | ||
6790178f RK |
1039 | #ifdef CONFIG_OF |
1040 | ||
1041 | static struct of_regulator_match tps65910_matches[] = { | |
33a6943d LD |
1042 | { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] }, |
1043 | { .name = "vio", .driver_data = (void *) &tps65910_regs[1] }, | |
1044 | { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] }, | |
1045 | { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] }, | |
1046 | { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] }, | |
1047 | { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] }, | |
1048 | { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] }, | |
1049 | { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] }, | |
1050 | { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] }, | |
1051 | { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] }, | |
1052 | { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] }, | |
1053 | { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] }, | |
1054 | { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] }, | |
6790178f RK |
1055 | }; |
1056 | ||
1057 | static struct of_regulator_match tps65911_matches[] = { | |
33a6943d LD |
1058 | { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] }, |
1059 | { .name = "vio", .driver_data = (void *) &tps65911_regs[1] }, | |
1060 | { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] }, | |
1061 | { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] }, | |
1062 | { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] }, | |
1063 | { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] }, | |
1064 | { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] }, | |
1065 | { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] }, | |
1066 | { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] }, | |
1067 | { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] }, | |
1068 | { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] }, | |
1069 | { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] }, | |
1070 | { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] }, | |
6790178f RK |
1071 | }; |
1072 | ||
1073 | static struct tps65910_board *tps65910_parse_dt_reg_data( | |
1074 | struct platform_device *pdev) | |
1075 | { | |
1076 | struct tps65910_board *pmic_plat_data; | |
1077 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
1078 | struct device_node *np = pdev->dev.parent->of_node; | |
1079 | struct device_node *regulators; | |
1080 | struct of_regulator_match *matches; | |
1081 | unsigned int prop; | |
1082 | int idx = 0, ret, count; | |
1083 | ||
1084 | pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data), | |
1085 | GFP_KERNEL); | |
1086 | ||
1087 | if (!pmic_plat_data) { | |
1088 | dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n"); | |
1089 | return NULL; | |
1090 | } | |
1091 | ||
1092 | regulators = of_find_node_by_name(np, "regulators"); | |
1093 | ||
1094 | switch (tps65910_chip_id(tps65910)) { | |
1095 | case TPS65910: | |
1096 | count = ARRAY_SIZE(tps65910_matches); | |
1097 | matches = tps65910_matches; | |
1098 | break; | |
1099 | case TPS65911: | |
1100 | count = ARRAY_SIZE(tps65911_matches); | |
1101 | matches = tps65911_matches; | |
1102 | break; | |
1103 | default: | |
1104 | pr_err("Invalid tps chip version\n"); | |
1105 | return NULL; | |
1106 | } | |
1107 | ||
1108 | ret = of_regulator_match(pdev->dev.parent, regulators, matches, count); | |
1109 | if (ret < 0) { | |
1110 | dev_err(&pdev->dev, "Error parsing regulator init data: %d\n", | |
1111 | ret); | |
1112 | return NULL; | |
1113 | } | |
1114 | ||
1115 | for (idx = 0; idx < count; idx++) { | |
1116 | if (!matches[idx].init_data || !matches[idx].of_node) | |
1117 | continue; | |
1118 | ||
1119 | pmic_plat_data->tps65910_pmic_init_data[idx] = | |
1120 | matches[idx].init_data; | |
1121 | ||
1122 | ret = of_property_read_u32(matches[idx].of_node, | |
1123 | "ti,regulator-ext-sleep-control", &prop); | |
1124 | if (!ret) | |
1125 | pmic_plat_data->regulator_ext_sleep_control[idx] = prop; | |
1126 | } | |
1127 | ||
1128 | return pmic_plat_data; | |
1129 | } | |
1130 | #else | |
1131 | static inline struct tps65910_board *tps65910_parse_dt_reg_data( | |
1132 | struct platform_device *pdev) | |
1133 | { | |
1134 | return 0; | |
1135 | } | |
1136 | #endif | |
1137 | ||
518fb721 GG |
1138 | static __devinit int tps65910_probe(struct platform_device *pdev) |
1139 | { | |
1140 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c172708d | 1141 | struct regulator_config config = { }; |
a320e3c3 | 1142 | struct tps_info *info; |
518fb721 GG |
1143 | struct regulator_init_data *reg_data; |
1144 | struct regulator_dev *rdev; | |
1145 | struct tps65910_reg *pmic; | |
1146 | struct tps65910_board *pmic_plat_data; | |
518fb721 GG |
1147 | int i, err; |
1148 | ||
1149 | pmic_plat_data = dev_get_platdata(tps65910->dev); | |
6790178f RK |
1150 | if (!pmic_plat_data && tps65910->dev->of_node) |
1151 | pmic_plat_data = tps65910_parse_dt_reg_data(pdev); | |
1152 | ||
518fb721 GG |
1153 | if (!pmic_plat_data) |
1154 | return -EINVAL; | |
1155 | ||
9eb0c421 | 1156 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); |
518fb721 GG |
1157 | if (!pmic) |
1158 | return -ENOMEM; | |
1159 | ||
1160 | mutex_init(&pmic->mutex); | |
1161 | pmic->mfd = tps65910; | |
1162 | platform_set_drvdata(pdev, pmic); | |
1163 | ||
1164 | /* Give control of all register to control port */ | |
1165 | tps65910_set_bits(pmic->mfd, TPS65910_DEVCTRL, | |
1166 | DEVCTRL_SR_CTL_I2C_SEL_MASK); | |
1167 | ||
a320e3c3 JEC |
1168 | switch(tps65910_chip_id(tps65910)) { |
1169 | case TPS65910: | |
1170 | pmic->get_ctrl_reg = &tps65910_get_ctrl_register; | |
39aa9b6e | 1171 | pmic->num_regulators = ARRAY_SIZE(tps65910_regs); |
1e0c66f4 | 1172 | pmic->ext_sleep_control = tps65910_ext_sleep_control; |
a320e3c3 | 1173 | info = tps65910_regs; |
d04156bc | 1174 | break; |
a320e3c3 JEC |
1175 | case TPS65911: |
1176 | pmic->get_ctrl_reg = &tps65911_get_ctrl_register; | |
39aa9b6e | 1177 | pmic->num_regulators = ARRAY_SIZE(tps65911_regs); |
1e0c66f4 | 1178 | pmic->ext_sleep_control = tps65911_ext_sleep_control; |
a320e3c3 | 1179 | info = tps65911_regs; |
d04156bc | 1180 | break; |
a320e3c3 JEC |
1181 | default: |
1182 | pr_err("Invalid tps chip version\n"); | |
1183 | return -ENODEV; | |
1184 | } | |
1185 | ||
39aa9b6e AL |
1186 | pmic->desc = kcalloc(pmic->num_regulators, |
1187 | sizeof(struct regulator_desc), GFP_KERNEL); | |
1188 | if (!pmic->desc) { | |
1189 | err = -ENOMEM; | |
9eb0c421 | 1190 | goto err_out; |
39aa9b6e AL |
1191 | } |
1192 | ||
1193 | pmic->info = kcalloc(pmic->num_regulators, | |
1194 | sizeof(struct tps_info *), GFP_KERNEL); | |
1195 | if (!pmic->info) { | |
1196 | err = -ENOMEM; | |
1197 | goto err_free_desc; | |
1198 | } | |
1199 | ||
1200 | pmic->rdev = kcalloc(pmic->num_regulators, | |
1201 | sizeof(struct regulator_dev *), GFP_KERNEL); | |
1202 | if (!pmic->rdev) { | |
1203 | err = -ENOMEM; | |
1204 | goto err_free_info; | |
1205 | } | |
1206 | ||
c1fc1480 KM |
1207 | for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS; |
1208 | i++, info++) { | |
1209 | ||
1210 | reg_data = pmic_plat_data->tps65910_pmic_init_data[i]; | |
1211 | ||
1212 | /* Regulator API handles empty constraints but not NULL | |
1213 | * constraints */ | |
1214 | if (!reg_data) | |
1215 | continue; | |
1216 | ||
518fb721 GG |
1217 | /* Register the regulators */ |
1218 | pmic->info[i] = info; | |
1219 | ||
1220 | pmic->desc[i].name = info->name; | |
77fa44d0 | 1221 | pmic->desc[i].id = i; |
7d38a3cb | 1222 | pmic->desc[i].n_voltages = info->n_voltages; |
518fb721 | 1223 | |
a320e3c3 | 1224 | if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { |
518fb721 | 1225 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
780dc9ba AM |
1226 | pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE * |
1227 | VDD1_2_NUM_VOLT_COARSE; | |
a320e3c3 JEC |
1228 | } else if (i == TPS65910_REG_VDD3) { |
1229 | if (tps65910_chip_id(tps65910) == TPS65910) | |
1230 | pmic->desc[i].ops = &tps65910_ops_vdd3; | |
1231 | else | |
1232 | pmic->desc[i].ops = &tps65910_ops_dcdc; | |
1233 | } else { | |
1234 | if (tps65910_chip_id(tps65910) == TPS65910) | |
1235 | pmic->desc[i].ops = &tps65910_ops; | |
1236 | else | |
1237 | pmic->desc[i].ops = &tps65911_ops; | |
1238 | } | |
518fb721 | 1239 | |
1e0c66f4 LD |
1240 | err = tps65910_set_ext_sleep_config(pmic, i, |
1241 | pmic_plat_data->regulator_ext_sleep_control[i]); | |
1242 | /* | |
1243 | * Failing on regulator for configuring externally control | |
1244 | * is not a serious issue, just throw warning. | |
1245 | */ | |
1246 | if (err < 0) | |
1247 | dev_warn(tps65910->dev, | |
1248 | "Failed to initialise ext control config\n"); | |
1249 | ||
518fb721 GG |
1250 | pmic->desc[i].type = REGULATOR_VOLTAGE; |
1251 | pmic->desc[i].owner = THIS_MODULE; | |
a40a9c43 AL |
1252 | pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); |
1253 | pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; | |
518fb721 | 1254 | |
c172708d MB |
1255 | config.dev = tps65910->dev; |
1256 | config.init_data = reg_data; | |
1257 | config.driver_data = pmic; | |
a40a9c43 | 1258 | config.regmap = tps65910->regmap; |
c172708d | 1259 | |
6790178f RK |
1260 | #ifdef CONFIG_OF |
1261 | config.of_node = of_find_node_by_name(tps65910->dev->of_node, | |
1262 | info->name); | |
1263 | #endif | |
1264 | ||
c172708d | 1265 | rdev = regulator_register(&pmic->desc[i], &config); |
518fb721 GG |
1266 | if (IS_ERR(rdev)) { |
1267 | dev_err(tps65910->dev, | |
1268 | "failed to register %s regulator\n", | |
1269 | pdev->name); | |
1270 | err = PTR_ERR(rdev); | |
39aa9b6e | 1271 | goto err_unregister_regulator; |
518fb721 GG |
1272 | } |
1273 | ||
1274 | /* Save regulator for cleanup */ | |
1275 | pmic->rdev[i] = rdev; | |
1276 | } | |
1277 | return 0; | |
1278 | ||
39aa9b6e | 1279 | err_unregister_regulator: |
518fb721 GG |
1280 | while (--i >= 0) |
1281 | regulator_unregister(pmic->rdev[i]); | |
39aa9b6e AL |
1282 | kfree(pmic->rdev); |
1283 | err_free_info: | |
1284 | kfree(pmic->info); | |
1285 | err_free_desc: | |
1286 | kfree(pmic->desc); | |
9eb0c421 | 1287 | err_out: |
518fb721 GG |
1288 | return err; |
1289 | } | |
1290 | ||
1291 | static int __devexit tps65910_remove(struct platform_device *pdev) | |
1292 | { | |
39aa9b6e | 1293 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); |
518fb721 GG |
1294 | int i; |
1295 | ||
39aa9b6e AL |
1296 | for (i = 0; i < pmic->num_regulators; i++) |
1297 | regulator_unregister(pmic->rdev[i]); | |
518fb721 | 1298 | |
39aa9b6e AL |
1299 | kfree(pmic->rdev); |
1300 | kfree(pmic->info); | |
1301 | kfree(pmic->desc); | |
518fb721 GG |
1302 | return 0; |
1303 | } | |
1304 | ||
1e0c66f4 LD |
1305 | static void tps65910_shutdown(struct platform_device *pdev) |
1306 | { | |
1307 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); | |
1308 | int i; | |
1309 | ||
1310 | /* | |
1311 | * Before bootloader jumps to kernel, it makes sure that required | |
1312 | * external control signals are in desired state so that given rails | |
1313 | * can be configure accordingly. | |
1314 | * If rails are configured to be controlled from external control | |
1315 | * then before shutting down/rebooting the system, the external | |
1316 | * control configuration need to be remove from the rails so that | |
1317 | * its output will be available as per register programming even | |
1318 | * if external controls are removed. This is require when the POR | |
1319 | * value of the control signals are not in active state and before | |
1320 | * bootloader initializes it, the system requires the rail output | |
1321 | * to be active for booting. | |
1322 | */ | |
1323 | for (i = 0; i < pmic->num_regulators; i++) { | |
1324 | int err; | |
1325 | if (!pmic->rdev[i]) | |
1326 | continue; | |
1327 | ||
1328 | err = tps65910_set_ext_sleep_config(pmic, i, 0); | |
1329 | if (err < 0) | |
1330 | dev_err(&pdev->dev, | |
1331 | "Error in clearing external control\n"); | |
1332 | } | |
1333 | } | |
1334 | ||
518fb721 GG |
1335 | static struct platform_driver tps65910_driver = { |
1336 | .driver = { | |
1337 | .name = "tps65910-pmic", | |
1338 | .owner = THIS_MODULE, | |
1339 | }, | |
1340 | .probe = tps65910_probe, | |
1341 | .remove = __devexit_p(tps65910_remove), | |
1e0c66f4 | 1342 | .shutdown = tps65910_shutdown, |
518fb721 GG |
1343 | }; |
1344 | ||
1345 | static int __init tps65910_init(void) | |
1346 | { | |
1347 | return platform_driver_register(&tps65910_driver); | |
1348 | } | |
1349 | subsys_initcall(tps65910_init); | |
1350 | ||
1351 | static void __exit tps65910_cleanup(void) | |
1352 | { | |
1353 | platform_driver_unregister(&tps65910_driver); | |
1354 | } | |
1355 | module_exit(tps65910_cleanup); | |
1356 | ||
1357 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
ae0e6544 | 1358 | MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver"); |
518fb721 GG |
1359 | MODULE_LICENSE("GPL v2"); |
1360 | MODULE_ALIAS("platform:tps65910-pmic"); |