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518fb721 GG |
1 | /* |
2 | * tps65910.c -- TI tps65910 | |
3 | * | |
4 | * Copyright 2010 Texas Instruments Inc. | |
5 | * | |
6 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
7 | * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
518fb721 GG |
23 | #include <linux/slab.h> |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mfd/tps65910.h> | |
6790178f | 26 | #include <linux/regulator/of_regulator.h> |
518fb721 | 27 | |
518fb721 | 28 | #define TPS65910_SUPPLY_STATE_ENABLED 0x1 |
1e0c66f4 LD |
29 | #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \ |
30 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \ | |
f30b0716 LD |
31 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \ |
32 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
518fb721 | 33 | |
91fe4d50 | 34 | /* supported VIO voltages in millivolts */ |
518fb721 GG |
35 | static const u16 VIO_VSEL_table[] = { |
36 | 1500, 1800, 2500, 3300, | |
37 | }; | |
38 | ||
a320e3c3 JEC |
39 | /* VSEL tables for TPS65910 specific LDOs and dcdc's */ |
40 | ||
91fe4d50 | 41 | /* supported VDD3 voltages in millivolts */ |
518fb721 GG |
42 | static const u16 VDD3_VSEL_table[] = { |
43 | 5000, | |
44 | }; | |
45 | ||
91fe4d50 | 46 | /* supported VDIG1 voltages in millivolts */ |
518fb721 GG |
47 | static const u16 VDIG1_VSEL_table[] = { |
48 | 1200, 1500, 1800, 2700, | |
49 | }; | |
50 | ||
91fe4d50 | 51 | /* supported VDIG2 voltages in millivolts */ |
518fb721 GG |
52 | static const u16 VDIG2_VSEL_table[] = { |
53 | 1000, 1100, 1200, 1800, | |
54 | }; | |
55 | ||
91fe4d50 | 56 | /* supported VPLL voltages in millivolts */ |
518fb721 GG |
57 | static const u16 VPLL_VSEL_table[] = { |
58 | 1000, 1100, 1800, 2500, | |
59 | }; | |
60 | ||
91fe4d50 | 61 | /* supported VDAC voltages in millivolts */ |
518fb721 GG |
62 | static const u16 VDAC_VSEL_table[] = { |
63 | 1800, 2600, 2800, 2850, | |
64 | }; | |
65 | ||
91fe4d50 | 66 | /* supported VAUX1 voltages in millivolts */ |
518fb721 GG |
67 | static const u16 VAUX1_VSEL_table[] = { |
68 | 1800, 2500, 2800, 2850, | |
69 | }; | |
70 | ||
91fe4d50 | 71 | /* supported VAUX2 voltages in millivolts */ |
518fb721 GG |
72 | static const u16 VAUX2_VSEL_table[] = { |
73 | 1800, 2800, 2900, 3300, | |
74 | }; | |
75 | ||
91fe4d50 | 76 | /* supported VAUX33 voltages in millivolts */ |
518fb721 GG |
77 | static const u16 VAUX33_VSEL_table[] = { |
78 | 1800, 2000, 2800, 3300, | |
79 | }; | |
80 | ||
91fe4d50 | 81 | /* supported VMMC voltages in millivolts */ |
518fb721 GG |
82 | static const u16 VMMC_VSEL_table[] = { |
83 | 1800, 2800, 3000, 3300, | |
84 | }; | |
85 | ||
86 | struct tps_info { | |
87 | const char *name; | |
88 | unsigned min_uV; | |
89 | unsigned max_uV; | |
7d38a3cb LD |
90 | u8 n_voltages; |
91 | const u16 *voltage_table; | |
0651eed5 | 92 | int enable_time_us; |
518fb721 GG |
93 | }; |
94 | ||
95 | static struct tps_info tps65910_regs[] = { | |
96 | { | |
33a6943d | 97 | .name = "vrtc", |
0651eed5 | 98 | .enable_time_us = 2200, |
518fb721 GG |
99 | }, |
100 | { | |
33a6943d | 101 | .name = "vio", |
518fb721 GG |
102 | .min_uV = 1500000, |
103 | .max_uV = 3300000, | |
7d38a3cb LD |
104 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
105 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 106 | .enable_time_us = 350, |
518fb721 GG |
107 | }, |
108 | { | |
33a6943d | 109 | .name = "vdd1", |
518fb721 GG |
110 | .min_uV = 600000, |
111 | .max_uV = 4500000, | |
0651eed5 | 112 | .enable_time_us = 350, |
518fb721 GG |
113 | }, |
114 | { | |
33a6943d | 115 | .name = "vdd2", |
518fb721 GG |
116 | .min_uV = 600000, |
117 | .max_uV = 4500000, | |
0651eed5 | 118 | .enable_time_us = 350, |
518fb721 GG |
119 | }, |
120 | { | |
33a6943d | 121 | .name = "vdd3", |
518fb721 GG |
122 | .min_uV = 5000000, |
123 | .max_uV = 5000000, | |
7d38a3cb LD |
124 | .n_voltages = ARRAY_SIZE(VDD3_VSEL_table), |
125 | .voltage_table = VDD3_VSEL_table, | |
0651eed5 | 126 | .enable_time_us = 200, |
518fb721 GG |
127 | }, |
128 | { | |
33a6943d | 129 | .name = "vdig1", |
518fb721 GG |
130 | .min_uV = 1200000, |
131 | .max_uV = 2700000, | |
7d38a3cb LD |
132 | .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table), |
133 | .voltage_table = VDIG1_VSEL_table, | |
0651eed5 | 134 | .enable_time_us = 100, |
518fb721 GG |
135 | }, |
136 | { | |
33a6943d | 137 | .name = "vdig2", |
518fb721 GG |
138 | .min_uV = 1000000, |
139 | .max_uV = 1800000, | |
7d38a3cb LD |
140 | .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table), |
141 | .voltage_table = VDIG2_VSEL_table, | |
0651eed5 | 142 | .enable_time_us = 100, |
518fb721 GG |
143 | }, |
144 | { | |
33a6943d | 145 | .name = "vpll", |
518fb721 GG |
146 | .min_uV = 1000000, |
147 | .max_uV = 2500000, | |
7d38a3cb LD |
148 | .n_voltages = ARRAY_SIZE(VPLL_VSEL_table), |
149 | .voltage_table = VPLL_VSEL_table, | |
0651eed5 | 150 | .enable_time_us = 100, |
518fb721 GG |
151 | }, |
152 | { | |
33a6943d | 153 | .name = "vdac", |
518fb721 GG |
154 | .min_uV = 1800000, |
155 | .max_uV = 2850000, | |
7d38a3cb LD |
156 | .n_voltages = ARRAY_SIZE(VDAC_VSEL_table), |
157 | .voltage_table = VDAC_VSEL_table, | |
0651eed5 | 158 | .enable_time_us = 100, |
518fb721 GG |
159 | }, |
160 | { | |
33a6943d | 161 | .name = "vaux1", |
518fb721 GG |
162 | .min_uV = 1800000, |
163 | .max_uV = 2850000, | |
7d38a3cb LD |
164 | .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table), |
165 | .voltage_table = VAUX1_VSEL_table, | |
0651eed5 | 166 | .enable_time_us = 100, |
518fb721 GG |
167 | }, |
168 | { | |
33a6943d | 169 | .name = "vaux2", |
518fb721 GG |
170 | .min_uV = 1800000, |
171 | .max_uV = 3300000, | |
7d38a3cb LD |
172 | .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table), |
173 | .voltage_table = VAUX2_VSEL_table, | |
0651eed5 | 174 | .enable_time_us = 100, |
518fb721 GG |
175 | }, |
176 | { | |
33a6943d | 177 | .name = "vaux33", |
518fb721 GG |
178 | .min_uV = 1800000, |
179 | .max_uV = 3300000, | |
7d38a3cb LD |
180 | .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table), |
181 | .voltage_table = VAUX33_VSEL_table, | |
0651eed5 | 182 | .enable_time_us = 100, |
518fb721 GG |
183 | }, |
184 | { | |
33a6943d | 185 | .name = "vmmc", |
518fb721 GG |
186 | .min_uV = 1800000, |
187 | .max_uV = 3300000, | |
7d38a3cb LD |
188 | .n_voltages = ARRAY_SIZE(VMMC_VSEL_table), |
189 | .voltage_table = VMMC_VSEL_table, | |
0651eed5 | 190 | .enable_time_us = 100, |
518fb721 GG |
191 | }, |
192 | }; | |
193 | ||
a320e3c3 | 194 | static struct tps_info tps65911_regs[] = { |
c2f8efd7 | 195 | { |
33a6943d | 196 | .name = "vrtc", |
0651eed5 | 197 | .enable_time_us = 2200, |
c2f8efd7 | 198 | }, |
a320e3c3 | 199 | { |
33a6943d | 200 | .name = "vio", |
a320e3c3 JEC |
201 | .min_uV = 1500000, |
202 | .max_uV = 3300000, | |
7d38a3cb LD |
203 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
204 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 205 | .enable_time_us = 350, |
a320e3c3 JEC |
206 | }, |
207 | { | |
33a6943d | 208 | .name = "vdd1", |
a320e3c3 JEC |
209 | .min_uV = 600000, |
210 | .max_uV = 4500000, | |
7d38a3cb | 211 | .n_voltages = 73, |
0651eed5 | 212 | .enable_time_us = 350, |
a320e3c3 JEC |
213 | }, |
214 | { | |
33a6943d | 215 | .name = "vdd2", |
a320e3c3 JEC |
216 | .min_uV = 600000, |
217 | .max_uV = 4500000, | |
7d38a3cb | 218 | .n_voltages = 73, |
0651eed5 | 219 | .enable_time_us = 350, |
a320e3c3 JEC |
220 | }, |
221 | { | |
33a6943d | 222 | .name = "vddctrl", |
a320e3c3 JEC |
223 | .min_uV = 600000, |
224 | .max_uV = 1400000, | |
7d38a3cb | 225 | .n_voltages = 65, |
0651eed5 | 226 | .enable_time_us = 900, |
a320e3c3 JEC |
227 | }, |
228 | { | |
33a6943d | 229 | .name = "ldo1", |
a320e3c3 JEC |
230 | .min_uV = 1000000, |
231 | .max_uV = 3300000, | |
7d38a3cb | 232 | .n_voltages = 47, |
0651eed5 | 233 | .enable_time_us = 420, |
a320e3c3 JEC |
234 | }, |
235 | { | |
33a6943d | 236 | .name = "ldo2", |
a320e3c3 JEC |
237 | .min_uV = 1000000, |
238 | .max_uV = 3300000, | |
7d38a3cb | 239 | .n_voltages = 47, |
0651eed5 | 240 | .enable_time_us = 420, |
a320e3c3 JEC |
241 | }, |
242 | { | |
33a6943d | 243 | .name = "ldo3", |
a320e3c3 JEC |
244 | .min_uV = 1000000, |
245 | .max_uV = 3300000, | |
7d38a3cb | 246 | .n_voltages = 24, |
0651eed5 | 247 | .enable_time_us = 230, |
a320e3c3 JEC |
248 | }, |
249 | { | |
33a6943d | 250 | .name = "ldo4", |
a320e3c3 JEC |
251 | .min_uV = 1000000, |
252 | .max_uV = 3300000, | |
7d38a3cb | 253 | .n_voltages = 47, |
0651eed5 | 254 | .enable_time_us = 230, |
a320e3c3 JEC |
255 | }, |
256 | { | |
33a6943d | 257 | .name = "ldo5", |
a320e3c3 JEC |
258 | .min_uV = 1000000, |
259 | .max_uV = 3300000, | |
7d38a3cb | 260 | .n_voltages = 24, |
0651eed5 | 261 | .enable_time_us = 230, |
a320e3c3 JEC |
262 | }, |
263 | { | |
33a6943d | 264 | .name = "ldo6", |
a320e3c3 JEC |
265 | .min_uV = 1000000, |
266 | .max_uV = 3300000, | |
7d38a3cb | 267 | .n_voltages = 24, |
0651eed5 | 268 | .enable_time_us = 230, |
a320e3c3 JEC |
269 | }, |
270 | { | |
33a6943d | 271 | .name = "ldo7", |
a320e3c3 JEC |
272 | .min_uV = 1000000, |
273 | .max_uV = 3300000, | |
7d38a3cb | 274 | .n_voltages = 24, |
0651eed5 | 275 | .enable_time_us = 230, |
a320e3c3 JEC |
276 | }, |
277 | { | |
33a6943d | 278 | .name = "ldo8", |
a320e3c3 JEC |
279 | .min_uV = 1000000, |
280 | .max_uV = 3300000, | |
7d38a3cb | 281 | .n_voltages = 24, |
0651eed5 | 282 | .enable_time_us = 230, |
a320e3c3 JEC |
283 | }, |
284 | }; | |
285 | ||
1e0c66f4 LD |
286 | #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) |
287 | static unsigned int tps65910_ext_sleep_control[] = { | |
288 | 0, | |
289 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
290 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
291 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
292 | EXT_CONTROL_REG_BITS(VDD3, 1, 3), | |
293 | EXT_CONTROL_REG_BITS(VDIG1, 0, 1), | |
294 | EXT_CONTROL_REG_BITS(VDIG2, 0, 2), | |
295 | EXT_CONTROL_REG_BITS(VPLL, 0, 6), | |
296 | EXT_CONTROL_REG_BITS(VDAC, 0, 7), | |
297 | EXT_CONTROL_REG_BITS(VAUX1, 0, 3), | |
298 | EXT_CONTROL_REG_BITS(VAUX2, 0, 4), | |
299 | EXT_CONTROL_REG_BITS(VAUX33, 0, 5), | |
300 | EXT_CONTROL_REG_BITS(VMMC, 0, 0), | |
301 | }; | |
302 | ||
303 | static unsigned int tps65911_ext_sleep_control[] = { | |
304 | 0, | |
305 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
306 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
307 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
308 | EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3), | |
309 | EXT_CONTROL_REG_BITS(LDO1, 0, 1), | |
310 | EXT_CONTROL_REG_BITS(LDO2, 0, 2), | |
311 | EXT_CONTROL_REG_BITS(LDO3, 0, 7), | |
312 | EXT_CONTROL_REG_BITS(LDO4, 0, 6), | |
313 | EXT_CONTROL_REG_BITS(LDO5, 0, 3), | |
314 | EXT_CONTROL_REG_BITS(LDO6, 0, 0), | |
315 | EXT_CONTROL_REG_BITS(LDO7, 0, 5), | |
316 | EXT_CONTROL_REG_BITS(LDO8, 0, 4), | |
317 | }; | |
318 | ||
518fb721 | 319 | struct tps65910_reg { |
39aa9b6e | 320 | struct regulator_desc *desc; |
518fb721 | 321 | struct tps65910 *mfd; |
39aa9b6e AL |
322 | struct regulator_dev **rdev; |
323 | struct tps_info **info; | |
518fb721 | 324 | struct mutex mutex; |
39aa9b6e | 325 | int num_regulators; |
518fb721 | 326 | int mode; |
a320e3c3 | 327 | int (*get_ctrl_reg)(int); |
1e0c66f4 LD |
328 | unsigned int *ext_sleep_control; |
329 | unsigned int board_ext_control[TPS65910_NUM_REGS]; | |
518fb721 GG |
330 | }; |
331 | ||
332 | static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg) | |
333 | { | |
3f7e8275 | 334 | unsigned int val; |
518fb721 GG |
335 | int err; |
336 | ||
3f7e8275 | 337 | err = tps65910_reg_read(pmic->mfd, reg, &val); |
518fb721 GG |
338 | if (err) |
339 | return err; | |
340 | ||
341 | return val; | |
342 | } | |
343 | ||
518fb721 GG |
344 | static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, |
345 | u8 set_mask, u8 clear_mask) | |
346 | { | |
347 | int err, data; | |
348 | ||
349 | mutex_lock(&pmic->mutex); | |
350 | ||
351 | data = tps65910_read(pmic, reg); | |
352 | if (data < 0) { | |
353 | dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
354 | err = data; | |
355 | goto out; | |
356 | } | |
357 | ||
358 | data &= ~clear_mask; | |
359 | data |= set_mask; | |
3f7e8275 | 360 | err = tps65910_reg_write(pmic->mfd, reg, data); |
518fb721 GG |
361 | if (err) |
362 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
363 | ||
364 | out: | |
365 | mutex_unlock(&pmic->mutex); | |
366 | return err; | |
367 | } | |
368 | ||
3f7e8275 | 369 | static int tps65910_reg_read_locked(struct tps65910_reg *pmic, u8 reg) |
518fb721 GG |
370 | { |
371 | int data; | |
372 | ||
373 | mutex_lock(&pmic->mutex); | |
374 | ||
375 | data = tps65910_read(pmic, reg); | |
376 | if (data < 0) | |
377 | dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
378 | ||
379 | mutex_unlock(&pmic->mutex); | |
380 | return data; | |
381 | } | |
382 | ||
3f7e8275 | 383 | static int tps65910_reg_write_locked(struct tps65910_reg *pmic, u8 reg, u8 val) |
518fb721 GG |
384 | { |
385 | int err; | |
386 | ||
387 | mutex_lock(&pmic->mutex); | |
388 | ||
3f7e8275 | 389 | err = tps65910_reg_write(pmic->mfd, reg, val); |
518fb721 GG |
390 | if (err < 0) |
391 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
392 | ||
393 | mutex_unlock(&pmic->mutex); | |
394 | return err; | |
395 | } | |
396 | ||
397 | static int tps65910_get_ctrl_register(int id) | |
398 | { | |
399 | switch (id) { | |
400 | case TPS65910_REG_VRTC: | |
401 | return TPS65910_VRTC; | |
402 | case TPS65910_REG_VIO: | |
403 | return TPS65910_VIO; | |
404 | case TPS65910_REG_VDD1: | |
405 | return TPS65910_VDD1; | |
406 | case TPS65910_REG_VDD2: | |
407 | return TPS65910_VDD2; | |
408 | case TPS65910_REG_VDD3: | |
409 | return TPS65910_VDD3; | |
410 | case TPS65910_REG_VDIG1: | |
411 | return TPS65910_VDIG1; | |
412 | case TPS65910_REG_VDIG2: | |
413 | return TPS65910_VDIG2; | |
414 | case TPS65910_REG_VPLL: | |
415 | return TPS65910_VPLL; | |
416 | case TPS65910_REG_VDAC: | |
417 | return TPS65910_VDAC; | |
418 | case TPS65910_REG_VAUX1: | |
419 | return TPS65910_VAUX1; | |
420 | case TPS65910_REG_VAUX2: | |
421 | return TPS65910_VAUX2; | |
422 | case TPS65910_REG_VAUX33: | |
423 | return TPS65910_VAUX33; | |
424 | case TPS65910_REG_VMMC: | |
425 | return TPS65910_VMMC; | |
426 | default: | |
427 | return -EINVAL; | |
428 | } | |
429 | } | |
430 | ||
a320e3c3 JEC |
431 | static int tps65911_get_ctrl_register(int id) |
432 | { | |
433 | switch (id) { | |
434 | case TPS65910_REG_VRTC: | |
435 | return TPS65910_VRTC; | |
436 | case TPS65910_REG_VIO: | |
437 | return TPS65910_VIO; | |
438 | case TPS65910_REG_VDD1: | |
439 | return TPS65910_VDD1; | |
440 | case TPS65910_REG_VDD2: | |
441 | return TPS65910_VDD2; | |
442 | case TPS65911_REG_VDDCTRL: | |
443 | return TPS65911_VDDCTRL; | |
444 | case TPS65911_REG_LDO1: | |
445 | return TPS65911_LDO1; | |
446 | case TPS65911_REG_LDO2: | |
447 | return TPS65911_LDO2; | |
448 | case TPS65911_REG_LDO3: | |
449 | return TPS65911_LDO3; | |
450 | case TPS65911_REG_LDO4: | |
451 | return TPS65911_LDO4; | |
452 | case TPS65911_REG_LDO5: | |
453 | return TPS65911_LDO5; | |
454 | case TPS65911_REG_LDO6: | |
455 | return TPS65911_LDO6; | |
456 | case TPS65911_REG_LDO7: | |
457 | return TPS65911_LDO7; | |
458 | case TPS65911_REG_LDO8: | |
459 | return TPS65911_LDO8; | |
460 | default: | |
461 | return -EINVAL; | |
462 | } | |
463 | } | |
464 | ||
0651eed5 LD |
465 | static int tps65910_enable_time(struct regulator_dev *dev) |
466 | { | |
467 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
468 | int id = rdev_get_id(dev); | |
469 | return pmic->info[id]->enable_time_us; | |
470 | } | |
518fb721 GG |
471 | |
472 | static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) | |
473 | { | |
474 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
475 | struct tps65910 *mfd = pmic->mfd; | |
476 | int reg, value, id = rdev_get_id(dev); | |
a320e3c3 JEC |
477 | |
478 | reg = pmic->get_ctrl_reg(id); | |
518fb721 GG |
479 | if (reg < 0) |
480 | return reg; | |
481 | ||
482 | switch (mode) { | |
483 | case REGULATOR_MODE_NORMAL: | |
484 | return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT, | |
485 | LDO_ST_MODE_BIT); | |
486 | case REGULATOR_MODE_IDLE: | |
487 | value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; | |
3f7e8275 | 488 | return tps65910_reg_set_bits(mfd, reg, value); |
518fb721 | 489 | case REGULATOR_MODE_STANDBY: |
3f7e8275 | 490 | return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT); |
518fb721 GG |
491 | } |
492 | ||
493 | return -EINVAL; | |
494 | } | |
495 | ||
496 | static unsigned int tps65910_get_mode(struct regulator_dev *dev) | |
497 | { | |
498 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
499 | int reg, value, id = rdev_get_id(dev); | |
500 | ||
a320e3c3 | 501 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
502 | if (reg < 0) |
503 | return reg; | |
504 | ||
3f7e8275 | 505 | value = tps65910_reg_read_locked(pmic, reg); |
518fb721 GG |
506 | if (value < 0) |
507 | return value; | |
508 | ||
58599393 | 509 | if (!(value & LDO_ST_ON_BIT)) |
518fb721 GG |
510 | return REGULATOR_MODE_STANDBY; |
511 | else if (value & LDO_ST_MODE_BIT) | |
512 | return REGULATOR_MODE_IDLE; | |
513 | else | |
514 | return REGULATOR_MODE_NORMAL; | |
515 | } | |
516 | ||
18039e0f | 517 | static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) |
518fb721 GG |
518 | { |
519 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
18039e0f | 520 | int id = rdev_get_id(dev); |
a320e3c3 | 521 | int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; |
518fb721 GG |
522 | |
523 | switch (id) { | |
524 | case TPS65910_REG_VDD1: | |
3f7e8275 RK |
525 | opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_OP); |
526 | mult = tps65910_reg_read_locked(pmic, TPS65910_VDD1); | |
518fb721 | 527 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; |
3f7e8275 | 528 | srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_SR); |
518fb721 GG |
529 | sr = opvsel & VDD1_OP_CMD_MASK; |
530 | opvsel &= VDD1_OP_SEL_MASK; | |
531 | srvsel &= VDD1_SR_SEL_MASK; | |
a320e3c3 | 532 | vselmax = 75; |
518fb721 GG |
533 | break; |
534 | case TPS65910_REG_VDD2: | |
3f7e8275 RK |
535 | opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_OP); |
536 | mult = tps65910_reg_read_locked(pmic, TPS65910_VDD2); | |
518fb721 | 537 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; |
3f7e8275 | 538 | srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_SR); |
518fb721 GG |
539 | sr = opvsel & VDD2_OP_CMD_MASK; |
540 | opvsel &= VDD2_OP_SEL_MASK; | |
541 | srvsel &= VDD2_SR_SEL_MASK; | |
a320e3c3 JEC |
542 | vselmax = 75; |
543 | break; | |
544 | case TPS65911_REG_VDDCTRL: | |
3f7e8275 RK |
545 | opvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_OP); |
546 | srvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_SR); | |
a320e3c3 JEC |
547 | sr = opvsel & VDDCTRL_OP_CMD_MASK; |
548 | opvsel &= VDDCTRL_OP_SEL_MASK; | |
549 | srvsel &= VDDCTRL_SR_SEL_MASK; | |
550 | vselmax = 64; | |
518fb721 GG |
551 | break; |
552 | } | |
553 | ||
554 | /* multiplier 0 == 1 but 2,3 normal */ | |
555 | if (!mult) | |
556 | mult=1; | |
557 | ||
558 | if (sr) { | |
a320e3c3 JEC |
559 | /* normalise to valid range */ |
560 | if (srvsel < 3) | |
561 | srvsel = 3; | |
562 | if (srvsel > vselmax) | |
563 | srvsel = vselmax; | |
18039e0f | 564 | return srvsel - 3; |
518fb721 GG |
565 | } else { |
566 | ||
a320e3c3 JEC |
567 | /* normalise to valid range*/ |
568 | if (opvsel < 3) | |
569 | opvsel = 3; | |
570 | if (opvsel > vselmax) | |
571 | opvsel = vselmax; | |
18039e0f | 572 | return opvsel - 3; |
518fb721 | 573 | } |
18039e0f | 574 | return -EINVAL; |
518fb721 GG |
575 | } |
576 | ||
1f904fd1 | 577 | static int tps65910_get_voltage_sel(struct regulator_dev *dev) |
518fb721 GG |
578 | { |
579 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
1f904fd1 | 580 | int reg, value, id = rdev_get_id(dev); |
518fb721 | 581 | |
a320e3c3 | 582 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
583 | if (reg < 0) |
584 | return reg; | |
585 | ||
3f7e8275 | 586 | value = tps65910_reg_read_locked(pmic, reg); |
518fb721 GG |
587 | if (value < 0) |
588 | return value; | |
589 | ||
590 | switch (id) { | |
591 | case TPS65910_REG_VIO: | |
592 | case TPS65910_REG_VDIG1: | |
593 | case TPS65910_REG_VDIG2: | |
594 | case TPS65910_REG_VPLL: | |
595 | case TPS65910_REG_VDAC: | |
596 | case TPS65910_REG_VAUX1: | |
597 | case TPS65910_REG_VAUX2: | |
598 | case TPS65910_REG_VAUX33: | |
599 | case TPS65910_REG_VMMC: | |
600 | value &= LDO_SEL_MASK; | |
601 | value >>= LDO_SEL_SHIFT; | |
602 | break; | |
603 | default: | |
604 | return -EINVAL; | |
605 | } | |
606 | ||
1f904fd1 | 607 | return value; |
518fb721 GG |
608 | } |
609 | ||
610 | static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) | |
611 | { | |
612 | return 5 * 1000 * 1000; | |
613 | } | |
614 | ||
1f904fd1 | 615 | static int tps65911_get_voltage_sel(struct regulator_dev *dev) |
a320e3c3 JEC |
616 | { |
617 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
1f904fd1 | 618 | int id = rdev_get_id(dev); |
a320e3c3 JEC |
619 | u8 value, reg; |
620 | ||
621 | reg = pmic->get_ctrl_reg(id); | |
622 | ||
3f7e8275 | 623 | value = tps65910_reg_read_locked(pmic, reg); |
a320e3c3 JEC |
624 | |
625 | switch (id) { | |
626 | case TPS65911_REG_LDO1: | |
627 | case TPS65911_REG_LDO2: | |
628 | case TPS65911_REG_LDO4: | |
629 | value &= LDO1_SEL_MASK; | |
630 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
631 | break; |
632 | case TPS65911_REG_LDO3: | |
633 | case TPS65911_REG_LDO5: | |
634 | case TPS65911_REG_LDO6: | |
635 | case TPS65911_REG_LDO7: | |
636 | case TPS65911_REG_LDO8: | |
637 | value &= LDO3_SEL_MASK; | |
638 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
639 | break; |
640 | case TPS65910_REG_VIO: | |
e882eae8 LD |
641 | value &= LDO_SEL_MASK; |
642 | value >>= LDO_SEL_SHIFT; | |
1f904fd1 | 643 | break; |
a320e3c3 JEC |
644 | default: |
645 | return -EINVAL; | |
646 | } | |
647 | ||
1f904fd1 | 648 | return value; |
a320e3c3 JEC |
649 | } |
650 | ||
94732b97 AL |
651 | static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, |
652 | unsigned selector) | |
518fb721 GG |
653 | { |
654 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
655 | int id = rdev_get_id(dev), vsel; | |
a320e3c3 | 656 | int dcdc_mult = 0; |
518fb721 | 657 | |
a320e3c3 JEC |
658 | switch (id) { |
659 | case TPS65910_REG_VDD1: | |
780dc9ba | 660 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
661 | if (dcdc_mult == 1) |
662 | dcdc_mult--; | |
780dc9ba | 663 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
518fb721 | 664 | |
518fb721 GG |
665 | tps65910_modify_bits(pmic, TPS65910_VDD1, |
666 | (dcdc_mult << VDD1_VGAIN_SEL_SHIFT), | |
667 | VDD1_VGAIN_SEL_MASK); | |
3f7e8275 | 668 | tps65910_reg_write_locked(pmic, TPS65910_VDD1_OP, vsel); |
a320e3c3 JEC |
669 | break; |
670 | case TPS65910_REG_VDD2: | |
780dc9ba | 671 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
672 | if (dcdc_mult == 1) |
673 | dcdc_mult--; | |
780dc9ba | 674 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
a320e3c3 | 675 | |
518fb721 GG |
676 | tps65910_modify_bits(pmic, TPS65910_VDD2, |
677 | (dcdc_mult << VDD2_VGAIN_SEL_SHIFT), | |
678 | VDD1_VGAIN_SEL_MASK); | |
3f7e8275 | 679 | tps65910_reg_write_locked(pmic, TPS65910_VDD2_OP, vsel); |
a320e3c3 JEC |
680 | break; |
681 | case TPS65911_REG_VDDCTRL: | |
c4632aed | 682 | vsel = selector + 3; |
3f7e8275 | 683 | tps65910_reg_write_locked(pmic, TPS65911_VDDCTRL_OP, vsel); |
518fb721 GG |
684 | } |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
94732b97 AL |
689 | static int tps65910_set_voltage_sel(struct regulator_dev *dev, |
690 | unsigned selector) | |
518fb721 GG |
691 | { |
692 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
693 | int reg, id = rdev_get_id(dev); | |
694 | ||
a320e3c3 | 695 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
696 | if (reg < 0) |
697 | return reg; | |
698 | ||
699 | switch (id) { | |
700 | case TPS65910_REG_VIO: | |
701 | case TPS65910_REG_VDIG1: | |
702 | case TPS65910_REG_VDIG2: | |
703 | case TPS65910_REG_VPLL: | |
704 | case TPS65910_REG_VDAC: | |
705 | case TPS65910_REG_VAUX1: | |
706 | case TPS65910_REG_VAUX2: | |
707 | case TPS65910_REG_VAUX33: | |
708 | case TPS65910_REG_VMMC: | |
709 | return tps65910_modify_bits(pmic, reg, | |
710 | (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); | |
711 | } | |
712 | ||
713 | return -EINVAL; | |
714 | } | |
715 | ||
94732b97 AL |
716 | static int tps65911_set_voltage_sel(struct regulator_dev *dev, |
717 | unsigned selector) | |
a320e3c3 JEC |
718 | { |
719 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
720 | int reg, id = rdev_get_id(dev); | |
721 | ||
722 | reg = pmic->get_ctrl_reg(id); | |
723 | if (reg < 0) | |
724 | return reg; | |
725 | ||
726 | switch (id) { | |
727 | case TPS65911_REG_LDO1: | |
728 | case TPS65911_REG_LDO2: | |
729 | case TPS65911_REG_LDO4: | |
730 | return tps65910_modify_bits(pmic, reg, | |
731 | (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK); | |
732 | case TPS65911_REG_LDO3: | |
733 | case TPS65911_REG_LDO5: | |
734 | case TPS65911_REG_LDO6: | |
735 | case TPS65911_REG_LDO7: | |
736 | case TPS65911_REG_LDO8: | |
a320e3c3 JEC |
737 | return tps65910_modify_bits(pmic, reg, |
738 | (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK); | |
e882eae8 LD |
739 | case TPS65910_REG_VIO: |
740 | return tps65910_modify_bits(pmic, reg, | |
741 | (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); | |
a320e3c3 JEC |
742 | } |
743 | ||
744 | return -EINVAL; | |
745 | } | |
746 | ||
747 | ||
518fb721 GG |
748 | static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, |
749 | unsigned selector) | |
750 | { | |
a320e3c3 | 751 | int volt, mult = 1, id = rdev_get_id(dev); |
518fb721 | 752 | |
a320e3c3 JEC |
753 | switch (id) { |
754 | case TPS65910_REG_VDD1: | |
755 | case TPS65910_REG_VDD2: | |
780dc9ba | 756 | mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 | 757 | volt = VDD1_2_MIN_VOLT + |
780dc9ba | 758 | (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET; |
d04156bc | 759 | break; |
a320e3c3 JEC |
760 | case TPS65911_REG_VDDCTRL: |
761 | volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); | |
d04156bc AL |
762 | break; |
763 | default: | |
764 | BUG(); | |
765 | return -EINVAL; | |
a320e3c3 | 766 | } |
518fb721 GG |
767 | |
768 | return volt * 100 * mult; | |
769 | } | |
770 | ||
771 | static int tps65910_list_voltage(struct regulator_dev *dev, | |
772 | unsigned selector) | |
773 | { | |
774 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
775 | int id = rdev_get_id(dev), voltage; | |
776 | ||
777 | if (id < TPS65910_REG_VIO || id > TPS65910_REG_VMMC) | |
778 | return -EINVAL; | |
779 | ||
7d38a3cb | 780 | if (selector >= pmic->info[id]->n_voltages) |
518fb721 GG |
781 | return -EINVAL; |
782 | else | |
7d38a3cb | 783 | voltage = pmic->info[id]->voltage_table[selector] * 1000; |
518fb721 GG |
784 | |
785 | return voltage; | |
786 | } | |
787 | ||
a320e3c3 JEC |
788 | static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) |
789 | { | |
790 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
791 | int step_mv = 0, id = rdev_get_id(dev); | |
792 | ||
793 | switch(id) { | |
794 | case TPS65911_REG_LDO1: | |
795 | case TPS65911_REG_LDO2: | |
796 | case TPS65911_REG_LDO4: | |
797 | /* The first 5 values of the selector correspond to 1V */ | |
798 | if (selector < 5) | |
799 | selector = 0; | |
800 | else | |
801 | selector -= 4; | |
802 | ||
803 | step_mv = 50; | |
804 | break; | |
805 | case TPS65911_REG_LDO3: | |
806 | case TPS65911_REG_LDO5: | |
807 | case TPS65911_REG_LDO6: | |
808 | case TPS65911_REG_LDO7: | |
809 | case TPS65911_REG_LDO8: | |
810 | /* The first 3 values of the selector correspond to 1V */ | |
811 | if (selector < 3) | |
812 | selector = 0; | |
813 | else | |
814 | selector -= 2; | |
815 | ||
816 | step_mv = 100; | |
817 | break; | |
818 | case TPS65910_REG_VIO: | |
7d38a3cb | 819 | return pmic->info[id]->voltage_table[selector] * 1000; |
a320e3c3 JEC |
820 | default: |
821 | return -EINVAL; | |
822 | } | |
823 | ||
824 | return (LDO_MIN_VOLT + selector * step_mv) * 1000; | |
825 | } | |
826 | ||
18039e0f LD |
827 | static int tps65910_set_voltage_dcdc_time_sel(struct regulator_dev *dev, |
828 | unsigned int old_selector, unsigned int new_selector) | |
829 | { | |
830 | int id = rdev_get_id(dev); | |
831 | int old_volt, new_volt; | |
832 | ||
833 | old_volt = tps65910_list_voltage_dcdc(dev, old_selector); | |
834 | if (old_volt < 0) | |
835 | return old_volt; | |
836 | ||
837 | new_volt = tps65910_list_voltage_dcdc(dev, new_selector); | |
838 | if (new_volt < 0) | |
839 | return new_volt; | |
840 | ||
841 | /* VDD1 and VDD2 are 12.5mV/us, VDDCTRL is 100mV/20us */ | |
842 | switch (id) { | |
843 | case TPS65910_REG_VDD1: | |
844 | case TPS65910_REG_VDD2: | |
845 | return DIV_ROUND_UP(abs(old_volt - new_volt), 12500); | |
846 | case TPS65911_REG_VDDCTRL: | |
847 | return DIV_ROUND_UP(abs(old_volt - new_volt), 5000); | |
848 | } | |
849 | return -EINVAL; | |
850 | } | |
851 | ||
518fb721 GG |
852 | /* Regulator ops (except VRTC) */ |
853 | static struct regulator_ops tps65910_ops_dcdc = { | |
a40a9c43 AL |
854 | .is_enabled = regulator_is_enabled_regmap, |
855 | .enable = regulator_enable_regmap, | |
856 | .disable = regulator_disable_regmap, | |
0651eed5 | 857 | .enable_time = tps65910_enable_time, |
518fb721 GG |
858 | .set_mode = tps65910_set_mode, |
859 | .get_mode = tps65910_get_mode, | |
18039e0f | 860 | .get_voltage_sel = tps65910_get_voltage_dcdc_sel, |
94732b97 | 861 | .set_voltage_sel = tps65910_set_voltage_dcdc_sel, |
18039e0f | 862 | .set_voltage_time_sel = tps65910_set_voltage_dcdc_time_sel, |
518fb721 GG |
863 | .list_voltage = tps65910_list_voltage_dcdc, |
864 | }; | |
865 | ||
866 | static struct regulator_ops tps65910_ops_vdd3 = { | |
a40a9c43 AL |
867 | .is_enabled = regulator_is_enabled_regmap, |
868 | .enable = regulator_enable_regmap, | |
869 | .disable = regulator_disable_regmap, | |
0651eed5 | 870 | .enable_time = tps65910_enable_time, |
518fb721 GG |
871 | .set_mode = tps65910_set_mode, |
872 | .get_mode = tps65910_get_mode, | |
873 | .get_voltage = tps65910_get_voltage_vdd3, | |
874 | .list_voltage = tps65910_list_voltage, | |
875 | }; | |
876 | ||
877 | static struct regulator_ops tps65910_ops = { | |
a40a9c43 AL |
878 | .is_enabled = regulator_is_enabled_regmap, |
879 | .enable = regulator_enable_regmap, | |
880 | .disable = regulator_disable_regmap, | |
0651eed5 | 881 | .enable_time = tps65910_enable_time, |
518fb721 GG |
882 | .set_mode = tps65910_set_mode, |
883 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 884 | .get_voltage_sel = tps65910_get_voltage_sel, |
94732b97 | 885 | .set_voltage_sel = tps65910_set_voltage_sel, |
518fb721 GG |
886 | .list_voltage = tps65910_list_voltage, |
887 | }; | |
888 | ||
a320e3c3 | 889 | static struct regulator_ops tps65911_ops = { |
a40a9c43 AL |
890 | .is_enabled = regulator_is_enabled_regmap, |
891 | .enable = regulator_enable_regmap, | |
892 | .disable = regulator_disable_regmap, | |
0651eed5 | 893 | .enable_time = tps65910_enable_time, |
a320e3c3 JEC |
894 | .set_mode = tps65910_set_mode, |
895 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 896 | .get_voltage_sel = tps65911_get_voltage_sel, |
94732b97 | 897 | .set_voltage_sel = tps65911_set_voltage_sel, |
a320e3c3 JEC |
898 | .list_voltage = tps65911_list_voltage, |
899 | }; | |
900 | ||
1e0c66f4 LD |
901 | static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, |
902 | int id, int ext_sleep_config) | |
903 | { | |
904 | struct tps65910 *mfd = pmic->mfd; | |
905 | u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF; | |
906 | u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF); | |
907 | int ret; | |
908 | ||
909 | /* | |
910 | * Regulator can not be control from multiple external input EN1, EN2 | |
911 | * and EN3 together. | |
912 | */ | |
913 | if (ext_sleep_config & EXT_SLEEP_CONTROL) { | |
914 | int en_count; | |
915 | en_count = ((ext_sleep_config & | |
916 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0); | |
917 | en_count += ((ext_sleep_config & | |
918 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0); | |
919 | en_count += ((ext_sleep_config & | |
920 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0); | |
f30b0716 LD |
921 | en_count += ((ext_sleep_config & |
922 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0); | |
1e0c66f4 LD |
923 | if (en_count > 1) { |
924 | dev_err(mfd->dev, | |
925 | "External sleep control flag is not proper\n"); | |
926 | return -EINVAL; | |
927 | } | |
928 | } | |
929 | ||
930 | pmic->board_ext_control[id] = ext_sleep_config; | |
931 | ||
932 | /* External EN1 control */ | |
933 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) | |
3f7e8275 | 934 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
935 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
936 | else | |
3f7e8275 | 937 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
938 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
939 | if (ret < 0) { | |
940 | dev_err(mfd->dev, | |
941 | "Error in configuring external control EN1\n"); | |
942 | return ret; | |
943 | } | |
944 | ||
945 | /* External EN2 control */ | |
946 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) | |
3f7e8275 | 947 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
948 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
949 | else | |
3f7e8275 | 950 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
951 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
952 | if (ret < 0) { | |
953 | dev_err(mfd->dev, | |
954 | "Error in configuring external control EN2\n"); | |
955 | return ret; | |
956 | } | |
957 | ||
958 | /* External EN3 control for TPS65910 LDO only */ | |
959 | if ((tps65910_chip_id(mfd) == TPS65910) && | |
960 | (id >= TPS65910_REG_VDIG1)) { | |
961 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) | |
3f7e8275 | 962 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
963 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
964 | else | |
3f7e8275 | 965 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
966 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
967 | if (ret < 0) { | |
968 | dev_err(mfd->dev, | |
969 | "Error in configuring external control EN3\n"); | |
970 | return ret; | |
971 | } | |
972 | } | |
973 | ||
974 | /* Return if no external control is selected */ | |
975 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { | |
976 | /* Clear all sleep controls */ | |
3f7e8275 | 977 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
978 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
979 | if (!ret) | |
3f7e8275 | 980 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
981 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
982 | if (ret < 0) | |
983 | dev_err(mfd->dev, | |
984 | "Error in configuring SLEEP register\n"); | |
985 | return ret; | |
986 | } | |
987 | ||
988 | /* | |
989 | * For regulator that has separate operational and sleep register make | |
990 | * sure that operational is used and clear sleep register to turn | |
991 | * regulator off when external control is inactive | |
992 | */ | |
993 | if ((id == TPS65910_REG_VDD1) || | |
994 | (id == TPS65910_REG_VDD2) || | |
995 | ((id == TPS65911_REG_VDDCTRL) && | |
996 | (tps65910_chip_id(mfd) == TPS65911))) { | |
997 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; | |
998 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; | |
3f7e8275 RK |
999 | int opvsel = tps65910_reg_read_locked(pmic, op_reg_add); |
1000 | int srvsel = tps65910_reg_read_locked(pmic, sr_reg_add); | |
1e0c66f4 LD |
1001 | if (opvsel & VDD1_OP_CMD_MASK) { |
1002 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; | |
3f7e8275 RK |
1003 | ret = tps65910_reg_write_locked(pmic, op_reg_add, |
1004 | reg_val); | |
1e0c66f4 LD |
1005 | if (ret < 0) { |
1006 | dev_err(mfd->dev, | |
1007 | "Error in configuring op register\n"); | |
1008 | return ret; | |
1009 | } | |
1010 | } | |
3f7e8275 | 1011 | ret = tps65910_reg_write_locked(pmic, sr_reg_add, 0); |
1e0c66f4 LD |
1012 | if (ret < 0) { |
1013 | dev_err(mfd->dev, "Error in settting sr register\n"); | |
1014 | return ret; | |
1015 | } | |
1016 | } | |
1017 | ||
3f7e8275 | 1018 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 | 1019 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
f30b0716 LD |
1020 | if (!ret) { |
1021 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
3f7e8275 | 1022 | ret = tps65910_reg_set_bits(mfd, |
f30b0716 LD |
1023 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
1024 | else | |
3f7e8275 | 1025 | ret = tps65910_reg_clear_bits(mfd, |
f30b0716 LD |
1026 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
1027 | } | |
1e0c66f4 LD |
1028 | if (ret < 0) |
1029 | dev_err(mfd->dev, | |
1030 | "Error in configuring SLEEP register\n"); | |
f30b0716 | 1031 | |
1e0c66f4 LD |
1032 | return ret; |
1033 | } | |
1034 | ||
6790178f RK |
1035 | #ifdef CONFIG_OF |
1036 | ||
1037 | static struct of_regulator_match tps65910_matches[] = { | |
33a6943d LD |
1038 | { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] }, |
1039 | { .name = "vio", .driver_data = (void *) &tps65910_regs[1] }, | |
1040 | { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] }, | |
1041 | { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] }, | |
1042 | { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] }, | |
1043 | { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] }, | |
1044 | { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] }, | |
1045 | { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] }, | |
1046 | { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] }, | |
1047 | { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] }, | |
1048 | { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] }, | |
1049 | { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] }, | |
1050 | { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] }, | |
6790178f RK |
1051 | }; |
1052 | ||
1053 | static struct of_regulator_match tps65911_matches[] = { | |
33a6943d LD |
1054 | { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] }, |
1055 | { .name = "vio", .driver_data = (void *) &tps65911_regs[1] }, | |
1056 | { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] }, | |
1057 | { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] }, | |
1058 | { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] }, | |
1059 | { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] }, | |
1060 | { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] }, | |
1061 | { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] }, | |
1062 | { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] }, | |
1063 | { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] }, | |
1064 | { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] }, | |
1065 | { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] }, | |
1066 | { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] }, | |
6790178f RK |
1067 | }; |
1068 | ||
1069 | static struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
1070 | struct platform_device *pdev, |
1071 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f RK |
1072 | { |
1073 | struct tps65910_board *pmic_plat_data; | |
1074 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
1075 | struct device_node *np = pdev->dev.parent->of_node; | |
1076 | struct device_node *regulators; | |
1077 | struct of_regulator_match *matches; | |
1078 | unsigned int prop; | |
1079 | int idx = 0, ret, count; | |
1080 | ||
1081 | pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data), | |
1082 | GFP_KERNEL); | |
1083 | ||
1084 | if (!pmic_plat_data) { | |
1085 | dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n"); | |
1086 | return NULL; | |
1087 | } | |
1088 | ||
1089 | regulators = of_find_node_by_name(np, "regulators"); | |
92ab953b LD |
1090 | if (!regulators) { |
1091 | dev_err(&pdev->dev, "regulator node not found\n"); | |
1092 | return NULL; | |
1093 | } | |
6790178f RK |
1094 | |
1095 | switch (tps65910_chip_id(tps65910)) { | |
1096 | case TPS65910: | |
1097 | count = ARRAY_SIZE(tps65910_matches); | |
1098 | matches = tps65910_matches; | |
1099 | break; | |
1100 | case TPS65911: | |
1101 | count = ARRAY_SIZE(tps65911_matches); | |
1102 | matches = tps65911_matches; | |
1103 | break; | |
1104 | default: | |
7e9a57e6 | 1105 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
6790178f RK |
1106 | return NULL; |
1107 | } | |
1108 | ||
1109 | ret = of_regulator_match(pdev->dev.parent, regulators, matches, count); | |
1110 | if (ret < 0) { | |
1111 | dev_err(&pdev->dev, "Error parsing regulator init data: %d\n", | |
1112 | ret); | |
1113 | return NULL; | |
1114 | } | |
1115 | ||
84df8c12 LD |
1116 | *tps65910_reg_matches = matches; |
1117 | ||
6790178f RK |
1118 | for (idx = 0; idx < count; idx++) { |
1119 | if (!matches[idx].init_data || !matches[idx].of_node) | |
1120 | continue; | |
1121 | ||
1122 | pmic_plat_data->tps65910_pmic_init_data[idx] = | |
1123 | matches[idx].init_data; | |
1124 | ||
1125 | ret = of_property_read_u32(matches[idx].of_node, | |
1126 | "ti,regulator-ext-sleep-control", &prop); | |
1127 | if (!ret) | |
1128 | pmic_plat_data->regulator_ext_sleep_control[idx] = prop; | |
1129 | } | |
1130 | ||
1131 | return pmic_plat_data; | |
1132 | } | |
1133 | #else | |
1134 | static inline struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
1135 | struct platform_device *pdev, |
1136 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f | 1137 | { |
84df8c12 | 1138 | *tps65910_reg_matches = NULL; |
74ea0e59 | 1139 | return NULL; |
6790178f RK |
1140 | } |
1141 | #endif | |
1142 | ||
518fb721 GG |
1143 | static __devinit int tps65910_probe(struct platform_device *pdev) |
1144 | { | |
1145 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c172708d | 1146 | struct regulator_config config = { }; |
a320e3c3 | 1147 | struct tps_info *info; |
518fb721 GG |
1148 | struct regulator_init_data *reg_data; |
1149 | struct regulator_dev *rdev; | |
1150 | struct tps65910_reg *pmic; | |
1151 | struct tps65910_board *pmic_plat_data; | |
84df8c12 | 1152 | struct of_regulator_match *tps65910_reg_matches = NULL; |
518fb721 GG |
1153 | int i, err; |
1154 | ||
1155 | pmic_plat_data = dev_get_platdata(tps65910->dev); | |
6790178f | 1156 | if (!pmic_plat_data && tps65910->dev->of_node) |
84df8c12 LD |
1157 | pmic_plat_data = tps65910_parse_dt_reg_data(pdev, |
1158 | &tps65910_reg_matches); | |
6790178f | 1159 | |
7e9a57e6 LD |
1160 | if (!pmic_plat_data) { |
1161 | dev_err(&pdev->dev, "Platform data not found\n"); | |
518fb721 | 1162 | return -EINVAL; |
7e9a57e6 | 1163 | } |
518fb721 | 1164 | |
9eb0c421 | 1165 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); |
7e9a57e6 LD |
1166 | if (!pmic) { |
1167 | dev_err(&pdev->dev, "Memory allocation failed for pmic\n"); | |
518fb721 | 1168 | return -ENOMEM; |
7e9a57e6 | 1169 | } |
518fb721 GG |
1170 | |
1171 | mutex_init(&pmic->mutex); | |
1172 | pmic->mfd = tps65910; | |
1173 | platform_set_drvdata(pdev, pmic); | |
1174 | ||
1175 | /* Give control of all register to control port */ | |
3f7e8275 | 1176 | tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL, |
518fb721 GG |
1177 | DEVCTRL_SR_CTL_I2C_SEL_MASK); |
1178 | ||
a320e3c3 JEC |
1179 | switch(tps65910_chip_id(tps65910)) { |
1180 | case TPS65910: | |
1181 | pmic->get_ctrl_reg = &tps65910_get_ctrl_register; | |
39aa9b6e | 1182 | pmic->num_regulators = ARRAY_SIZE(tps65910_regs); |
1e0c66f4 | 1183 | pmic->ext_sleep_control = tps65910_ext_sleep_control; |
a320e3c3 | 1184 | info = tps65910_regs; |
d04156bc | 1185 | break; |
a320e3c3 JEC |
1186 | case TPS65911: |
1187 | pmic->get_ctrl_reg = &tps65911_get_ctrl_register; | |
39aa9b6e | 1188 | pmic->num_regulators = ARRAY_SIZE(tps65911_regs); |
1e0c66f4 | 1189 | pmic->ext_sleep_control = tps65911_ext_sleep_control; |
a320e3c3 | 1190 | info = tps65911_regs; |
d04156bc | 1191 | break; |
a320e3c3 | 1192 | default: |
7e9a57e6 | 1193 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
a320e3c3 JEC |
1194 | return -ENODEV; |
1195 | } | |
1196 | ||
68d8c1cd | 1197 | pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1198 | sizeof(struct regulator_desc), GFP_KERNEL); |
1199 | if (!pmic->desc) { | |
68d8c1cd LD |
1200 | dev_err(&pdev->dev, "Memory alloc fails for desc\n"); |
1201 | return -ENOMEM; | |
39aa9b6e AL |
1202 | } |
1203 | ||
68d8c1cd | 1204 | pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1205 | sizeof(struct tps_info *), GFP_KERNEL); |
1206 | if (!pmic->info) { | |
68d8c1cd LD |
1207 | dev_err(&pdev->dev, "Memory alloc fails for info\n"); |
1208 | return -ENOMEM; | |
39aa9b6e AL |
1209 | } |
1210 | ||
68d8c1cd | 1211 | pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1212 | sizeof(struct regulator_dev *), GFP_KERNEL); |
1213 | if (!pmic->rdev) { | |
68d8c1cd LD |
1214 | dev_err(&pdev->dev, "Memory alloc fails for rdev\n"); |
1215 | return -ENOMEM; | |
39aa9b6e AL |
1216 | } |
1217 | ||
c1fc1480 KM |
1218 | for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS; |
1219 | i++, info++) { | |
1220 | ||
1221 | reg_data = pmic_plat_data->tps65910_pmic_init_data[i]; | |
1222 | ||
1223 | /* Regulator API handles empty constraints but not NULL | |
1224 | * constraints */ | |
1225 | if (!reg_data) | |
1226 | continue; | |
1227 | ||
518fb721 GG |
1228 | /* Register the regulators */ |
1229 | pmic->info[i] = info; | |
1230 | ||
1231 | pmic->desc[i].name = info->name; | |
77fa44d0 | 1232 | pmic->desc[i].id = i; |
7d38a3cb | 1233 | pmic->desc[i].n_voltages = info->n_voltages; |
518fb721 | 1234 | |
a320e3c3 | 1235 | if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { |
518fb721 | 1236 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
780dc9ba AM |
1237 | pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE * |
1238 | VDD1_2_NUM_VOLT_COARSE; | |
a320e3c3 JEC |
1239 | } else if (i == TPS65910_REG_VDD3) { |
1240 | if (tps65910_chip_id(tps65910) == TPS65910) | |
1241 | pmic->desc[i].ops = &tps65910_ops_vdd3; | |
1242 | else | |
1243 | pmic->desc[i].ops = &tps65910_ops_dcdc; | |
1244 | } else { | |
1245 | if (tps65910_chip_id(tps65910) == TPS65910) | |
1246 | pmic->desc[i].ops = &tps65910_ops; | |
1247 | else | |
1248 | pmic->desc[i].ops = &tps65911_ops; | |
1249 | } | |
518fb721 | 1250 | |
1e0c66f4 LD |
1251 | err = tps65910_set_ext_sleep_config(pmic, i, |
1252 | pmic_plat_data->regulator_ext_sleep_control[i]); | |
1253 | /* | |
1254 | * Failing on regulator for configuring externally control | |
1255 | * is not a serious issue, just throw warning. | |
1256 | */ | |
1257 | if (err < 0) | |
1258 | dev_warn(tps65910->dev, | |
1259 | "Failed to initialise ext control config\n"); | |
1260 | ||
518fb721 GG |
1261 | pmic->desc[i].type = REGULATOR_VOLTAGE; |
1262 | pmic->desc[i].owner = THIS_MODULE; | |
a40a9c43 AL |
1263 | pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); |
1264 | pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; | |
518fb721 | 1265 | |
c172708d MB |
1266 | config.dev = tps65910->dev; |
1267 | config.init_data = reg_data; | |
1268 | config.driver_data = pmic; | |
a40a9c43 | 1269 | config.regmap = tps65910->regmap; |
c172708d | 1270 | |
84df8c12 LD |
1271 | if (tps65910_reg_matches) |
1272 | config.of_node = tps65910_reg_matches[i].of_node; | |
6790178f | 1273 | |
c172708d | 1274 | rdev = regulator_register(&pmic->desc[i], &config); |
518fb721 GG |
1275 | if (IS_ERR(rdev)) { |
1276 | dev_err(tps65910->dev, | |
1277 | "failed to register %s regulator\n", | |
1278 | pdev->name); | |
1279 | err = PTR_ERR(rdev); | |
39aa9b6e | 1280 | goto err_unregister_regulator; |
518fb721 GG |
1281 | } |
1282 | ||
1283 | /* Save regulator for cleanup */ | |
1284 | pmic->rdev[i] = rdev; | |
1285 | } | |
1286 | return 0; | |
1287 | ||
39aa9b6e | 1288 | err_unregister_regulator: |
518fb721 GG |
1289 | while (--i >= 0) |
1290 | regulator_unregister(pmic->rdev[i]); | |
518fb721 GG |
1291 | return err; |
1292 | } | |
1293 | ||
1294 | static int __devexit tps65910_remove(struct platform_device *pdev) | |
1295 | { | |
39aa9b6e | 1296 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); |
518fb721 GG |
1297 | int i; |
1298 | ||
39aa9b6e AL |
1299 | for (i = 0; i < pmic->num_regulators; i++) |
1300 | regulator_unregister(pmic->rdev[i]); | |
518fb721 | 1301 | |
518fb721 GG |
1302 | return 0; |
1303 | } | |
1304 | ||
1e0c66f4 LD |
1305 | static void tps65910_shutdown(struct platform_device *pdev) |
1306 | { | |
1307 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); | |
1308 | int i; | |
1309 | ||
1310 | /* | |
1311 | * Before bootloader jumps to kernel, it makes sure that required | |
1312 | * external control signals are in desired state so that given rails | |
1313 | * can be configure accordingly. | |
1314 | * If rails are configured to be controlled from external control | |
1315 | * then before shutting down/rebooting the system, the external | |
1316 | * control configuration need to be remove from the rails so that | |
1317 | * its output will be available as per register programming even | |
1318 | * if external controls are removed. This is require when the POR | |
1319 | * value of the control signals are not in active state and before | |
1320 | * bootloader initializes it, the system requires the rail output | |
1321 | * to be active for booting. | |
1322 | */ | |
1323 | for (i = 0; i < pmic->num_regulators; i++) { | |
1324 | int err; | |
1325 | if (!pmic->rdev[i]) | |
1326 | continue; | |
1327 | ||
1328 | err = tps65910_set_ext_sleep_config(pmic, i, 0); | |
1329 | if (err < 0) | |
1330 | dev_err(&pdev->dev, | |
1331 | "Error in clearing external control\n"); | |
1332 | } | |
1333 | } | |
1334 | ||
518fb721 GG |
1335 | static struct platform_driver tps65910_driver = { |
1336 | .driver = { | |
1337 | .name = "tps65910-pmic", | |
1338 | .owner = THIS_MODULE, | |
1339 | }, | |
1340 | .probe = tps65910_probe, | |
1341 | .remove = __devexit_p(tps65910_remove), | |
1e0c66f4 | 1342 | .shutdown = tps65910_shutdown, |
518fb721 GG |
1343 | }; |
1344 | ||
1345 | static int __init tps65910_init(void) | |
1346 | { | |
1347 | return platform_driver_register(&tps65910_driver); | |
1348 | } | |
1349 | subsys_initcall(tps65910_init); | |
1350 | ||
1351 | static void __exit tps65910_cleanup(void) | |
1352 | { | |
1353 | platform_driver_unregister(&tps65910_driver); | |
1354 | } | |
1355 | module_exit(tps65910_cleanup); | |
1356 | ||
1357 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
ae0e6544 | 1358 | MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver"); |
518fb721 GG |
1359 | MODULE_LICENSE("GPL v2"); |
1360 | MODULE_ALIAS("platform:tps65910-pmic"); |