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518fb721 GG |
1 | /* |
2 | * tps65910.c -- TI tps65910 | |
3 | * | |
4 | * Copyright 2010 Texas Instruments Inc. | |
5 | * | |
6 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
7 | * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
518fb721 GG |
23 | #include <linux/slab.h> |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mfd/tps65910.h> | |
6790178f | 26 | #include <linux/regulator/of_regulator.h> |
518fb721 | 27 | |
518fb721 | 28 | #define TPS65910_SUPPLY_STATE_ENABLED 0x1 |
1e0c66f4 LD |
29 | #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \ |
30 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \ | |
f30b0716 LD |
31 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \ |
32 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
518fb721 | 33 | |
d9fe28f9 AL |
34 | /* supported VIO voltages in microvolts */ |
35 | static const unsigned int VIO_VSEL_table[] = { | |
36 | 1500000, 1800000, 2500000, 3300000, | |
518fb721 GG |
37 | }; |
38 | ||
a320e3c3 JEC |
39 | /* VSEL tables for TPS65910 specific LDOs and dcdc's */ |
40 | ||
d9fe28f9 AL |
41 | /* supported VDD3 voltages in microvolts */ |
42 | static const unsigned int VDD3_VSEL_table[] = { | |
43 | 5000000, | |
518fb721 GG |
44 | }; |
45 | ||
d9fe28f9 AL |
46 | /* supported VDIG1 voltages in microvolts */ |
47 | static const unsigned int VDIG1_VSEL_table[] = { | |
48 | 1200000, 1500000, 1800000, 2700000, | |
518fb721 GG |
49 | }; |
50 | ||
d9fe28f9 AL |
51 | /* supported VDIG2 voltages in microvolts */ |
52 | static const unsigned int VDIG2_VSEL_table[] = { | |
53 | 1000000, 1100000, 1200000, 1800000, | |
518fb721 GG |
54 | }; |
55 | ||
d9fe28f9 AL |
56 | /* supported VPLL voltages in microvolts */ |
57 | static const unsigned int VPLL_VSEL_table[] = { | |
58 | 1000000, 1100000, 1800000, 2500000, | |
518fb721 GG |
59 | }; |
60 | ||
d9fe28f9 AL |
61 | /* supported VDAC voltages in microvolts */ |
62 | static const unsigned int VDAC_VSEL_table[] = { | |
63 | 1800000, 2600000, 2800000, 2850000, | |
518fb721 GG |
64 | }; |
65 | ||
d9fe28f9 AL |
66 | /* supported VAUX1 voltages in microvolts */ |
67 | static const unsigned int VAUX1_VSEL_table[] = { | |
68 | 1800000, 2500000, 2800000, 2850000, | |
518fb721 GG |
69 | }; |
70 | ||
d9fe28f9 AL |
71 | /* supported VAUX2 voltages in microvolts */ |
72 | static const unsigned int VAUX2_VSEL_table[] = { | |
73 | 1800000, 2800000, 2900000, 3300000, | |
518fb721 GG |
74 | }; |
75 | ||
d9fe28f9 AL |
76 | /* supported VAUX33 voltages in microvolts */ |
77 | static const unsigned int VAUX33_VSEL_table[] = { | |
78 | 1800000, 2000000, 2800000, 3300000, | |
518fb721 GG |
79 | }; |
80 | ||
d9fe28f9 AL |
81 | /* supported VMMC voltages in microvolts */ |
82 | static const unsigned int VMMC_VSEL_table[] = { | |
83 | 1800000, 2800000, 3000000, 3300000, | |
518fb721 GG |
84 | }; |
85 | ||
86 | struct tps_info { | |
87 | const char *name; | |
19228a6a | 88 | const char *vin_name; |
7d38a3cb | 89 | u8 n_voltages; |
d9fe28f9 | 90 | const unsigned int *voltage_table; |
0651eed5 | 91 | int enable_time_us; |
518fb721 GG |
92 | }; |
93 | ||
94 | static struct tps_info tps65910_regs[] = { | |
95 | { | |
33a6943d | 96 | .name = "vrtc", |
19228a6a | 97 | .vin_name = "vcc7", |
0651eed5 | 98 | .enable_time_us = 2200, |
518fb721 GG |
99 | }, |
100 | { | |
33a6943d | 101 | .name = "vio", |
19228a6a | 102 | .vin_name = "vccio", |
7d38a3cb LD |
103 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
104 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 105 | .enable_time_us = 350, |
518fb721 GG |
106 | }, |
107 | { | |
33a6943d | 108 | .name = "vdd1", |
19228a6a | 109 | .vin_name = "vcc1", |
0651eed5 | 110 | .enable_time_us = 350, |
518fb721 GG |
111 | }, |
112 | { | |
33a6943d | 113 | .name = "vdd2", |
19228a6a | 114 | .vin_name = "vcc2", |
0651eed5 | 115 | .enable_time_us = 350, |
518fb721 GG |
116 | }, |
117 | { | |
33a6943d | 118 | .name = "vdd3", |
7d38a3cb LD |
119 | .n_voltages = ARRAY_SIZE(VDD3_VSEL_table), |
120 | .voltage_table = VDD3_VSEL_table, | |
0651eed5 | 121 | .enable_time_us = 200, |
518fb721 GG |
122 | }, |
123 | { | |
33a6943d | 124 | .name = "vdig1", |
19228a6a | 125 | .vin_name = "vcc6", |
7d38a3cb LD |
126 | .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table), |
127 | .voltage_table = VDIG1_VSEL_table, | |
0651eed5 | 128 | .enable_time_us = 100, |
518fb721 GG |
129 | }, |
130 | { | |
33a6943d | 131 | .name = "vdig2", |
19228a6a | 132 | .vin_name = "vcc6", |
7d38a3cb LD |
133 | .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table), |
134 | .voltage_table = VDIG2_VSEL_table, | |
0651eed5 | 135 | .enable_time_us = 100, |
518fb721 GG |
136 | }, |
137 | { | |
33a6943d | 138 | .name = "vpll", |
19228a6a | 139 | .vin_name = "vcc5", |
7d38a3cb LD |
140 | .n_voltages = ARRAY_SIZE(VPLL_VSEL_table), |
141 | .voltage_table = VPLL_VSEL_table, | |
0651eed5 | 142 | .enable_time_us = 100, |
518fb721 GG |
143 | }, |
144 | { | |
33a6943d | 145 | .name = "vdac", |
19228a6a | 146 | .vin_name = "vcc5", |
7d38a3cb LD |
147 | .n_voltages = ARRAY_SIZE(VDAC_VSEL_table), |
148 | .voltage_table = VDAC_VSEL_table, | |
0651eed5 | 149 | .enable_time_us = 100, |
518fb721 GG |
150 | }, |
151 | { | |
33a6943d | 152 | .name = "vaux1", |
19228a6a | 153 | .vin_name = "vcc4", |
7d38a3cb LD |
154 | .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table), |
155 | .voltage_table = VAUX1_VSEL_table, | |
0651eed5 | 156 | .enable_time_us = 100, |
518fb721 GG |
157 | }, |
158 | { | |
33a6943d | 159 | .name = "vaux2", |
19228a6a | 160 | .vin_name = "vcc4", |
7d38a3cb LD |
161 | .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table), |
162 | .voltage_table = VAUX2_VSEL_table, | |
0651eed5 | 163 | .enable_time_us = 100, |
518fb721 GG |
164 | }, |
165 | { | |
33a6943d | 166 | .name = "vaux33", |
19228a6a | 167 | .vin_name = "vcc3", |
7d38a3cb LD |
168 | .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table), |
169 | .voltage_table = VAUX33_VSEL_table, | |
0651eed5 | 170 | .enable_time_us = 100, |
518fb721 GG |
171 | }, |
172 | { | |
33a6943d | 173 | .name = "vmmc", |
19228a6a | 174 | .vin_name = "vcc3", |
7d38a3cb LD |
175 | .n_voltages = ARRAY_SIZE(VMMC_VSEL_table), |
176 | .voltage_table = VMMC_VSEL_table, | |
0651eed5 | 177 | .enable_time_us = 100, |
518fb721 GG |
178 | }, |
179 | }; | |
180 | ||
a320e3c3 | 181 | static struct tps_info tps65911_regs[] = { |
c2f8efd7 | 182 | { |
33a6943d | 183 | .name = "vrtc", |
19228a6a | 184 | .vin_name = "vcc7", |
0651eed5 | 185 | .enable_time_us = 2200, |
c2f8efd7 | 186 | }, |
a320e3c3 | 187 | { |
33a6943d | 188 | .name = "vio", |
19228a6a | 189 | .vin_name = "vccio", |
7d38a3cb LD |
190 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
191 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 192 | .enable_time_us = 350, |
a320e3c3 JEC |
193 | }, |
194 | { | |
33a6943d | 195 | .name = "vdd1", |
19228a6a | 196 | .vin_name = "vcc1", |
7be53188 | 197 | .n_voltages = 0x4C, |
0651eed5 | 198 | .enable_time_us = 350, |
a320e3c3 JEC |
199 | }, |
200 | { | |
33a6943d | 201 | .name = "vdd2", |
19228a6a | 202 | .vin_name = "vcc2", |
7be53188 | 203 | .n_voltages = 0x4C, |
0651eed5 | 204 | .enable_time_us = 350, |
a320e3c3 JEC |
205 | }, |
206 | { | |
33a6943d | 207 | .name = "vddctrl", |
7be53188 | 208 | .n_voltages = 0x44, |
0651eed5 | 209 | .enable_time_us = 900, |
a320e3c3 JEC |
210 | }, |
211 | { | |
33a6943d | 212 | .name = "ldo1", |
19228a6a | 213 | .vin_name = "vcc6", |
7be53188 | 214 | .n_voltages = 0x33, |
0651eed5 | 215 | .enable_time_us = 420, |
a320e3c3 JEC |
216 | }, |
217 | { | |
33a6943d | 218 | .name = "ldo2", |
19228a6a | 219 | .vin_name = "vcc6", |
7be53188 | 220 | .n_voltages = 0x33, |
0651eed5 | 221 | .enable_time_us = 420, |
a320e3c3 JEC |
222 | }, |
223 | { | |
33a6943d | 224 | .name = "ldo3", |
19228a6a | 225 | .vin_name = "vcc5", |
7be53188 | 226 | .n_voltages = 0x1A, |
0651eed5 | 227 | .enable_time_us = 230, |
a320e3c3 JEC |
228 | }, |
229 | { | |
33a6943d | 230 | .name = "ldo4", |
19228a6a | 231 | .vin_name = "vcc5", |
7be53188 | 232 | .n_voltages = 0x33, |
0651eed5 | 233 | .enable_time_us = 230, |
a320e3c3 JEC |
234 | }, |
235 | { | |
33a6943d | 236 | .name = "ldo5", |
19228a6a | 237 | .vin_name = "vcc4", |
7be53188 | 238 | .n_voltages = 0x1A, |
0651eed5 | 239 | .enable_time_us = 230, |
a320e3c3 JEC |
240 | }, |
241 | { | |
33a6943d | 242 | .name = "ldo6", |
19228a6a | 243 | .vin_name = "vcc3", |
7be53188 | 244 | .n_voltages = 0x1A, |
0651eed5 | 245 | .enable_time_us = 230, |
a320e3c3 JEC |
246 | }, |
247 | { | |
33a6943d | 248 | .name = "ldo7", |
19228a6a | 249 | .vin_name = "vcc3", |
7be53188 | 250 | .n_voltages = 0x1A, |
0651eed5 | 251 | .enable_time_us = 230, |
a320e3c3 JEC |
252 | }, |
253 | { | |
33a6943d | 254 | .name = "ldo8", |
19228a6a | 255 | .vin_name = "vcc3", |
7be53188 | 256 | .n_voltages = 0x1A, |
0651eed5 | 257 | .enable_time_us = 230, |
a320e3c3 JEC |
258 | }, |
259 | }; | |
260 | ||
1e0c66f4 LD |
261 | #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) |
262 | static unsigned int tps65910_ext_sleep_control[] = { | |
263 | 0, | |
264 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
265 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
266 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
267 | EXT_CONTROL_REG_BITS(VDD3, 1, 3), | |
268 | EXT_CONTROL_REG_BITS(VDIG1, 0, 1), | |
269 | EXT_CONTROL_REG_BITS(VDIG2, 0, 2), | |
270 | EXT_CONTROL_REG_BITS(VPLL, 0, 6), | |
271 | EXT_CONTROL_REG_BITS(VDAC, 0, 7), | |
272 | EXT_CONTROL_REG_BITS(VAUX1, 0, 3), | |
273 | EXT_CONTROL_REG_BITS(VAUX2, 0, 4), | |
274 | EXT_CONTROL_REG_BITS(VAUX33, 0, 5), | |
275 | EXT_CONTROL_REG_BITS(VMMC, 0, 0), | |
276 | }; | |
277 | ||
278 | static unsigned int tps65911_ext_sleep_control[] = { | |
279 | 0, | |
280 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
281 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
282 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
283 | EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3), | |
284 | EXT_CONTROL_REG_BITS(LDO1, 0, 1), | |
285 | EXT_CONTROL_REG_BITS(LDO2, 0, 2), | |
286 | EXT_CONTROL_REG_BITS(LDO3, 0, 7), | |
287 | EXT_CONTROL_REG_BITS(LDO4, 0, 6), | |
288 | EXT_CONTROL_REG_BITS(LDO5, 0, 3), | |
289 | EXT_CONTROL_REG_BITS(LDO6, 0, 0), | |
290 | EXT_CONTROL_REG_BITS(LDO7, 0, 5), | |
291 | EXT_CONTROL_REG_BITS(LDO8, 0, 4), | |
292 | }; | |
293 | ||
518fb721 | 294 | struct tps65910_reg { |
39aa9b6e | 295 | struct regulator_desc *desc; |
518fb721 | 296 | struct tps65910 *mfd; |
39aa9b6e AL |
297 | struct regulator_dev **rdev; |
298 | struct tps_info **info; | |
518fb721 | 299 | struct mutex mutex; |
39aa9b6e | 300 | int num_regulators; |
518fb721 | 301 | int mode; |
a320e3c3 | 302 | int (*get_ctrl_reg)(int); |
1e0c66f4 LD |
303 | unsigned int *ext_sleep_control; |
304 | unsigned int board_ext_control[TPS65910_NUM_REGS]; | |
518fb721 GG |
305 | }; |
306 | ||
307 | static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg) | |
308 | { | |
3f7e8275 | 309 | unsigned int val; |
518fb721 GG |
310 | int err; |
311 | ||
3f7e8275 | 312 | err = tps65910_reg_read(pmic->mfd, reg, &val); |
518fb721 GG |
313 | if (err) |
314 | return err; | |
315 | ||
316 | return val; | |
317 | } | |
318 | ||
518fb721 GG |
319 | static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, |
320 | u8 set_mask, u8 clear_mask) | |
321 | { | |
322 | int err, data; | |
323 | ||
324 | mutex_lock(&pmic->mutex); | |
325 | ||
326 | data = tps65910_read(pmic, reg); | |
327 | if (data < 0) { | |
328 | dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
329 | err = data; | |
330 | goto out; | |
331 | } | |
332 | ||
333 | data &= ~clear_mask; | |
334 | data |= set_mask; | |
3f7e8275 | 335 | err = tps65910_reg_write(pmic->mfd, reg, data); |
518fb721 GG |
336 | if (err) |
337 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
338 | ||
339 | out: | |
340 | mutex_unlock(&pmic->mutex); | |
341 | return err; | |
342 | } | |
343 | ||
3f7e8275 | 344 | static int tps65910_reg_read_locked(struct tps65910_reg *pmic, u8 reg) |
518fb721 GG |
345 | { |
346 | int data; | |
347 | ||
348 | mutex_lock(&pmic->mutex); | |
349 | ||
350 | data = tps65910_read(pmic, reg); | |
351 | if (data < 0) | |
352 | dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); | |
353 | ||
354 | mutex_unlock(&pmic->mutex); | |
355 | return data; | |
356 | } | |
357 | ||
3f7e8275 | 358 | static int tps65910_reg_write_locked(struct tps65910_reg *pmic, u8 reg, u8 val) |
518fb721 GG |
359 | { |
360 | int err; | |
361 | ||
362 | mutex_lock(&pmic->mutex); | |
363 | ||
3f7e8275 | 364 | err = tps65910_reg_write(pmic->mfd, reg, val); |
518fb721 GG |
365 | if (err < 0) |
366 | dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); | |
367 | ||
368 | mutex_unlock(&pmic->mutex); | |
369 | return err; | |
370 | } | |
371 | ||
372 | static int tps65910_get_ctrl_register(int id) | |
373 | { | |
374 | switch (id) { | |
375 | case TPS65910_REG_VRTC: | |
376 | return TPS65910_VRTC; | |
377 | case TPS65910_REG_VIO: | |
378 | return TPS65910_VIO; | |
379 | case TPS65910_REG_VDD1: | |
380 | return TPS65910_VDD1; | |
381 | case TPS65910_REG_VDD2: | |
382 | return TPS65910_VDD2; | |
383 | case TPS65910_REG_VDD3: | |
384 | return TPS65910_VDD3; | |
385 | case TPS65910_REG_VDIG1: | |
386 | return TPS65910_VDIG1; | |
387 | case TPS65910_REG_VDIG2: | |
388 | return TPS65910_VDIG2; | |
389 | case TPS65910_REG_VPLL: | |
390 | return TPS65910_VPLL; | |
391 | case TPS65910_REG_VDAC: | |
392 | return TPS65910_VDAC; | |
393 | case TPS65910_REG_VAUX1: | |
394 | return TPS65910_VAUX1; | |
395 | case TPS65910_REG_VAUX2: | |
396 | return TPS65910_VAUX2; | |
397 | case TPS65910_REG_VAUX33: | |
398 | return TPS65910_VAUX33; | |
399 | case TPS65910_REG_VMMC: | |
400 | return TPS65910_VMMC; | |
401 | default: | |
402 | return -EINVAL; | |
403 | } | |
404 | } | |
405 | ||
a320e3c3 JEC |
406 | static int tps65911_get_ctrl_register(int id) |
407 | { | |
408 | switch (id) { | |
409 | case TPS65910_REG_VRTC: | |
410 | return TPS65910_VRTC; | |
411 | case TPS65910_REG_VIO: | |
412 | return TPS65910_VIO; | |
413 | case TPS65910_REG_VDD1: | |
414 | return TPS65910_VDD1; | |
415 | case TPS65910_REG_VDD2: | |
416 | return TPS65910_VDD2; | |
417 | case TPS65911_REG_VDDCTRL: | |
418 | return TPS65911_VDDCTRL; | |
419 | case TPS65911_REG_LDO1: | |
420 | return TPS65911_LDO1; | |
421 | case TPS65911_REG_LDO2: | |
422 | return TPS65911_LDO2; | |
423 | case TPS65911_REG_LDO3: | |
424 | return TPS65911_LDO3; | |
425 | case TPS65911_REG_LDO4: | |
426 | return TPS65911_LDO4; | |
427 | case TPS65911_REG_LDO5: | |
428 | return TPS65911_LDO5; | |
429 | case TPS65911_REG_LDO6: | |
430 | return TPS65911_LDO6; | |
431 | case TPS65911_REG_LDO7: | |
432 | return TPS65911_LDO7; | |
433 | case TPS65911_REG_LDO8: | |
434 | return TPS65911_LDO8; | |
435 | default: | |
436 | return -EINVAL; | |
437 | } | |
438 | } | |
439 | ||
518fb721 GG |
440 | static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) |
441 | { | |
442 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
443 | struct tps65910 *mfd = pmic->mfd; | |
444 | int reg, value, id = rdev_get_id(dev); | |
a320e3c3 JEC |
445 | |
446 | reg = pmic->get_ctrl_reg(id); | |
518fb721 GG |
447 | if (reg < 0) |
448 | return reg; | |
449 | ||
450 | switch (mode) { | |
451 | case REGULATOR_MODE_NORMAL: | |
452 | return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT, | |
453 | LDO_ST_MODE_BIT); | |
454 | case REGULATOR_MODE_IDLE: | |
455 | value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; | |
3f7e8275 | 456 | return tps65910_reg_set_bits(mfd, reg, value); |
518fb721 | 457 | case REGULATOR_MODE_STANDBY: |
3f7e8275 | 458 | return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT); |
518fb721 GG |
459 | } |
460 | ||
461 | return -EINVAL; | |
462 | } | |
463 | ||
464 | static unsigned int tps65910_get_mode(struct regulator_dev *dev) | |
465 | { | |
466 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
467 | int reg, value, id = rdev_get_id(dev); | |
468 | ||
a320e3c3 | 469 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
470 | if (reg < 0) |
471 | return reg; | |
472 | ||
3f7e8275 | 473 | value = tps65910_reg_read_locked(pmic, reg); |
518fb721 GG |
474 | if (value < 0) |
475 | return value; | |
476 | ||
58599393 | 477 | if (!(value & LDO_ST_ON_BIT)) |
518fb721 GG |
478 | return REGULATOR_MODE_STANDBY; |
479 | else if (value & LDO_ST_MODE_BIT) | |
480 | return REGULATOR_MODE_IDLE; | |
481 | else | |
482 | return REGULATOR_MODE_NORMAL; | |
483 | } | |
484 | ||
18039e0f | 485 | static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) |
518fb721 GG |
486 | { |
487 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
18039e0f | 488 | int id = rdev_get_id(dev); |
a320e3c3 | 489 | int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; |
518fb721 GG |
490 | |
491 | switch (id) { | |
492 | case TPS65910_REG_VDD1: | |
3f7e8275 RK |
493 | opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_OP); |
494 | mult = tps65910_reg_read_locked(pmic, TPS65910_VDD1); | |
518fb721 | 495 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; |
3f7e8275 | 496 | srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD1_SR); |
518fb721 GG |
497 | sr = opvsel & VDD1_OP_CMD_MASK; |
498 | opvsel &= VDD1_OP_SEL_MASK; | |
499 | srvsel &= VDD1_SR_SEL_MASK; | |
a320e3c3 | 500 | vselmax = 75; |
518fb721 GG |
501 | break; |
502 | case TPS65910_REG_VDD2: | |
3f7e8275 RK |
503 | opvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_OP); |
504 | mult = tps65910_reg_read_locked(pmic, TPS65910_VDD2); | |
518fb721 | 505 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; |
3f7e8275 | 506 | srvsel = tps65910_reg_read_locked(pmic, TPS65910_VDD2_SR); |
518fb721 GG |
507 | sr = opvsel & VDD2_OP_CMD_MASK; |
508 | opvsel &= VDD2_OP_SEL_MASK; | |
509 | srvsel &= VDD2_SR_SEL_MASK; | |
a320e3c3 JEC |
510 | vselmax = 75; |
511 | break; | |
512 | case TPS65911_REG_VDDCTRL: | |
3f7e8275 RK |
513 | opvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_OP); |
514 | srvsel = tps65910_reg_read_locked(pmic, TPS65911_VDDCTRL_SR); | |
a320e3c3 JEC |
515 | sr = opvsel & VDDCTRL_OP_CMD_MASK; |
516 | opvsel &= VDDCTRL_OP_SEL_MASK; | |
517 | srvsel &= VDDCTRL_SR_SEL_MASK; | |
518 | vselmax = 64; | |
518fb721 GG |
519 | break; |
520 | } | |
521 | ||
522 | /* multiplier 0 == 1 but 2,3 normal */ | |
523 | if (!mult) | |
524 | mult=1; | |
525 | ||
526 | if (sr) { | |
a320e3c3 JEC |
527 | /* normalise to valid range */ |
528 | if (srvsel < 3) | |
529 | srvsel = 3; | |
530 | if (srvsel > vselmax) | |
531 | srvsel = vselmax; | |
18039e0f | 532 | return srvsel - 3; |
518fb721 GG |
533 | } else { |
534 | ||
a320e3c3 JEC |
535 | /* normalise to valid range*/ |
536 | if (opvsel < 3) | |
537 | opvsel = 3; | |
538 | if (opvsel > vselmax) | |
539 | opvsel = vselmax; | |
18039e0f | 540 | return opvsel - 3; |
518fb721 | 541 | } |
18039e0f | 542 | return -EINVAL; |
518fb721 GG |
543 | } |
544 | ||
1f904fd1 | 545 | static int tps65910_get_voltage_sel(struct regulator_dev *dev) |
518fb721 GG |
546 | { |
547 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
1f904fd1 | 548 | int reg, value, id = rdev_get_id(dev); |
518fb721 | 549 | |
a320e3c3 | 550 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
551 | if (reg < 0) |
552 | return reg; | |
553 | ||
3f7e8275 | 554 | value = tps65910_reg_read_locked(pmic, reg); |
518fb721 GG |
555 | if (value < 0) |
556 | return value; | |
557 | ||
558 | switch (id) { | |
559 | case TPS65910_REG_VIO: | |
560 | case TPS65910_REG_VDIG1: | |
561 | case TPS65910_REG_VDIG2: | |
562 | case TPS65910_REG_VPLL: | |
563 | case TPS65910_REG_VDAC: | |
564 | case TPS65910_REG_VAUX1: | |
565 | case TPS65910_REG_VAUX2: | |
566 | case TPS65910_REG_VAUX33: | |
567 | case TPS65910_REG_VMMC: | |
568 | value &= LDO_SEL_MASK; | |
569 | value >>= LDO_SEL_SHIFT; | |
570 | break; | |
571 | default: | |
572 | return -EINVAL; | |
573 | } | |
574 | ||
1f904fd1 | 575 | return value; |
518fb721 GG |
576 | } |
577 | ||
578 | static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) | |
579 | { | |
d9fe28f9 | 580 | return dev->desc->volt_table[0]; |
518fb721 GG |
581 | } |
582 | ||
1f904fd1 | 583 | static int tps65911_get_voltage_sel(struct regulator_dev *dev) |
a320e3c3 JEC |
584 | { |
585 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
1f904fd1 | 586 | int id = rdev_get_id(dev); |
a320e3c3 JEC |
587 | u8 value, reg; |
588 | ||
589 | reg = pmic->get_ctrl_reg(id); | |
590 | ||
3f7e8275 | 591 | value = tps65910_reg_read_locked(pmic, reg); |
a320e3c3 JEC |
592 | |
593 | switch (id) { | |
594 | case TPS65911_REG_LDO1: | |
595 | case TPS65911_REG_LDO2: | |
596 | case TPS65911_REG_LDO4: | |
597 | value &= LDO1_SEL_MASK; | |
598 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
599 | break; |
600 | case TPS65911_REG_LDO3: | |
601 | case TPS65911_REG_LDO5: | |
602 | case TPS65911_REG_LDO6: | |
603 | case TPS65911_REG_LDO7: | |
604 | case TPS65911_REG_LDO8: | |
605 | value &= LDO3_SEL_MASK; | |
606 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
607 | break; |
608 | case TPS65910_REG_VIO: | |
e882eae8 LD |
609 | value &= LDO_SEL_MASK; |
610 | value >>= LDO_SEL_SHIFT; | |
1f904fd1 | 611 | break; |
a320e3c3 JEC |
612 | default: |
613 | return -EINVAL; | |
614 | } | |
615 | ||
1f904fd1 | 616 | return value; |
a320e3c3 JEC |
617 | } |
618 | ||
94732b97 AL |
619 | static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, |
620 | unsigned selector) | |
518fb721 GG |
621 | { |
622 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
623 | int id = rdev_get_id(dev), vsel; | |
a320e3c3 | 624 | int dcdc_mult = 0; |
518fb721 | 625 | |
a320e3c3 JEC |
626 | switch (id) { |
627 | case TPS65910_REG_VDD1: | |
780dc9ba | 628 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
629 | if (dcdc_mult == 1) |
630 | dcdc_mult--; | |
780dc9ba | 631 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
518fb721 | 632 | |
518fb721 GG |
633 | tps65910_modify_bits(pmic, TPS65910_VDD1, |
634 | (dcdc_mult << VDD1_VGAIN_SEL_SHIFT), | |
635 | VDD1_VGAIN_SEL_MASK); | |
3f7e8275 | 636 | tps65910_reg_write_locked(pmic, TPS65910_VDD1_OP, vsel); |
a320e3c3 JEC |
637 | break; |
638 | case TPS65910_REG_VDD2: | |
780dc9ba | 639 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
640 | if (dcdc_mult == 1) |
641 | dcdc_mult--; | |
780dc9ba | 642 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
a320e3c3 | 643 | |
518fb721 GG |
644 | tps65910_modify_bits(pmic, TPS65910_VDD2, |
645 | (dcdc_mult << VDD2_VGAIN_SEL_SHIFT), | |
646 | VDD1_VGAIN_SEL_MASK); | |
3f7e8275 | 647 | tps65910_reg_write_locked(pmic, TPS65910_VDD2_OP, vsel); |
a320e3c3 JEC |
648 | break; |
649 | case TPS65911_REG_VDDCTRL: | |
c4632aed | 650 | vsel = selector + 3; |
3f7e8275 | 651 | tps65910_reg_write_locked(pmic, TPS65911_VDDCTRL_OP, vsel); |
518fb721 GG |
652 | } |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
94732b97 AL |
657 | static int tps65910_set_voltage_sel(struct regulator_dev *dev, |
658 | unsigned selector) | |
518fb721 GG |
659 | { |
660 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
661 | int reg, id = rdev_get_id(dev); | |
662 | ||
a320e3c3 | 663 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
664 | if (reg < 0) |
665 | return reg; | |
666 | ||
667 | switch (id) { | |
668 | case TPS65910_REG_VIO: | |
669 | case TPS65910_REG_VDIG1: | |
670 | case TPS65910_REG_VDIG2: | |
671 | case TPS65910_REG_VPLL: | |
672 | case TPS65910_REG_VDAC: | |
673 | case TPS65910_REG_VAUX1: | |
674 | case TPS65910_REG_VAUX2: | |
675 | case TPS65910_REG_VAUX33: | |
676 | case TPS65910_REG_VMMC: | |
677 | return tps65910_modify_bits(pmic, reg, | |
678 | (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); | |
679 | } | |
680 | ||
681 | return -EINVAL; | |
682 | } | |
683 | ||
94732b97 AL |
684 | static int tps65911_set_voltage_sel(struct regulator_dev *dev, |
685 | unsigned selector) | |
a320e3c3 JEC |
686 | { |
687 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
688 | int reg, id = rdev_get_id(dev); | |
689 | ||
690 | reg = pmic->get_ctrl_reg(id); | |
691 | if (reg < 0) | |
692 | return reg; | |
693 | ||
694 | switch (id) { | |
695 | case TPS65911_REG_LDO1: | |
696 | case TPS65911_REG_LDO2: | |
697 | case TPS65911_REG_LDO4: | |
698 | return tps65910_modify_bits(pmic, reg, | |
699 | (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK); | |
700 | case TPS65911_REG_LDO3: | |
701 | case TPS65911_REG_LDO5: | |
702 | case TPS65911_REG_LDO6: | |
703 | case TPS65911_REG_LDO7: | |
704 | case TPS65911_REG_LDO8: | |
a320e3c3 JEC |
705 | return tps65910_modify_bits(pmic, reg, |
706 | (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK); | |
e882eae8 LD |
707 | case TPS65910_REG_VIO: |
708 | return tps65910_modify_bits(pmic, reg, | |
709 | (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); | |
a320e3c3 JEC |
710 | } |
711 | ||
712 | return -EINVAL; | |
713 | } | |
714 | ||
715 | ||
518fb721 GG |
716 | static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, |
717 | unsigned selector) | |
718 | { | |
a320e3c3 | 719 | int volt, mult = 1, id = rdev_get_id(dev); |
518fb721 | 720 | |
a320e3c3 JEC |
721 | switch (id) { |
722 | case TPS65910_REG_VDD1: | |
723 | case TPS65910_REG_VDD2: | |
780dc9ba | 724 | mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 | 725 | volt = VDD1_2_MIN_VOLT + |
780dc9ba | 726 | (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET; |
d04156bc | 727 | break; |
a320e3c3 JEC |
728 | case TPS65911_REG_VDDCTRL: |
729 | volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); | |
d04156bc AL |
730 | break; |
731 | default: | |
732 | BUG(); | |
733 | return -EINVAL; | |
a320e3c3 | 734 | } |
518fb721 GG |
735 | |
736 | return volt * 100 * mult; | |
737 | } | |
738 | ||
a320e3c3 JEC |
739 | static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) |
740 | { | |
741 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
742 | int step_mv = 0, id = rdev_get_id(dev); | |
743 | ||
744 | switch(id) { | |
745 | case TPS65911_REG_LDO1: | |
746 | case TPS65911_REG_LDO2: | |
747 | case TPS65911_REG_LDO4: | |
748 | /* The first 5 values of the selector correspond to 1V */ | |
749 | if (selector < 5) | |
750 | selector = 0; | |
751 | else | |
752 | selector -= 4; | |
753 | ||
754 | step_mv = 50; | |
755 | break; | |
756 | case TPS65911_REG_LDO3: | |
757 | case TPS65911_REG_LDO5: | |
758 | case TPS65911_REG_LDO6: | |
759 | case TPS65911_REG_LDO7: | |
760 | case TPS65911_REG_LDO8: | |
761 | /* The first 3 values of the selector correspond to 1V */ | |
762 | if (selector < 3) | |
763 | selector = 0; | |
764 | else | |
765 | selector -= 2; | |
766 | ||
767 | step_mv = 100; | |
768 | break; | |
769 | case TPS65910_REG_VIO: | |
d9fe28f9 | 770 | return pmic->info[id]->voltage_table[selector]; |
a320e3c3 JEC |
771 | default: |
772 | return -EINVAL; | |
773 | } | |
774 | ||
775 | return (LDO_MIN_VOLT + selector * step_mv) * 1000; | |
776 | } | |
777 | ||
518fb721 GG |
778 | /* Regulator ops (except VRTC) */ |
779 | static struct regulator_ops tps65910_ops_dcdc = { | |
a40a9c43 AL |
780 | .is_enabled = regulator_is_enabled_regmap, |
781 | .enable = regulator_enable_regmap, | |
782 | .disable = regulator_disable_regmap, | |
518fb721 GG |
783 | .set_mode = tps65910_set_mode, |
784 | .get_mode = tps65910_get_mode, | |
18039e0f | 785 | .get_voltage_sel = tps65910_get_voltage_dcdc_sel, |
94732b97 | 786 | .set_voltage_sel = tps65910_set_voltage_dcdc_sel, |
01bc3a14 | 787 | .set_voltage_time_sel = regulator_set_voltage_time_sel, |
518fb721 GG |
788 | .list_voltage = tps65910_list_voltage_dcdc, |
789 | }; | |
790 | ||
791 | static struct regulator_ops tps65910_ops_vdd3 = { | |
a40a9c43 AL |
792 | .is_enabled = regulator_is_enabled_regmap, |
793 | .enable = regulator_enable_regmap, | |
794 | .disable = regulator_disable_regmap, | |
518fb721 GG |
795 | .set_mode = tps65910_set_mode, |
796 | .get_mode = tps65910_get_mode, | |
797 | .get_voltage = tps65910_get_voltage_vdd3, | |
d9fe28f9 | 798 | .list_voltage = regulator_list_voltage_table, |
518fb721 GG |
799 | }; |
800 | ||
801 | static struct regulator_ops tps65910_ops = { | |
a40a9c43 AL |
802 | .is_enabled = regulator_is_enabled_regmap, |
803 | .enable = regulator_enable_regmap, | |
804 | .disable = regulator_disable_regmap, | |
518fb721 GG |
805 | .set_mode = tps65910_set_mode, |
806 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 807 | .get_voltage_sel = tps65910_get_voltage_sel, |
94732b97 | 808 | .set_voltage_sel = tps65910_set_voltage_sel, |
d9fe28f9 | 809 | .list_voltage = regulator_list_voltage_table, |
518fb721 GG |
810 | }; |
811 | ||
a320e3c3 | 812 | static struct regulator_ops tps65911_ops = { |
a40a9c43 AL |
813 | .is_enabled = regulator_is_enabled_regmap, |
814 | .enable = regulator_enable_regmap, | |
815 | .disable = regulator_disable_regmap, | |
a320e3c3 JEC |
816 | .set_mode = tps65910_set_mode, |
817 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 818 | .get_voltage_sel = tps65911_get_voltage_sel, |
94732b97 | 819 | .set_voltage_sel = tps65911_set_voltage_sel, |
a320e3c3 JEC |
820 | .list_voltage = tps65911_list_voltage, |
821 | }; | |
822 | ||
1e0c66f4 LD |
823 | static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, |
824 | int id, int ext_sleep_config) | |
825 | { | |
826 | struct tps65910 *mfd = pmic->mfd; | |
827 | u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF; | |
828 | u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF); | |
829 | int ret; | |
830 | ||
831 | /* | |
832 | * Regulator can not be control from multiple external input EN1, EN2 | |
833 | * and EN3 together. | |
834 | */ | |
835 | if (ext_sleep_config & EXT_SLEEP_CONTROL) { | |
836 | int en_count; | |
837 | en_count = ((ext_sleep_config & | |
838 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0); | |
839 | en_count += ((ext_sleep_config & | |
840 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0); | |
841 | en_count += ((ext_sleep_config & | |
842 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0); | |
f30b0716 LD |
843 | en_count += ((ext_sleep_config & |
844 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0); | |
1e0c66f4 LD |
845 | if (en_count > 1) { |
846 | dev_err(mfd->dev, | |
847 | "External sleep control flag is not proper\n"); | |
848 | return -EINVAL; | |
849 | } | |
850 | } | |
851 | ||
852 | pmic->board_ext_control[id] = ext_sleep_config; | |
853 | ||
854 | /* External EN1 control */ | |
855 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) | |
3f7e8275 | 856 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
857 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
858 | else | |
3f7e8275 | 859 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
860 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
861 | if (ret < 0) { | |
862 | dev_err(mfd->dev, | |
863 | "Error in configuring external control EN1\n"); | |
864 | return ret; | |
865 | } | |
866 | ||
867 | /* External EN2 control */ | |
868 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) | |
3f7e8275 | 869 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
870 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
871 | else | |
3f7e8275 | 872 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
873 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
874 | if (ret < 0) { | |
875 | dev_err(mfd->dev, | |
876 | "Error in configuring external control EN2\n"); | |
877 | return ret; | |
878 | } | |
879 | ||
880 | /* External EN3 control for TPS65910 LDO only */ | |
881 | if ((tps65910_chip_id(mfd) == TPS65910) && | |
882 | (id >= TPS65910_REG_VDIG1)) { | |
883 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) | |
3f7e8275 | 884 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
885 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
886 | else | |
3f7e8275 | 887 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
888 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
889 | if (ret < 0) { | |
890 | dev_err(mfd->dev, | |
891 | "Error in configuring external control EN3\n"); | |
892 | return ret; | |
893 | } | |
894 | } | |
895 | ||
896 | /* Return if no external control is selected */ | |
897 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { | |
898 | /* Clear all sleep controls */ | |
3f7e8275 | 899 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
900 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
901 | if (!ret) | |
3f7e8275 | 902 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
903 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
904 | if (ret < 0) | |
905 | dev_err(mfd->dev, | |
906 | "Error in configuring SLEEP register\n"); | |
907 | return ret; | |
908 | } | |
909 | ||
910 | /* | |
911 | * For regulator that has separate operational and sleep register make | |
912 | * sure that operational is used and clear sleep register to turn | |
913 | * regulator off when external control is inactive | |
914 | */ | |
915 | if ((id == TPS65910_REG_VDD1) || | |
916 | (id == TPS65910_REG_VDD2) || | |
917 | ((id == TPS65911_REG_VDDCTRL) && | |
918 | (tps65910_chip_id(mfd) == TPS65911))) { | |
919 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; | |
920 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; | |
3f7e8275 RK |
921 | int opvsel = tps65910_reg_read_locked(pmic, op_reg_add); |
922 | int srvsel = tps65910_reg_read_locked(pmic, sr_reg_add); | |
1e0c66f4 LD |
923 | if (opvsel & VDD1_OP_CMD_MASK) { |
924 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; | |
3f7e8275 RK |
925 | ret = tps65910_reg_write_locked(pmic, op_reg_add, |
926 | reg_val); | |
1e0c66f4 LD |
927 | if (ret < 0) { |
928 | dev_err(mfd->dev, | |
929 | "Error in configuring op register\n"); | |
930 | return ret; | |
931 | } | |
932 | } | |
3f7e8275 | 933 | ret = tps65910_reg_write_locked(pmic, sr_reg_add, 0); |
1e0c66f4 LD |
934 | if (ret < 0) { |
935 | dev_err(mfd->dev, "Error in settting sr register\n"); | |
936 | return ret; | |
937 | } | |
938 | } | |
939 | ||
3f7e8275 | 940 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 | 941 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
f30b0716 LD |
942 | if (!ret) { |
943 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
3f7e8275 | 944 | ret = tps65910_reg_set_bits(mfd, |
f30b0716 LD |
945 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
946 | else | |
3f7e8275 | 947 | ret = tps65910_reg_clear_bits(mfd, |
f30b0716 LD |
948 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
949 | } | |
1e0c66f4 LD |
950 | if (ret < 0) |
951 | dev_err(mfd->dev, | |
952 | "Error in configuring SLEEP register\n"); | |
f30b0716 | 953 | |
1e0c66f4 LD |
954 | return ret; |
955 | } | |
956 | ||
6790178f RK |
957 | #ifdef CONFIG_OF |
958 | ||
959 | static struct of_regulator_match tps65910_matches[] = { | |
33a6943d LD |
960 | { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] }, |
961 | { .name = "vio", .driver_data = (void *) &tps65910_regs[1] }, | |
962 | { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] }, | |
963 | { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] }, | |
964 | { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] }, | |
965 | { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] }, | |
966 | { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] }, | |
967 | { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] }, | |
968 | { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] }, | |
969 | { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] }, | |
970 | { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] }, | |
971 | { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] }, | |
972 | { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] }, | |
6790178f RK |
973 | }; |
974 | ||
975 | static struct of_regulator_match tps65911_matches[] = { | |
33a6943d LD |
976 | { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] }, |
977 | { .name = "vio", .driver_data = (void *) &tps65911_regs[1] }, | |
978 | { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] }, | |
979 | { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] }, | |
980 | { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] }, | |
981 | { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] }, | |
982 | { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] }, | |
983 | { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] }, | |
984 | { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] }, | |
985 | { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] }, | |
986 | { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] }, | |
987 | { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] }, | |
988 | { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] }, | |
6790178f RK |
989 | }; |
990 | ||
991 | static struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
992 | struct platform_device *pdev, |
993 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f RK |
994 | { |
995 | struct tps65910_board *pmic_plat_data; | |
996 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
997 | struct device_node *np = pdev->dev.parent->of_node; | |
998 | struct device_node *regulators; | |
999 | struct of_regulator_match *matches; | |
1000 | unsigned int prop; | |
1001 | int idx = 0, ret, count; | |
1002 | ||
1003 | pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data), | |
1004 | GFP_KERNEL); | |
1005 | ||
1006 | if (!pmic_plat_data) { | |
1007 | dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n"); | |
1008 | return NULL; | |
1009 | } | |
1010 | ||
1011 | regulators = of_find_node_by_name(np, "regulators"); | |
92ab953b LD |
1012 | if (!regulators) { |
1013 | dev_err(&pdev->dev, "regulator node not found\n"); | |
1014 | return NULL; | |
1015 | } | |
6790178f RK |
1016 | |
1017 | switch (tps65910_chip_id(tps65910)) { | |
1018 | case TPS65910: | |
1019 | count = ARRAY_SIZE(tps65910_matches); | |
1020 | matches = tps65910_matches; | |
1021 | break; | |
1022 | case TPS65911: | |
1023 | count = ARRAY_SIZE(tps65911_matches); | |
1024 | matches = tps65911_matches; | |
1025 | break; | |
1026 | default: | |
7e9a57e6 | 1027 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
6790178f RK |
1028 | return NULL; |
1029 | } | |
1030 | ||
1031 | ret = of_regulator_match(pdev->dev.parent, regulators, matches, count); | |
1032 | if (ret < 0) { | |
1033 | dev_err(&pdev->dev, "Error parsing regulator init data: %d\n", | |
1034 | ret); | |
1035 | return NULL; | |
1036 | } | |
1037 | ||
84df8c12 LD |
1038 | *tps65910_reg_matches = matches; |
1039 | ||
6790178f | 1040 | for (idx = 0; idx < count; idx++) { |
19228a6a LD |
1041 | struct tps_info *info = matches[idx].driver_data; |
1042 | char in_supply[32]; /* 32 is max size of property name */ | |
1043 | ||
6790178f RK |
1044 | if (!matches[idx].init_data || !matches[idx].of_node) |
1045 | continue; | |
1046 | ||
1047 | pmic_plat_data->tps65910_pmic_init_data[idx] = | |
1048 | matches[idx].init_data; | |
1049 | ||
1050 | ret = of_property_read_u32(matches[idx].of_node, | |
1051 | "ti,regulator-ext-sleep-control", &prop); | |
1052 | if (!ret) | |
1053 | pmic_plat_data->regulator_ext_sleep_control[idx] = prop; | |
19228a6a LD |
1054 | |
1055 | if (info->vin_name) { | |
1056 | snprintf(in_supply, 32, "%s-supply", info->vin_name); | |
1057 | if (of_find_property(np, in_supply, 0)) | |
1058 | pmic_plat_data->input_supply[idx] = | |
1059 | info->vin_name; | |
1060 | } | |
6790178f RK |
1061 | } |
1062 | ||
1063 | return pmic_plat_data; | |
1064 | } | |
1065 | #else | |
1066 | static inline struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
1067 | struct platform_device *pdev, |
1068 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f | 1069 | { |
84df8c12 | 1070 | *tps65910_reg_matches = NULL; |
74ea0e59 | 1071 | return NULL; |
6790178f RK |
1072 | } |
1073 | #endif | |
1074 | ||
518fb721 GG |
1075 | static __devinit int tps65910_probe(struct platform_device *pdev) |
1076 | { | |
1077 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c172708d | 1078 | struct regulator_config config = { }; |
a320e3c3 | 1079 | struct tps_info *info; |
518fb721 GG |
1080 | struct regulator_init_data *reg_data; |
1081 | struct regulator_dev *rdev; | |
1082 | struct tps65910_reg *pmic; | |
1083 | struct tps65910_board *pmic_plat_data; | |
84df8c12 | 1084 | struct of_regulator_match *tps65910_reg_matches = NULL; |
518fb721 GG |
1085 | int i, err; |
1086 | ||
1087 | pmic_plat_data = dev_get_platdata(tps65910->dev); | |
6790178f | 1088 | if (!pmic_plat_data && tps65910->dev->of_node) |
84df8c12 LD |
1089 | pmic_plat_data = tps65910_parse_dt_reg_data(pdev, |
1090 | &tps65910_reg_matches); | |
6790178f | 1091 | |
7e9a57e6 LD |
1092 | if (!pmic_plat_data) { |
1093 | dev_err(&pdev->dev, "Platform data not found\n"); | |
518fb721 | 1094 | return -EINVAL; |
7e9a57e6 | 1095 | } |
518fb721 | 1096 | |
9eb0c421 | 1097 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); |
7e9a57e6 LD |
1098 | if (!pmic) { |
1099 | dev_err(&pdev->dev, "Memory allocation failed for pmic\n"); | |
518fb721 | 1100 | return -ENOMEM; |
7e9a57e6 | 1101 | } |
518fb721 GG |
1102 | |
1103 | mutex_init(&pmic->mutex); | |
1104 | pmic->mfd = tps65910; | |
1105 | platform_set_drvdata(pdev, pmic); | |
1106 | ||
1107 | /* Give control of all register to control port */ | |
3f7e8275 | 1108 | tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL, |
518fb721 GG |
1109 | DEVCTRL_SR_CTL_I2C_SEL_MASK); |
1110 | ||
a320e3c3 JEC |
1111 | switch(tps65910_chip_id(tps65910)) { |
1112 | case TPS65910: | |
1113 | pmic->get_ctrl_reg = &tps65910_get_ctrl_register; | |
39aa9b6e | 1114 | pmic->num_regulators = ARRAY_SIZE(tps65910_regs); |
1e0c66f4 | 1115 | pmic->ext_sleep_control = tps65910_ext_sleep_control; |
a320e3c3 | 1116 | info = tps65910_regs; |
d04156bc | 1117 | break; |
a320e3c3 JEC |
1118 | case TPS65911: |
1119 | pmic->get_ctrl_reg = &tps65911_get_ctrl_register; | |
39aa9b6e | 1120 | pmic->num_regulators = ARRAY_SIZE(tps65911_regs); |
1e0c66f4 | 1121 | pmic->ext_sleep_control = tps65911_ext_sleep_control; |
a320e3c3 | 1122 | info = tps65911_regs; |
d04156bc | 1123 | break; |
a320e3c3 | 1124 | default: |
7e9a57e6 | 1125 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
a320e3c3 JEC |
1126 | return -ENODEV; |
1127 | } | |
1128 | ||
68d8c1cd | 1129 | pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1130 | sizeof(struct regulator_desc), GFP_KERNEL); |
1131 | if (!pmic->desc) { | |
68d8c1cd LD |
1132 | dev_err(&pdev->dev, "Memory alloc fails for desc\n"); |
1133 | return -ENOMEM; | |
39aa9b6e AL |
1134 | } |
1135 | ||
68d8c1cd | 1136 | pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1137 | sizeof(struct tps_info *), GFP_KERNEL); |
1138 | if (!pmic->info) { | |
68d8c1cd LD |
1139 | dev_err(&pdev->dev, "Memory alloc fails for info\n"); |
1140 | return -ENOMEM; | |
39aa9b6e AL |
1141 | } |
1142 | ||
68d8c1cd | 1143 | pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1144 | sizeof(struct regulator_dev *), GFP_KERNEL); |
1145 | if (!pmic->rdev) { | |
68d8c1cd LD |
1146 | dev_err(&pdev->dev, "Memory alloc fails for rdev\n"); |
1147 | return -ENOMEM; | |
39aa9b6e AL |
1148 | } |
1149 | ||
c1fc1480 KM |
1150 | for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS; |
1151 | i++, info++) { | |
1152 | ||
1153 | reg_data = pmic_plat_data->tps65910_pmic_init_data[i]; | |
1154 | ||
1155 | /* Regulator API handles empty constraints but not NULL | |
1156 | * constraints */ | |
1157 | if (!reg_data) | |
1158 | continue; | |
1159 | ||
518fb721 GG |
1160 | /* Register the regulators */ |
1161 | pmic->info[i] = info; | |
1162 | ||
1163 | pmic->desc[i].name = info->name; | |
19228a6a | 1164 | pmic->desc[i].supply_name = pmic_plat_data->input_supply[i]; |
77fa44d0 | 1165 | pmic->desc[i].id = i; |
7d38a3cb | 1166 | pmic->desc[i].n_voltages = info->n_voltages; |
94f48ab3 | 1167 | pmic->desc[i].enable_time = info->enable_time_us; |
518fb721 | 1168 | |
a320e3c3 | 1169 | if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { |
518fb721 | 1170 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
780dc9ba AM |
1171 | pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE * |
1172 | VDD1_2_NUM_VOLT_COARSE; | |
01bc3a14 | 1173 | pmic->desc[i].ramp_delay = 12500; |
a320e3c3 | 1174 | } else if (i == TPS65910_REG_VDD3) { |
01bc3a14 | 1175 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1176 | pmic->desc[i].ops = &tps65910_ops_vdd3; |
d9fe28f9 | 1177 | pmic->desc[i].volt_table = info->voltage_table; |
01bc3a14 | 1178 | } else { |
a320e3c3 | 1179 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
01bc3a14 AL |
1180 | pmic->desc[i].ramp_delay = 5000; |
1181 | } | |
a320e3c3 | 1182 | } else { |
d9fe28f9 | 1183 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1184 | pmic->desc[i].ops = &tps65910_ops; |
d9fe28f9 AL |
1185 | pmic->desc[i].volt_table = info->voltage_table; |
1186 | } else { | |
a320e3c3 | 1187 | pmic->desc[i].ops = &tps65911_ops; |
d9fe28f9 | 1188 | } |
a320e3c3 | 1189 | } |
518fb721 | 1190 | |
1e0c66f4 LD |
1191 | err = tps65910_set_ext_sleep_config(pmic, i, |
1192 | pmic_plat_data->regulator_ext_sleep_control[i]); | |
1193 | /* | |
1194 | * Failing on regulator for configuring externally control | |
1195 | * is not a serious issue, just throw warning. | |
1196 | */ | |
1197 | if (err < 0) | |
1198 | dev_warn(tps65910->dev, | |
1199 | "Failed to initialise ext control config\n"); | |
1200 | ||
518fb721 GG |
1201 | pmic->desc[i].type = REGULATOR_VOLTAGE; |
1202 | pmic->desc[i].owner = THIS_MODULE; | |
a40a9c43 AL |
1203 | pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); |
1204 | pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; | |
518fb721 | 1205 | |
c172708d MB |
1206 | config.dev = tps65910->dev; |
1207 | config.init_data = reg_data; | |
1208 | config.driver_data = pmic; | |
a40a9c43 | 1209 | config.regmap = tps65910->regmap; |
c172708d | 1210 | |
84df8c12 LD |
1211 | if (tps65910_reg_matches) |
1212 | config.of_node = tps65910_reg_matches[i].of_node; | |
6790178f | 1213 | |
c172708d | 1214 | rdev = regulator_register(&pmic->desc[i], &config); |
518fb721 GG |
1215 | if (IS_ERR(rdev)) { |
1216 | dev_err(tps65910->dev, | |
1217 | "failed to register %s regulator\n", | |
1218 | pdev->name); | |
1219 | err = PTR_ERR(rdev); | |
39aa9b6e | 1220 | goto err_unregister_regulator; |
518fb721 GG |
1221 | } |
1222 | ||
1223 | /* Save regulator for cleanup */ | |
1224 | pmic->rdev[i] = rdev; | |
1225 | } | |
1226 | return 0; | |
1227 | ||
39aa9b6e | 1228 | err_unregister_regulator: |
518fb721 GG |
1229 | while (--i >= 0) |
1230 | regulator_unregister(pmic->rdev[i]); | |
518fb721 GG |
1231 | return err; |
1232 | } | |
1233 | ||
1234 | static int __devexit tps65910_remove(struct platform_device *pdev) | |
1235 | { | |
39aa9b6e | 1236 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); |
518fb721 GG |
1237 | int i; |
1238 | ||
39aa9b6e AL |
1239 | for (i = 0; i < pmic->num_regulators; i++) |
1240 | regulator_unregister(pmic->rdev[i]); | |
518fb721 | 1241 | |
518fb721 GG |
1242 | return 0; |
1243 | } | |
1244 | ||
1e0c66f4 LD |
1245 | static void tps65910_shutdown(struct platform_device *pdev) |
1246 | { | |
1247 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); | |
1248 | int i; | |
1249 | ||
1250 | /* | |
1251 | * Before bootloader jumps to kernel, it makes sure that required | |
1252 | * external control signals are in desired state so that given rails | |
1253 | * can be configure accordingly. | |
1254 | * If rails are configured to be controlled from external control | |
1255 | * then before shutting down/rebooting the system, the external | |
1256 | * control configuration need to be remove from the rails so that | |
1257 | * its output will be available as per register programming even | |
1258 | * if external controls are removed. This is require when the POR | |
1259 | * value of the control signals are not in active state and before | |
1260 | * bootloader initializes it, the system requires the rail output | |
1261 | * to be active for booting. | |
1262 | */ | |
1263 | for (i = 0; i < pmic->num_regulators; i++) { | |
1264 | int err; | |
1265 | if (!pmic->rdev[i]) | |
1266 | continue; | |
1267 | ||
1268 | err = tps65910_set_ext_sleep_config(pmic, i, 0); | |
1269 | if (err < 0) | |
1270 | dev_err(&pdev->dev, | |
1271 | "Error in clearing external control\n"); | |
1272 | } | |
1273 | } | |
1274 | ||
518fb721 GG |
1275 | static struct platform_driver tps65910_driver = { |
1276 | .driver = { | |
1277 | .name = "tps65910-pmic", | |
1278 | .owner = THIS_MODULE, | |
1279 | }, | |
1280 | .probe = tps65910_probe, | |
1281 | .remove = __devexit_p(tps65910_remove), | |
1e0c66f4 | 1282 | .shutdown = tps65910_shutdown, |
518fb721 GG |
1283 | }; |
1284 | ||
1285 | static int __init tps65910_init(void) | |
1286 | { | |
1287 | return platform_driver_register(&tps65910_driver); | |
1288 | } | |
1289 | subsys_initcall(tps65910_init); | |
1290 | ||
1291 | static void __exit tps65910_cleanup(void) | |
1292 | { | |
1293 | platform_driver_unregister(&tps65910_driver); | |
1294 | } | |
1295 | module_exit(tps65910_cleanup); | |
1296 | ||
1297 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
ae0e6544 | 1298 | MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver"); |
518fb721 GG |
1299 | MODULE_LICENSE("GPL v2"); |
1300 | MODULE_ALIAS("platform:tps65910-pmic"); |