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Commit | Line | Data |
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a3a42806 GC |
1 | /* |
2 | * RTC driver for the Armada 38x Marvell SoCs | |
3 | * | |
4 | * Copyright (C) 2015 Marvell | |
5 | * | |
6 | * Gregory Clement <gregory.clement@free-electrons.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of the | |
11 | * License, or (at your option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
75faea91 | 19 | #include <linux/of_device.h> |
a3a42806 GC |
20 | #include <linux/platform_device.h> |
21 | #include <linux/rtc.h> | |
22 | ||
23 | #define RTC_STATUS 0x0 | |
24 | #define RTC_STATUS_ALARM1 BIT(0) | |
25 | #define RTC_STATUS_ALARM2 BIT(1) | |
26 | #define RTC_IRQ1_CONF 0x4 | |
34f54f57 | 27 | #define RTC_IRQ2_CONF 0x8 |
75faea91 GC |
28 | #define RTC_IRQ_AL_EN BIT(0) |
29 | #define RTC_IRQ_FREQ_EN BIT(1) | |
30 | #define RTC_IRQ_FREQ_1HZ BIT(2) | |
31 | ||
a3a42806 GC |
32 | #define RTC_TIME 0xC |
33 | #define RTC_ALARM1 0x10 | |
34f54f57 GC |
34 | #define RTC_ALARM2 0x14 |
35 | ||
36 | /* Armada38x SoC registers */ | |
75faea91 GC |
37 | #define RTC_38X_BRIDGE_TIMING_CTL 0x0 |
38 | #define RTC_38X_PERIOD_OFFS 0 | |
39 | #define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS) | |
40 | #define RTC_38X_READ_DELAY_OFFS 26 | |
41 | #define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS) | |
42 | ||
34f54f57 GC |
43 | /* Armada 7K/8K registers */ |
44 | #define RTC_8K_BRIDGE_TIMING_CTL0 0x0 | |
45 | #define RTC_8K_WRCLK_PERIOD_OFFS 0 | |
46 | #define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS) | |
47 | #define RTC_8K_WRCLK_SETUP_OFFS 16 | |
48 | #define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS) | |
49 | #define RTC_8K_BRIDGE_TIMING_CTL1 0x4 | |
50 | #define RTC_8K_READ_DELAY_OFFS 0 | |
51 | #define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS) | |
52 | ||
53 | #define RTC_8K_ISR 0x10 | |
54 | #define RTC_8K_IMR 0x14 | |
55 | #define RTC_8K_ALARM2 BIT(0) | |
56 | ||
75faea91 GC |
57 | #define SOC_RTC_INTERRUPT 0x8 |
58 | #define SOC_RTC_ALARM1 BIT(0) | |
59 | #define SOC_RTC_ALARM2 BIT(1) | |
60 | #define SOC_RTC_ALARM1_MASK BIT(2) | |
61 | #define SOC_RTC_ALARM2_MASK BIT(3) | |
a3a42806 | 62 | |
844a3073 GC |
63 | #define SAMPLE_NR 100 |
64 | ||
65 | struct value_to_freq { | |
66 | u32 value; | |
67 | u8 freq; | |
68 | }; | |
69 | ||
a3a42806 GC |
70 | struct armada38x_rtc { |
71 | struct rtc_device *rtc_dev; | |
72 | void __iomem *regs; | |
73 | void __iomem *regs_soc; | |
74 | spinlock_t lock; | |
75 | int irq; | |
844a3073 | 76 | struct value_to_freq *val_to_freq; |
75faea91 GC |
77 | struct armada38x_rtc_data *data; |
78 | }; | |
79 | ||
80 | #define ALARM1 0 | |
34f54f57 GC |
81 | #define ALARM2 1 |
82 | ||
75faea91 GC |
83 | #define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32)) |
84 | ||
85 | struct armada38x_rtc_data { | |
86 | /* Initialize the RTC-MBUS bridge timing */ | |
87 | void (*update_mbus_timing)(struct armada38x_rtc *rtc); | |
88 | u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg); | |
89 | void (*clear_isr)(struct armada38x_rtc *rtc); | |
90 | void (*unmask_interrupt)(struct armada38x_rtc *rtc); | |
91 | u32 alarm; | |
a3a42806 GC |
92 | }; |
93 | ||
94 | /* | |
95 | * According to the datasheet, the OS should wait 5us after every | |
96 | * register write to the RTC hard macro so that the required update | |
97 | * can occur without holding off the system bus | |
844a3073 GC |
98 | * According to errata RES-3124064, Write to any RTC register |
99 | * may fail. As a workaround, before writing to RTC | |
100 | * register, issue a dummy write of 0x0 twice to RTC Status | |
101 | * register. | |
a3a42806 | 102 | */ |
844a3073 | 103 | |
a3a42806 GC |
104 | static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset) |
105 | { | |
844a3073 GC |
106 | writel(0, rtc->regs + RTC_STATUS); |
107 | writel(0, rtc->regs + RTC_STATUS); | |
a3a42806 GC |
108 | writel(val, rtc->regs + offset); |
109 | udelay(5); | |
110 | } | |
111 | ||
844a3073 | 112 | /* Update RTC-MBUS bridge timing parameters */ |
75faea91 | 113 | static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc) |
844a3073 GC |
114 | { |
115 | u32 reg; | |
116 | ||
75faea91 GC |
117 | reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); |
118 | reg &= ~RTC_38X_PERIOD_MASK; | |
119 | reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */ | |
120 | reg &= ~RTC_38X_READ_DELAY_MASK; | |
121 | reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */ | |
122 | writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); | |
844a3073 GC |
123 | } |
124 | ||
34f54f57 GC |
125 | static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc) |
126 | { | |
127 | u32 reg; | |
128 | ||
129 | reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0); | |
130 | reg &= ~RTC_8K_WRCLK_PERIOD_MASK; | |
131 | reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS; | |
132 | reg &= ~RTC_8K_WRCLK_SETUP_MASK; | |
133 | reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS; | |
134 | writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0); | |
135 | ||
136 | reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1); | |
137 | reg &= ~RTC_8K_READ_DELAY_MASK; | |
138 | reg |= 0x3F << RTC_8K_READ_DELAY_OFFS; | |
139 | writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1); | |
140 | } | |
141 | ||
142 | static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg) | |
143 | { | |
144 | return readl(rtc->regs + rtc_reg); | |
145 | } | |
146 | ||
75faea91 | 147 | static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg) |
844a3073 GC |
148 | { |
149 | int i, index_max = 0, max = 0; | |
150 | ||
151 | for (i = 0; i < SAMPLE_NR; i++) { | |
152 | rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg); | |
153 | rtc->val_to_freq[i].freq = 0; | |
154 | } | |
155 | ||
156 | for (i = 0; i < SAMPLE_NR; i++) { | |
157 | int j = 0; | |
158 | u32 value = rtc->val_to_freq[i].value; | |
159 | ||
160 | while (rtc->val_to_freq[j].freq) { | |
161 | if (rtc->val_to_freq[j].value == value) { | |
162 | rtc->val_to_freq[j].freq++; | |
163 | break; | |
164 | } | |
165 | j++; | |
166 | } | |
167 | ||
168 | if (!rtc->val_to_freq[j].freq) { | |
169 | rtc->val_to_freq[j].value = value; | |
170 | rtc->val_to_freq[j].freq = 1; | |
171 | } | |
172 | ||
173 | if (rtc->val_to_freq[j].freq > max) { | |
174 | index_max = j; | |
175 | max = rtc->val_to_freq[j].freq; | |
176 | } | |
177 | ||
178 | /* | |
179 | * If a value already has half of the sample this is the most | |
180 | * frequent one and we can stop the research right now | |
181 | */ | |
182 | if (max > SAMPLE_NR / 2) | |
183 | break; | |
184 | } | |
185 | ||
186 | return rtc->val_to_freq[index_max].value; | |
187 | } | |
188 | ||
75faea91 GC |
189 | static void armada38x_clear_isr(struct armada38x_rtc *rtc) |
190 | { | |
191 | u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); | |
192 | ||
193 | writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT); | |
194 | } | |
195 | ||
196 | static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc) | |
197 | { | |
198 | u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); | |
199 | ||
200 | writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT); | |
201 | } | |
34f54f57 GC |
202 | |
203 | static void armada8k_clear_isr(struct armada38x_rtc *rtc) | |
204 | { | |
205 | writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR); | |
206 | } | |
207 | ||
208 | static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc) | |
209 | { | |
210 | writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR); | |
211 | } | |
212 | ||
a3a42806 GC |
213 | static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm) |
214 | { | |
215 | struct armada38x_rtc *rtc = dev_get_drvdata(dev); | |
844a3073 | 216 | unsigned long time, flags; |
a3a42806 | 217 | |
0c6e7183 | 218 | spin_lock_irqsave(&rtc->lock, flags); |
75faea91 | 219 | time = rtc->data->read_rtc_reg(rtc, RTC_TIME); |
0c6e7183 | 220 | spin_unlock_irqrestore(&rtc->lock, flags); |
a3a42806 | 221 | |
844a3073 | 222 | rtc_time_to_tm(time, tm); |
a3a42806 GC |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
228 | { | |
229 | struct armada38x_rtc *rtc = dev_get_drvdata(dev); | |
230 | int ret = 0; | |
0c6e7183 | 231 | unsigned long time, flags; |
a3a42806 GC |
232 | |
233 | ret = rtc_tm_to_time(tm, &time); | |
234 | ||
235 | if (ret) | |
236 | goto out; | |
844a3073 | 237 | |
0c6e7183 | 238 | spin_lock_irqsave(&rtc->lock, flags); |
a3a42806 | 239 | rtc_delayed_write(time, rtc, RTC_TIME); |
0c6e7183 | 240 | spin_unlock_irqrestore(&rtc->lock, flags); |
a3a42806 | 241 | |
a3a42806 GC |
242 | out: |
243 | return ret; | |
244 | } | |
245 | ||
246 | static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
247 | { | |
248 | struct armada38x_rtc *rtc = dev_get_drvdata(dev); | |
249 | unsigned long time, flags; | |
75faea91 GC |
250 | u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm); |
251 | u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); | |
a3a42806 GC |
252 | u32 val; |
253 | ||
254 | spin_lock_irqsave(&rtc->lock, flags); | |
255 | ||
75faea91 GC |
256 | time = rtc->data->read_rtc_reg(rtc, reg); |
257 | val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN; | |
a3a42806 GC |
258 | |
259 | spin_unlock_irqrestore(&rtc->lock, flags); | |
260 | ||
261 | alrm->enabled = val ? 1 : 0; | |
262 | rtc_time_to_tm(time, &alrm->time); | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
268 | { | |
269 | struct armada38x_rtc *rtc = dev_get_drvdata(dev); | |
75faea91 GC |
270 | u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm); |
271 | u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); | |
a3a42806 GC |
272 | unsigned long time, flags; |
273 | int ret = 0; | |
a3a42806 GC |
274 | |
275 | ret = rtc_tm_to_time(&alrm->time, &time); | |
276 | ||
277 | if (ret) | |
278 | goto out; | |
279 | ||
280 | spin_lock_irqsave(&rtc->lock, flags); | |
281 | ||
75faea91 | 282 | rtc_delayed_write(time, rtc, reg); |
a3a42806 GC |
283 | |
284 | if (alrm->enabled) { | |
75faea91 GC |
285 | rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq); |
286 | rtc->data->unmask_interrupt(rtc); | |
a3a42806 GC |
287 | } |
288 | ||
289 | spin_unlock_irqrestore(&rtc->lock, flags); | |
290 | ||
291 | out: | |
292 | return ret; | |
293 | } | |
294 | ||
295 | static int armada38x_rtc_alarm_irq_enable(struct device *dev, | |
296 | unsigned int enabled) | |
297 | { | |
298 | struct armada38x_rtc *rtc = dev_get_drvdata(dev); | |
75faea91 | 299 | u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); |
a3a42806 GC |
300 | unsigned long flags; |
301 | ||
302 | spin_lock_irqsave(&rtc->lock, flags); | |
303 | ||
304 | if (enabled) | |
75faea91 | 305 | rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq); |
a3a42806 | 306 | else |
75faea91 | 307 | rtc_delayed_write(0, rtc, reg_irq); |
a3a42806 GC |
308 | |
309 | spin_unlock_irqrestore(&rtc->lock, flags); | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data) | |
315 | { | |
316 | struct armada38x_rtc *rtc = data; | |
317 | u32 val; | |
318 | int event = RTC_IRQF | RTC_AF; | |
75faea91 | 319 | u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); |
a3a42806 GC |
320 | |
321 | dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq); | |
322 | ||
323 | spin_lock(&rtc->lock); | |
324 | ||
75faea91 GC |
325 | rtc->data->clear_isr(rtc); |
326 | val = rtc->data->read_rtc_reg(rtc, reg_irq); | |
327 | /* disable all the interrupts for alarm*/ | |
328 | rtc_delayed_write(0, rtc, reg_irq); | |
a3a42806 | 329 | /* Ack the event */ |
75faea91 | 330 | rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS); |
a3a42806 GC |
331 | |
332 | spin_unlock(&rtc->lock); | |
333 | ||
75faea91 GC |
334 | if (val & RTC_IRQ_FREQ_EN) { |
335 | if (val & RTC_IRQ_FREQ_1HZ) | |
a3a42806 GC |
336 | event |= RTC_UF; |
337 | else | |
338 | event |= RTC_PF; | |
339 | } | |
340 | ||
341 | rtc_update_irq(rtc->rtc_dev, 1, event); | |
342 | ||
343 | return IRQ_HANDLED; | |
344 | } | |
345 | ||
d748c981 | 346 | static const struct rtc_class_ops armada38x_rtc_ops = { |
a3a42806 GC |
347 | .read_time = armada38x_rtc_read_time, |
348 | .set_time = armada38x_rtc_set_time, | |
349 | .read_alarm = armada38x_rtc_read_alarm, | |
350 | .set_alarm = armada38x_rtc_set_alarm, | |
351 | .alarm_irq_enable = armada38x_rtc_alarm_irq_enable, | |
352 | }; | |
353 | ||
d748c981 RK |
354 | static const struct rtc_class_ops armada38x_rtc_ops_noirq = { |
355 | .read_time = armada38x_rtc_read_time, | |
356 | .set_time = armada38x_rtc_set_time, | |
357 | .read_alarm = armada38x_rtc_read_alarm, | |
358 | }; | |
359 | ||
75faea91 GC |
360 | static const struct armada38x_rtc_data armada38x_data = { |
361 | .update_mbus_timing = rtc_update_38x_mbus_timing_params, | |
362 | .read_rtc_reg = read_rtc_register_38x_wa, | |
363 | .clear_isr = armada38x_clear_isr, | |
364 | .unmask_interrupt = armada38x_unmask_interrupt, | |
365 | .alarm = ALARM1, | |
366 | }; | |
367 | ||
34f54f57 GC |
368 | static const struct armada38x_rtc_data armada8k_data = { |
369 | .update_mbus_timing = rtc_update_8k_mbus_timing_params, | |
370 | .read_rtc_reg = read_rtc_register, | |
371 | .clear_isr = armada8k_clear_isr, | |
372 | .unmask_interrupt = armada8k_unmask_interrupt, | |
373 | .alarm = ALARM2, | |
374 | }; | |
375 | ||
75faea91 GC |
376 | #ifdef CONFIG_OF |
377 | static const struct of_device_id armada38x_rtc_of_match_table[] = { | |
378 | { | |
379 | .compatible = "marvell,armada-380-rtc", | |
380 | .data = &armada38x_data, | |
381 | }, | |
34f54f57 GC |
382 | { |
383 | .compatible = "marvell,armada-8k-rtc", | |
384 | .data = &armada8k_data, | |
385 | }, | |
75faea91 GC |
386 | {} |
387 | }; | |
388 | MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table); | |
389 | #endif | |
390 | ||
a3a42806 GC |
391 | static __init int armada38x_rtc_probe(struct platform_device *pdev) |
392 | { | |
d748c981 | 393 | const struct rtc_class_ops *ops; |
a3a42806 GC |
394 | struct resource *res; |
395 | struct armada38x_rtc *rtc; | |
75faea91 | 396 | const struct of_device_id *match; |
a3a42806 GC |
397 | int ret; |
398 | ||
75faea91 GC |
399 | match = of_match_device(armada38x_rtc_of_match_table, &pdev->dev); |
400 | if (!match) | |
401 | return -ENODEV; | |
402 | ||
a3a42806 GC |
403 | rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc), |
404 | GFP_KERNEL); | |
405 | if (!rtc) | |
406 | return -ENOMEM; | |
407 | ||
844a3073 GC |
408 | rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR, |
409 | sizeof(struct value_to_freq), GFP_KERNEL); | |
410 | if (!rtc->val_to_freq) | |
411 | return -ENOMEM; | |
412 | ||
a3a42806 GC |
413 | spin_lock_init(&rtc->lock); |
414 | ||
415 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc"); | |
416 | rtc->regs = devm_ioremap_resource(&pdev->dev, res); | |
417 | if (IS_ERR(rtc->regs)) | |
418 | return PTR_ERR(rtc->regs); | |
419 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc"); | |
420 | rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res); | |
421 | if (IS_ERR(rtc->regs_soc)) | |
422 | return PTR_ERR(rtc->regs_soc); | |
423 | ||
424 | rtc->irq = platform_get_irq(pdev, 0); | |
425 | ||
426 | if (rtc->irq < 0) { | |
427 | dev_err(&pdev->dev, "no irq\n"); | |
428 | return rtc->irq; | |
429 | } | |
430 | if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq, | |
431 | 0, pdev->name, rtc) < 0) { | |
432 | dev_warn(&pdev->dev, "Interrupt not available.\n"); | |
433 | rtc->irq = -1; | |
d748c981 RK |
434 | } |
435 | platform_set_drvdata(pdev, rtc); | |
436 | ||
437 | if (rtc->irq != -1) { | |
438 | device_init_wakeup(&pdev->dev, 1); | |
439 | ops = &armada38x_rtc_ops; | |
440 | } else { | |
a3a42806 GC |
441 | /* |
442 | * If there is no interrupt available then we can't | |
443 | * use the alarm | |
444 | */ | |
d748c981 | 445 | ops = &armada38x_rtc_ops_noirq; |
a3a42806 | 446 | } |
75faea91 GC |
447 | rtc->data = (struct armada38x_rtc_data *)match->data; |
448 | ||
a3a42806 | 449 | |
844a3073 | 450 | /* Update RTC-MBUS bridge timing parameters */ |
75faea91 | 451 | rtc->data->update_mbus_timing(rtc); |
844a3073 | 452 | |
a3a42806 | 453 | rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name, |
d748c981 | 454 | ops, THIS_MODULE); |
a3a42806 GC |
455 | if (IS_ERR(rtc->rtc_dev)) { |
456 | ret = PTR_ERR(rtc->rtc_dev); | |
457 | dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); | |
458 | return ret; | |
459 | } | |
460 | return 0; | |
461 | } | |
462 | ||
463 | #ifdef CONFIG_PM_SLEEP | |
464 | static int armada38x_rtc_suspend(struct device *dev) | |
465 | { | |
466 | if (device_may_wakeup(dev)) { | |
467 | struct armada38x_rtc *rtc = dev_get_drvdata(dev); | |
468 | ||
469 | return enable_irq_wake(rtc->irq); | |
470 | } | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int armada38x_rtc_resume(struct device *dev) | |
476 | { | |
477 | if (device_may_wakeup(dev)) { | |
478 | struct armada38x_rtc *rtc = dev_get_drvdata(dev); | |
479 | ||
844a3073 | 480 | /* Update RTC-MBUS bridge timing parameters */ |
75faea91 | 481 | rtc->data->update_mbus_timing(rtc); |
844a3073 | 482 | |
a3a42806 GC |
483 | return disable_irq_wake(rtc->irq); |
484 | } | |
485 | ||
486 | return 0; | |
487 | } | |
488 | #endif | |
489 | ||
490 | static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops, | |
491 | armada38x_rtc_suspend, armada38x_rtc_resume); | |
492 | ||
a3a42806 GC |
493 | static struct platform_driver armada38x_rtc_driver = { |
494 | .driver = { | |
495 | .name = "armada38x-rtc", | |
496 | .pm = &armada38x_rtc_pm_ops, | |
497 | .of_match_table = of_match_ptr(armada38x_rtc_of_match_table), | |
498 | }, | |
499 | }; | |
500 | ||
501 | module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe); | |
502 | ||
503 | MODULE_DESCRIPTION("Marvell Armada 38x RTC driver"); | |
504 | MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>"); | |
505 | MODULE_LICENSE("GPL"); |