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1fcbe42c JG |
1 | /* |
2 | * SPI Driver for Microchip MCP795 RTC | |
3 | * | |
4 | * Copyright (C) Josef Gajdusek <atx@atx.name> | |
5 | * | |
6 | * based on other Linux RTC drivers | |
7 | * | |
8 | * Device datasheet: | |
9 | * http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
d3e59259 | 15 | */ |
1fcbe42c JG |
16 | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/printk.h> | |
21 | #include <linux/spi/spi.h> | |
22 | #include <linux/rtc.h> | |
7f8a5892 | 23 | #include <linux/of.h> |
bcf18d88 | 24 | #include <linux/bcd.h> |
43d0b10f | 25 | #include <linux/delay.h> |
1fcbe42c JG |
26 | |
27 | /* MCP795 Instructions, see datasheet table 3-1 */ | |
28 | #define MCP795_EEREAD 0x03 | |
29 | #define MCP795_EEWRITE 0x02 | |
30 | #define MCP795_EEWRDI 0x04 | |
31 | #define MCP795_EEWREN 0x06 | |
32 | #define MCP795_SRREAD 0x05 | |
33 | #define MCP795_SRWRITE 0x01 | |
d3e59259 | 34 | #define MCP795_READ 0x13 |
1fcbe42c JG |
35 | #define MCP795_WRITE 0x12 |
36 | #define MCP795_UNLOCK 0x14 | |
37 | #define MCP795_IDWRITE 0x32 | |
38 | #define MCP795_IDREAD 0x33 | |
39 | #define MCP795_CLRWDT 0x44 | |
40 | #define MCP795_CLRRAM 0x54 | |
41 | ||
43d0b10f EB |
42 | /* MCP795 RTCC registers, see datasheet table 4-1 */ |
43 | #define MCP795_REG_SECONDS 0x01 | |
44 | #define MCP795_REG_DAY 0x04 | |
45 | #define MCP795_REG_MONTH 0x06 | |
46 | #define MCP795_REG_CONTROL 0x08 | |
47 | ||
d3e59259 EB |
48 | #define MCP795_ST_BIT BIT(7) |
49 | #define MCP795_24_BIT BIT(6) | |
50 | #define MCP795_LP_BIT BIT(5) | |
43d0b10f EB |
51 | #define MCP795_EXTOSC_BIT BIT(3) |
52 | #define MCP795_OSCON_BIT BIT(5) | |
1fcbe42c JG |
53 | |
54 | static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count) | |
55 | { | |
56 | struct spi_device *spi = to_spi_device(dev); | |
57 | int ret; | |
58 | u8 tx[2]; | |
59 | ||
60 | tx[0] = MCP795_READ; | |
61 | tx[1] = addr; | |
62 | ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count); | |
63 | ||
64 | if (ret) | |
65 | dev_err(dev, "Failed reading %d bytes from address %x.\n", | |
66 | count, addr); | |
67 | ||
68 | return ret; | |
69 | } | |
70 | ||
71 | static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count) | |
72 | { | |
73 | struct spi_device *spi = to_spi_device(dev); | |
74 | int ret; | |
75 | u8 tx[2 + count]; | |
76 | ||
77 | tx[0] = MCP795_WRITE; | |
78 | tx[1] = addr; | |
79 | memcpy(&tx[2], data, count); | |
80 | ||
81 | ret = spi_write(spi, tx, 2 + count); | |
82 | ||
83 | if (ret) | |
84 | dev_err(dev, "Failed to write %d bytes to address %x.\n", | |
85 | count, addr); | |
86 | ||
87 | return ret; | |
88 | } | |
89 | ||
90 | static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state) | |
91 | { | |
92 | int ret; | |
93 | u8 tmp; | |
94 | ||
95 | ret = mcp795_rtcc_read(dev, addr, &tmp, 1); | |
96 | if (ret) | |
97 | return ret; | |
98 | ||
99 | if ((tmp & mask) != state) { | |
100 | tmp = (tmp & ~mask) | state; | |
101 | ret = mcp795_rtcc_write(dev, addr, &tmp, 1); | |
102 | } | |
103 | ||
104 | return ret; | |
105 | } | |
106 | ||
43d0b10f EB |
107 | static int mcp795_stop_oscillator(struct device *dev, bool *extosc) |
108 | { | |
109 | int retries = 5; | |
110 | int ret; | |
111 | u8 data; | |
112 | ||
113 | ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0); | |
114 | if (ret) | |
115 | return ret; | |
116 | ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1); | |
117 | if (ret) | |
118 | return ret; | |
119 | *extosc = !!(data & MCP795_EXTOSC_BIT); | |
120 | ret = mcp795_rtcc_set_bits( | |
121 | dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0); | |
122 | if (ret) | |
123 | return ret; | |
124 | /* wait for the OSCON bit to clear */ | |
125 | do { | |
126 | usleep_range(700, 800); | |
127 | ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1); | |
128 | if (ret) | |
129 | break; | |
130 | if (!(data & MCP795_OSCON_BIT)) | |
131 | break; | |
132 | ||
133 | } while (--retries); | |
134 | ||
135 | return !retries ? -EIO : ret; | |
136 | } | |
137 | ||
138 | static int mcp795_start_oscillator(struct device *dev, bool *extosc) | |
139 | { | |
140 | if (extosc) { | |
141 | u8 data = *extosc ? MCP795_EXTOSC_BIT : 0; | |
142 | int ret; | |
143 | ||
144 | ret = mcp795_rtcc_set_bits( | |
145 | dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data); | |
146 | if (ret) | |
147 | return ret; | |
148 | } | |
149 | return mcp795_rtcc_set_bits( | |
150 | dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT); | |
151 | } | |
152 | ||
1fcbe42c JG |
153 | static int mcp795_set_time(struct device *dev, struct rtc_time *tim) |
154 | { | |
155 | int ret; | |
156 | u8 data[7]; | |
43d0b10f EB |
157 | bool extosc; |
158 | ||
159 | /* Stop RTC and store current value of EXTOSC bit */ | |
160 | ret = mcp795_stop_oscillator(dev, &extosc); | |
161 | if (ret) | |
162 | return ret; | |
1fcbe42c JG |
163 | |
164 | /* Read first, so we can leave config bits untouched */ | |
43d0b10f | 165 | ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data)); |
1fcbe42c JG |
166 | |
167 | if (ret) | |
168 | return ret; | |
169 | ||
bcf18d88 EB |
170 | data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec); |
171 | data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min); | |
172 | data[2] = bin2bcd(tim->tm_hour); | |
173 | data[4] = bin2bcd(tim->tm_mday); | |
26eeefd5 | 174 | data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1); |
1fcbe42c JG |
175 | |
176 | if (tim->tm_year > 100) | |
177 | tim->tm_year -= 100; | |
178 | ||
bcf18d88 | 179 | data[6] = bin2bcd(tim->tm_year); |
1fcbe42c | 180 | |
43d0b10f EB |
181 | /* Always write the date and month using a separate Write command. |
182 | * This is a workaround for a know silicon issue that some combinations | |
183 | * of date and month values may result in the date being reset to 1. | |
184 | */ | |
185 | ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5); | |
186 | if (ret) | |
187 | return ret; | |
188 | ||
189 | ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2); | |
190 | if (ret) | |
191 | return ret; | |
1fcbe42c | 192 | |
43d0b10f EB |
193 | /* Start back RTC and restore previous value of EXTOSC bit. |
194 | * There is no need to clear EXTOSC bit when the previous value was 0 | |
195 | * because it was already cleared when stopping the RTC oscillator. | |
196 | */ | |
197 | ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL); | |
1fcbe42c JG |
198 | if (ret) |
199 | return ret; | |
200 | ||
201 | dev_dbg(dev, "Set mcp795: %04d-%02d-%02d %02d:%02d:%02d\n", | |
202 | tim->tm_year + 1900, tim->tm_mon, tim->tm_mday, | |
203 | tim->tm_hour, tim->tm_min, tim->tm_sec); | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | static int mcp795_read_time(struct device *dev, struct rtc_time *tim) | |
209 | { | |
210 | int ret; | |
211 | u8 data[7]; | |
212 | ||
43d0b10f | 213 | ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data)); |
1fcbe42c JG |
214 | |
215 | if (ret) | |
216 | return ret; | |
217 | ||
bcf18d88 EB |
218 | tim->tm_sec = bcd2bin(data[0] & 0x7F); |
219 | tim->tm_min = bcd2bin(data[1] & 0x7F); | |
220 | tim->tm_hour = bcd2bin(data[2] & 0x3F); | |
221 | tim->tm_mday = bcd2bin(data[4] & 0x3F); | |
26eeefd5 | 222 | tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1; |
bcf18d88 | 223 | tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */ |
1fcbe42c JG |
224 | |
225 | dev_dbg(dev, "Read from mcp795: %04d-%02d-%02d %02d:%02d:%02d\n", | |
226 | tim->tm_year + 1900, tim->tm_mon, tim->tm_mday, | |
227 | tim->tm_hour, tim->tm_min, tim->tm_sec); | |
228 | ||
229 | return rtc_valid_tm(tim); | |
230 | } | |
231 | ||
34c7b3ac | 232 | static const struct rtc_class_ops mcp795_rtc_ops = { |
1fcbe42c JG |
233 | .read_time = mcp795_read_time, |
234 | .set_time = mcp795_set_time | |
235 | }; | |
236 | ||
237 | static int mcp795_probe(struct spi_device *spi) | |
238 | { | |
239 | struct rtc_device *rtc; | |
240 | int ret; | |
241 | ||
242 | spi->mode = SPI_MODE_0; | |
243 | spi->bits_per_word = 8; | |
244 | ret = spi_setup(spi); | |
245 | if (ret) { | |
246 | dev_err(&spi->dev, "Unable to setup SPI\n"); | |
247 | return ret; | |
248 | } | |
249 | ||
43d0b10f EB |
250 | /* Start the oscillator but don't set the value of EXTOSC bit */ |
251 | mcp795_start_oscillator(&spi->dev, NULL); | |
1fcbe42c JG |
252 | /* Clear the 12 hour mode flag*/ |
253 | mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0); | |
254 | ||
255 | rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795", | |
d3e59259 | 256 | &mcp795_rtc_ops, THIS_MODULE); |
1fcbe42c JG |
257 | if (IS_ERR(rtc)) |
258 | return PTR_ERR(rtc); | |
259 | ||
260 | spi_set_drvdata(spi, rtc); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
7f8a5892 EB |
265 | #ifdef CONFIG_OF |
266 | static const struct of_device_id mcp795_of_match[] = { | |
267 | { .compatible = "maxim,mcp795" }, | |
268 | { } | |
269 | }; | |
270 | MODULE_DEVICE_TABLE(of, mcp795_of_match); | |
271 | #endif | |
272 | ||
1fcbe42c JG |
273 | static struct spi_driver mcp795_driver = { |
274 | .driver = { | |
275 | .name = "rtc-mcp795", | |
7f8a5892 | 276 | .of_match_table = of_match_ptr(mcp795_of_match), |
1fcbe42c JG |
277 | }, |
278 | .probe = mcp795_probe, | |
279 | }; | |
280 | ||
281 | module_spi_driver(mcp795_driver); | |
282 | ||
283 | MODULE_DESCRIPTION("MCP795 RTC SPI Driver"); | |
284 | MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>"); | |
285 | MODULE_LICENSE("GPL"); | |
286 | MODULE_ALIAS("spi:mcp795"); |