[mirror_ubuntu-jammy-kernel.git] / drivers / rtc / rtc-mxc.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.

#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>

#define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
#define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
#define RTC_INPUT_CLK_38400HZ	(0x02 << 5)

#define RTC_SW_BIT      (1 << 0)
#define RTC_ALM_BIT     (1 << 2)
#define RTC_1HZ_BIT     (1 << 4)
#define RTC_2HZ_BIT     (1 << 7)
#define RTC_SAM0_BIT    (1 << 8)
#define RTC_SAM1_BIT    (1 << 9)
#define RTC_SAM2_BIT    (1 << 10)
#define RTC_SAM3_BIT    (1 << 11)
#define RTC_SAM4_BIT    (1 << 12)
#define RTC_SAM5_BIT    (1 << 13)
#define RTC_SAM6_BIT    (1 << 14)
#define RTC_SAM7_BIT    (1 << 15)
#define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
			 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
			 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)

#define RTC_ENABLE_BIT  (1 << 7)

#define MAX_PIE_NUM     9
#define MAX_PIE_FREQ    512

#define MXC_RTC_TIME	0
#define MXC_RTC_ALARM	1

#define RTC_HOURMIN	0x00	/*  32bit rtc hour/min counter reg */
#define RTC_SECOND	0x04	/*  32bit rtc seconds counter reg */
#define RTC_ALRM_HM	0x08	/*  32bit rtc alarm hour/min reg */
#define RTC_ALRM_SEC	0x0C	/*  32bit rtc alarm seconds reg */
#define RTC_RTCCTL	0x10	/*  32bit rtc control reg */
#define RTC_RTCISR	0x14	/*  32bit rtc interrupt status reg */
#define RTC_RTCIENR	0x18	/*  32bit rtc interrupt enable reg */
#define RTC_STPWCH	0x1C	/*  32bit rtc stopwatch min reg */
#define RTC_DAYR	0x20	/*  32bit rtc days counter reg */
#define RTC_DAYALARM	0x24	/*  32bit rtc day alarm reg */
#define RTC_TEST1	0x28	/*  32bit rtc test reg 1 */
#define RTC_TEST2	0x2C	/*  32bit rtc test reg 2 */
#define RTC_TEST3	0x30	/*  32bit rtc test reg 3 */

enum imx_rtc_type {
	IMX1_RTC,
	IMX21_RTC,
};

struct rtc_plat_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	int irq;
	struct clk *clk_ref;
	struct clk *clk_ipg;
	struct rtc_time g_rtc_alarm;
	enum imx_rtc_type devtype;
};

static const struct platform_device_id imx_rtc_devtype[] = {
	{
		.name = "imx1-rtc",
		.driver_data = IMX1_RTC,
	}, {
		.name = "imx21-rtc",
		.driver_data = IMX21_RTC,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);

#ifdef CONFIG_OF
static const struct of_device_id imx_rtc_dt_ids[] = {
	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	{}
};
MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
#endif

static inline int is_imx1_rtc(struct rtc_plat_data *data)
{
	return data->devtype == IMX1_RTC;
}

/*
 * This function is used to obtain the RTC time or the alarm value in
 * second.
 */
static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		day = readw(ioaddr + RTC_DAYR);
		hr_min = readw(ioaddr + RTC_HOURMIN);
		sec = readw(ioaddr + RTC_SECOND);
		break;
	case MXC_RTC_ALARM:
		day = readw(ioaddr + RTC_DAYALARM);
		hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
		sec = readw(ioaddr + RTC_ALRM_SEC);
		break;
	}

	hr = hr_min >> 8;
	min = hr_min & 0xff;

	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
}

/*
 * This function sets the RTC alarm value or the time value.
 */
static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
{
	u32 tod, day, hr, min, sec, temp;
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	day = div_s64_rem(time, 86400, &tod);

	/* time is within a day now */
	hr = tod / 3600;
	tod -= hr * 3600;

	/* time is within an hour now */
	min = tod / 60;
	sec = tod - min * 60;

	temp = (hr << 8) + min;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		writew(day, ioaddr + RTC_DAYR);
		writew(sec, ioaddr + RTC_SECOND);
		writew(temp, ioaddr + RTC_HOURMIN);
		break;
	case MXC_RTC_ALARM:
		writew(day, ioaddr + RTC_DAYALARM);
		writew(sec, ioaddr + RTC_ALRM_SEC);
		writew(temp, ioaddr + RTC_ALRM_HM);
		break;
	}
}

/*
 * This function updates the RTC alarm registers and then clears all the
 * interrupt status bits.
 */
static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
{
	time64_t time;
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	time = rtc_tm_to_time64(alrm);

	/* clear all the interrupt status bits */
	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
}

static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
				unsigned int enabled)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 reg;

	spin_lock_irq(&pdata->rtc->irq_lock);
	reg = readw(ioaddr + RTC_RTCIENR);

	if (enabled)
		reg |= bit;
	else
		reg &= ~bit;

	writew(reg, ioaddr + RTC_RTCIENR);
	spin_unlock_irq(&pdata->rtc->irq_lock);
}

/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = dev_id;
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	unsigned long flags;
	u32 status;
	u32 events = 0;

	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	/* clear interrupt sources */
	writew(status, ioaddr + RTC_RTCISR);

	/* update irq data & counter */
	if (status & RTC_ALM_BIT) {
		events |= (RTC_AF | RTC_IRQF);
		/* RTC alarm should be one-shot */
		mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	}

	if (status & PIT_ALL_ON)
		events |= (RTC_PF | RTC_IRQF);

	rtc_update_irq(pdata->rtc, 1, events);
	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);

	return IRQ_HANDLED;
}

static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	return 0;
}

/*
 * This function reads the current RTC time into tm in Gregorian date.
 */
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	time64_t val;

	/* Avoid roll-over from reading the different registers */
	do {
		val = get_alarm_or_time(dev, MXC_RTC_TIME);
	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));

	rtc_time64_to_tm(val, tm);

	return 0;
}

/*
 * This function sets the internal RTC time based on tm in Gregorian date.
 */
static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
{
	/* Avoid roll-over from reading the different registers */
	do {
		set_alarm_or_time(dev, MXC_RTC_TIME, time);
	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));

	return 0;
}

/*
 * This function reads the current alarm value into the passed in 'alrm'
 * argument. It updates the alrm's pending field value based on the whether
 * an alarm interrupt occurs or not.
 */
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;

	return 0;
}

/*
 * This function sets the RTC alarm based on passed in alrm.
 */
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	rtc_update_alarm(dev, &alrm->time);

	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);

	return 0;
}

/* RTC layer */
static const struct rtc_class_ops mxc_rtc_ops = {
	.read_time		= mxc_rtc_read_time,
	.set_mmss64		= mxc_rtc_set_mmss,
	.read_alarm		= mxc_rtc_read_alarm,
	.set_alarm		= mxc_rtc_set_alarm,
	.alarm_irq_enable	= mxc_rtc_alarm_irq_enable,
};

static int mxc_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;
	struct rtc_plat_data *pdata = NULL;
	u32 reg;
	unsigned long rate;
	int ret;
	const struct of_device_id *of_id;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	if (of_id)
		pdata->devtype = (enum imx_rtc_type)of_id->data;
	else
		pdata->devtype = pdev->id_entry->driver_data;

	pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pdata->ioaddr))
		return PTR_ERR(pdata->ioaddr);

	rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	pdata->rtc = rtc;
	rtc->ops = &mxc_rtc_ops;
	if (is_imx1_rtc(pdata)) {
		struct rtc_time tm;

		/* 9bit days + hours minutes seconds */
		rtc->range_max = (1 << 9) * 86400 - 1;

		/*
		 * Set the start date as beginning of the current year. This can
		 * be overridden using device tree.
		 */
		rtc_time64_to_tm(ktime_get_real_seconds(), &tm);
		rtc->start_secs =  mktime64(tm.tm_year, 1, 1, 0, 0, 0);
		rtc->set_start_time = true;
	} else {
		/* 16bit days + hours minutes seconds */
		rtc->range_max = (1 << 16) * 86400ULL - 1;
	}

	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(pdata->clk_ipg)) {
		dev_err(&pdev->dev, "unable to get ipg clock!\n");
		return PTR_ERR(pdata->clk_ipg);
	}

	ret = clk_prepare_enable(pdata->clk_ipg);
	if (ret)
		return ret;

	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	if (IS_ERR(pdata->clk_ref)) {
		dev_err(&pdev->dev, "unable to get ref clock!\n");
		ret = PTR_ERR(pdata->clk_ref);
		goto exit_put_clk_ipg;
	}

	ret = clk_prepare_enable(pdata->clk_ref);
	if (ret)
		goto exit_put_clk_ipg;

	rate = clk_get_rate(pdata->clk_ref);

	if (rate == 32768)
		reg = RTC_INPUT_CLK_32768HZ;
	else if (rate == 32000)
		reg = RTC_INPUT_CLK_32000HZ;
	else if (rate == 38400)
		reg = RTC_INPUT_CLK_38400HZ;
	else {
		dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
		ret = -EINVAL;
		goto exit_put_clk_ref;
	}

	reg |= RTC_ENABLE_BIT;
	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
		dev_err(&pdev->dev, "hardware module can't be enabled!\n");
		ret = -EIO;
		goto exit_put_clk_ref;
	}

	platform_set_drvdata(pdev, pdata);

	/* Configure and enable the RTC */
	pdata->irq = platform_get_irq(pdev, 0);

	if (pdata->irq >= 0 &&
	    devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
			     IRQF_SHARED, pdev->name, pdev) < 0) {
		dev_warn(&pdev->dev, "interrupt not available.\n");
		pdata->irq = -1;
	}

	if (pdata->irq >= 0) {
		device_init_wakeup(&pdev->dev, 1);
		ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
		if (ret)
			dev_err(&pdev->dev, "failed to enable irq wake\n");
	}

	ret = rtc_register_device(rtc);
	if (ret)
		goto exit_put_clk_ref;

	return 0;

exit_put_clk_ref:
	clk_disable_unprepare(pdata->clk_ref);
exit_put_clk_ipg:
	clk_disable_unprepare(pdata->clk_ipg);

	return ret;
}

static int mxc_rtc_remove(struct platform_device *pdev)
{
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	clk_disable_unprepare(pdata->clk_ref);
	clk_disable_unprepare(pdata->clk_ipg);

	return 0;
}

static struct platform_driver mxc_rtc_driver = {
	.driver = {
		   .name	= "mxc_rtc",
		   .of_match_table = of_match_ptr(imx_rtc_dt_ids),
	},
	.id_table = imx_rtc_devtype,
	.probe = mxc_rtc_probe,
	.remove = mxc_rtc_remove,
};

module_platform_driver(mxc_rtc_driver)

MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
MODULE_DESCRIPTION("RTC driver for Freescale MXC");
MODULE_LICENSE("GPL");
Commit	Line	Data
75d01b75 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
d00ed3cf DM	4
	5	#include <linux/io.h>
	6	#include <linux/rtc.h>
	7	#include <linux/module.h>
5a0e3ad6	8	#include <linux/slab.h>
d00ed3cf DM	9	#include <linux/interrupt.h>
d00ed3cf DM	10	#include <linux/platform_device.h>
bc0e731f	11	#include <linux/pm_wakeirq.h>
d00ed3cf	12	#include <linux/clk.h>
cec13c26 PR	13	#include <linux/of.h>
cec13c26 PR	14	#include <linux/of_device.h>
d00ed3cf	15
d00ed3cf DM	16	#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
	17	#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
	18	#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
	19
	20	#define RTC_SW_BIT (1 << 0)
	21	#define RTC_ALM_BIT (1 << 2)
	22	#define RTC_1HZ_BIT (1 << 4)
	23	#define RTC_2HZ_BIT (1 << 7)
	24	#define RTC_SAM0_BIT (1 << 8)
	25	#define RTC_SAM1_BIT (1 << 9)
	26	#define RTC_SAM2_BIT (1 << 10)
	27	#define RTC_SAM3_BIT (1 << 11)
	28	#define RTC_SAM4_BIT (1 << 12)
	29	#define RTC_SAM5_BIT (1 << 13)
	30	#define RTC_SAM6_BIT (1 << 14)
	31	#define RTC_SAM7_BIT (1 << 15)
	32	#define PIT_ALL_ON (RTC_2HZ_BIT \| RTC_SAM0_BIT \| RTC_SAM1_BIT \| \
	33	RTC_SAM2_BIT \| RTC_SAM3_BIT \| RTC_SAM4_BIT \| \
	34	RTC_SAM5_BIT \| RTC_SAM6_BIT \| RTC_SAM7_BIT)
	35
	36	#define RTC_ENABLE_BIT (1 << 7)
	37
	38	#define MAX_PIE_NUM 9
	39	#define MAX_PIE_FREQ 512
d00ed3cf	40
d00ed3cf DM	41	#define MXC_RTC_TIME 0
	42	#define MXC_RTC_ALARM 1
	43
	44	#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
	45	#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
	46	#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
	47	#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
	48	#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
	49	#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
	50	#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
	51	#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
	52	#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
	53	#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
	54	#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
	55	#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
	56	#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
	57
bb1d34a2 SG	58	enum imx_rtc_type {
	59	IMX1_RTC,
	60	IMX21_RTC,
	61	};
	62
d00ed3cf DM	63	struct rtc_plat_data {
	64	struct rtc_device *rtc;
	65	void __iomem *ioaddr;
	66	int irq;
8f5fe778 PR	67	struct clk *clk_ref;
8f5fe778 PR	68	struct clk *clk_ipg;
d00ed3cf	69	struct rtc_time g_rtc_alarm;
bb1d34a2	70	enum imx_rtc_type devtype;
d00ed3cf DM	71	};
d00ed3cf DM	72
cd6ba00a	73	static const struct platform_device_id imx_rtc_devtype[] = {
bb1d34a2 SG	74	{
	75	.name = "imx1-rtc",
	76	.driver_data = IMX1_RTC,
	77	}, {
	78	.name = "imx21-rtc",
	79	.driver_data = IMX21_RTC,
	80	}, {
	81	/* sentinel */
	82	}
	83	};
	84	MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
	85
cec13c26 PR	86	#ifdef CONFIG_OF
	87	static const struct of_device_id imx_rtc_dt_ids[] = {
	88	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	89	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	90	{}
	91	};
	92	MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
	93	#endif
	94
bb1d34a2 SG	95	static inline int is_imx1_rtc(struct rtc_plat_data *data)
	96	{
	97	return data->devtype == IMX1_RTC;
	98	}
	99
d00ed3cf DM	100	/*
	101	* This function is used to obtain the RTC time or the alarm value in
	102	* second.
	103	*/
a015b8aa	104	static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
d00ed3cf	105	{
85368bb9	106	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	107	void __iomem *ioaddr = pdata->ioaddr;
	108	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
	109
	110	switch (time_alarm) {
	111	case MXC_RTC_TIME:
	112	day = readw(ioaddr + RTC_DAYR);
	113	hr_min = readw(ioaddr + RTC_HOURMIN);
	114	sec = readw(ioaddr + RTC_SECOND);
	115	break;
	116	case MXC_RTC_ALARM:
	117	day = readw(ioaddr + RTC_DAYALARM);
	118	hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
	119	sec = readw(ioaddr + RTC_ALRM_SEC);
	120	break;
	121	}
	122
	123	hr = hr_min >> 8;
	124	min = hr_min & 0xff;
	125
a015b8aa	126	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
d00ed3cf DM	127	}
	128
	129	/*
	130	* This function sets the RTC alarm value or the time value.
	131	*/
a015b8aa	132	static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
d00ed3cf	133	{
a015b8aa	134	u32 tod, day, hr, min, sec, temp;
85368bb9	135	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	136	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	137
a015b8aa	138	day = div_s64_rem(time, 86400, &tod);
d00ed3cf DM	139
d00ed3cf DM	140	/* time is within a day now */
a015b8aa XP	141	hr = tod / 3600;
a015b8aa XP	142	tod -= hr * 3600;
d00ed3cf DM	143
d00ed3cf DM	144	/* time is within an hour now */
a015b8aa XP	145	min = tod / 60;
a015b8aa XP	146	sec = tod - min * 60;
d00ed3cf DM	147
	148	temp = (hr << 8) + min;
	149
	150	switch (time_alarm) {
	151	case MXC_RTC_TIME:
	152	writew(day, ioaddr + RTC_DAYR);
	153	writew(sec, ioaddr + RTC_SECOND);
	154	writew(temp, ioaddr + RTC_HOURMIN);
	155	break;
	156	case MXC_RTC_ALARM:
	157	writew(day, ioaddr + RTC_DAYALARM);
	158	writew(sec, ioaddr + RTC_ALRM_SEC);
	159	writew(temp, ioaddr + RTC_ALRM_HM);
	160	break;
	161	}
	162	}
	163
	164	/*
	165	* This function updates the RTC alarm registers and then clears all the
	166	* interrupt status bits.
	167	*/
482494a8	168	static void rtc_update_alarm(struct device dev, struct rtc_time alrm)
d00ed3cf	169	{
a015b8aa	170	time64_t time;
85368bb9	171	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	172	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	173
a015b8aa	174	time = rtc_tm_to_time64(alrm);
d00ed3cf	175
d00ed3cf DM	176	/* clear all the interrupt status bits */
	177	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	178	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
c92182ee YK	179	}
	180
	181	static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
	182	unsigned int enabled)
	183	{
85368bb9	184	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
c92182ee YK	185	void __iomem *ioaddr = pdata->ioaddr;
	186	u32 reg;
	187
	188	spin_lock_irq(&pdata->rtc->irq_lock);
	189	reg = readw(ioaddr + RTC_RTCIENR);
	190
	191	if (enabled)
	192	reg \|= bit;
	193	else
	194	reg &= ~bit;
	195
	196	writew(reg, ioaddr + RTC_RTCIENR);
	197	spin_unlock_irq(&pdata->rtc->irq_lock);
d00ed3cf DM	198	}
	199
	200	/* This function is the RTC interrupt service routine. */
	201	static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
	202	{
	203	struct platform_device *pdev = dev_id;
	204	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	205	void __iomem *ioaddr = pdata->ioaddr;
b59f6d1f	206	unsigned long flags;
d00ed3cf DM	207	u32 status;
	208	u32 events = 0;
	209
b59f6d1f	210	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	211	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	212	/* clear interrupt sources */
	213	writew(status, ioaddr + RTC_RTCISR);
	214
d00ed3cf	215	/* update irq data & counter */
c92182ee	216	if (status & RTC_ALM_BIT) {
d00ed3cf	217	events \|= (RTC_AF \| RTC_IRQF);
c92182ee YK	218	/* RTC alarm should be one-shot */
	219	mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	220	}
d00ed3cf	221
d00ed3cf DM	222	if (status & PIT_ALL_ON)
	223	events \|= (RTC_PF \| RTC_IRQF);
	224
d00ed3cf	225	rtc_update_irq(pdata->rtc, 1, events);
b59f6d1f	226	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	227
	228	return IRQ_HANDLED;
	229	}
	230
d00ed3cf DM	231	static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	232	{
	233	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	234	return 0;
	235	}
	236
d00ed3cf DM	237	/*
	238	* This function reads the current RTC time into tm in Gregorian date.
	239	*/
	240	static int mxc_rtc_read_time(struct device dev, struct rtc_time tm)
	241	{
a015b8aa	242	time64_t val;
d00ed3cf DM	243
	244	/* Avoid roll-over from reading the different registers */
	245	do {
	246	val = get_alarm_or_time(dev, MXC_RTC_TIME);
	247	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
	248
a015b8aa	249	rtc_time64_to_tm(val, tm);
d00ed3cf DM	250
	251	return 0;
	252	}
	253
	254	/*
	255	* This function sets the internal RTC time based on tm in Gregorian date.
	256	*/
933623c3	257	static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
d00ed3cf DM	258	{
	259	/* Avoid roll-over from reading the different registers */
	260	do {
	261	set_alarm_or_time(dev, MXC_RTC_TIME, time);
	262	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
	263
	264	return 0;
	265	}
	266
	267	/*
	268	* This function reads the current alarm value into the passed in 'alrm'
	269	* argument. It updates the alrm's pending field value based on the whether
	270	* an alarm interrupt occurs or not.
	271	*/
	272	static int mxc_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	273	{
85368bb9	274	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	275	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	276
a015b8aa	277	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
d00ed3cf DM	278	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
	279
	280	return 0;
	281	}
	282
	283	/*
	284	* This function sets the RTC alarm based on passed in alrm.
	285	*/
	286	static int mxc_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	287	{
85368bb9	288	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf	289
482494a8	290	rtc_update_alarm(dev, &alrm->time);
d00ed3cf DM	291
	292	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	293	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
	294
	295	return 0;
	296	}
	297
	298	/* RTC layer */
8bc57e7f	299	static const struct rtc_class_ops mxc_rtc_ops = {
d00ed3cf	300	.read_time = mxc_rtc_read_time,
933623c3	301	.set_mmss64 = mxc_rtc_set_mmss,
d00ed3cf DM	302	.read_alarm = mxc_rtc_read_alarm,
	303	.set_alarm = mxc_rtc_set_alarm,
	304	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
d00ed3cf DM	305	};
d00ed3cf DM	306
5a167f45	307	static int mxc_rtc_probe(struct platform_device *pdev)
d00ed3cf	308	{
d00ed3cf DM	309	struct rtc_device *rtc;
	310	struct rtc_plat_data *pdata = NULL;
	311	u32 reg;
c783a29e VZ	312	unsigned long rate;
c783a29e VZ	313	int ret;
cec13c26	314	const struct of_device_id *of_id;
d00ed3cf	315
c783a29e	316	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
d00ed3cf DM	317	if (!pdata)
	318	return -ENOMEM;
	319
cec13c26 PR	320	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	321	if (of_id)
	322	pdata->devtype = (enum imx_rtc_type)of_id->data;
	323	else
	324	pdata->devtype = pdev->id_entry->driver_data;
bb1d34a2	325
cf37fa79	326	pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
7c1d69ee JL	327	if (IS_ERR(pdata->ioaddr))
7c1d69ee JL	328	return PTR_ERR(pdata->ioaddr);
d00ed3cf	329
ebc2ec4e AB	330	rtc = devm_rtc_allocate_device(&pdev->dev);
	331	if (IS_ERR(rtc))
	332	return PTR_ERR(rtc);
	333
	334	pdata->rtc = rtc;
	335	rtc->ops = &mxc_rtc_ops;
83888df4 AB	336	if (is_imx1_rtc(pdata)) {
	337	struct rtc_time tm;
	338
	339	/* 9bit days + hours minutes seconds */
	340	rtc->range_max = (1 << 9) * 86400 - 1;
	341
	342	/*
	343	* Set the start date as beginning of the current year. This can
	344	* be overridden using device tree.
	345	*/
	346	rtc_time64_to_tm(ktime_get_real_seconds(), &tm);
	347	rtc->start_secs = mktime64(tm.tm_year, 1, 1, 0, 0, 0);
	348	rtc->set_start_time = true;
	349	} else {
	350	/* 16bit days + hours minutes seconds */
	351	rtc->range_max = (1 << 16) * 86400ULL - 1;
	352	}
ebc2ec4e	353
8f5fe778 PR	354	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	355	if (IS_ERR(pdata->clk_ipg)) {
	356	dev_err(&pdev->dev, "unable to get ipg clock!\n");
	357	return PTR_ERR(pdata->clk_ipg);
49908e73	358	}
d00ed3cf	359
8f5fe778	360	ret = clk_prepare_enable(pdata->clk_ipg);
1b3d2243 FE	361	if (ret)
	362	return ret;
	363
8f5fe778 PR	364	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	365	if (IS_ERR(pdata->clk_ref)) {
	366	dev_err(&pdev->dev, "unable to get ref clock!\n");
	367	ret = PTR_ERR(pdata->clk_ref);
	368	goto exit_put_clk_ipg;
	369	}
	370
	371	ret = clk_prepare_enable(pdata->clk_ref);
	372	if (ret)
	373	goto exit_put_clk_ipg;
	374
	375	rate = clk_get_rate(pdata->clk_ref);
d00ed3cf DM	376
	377	if (rate == 32768)
	378	reg = RTC_INPUT_CLK_32768HZ;
	379	else if (rate == 32000)
	380	reg = RTC_INPUT_CLK_32000HZ;
	381	else if (rate == 38400)
	382	reg = RTC_INPUT_CLK_38400HZ;
	383	else {
c783a29e	384	dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
d00ed3cf	385	ret = -EINVAL;
8f5fe778	386	goto exit_put_clk_ref;
d00ed3cf DM	387	}
	388
	389	reg \|= RTC_ENABLE_BIT;
	390	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	391	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
	392	dev_err(&pdev->dev, "hardware module can't be enabled!\n");
	393	ret = -EIO;
8f5fe778	394	goto exit_put_clk_ref;
d00ed3cf DM	395	}
d00ed3cf DM	396
d00ed3cf DM	397	platform_set_drvdata(pdev, pdata);
	398
	399	/* Configure and enable the RTC */
	400	pdata->irq = platform_get_irq(pdev, 0);
	401
	402	if (pdata->irq >= 0 &&
c783a29e VZ	403	devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
c783a29e VZ	404	IRQF_SHARED, pdev->name, pdev) < 0) {
d00ed3cf DM	405	dev_warn(&pdev->dev, "interrupt not available.\n");
	406	pdata->irq = -1;
	407	}
	408
bc0e731f	409	if (pdata->irq >= 0) {
c92182ee	410	device_init_wakeup(&pdev->dev, 1);
bc0e731f AH	411	ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
	412	if (ret)
	413	dev_err(&pdev->dev, "failed to enable irq wake\n");
	414	}
c92182ee	415
ebc2ec4e AB	416	ret = rtc_register_device(rtc);
ebc2ec4e AB	417	if (ret)
8f5fe778	418	goto exit_put_clk_ref;
5f54c8a0	419
d00ed3cf DM	420	return 0;
d00ed3cf DM	421
8f5fe778 PR	422	exit_put_clk_ref:
	423	clk_disable_unprepare(pdata->clk_ref);
	424	exit_put_clk_ipg:
	425	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf	426
d00ed3cf DM	427	return ret;
	428	}
	429
5a167f45	430	static int mxc_rtc_remove(struct platform_device *pdev)
d00ed3cf DM	431	{
	432	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	433
8f5fe778 PR	434	clk_disable_unprepare(pdata->clk_ref);
8f5fe778 PR	435	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf DM	436
	437	return 0;
	438	}
	439
	440	static struct platform_driver mxc_rtc_driver = {
	441	.driver = {
	442	.name = "mxc_rtc",
cec13c26	443	.of_match_table = of_match_ptr(imx_rtc_dt_ids),
d00ed3cf	444	},
bb1d34a2	445	.id_table = imx_rtc_devtype,
be8b6d51	446	.probe = mxc_rtc_probe,
5a167f45	447	.remove = mxc_rtc_remove,
d00ed3cf DM	448	};
d00ed3cf DM	449
be8b6d51	450	module_platform_driver(mxc_rtc_driver)
d00ed3cf DM	451
	452	MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
	453	MODULE_DESCRIPTION("RTC driver for Freescale MXC");
	454	MODULE_LICENSE("GPL");
	455