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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e842f1c8 RP |
2 | /* |
3 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
4 | * | |
5 | * Copyright (c) 2000 Nils Faerber | |
6 | * | |
7 | * Based on rtc.c by Paul Gortmaker | |
8 | * | |
9 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
10 | * | |
11 | * Modifications from: | |
12 | * CIH <cih@coventive.com> | |
2f82af08 | 13 | * Nicolas Pitre <nico@fluxnic.net> |
e842f1c8 RP |
14 | * Andrew Christian <andrew.christian@hp.com> |
15 | * | |
16 | * Converted to the RTC subsystem and Driver Model | |
17 | * by Richard Purdie <rpurdie@rpsys.net> | |
e842f1c8 RP |
18 | */ |
19 | ||
20 | #include <linux/platform_device.h> | |
21 | #include <linux/module.h> | |
8e8bbcb3 | 22 | #include <linux/clk.h> |
e842f1c8 RP |
23 | #include <linux/rtc.h> |
24 | #include <linux/init.h> | |
25 | #include <linux/fs.h> | |
26 | #include <linux/interrupt.h> | |
3888c090 | 27 | #include <linux/slab.h> |
a0164a57 | 28 | #include <linux/string.h> |
8bec2e9e | 29 | #include <linux/of.h> |
e842f1c8 | 30 | #include <linux/pm.h> |
a0164a57 | 31 | #include <linux/bitops.h> |
23019a73 | 32 | #include <linux/io.h> |
e842f1c8 | 33 | |
90d0ae8e RH |
34 | #define RTSR_HZE BIT(3) /* HZ interrupt enable */ |
35 | #define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */ | |
36 | #define RTSR_HZ BIT(1) /* HZ rising-edge detected */ | |
37 | #define RTSR_AL BIT(0) /* RTC alarm detected */ | |
a0164a57 | 38 | |
8c0961ba RH |
39 | #include "rtc-sa1100.h" |
40 | ||
a404ad1f | 41 | #define RTC_DEF_DIVIDER (32768 - 1) |
e842f1c8 | 42 | #define RTC_DEF_TRIM 0 |
3888c090 | 43 | #define RTC_FREQ 1024 |
a0164a57 | 44 | |
a0164a57 | 45 | |
7d12e780 | 46 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
e842f1c8 | 47 | { |
3888c090 HZ |
48 | struct sa1100_rtc *info = dev_get_drvdata(dev_id); |
49 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
50 | unsigned int rtsr; |
51 | unsigned long events = 0; | |
52 | ||
3888c090 | 53 | spin_lock(&info->lock); |
e842f1c8 | 54 | |
90d0ae8e | 55 | rtsr = readl_relaxed(info->rtsr); |
e842f1c8 | 56 | /* clear interrupt sources */ |
90d0ae8e | 57 | writel_relaxed(0, info->rtsr); |
7decaa55 MRJ |
58 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
59 | * See also the comments in sa1100_rtc_probe(). */ | |
60 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { | |
61 | /* This is the original code, before there was the if test | |
62 | * above. This code does not clear interrupts that were not | |
63 | * enabled. */ | |
90d0ae8e | 64 | writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); |
7decaa55 MRJ |
65 | } else { |
66 | /* For some reason, it is possible to enter this routine | |
67 | * without interruptions enabled, it has been tested with | |
68 | * several units (Bug in SA11xx chip?). | |
69 | * | |
70 | * This situation leads to an infinite "loop" of interrupt | |
71 | * routine calling and as a result the processor seems to | |
72 | * lock on its first call to open(). */ | |
90d0ae8e | 73 | writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); |
7decaa55 | 74 | } |
e842f1c8 RP |
75 | |
76 | /* clear alarm interrupt if it has occurred */ | |
77 | if (rtsr & RTSR_AL) | |
78 | rtsr &= ~RTSR_ALE; | |
90d0ae8e | 79 | writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); |
e842f1c8 RP |
80 | |
81 | /* update irq data & counter */ | |
82 | if (rtsr & RTSR_AL) | |
83 | events |= RTC_AF | RTC_IRQF; | |
84 | if (rtsr & RTSR_HZ) | |
85 | events |= RTC_UF | RTC_IRQF; | |
86 | ||
a0164a57 | 87 | rtc_update_irq(rtc, 1, events); |
e842f1c8 | 88 | |
3888c090 | 89 | spin_unlock(&info->lock); |
e842f1c8 RP |
90 | |
91 | return IRQ_HANDLED; | |
92 | } | |
93 | ||
16380c15 JS |
94 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
95 | { | |
90d0ae8e | 96 | u32 rtsr; |
3888c090 HZ |
97 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
98 | ||
99 | spin_lock_irq(&info->lock); | |
90d0ae8e | 100 | rtsr = readl_relaxed(info->rtsr); |
16380c15 | 101 | if (enabled) |
90d0ae8e | 102 | rtsr |= RTSR_ALE; |
16380c15 | 103 | else |
90d0ae8e RH |
104 | rtsr &= ~RTSR_ALE; |
105 | writel_relaxed(rtsr, info->rtsr); | |
3888c090 | 106 | spin_unlock_irq(&info->lock); |
16380c15 JS |
107 | return 0; |
108 | } | |
109 | ||
e842f1c8 RP |
110 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
111 | { | |
90d0ae8e RH |
112 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
113 | ||
114 | rtc_time_to_tm(readl_relaxed(info->rcnr), tm); | |
e842f1c8 RP |
115 | return 0; |
116 | } | |
117 | ||
118 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
119 | { | |
90d0ae8e | 120 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
e842f1c8 RP |
121 | unsigned long time; |
122 | int ret; | |
123 | ||
124 | ret = rtc_tm_to_time(tm, &time); | |
125 | if (ret == 0) | |
90d0ae8e | 126 | writel_relaxed(time, info->rcnr); |
e842f1c8 RP |
127 | return ret; |
128 | } | |
129 | ||
130 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
131 | { | |
a0164a57 | 132 | u32 rtsr; |
90d0ae8e | 133 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
32b49da4 | 134 | |
90d0ae8e | 135 | rtsr = readl_relaxed(info->rtsr); |
32b49da4 DB |
136 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; |
137 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; | |
e842f1c8 RP |
138 | return 0; |
139 | } | |
140 | ||
141 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
142 | { | |
3888c090 | 143 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
1d8c38c3 | 144 | unsigned long time; |
a0164a57 | 145 | int ret; |
e842f1c8 | 146 | |
3888c090 | 147 | spin_lock_irq(&info->lock); |
1d8c38c3 HZ |
148 | ret = rtc_tm_to_time(&alrm->time, &time); |
149 | if (ret != 0) | |
150 | goto out; | |
90d0ae8e RH |
151 | writel_relaxed(readl_relaxed(info->rtsr) & |
152 | (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr); | |
153 | writel_relaxed(time, info->rtar); | |
1d8c38c3 | 154 | if (alrm->enabled) |
90d0ae8e | 155 | writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); |
1d8c38c3 | 156 | else |
90d0ae8e | 157 | writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr); |
1d8c38c3 | 158 | out: |
3888c090 | 159 | spin_unlock_irq(&info->lock); |
e842f1c8 | 160 | |
a0164a57 | 161 | return ret; |
e842f1c8 RP |
162 | } |
163 | ||
164 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
165 | { | |
90d0ae8e RH |
166 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
167 | ||
168 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr)); | |
169 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr)); | |
e842f1c8 RP |
170 | |
171 | return 0; | |
172 | } | |
173 | ||
ff8371ac | 174 | static const struct rtc_class_ops sa1100_rtc_ops = { |
e842f1c8 RP |
175 | .read_time = sa1100_rtc_read_time, |
176 | .set_time = sa1100_rtc_set_time, | |
177 | .read_alarm = sa1100_rtc_read_alarm, | |
178 | .set_alarm = sa1100_rtc_set_alarm, | |
179 | .proc = sa1100_rtc_proc, | |
16380c15 | 180 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
e842f1c8 RP |
181 | }; |
182 | ||
8c0961ba | 183 | int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info) |
e842f1c8 | 184 | { |
8c0961ba | 185 | int ret; |
3888c090 | 186 | |
8c0961ba | 187 | spin_lock_init(&info->lock); |
3888c090 | 188 | |
55d735ef | 189 | info->clk = devm_clk_get(&pdev->dev, NULL); |
8e8bbcb3 HZ |
190 | if (IS_ERR(info->clk)) { |
191 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
55d735ef | 192 | return PTR_ERR(info->clk); |
8e8bbcb3 | 193 | } |
e842f1c8 | 194 | |
0cc0c38e CX |
195 | ret = clk_prepare_enable(info->clk); |
196 | if (ret) | |
66600bbe | 197 | return ret; |
e842f1c8 RP |
198 | /* |
199 | * According to the manual we should be able to let RTTR be zero | |
200 | * and then a default diviser for a 32.768KHz clock is used. | |
201 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
202 | * If the clock divider is uninitialized then reset it to the | |
203 | * default value to get the 1Hz clock. | |
204 | */ | |
90d0ae8e RH |
205 | if (readl_relaxed(info->rttr) == 0) { |
206 | writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr); | |
a0164a57 RK |
207 | dev_warn(&pdev->dev, "warning: " |
208 | "initializing default clock divider/trim value\n"); | |
e842f1c8 | 209 | /* The current RTC value probably doesn't make sense either */ |
90d0ae8e | 210 | writel_relaxed(0, info->rcnr); |
e842f1c8 RP |
211 | } |
212 | ||
36ac0a06 AB |
213 | info->rtc->ops = &sa1100_rtc_ops; |
214 | info->rtc->max_user_freq = RTC_FREQ; | |
215 | ||
216 | ret = rtc_register_device(info->rtc); | |
217 | if (ret) { | |
8c0961ba | 218 | clk_disable_unprepare(info->clk); |
36ac0a06 | 219 | return ret; |
3888c090 | 220 | } |
512053a4 | 221 | |
7decaa55 MRJ |
222 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
223 | * See also the comments in sa1100_rtc_interrupt(). | |
224 | * | |
225 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an | |
226 | * interrupt pending, even though interrupts were never enabled. | |
227 | * In this case, this bit it must be reset before enabling | |
228 | * interruptions to avoid a nonexistent interrupt to occur. | |
229 | * | |
230 | * In principle, the same problem would apply to bit 0, although it has | |
231 | * never been observed to happen. | |
232 | * | |
233 | * This issue is addressed both here and in sa1100_rtc_interrupt(). | |
234 | * If the issue is not addressed here, in the times when the processor | |
235 | * wakes up with the bit set there will be one spurious interrupt. | |
236 | * | |
237 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the | |
238 | * safe side, once the condition that lead to this strange | |
239 | * initialization is unknown and could in principle happen during | |
240 | * normal processing. | |
241 | * | |
242 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to | |
243 | * the corresponding bits in RTSR. */ | |
90d0ae8e | 244 | writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); |
7decaa55 | 245 | |
e842f1c8 | 246 | return 0; |
8c0961ba RH |
247 | } |
248 | EXPORT_SYMBOL_GPL(sa1100_rtc_init); | |
249 | ||
250 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
251 | { | |
252 | struct sa1100_rtc *info; | |
90d0ae8e RH |
253 | struct resource *iores; |
254 | void __iomem *base; | |
8c0961ba | 255 | int irq_1hz, irq_alarm; |
512053a4 | 256 | int ret; |
8c0961ba RH |
257 | |
258 | irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz"); | |
259 | irq_alarm = platform_get_irq_byname(pdev, "rtc alarm"); | |
260 | if (irq_1hz < 0 || irq_alarm < 0) | |
261 | return -ENODEV; | |
262 | ||
263 | info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL); | |
264 | if (!info) | |
265 | return -ENOMEM; | |
266 | info->irq_1hz = irq_1hz; | |
267 | info->irq_alarm = irq_alarm; | |
268 | ||
36ac0a06 AB |
269 | info->rtc = devm_rtc_allocate_device(&pdev->dev); |
270 | if (IS_ERR(info->rtc)) | |
271 | return PTR_ERR(info->rtc); | |
272 | ||
512053a4 AB |
273 | ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0, |
274 | "rtc 1Hz", &pdev->dev); | |
275 | if (ret) { | |
276 | dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz); | |
277 | return ret; | |
278 | } | |
279 | ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0, | |
280 | "rtc Alrm", &pdev->dev); | |
281 | if (ret) { | |
282 | dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm); | |
283 | return ret; | |
284 | } | |
285 | ||
90d0ae8e RH |
286 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
287 | base = devm_ioremap_resource(&pdev->dev, iores); | |
288 | if (IS_ERR(base)) | |
289 | return PTR_ERR(base); | |
290 | ||
291 | if (IS_ENABLED(CONFIG_ARCH_SA1100) || | |
292 | of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) { | |
293 | info->rcnr = base + 0x04; | |
294 | info->rtsr = base + 0x10; | |
295 | info->rtar = base + 0x00; | |
296 | info->rttr = base + 0x08; | |
297 | } else { | |
298 | info->rcnr = base + 0x0; | |
299 | info->rtsr = base + 0x8; | |
300 | info->rtar = base + 0x4; | |
301 | info->rttr = base + 0xc; | |
302 | } | |
303 | ||
8c0961ba RH |
304 | platform_set_drvdata(pdev, info); |
305 | device_init_wakeup(&pdev->dev, 1); | |
306 | ||
307 | return sa1100_rtc_init(pdev, info); | |
e842f1c8 RP |
308 | } |
309 | ||
310 | static int sa1100_rtc_remove(struct platform_device *pdev) | |
311 | { | |
3888c090 | 312 | struct sa1100_rtc *info = platform_get_drvdata(pdev); |
a0164a57 | 313 | |
512053a4 AB |
314 | if (info) { |
315 | spin_lock_irq(&info->lock); | |
316 | writel_relaxed(0, info->rtsr); | |
317 | spin_unlock_irq(&info->lock); | |
0cc0c38e | 318 | clk_disable_unprepare(info->clk); |
512053a4 | 319 | } |
e842f1c8 RP |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
aaa92fae | 324 | #ifdef CONFIG_PM_SLEEP |
5d027cd2 | 325 | static int sa1100_rtc_suspend(struct device *dev) |
6bc54e69 | 326 | { |
3888c090 | 327 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 328 | if (device_may_wakeup(dev)) |
3888c090 | 329 | enable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
330 | return 0; |
331 | } | |
332 | ||
5d027cd2 | 333 | static int sa1100_rtc_resume(struct device *dev) |
6bc54e69 | 334 | { |
3888c090 | 335 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 336 | if (device_may_wakeup(dev)) |
3888c090 | 337 | disable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
338 | return 0; |
339 | } | |
6bc54e69 RK |
340 | #endif |
341 | ||
aaa92fae JH |
342 | static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend, |
343 | sa1100_rtc_resume); | |
344 | ||
c8a6046e | 345 | #ifdef CONFIG_OF |
dee21a6f | 346 | static const struct of_device_id sa1100_rtc_dt_ids[] = { |
8bec2e9e HZ |
347 | { .compatible = "mrvl,sa1100-rtc", }, |
348 | { .compatible = "mrvl,mmp-rtc", }, | |
349 | {} | |
350 | }; | |
351 | MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids); | |
c8a6046e | 352 | #endif |
8bec2e9e | 353 | |
e842f1c8 RP |
354 | static struct platform_driver sa1100_rtc_driver = { |
355 | .probe = sa1100_rtc_probe, | |
356 | .remove = sa1100_rtc_remove, | |
357 | .driver = { | |
5d027cd2 | 358 | .name = "sa1100-rtc", |
5d027cd2 | 359 | .pm = &sa1100_rtc_pm_ops, |
c8a6046e | 360 | .of_match_table = of_match_ptr(sa1100_rtc_dt_ids), |
e842f1c8 RP |
361 | }, |
362 | }; | |
363 | ||
0c4eae66 | 364 | module_platform_driver(sa1100_rtc_driver); |
e842f1c8 RP |
365 | |
366 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
367 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
368 | MODULE_LICENSE("GPL"); | |
ad28a07b | 369 | MODULE_ALIAS("platform:sa1100-rtc"); |