[mirror_ubuntu-artful-kernel.git] / drivers / scsi / NCR5380.h

/* 
 * NCR 5380 defines
 *
 * Copyright 1993, Drew Eckhardt
 *	Visionary Computing
 *	(Unix consulting and custom programming)
 * 	drew@colorado.edu
 *      +1 (303) 666-5836
 *
 * For more information, please consult 
 *
 * NCR 5380 Family
 * SCSI Protocol Controller
 * Databook
 * NCR Microelectronics
 * 1635 Aeroplaza Drive
 * Colorado Springs, CO 80916
 * 1+ (719) 578-3400
 * 1+ (800) 334-5454
 */

#ifndef NCR5380_H
#define NCR5380_H

#include <linux/interrupt.h>
#include <scsi/scsi_eh.h>

#define NDEBUG_ARBITRATION	0x1
#define NDEBUG_AUTOSENSE	0x2
#define NDEBUG_DMA		0x4
#define NDEBUG_HANDSHAKE	0x8
#define NDEBUG_INFORMATION	0x10
#define NDEBUG_INIT		0x20
#define NDEBUG_INTR		0x40
#define NDEBUG_LINKED		0x80
#define NDEBUG_MAIN		0x100
#define NDEBUG_NO_DATAOUT	0x200
#define NDEBUG_NO_WRITE		0x400
#define NDEBUG_PIO		0x800
#define NDEBUG_PSEUDO_DMA	0x1000
#define NDEBUG_QUEUES		0x2000
#define NDEBUG_RESELECTION	0x4000
#define NDEBUG_SELECTION	0x8000
#define NDEBUG_USLEEP		0x10000
#define NDEBUG_LAST_BYTE_SENT	0x20000
#define NDEBUG_RESTART_SELECT	0x40000
#define NDEBUG_EXTENDED		0x80000
#define NDEBUG_C400_PREAD	0x100000
#define NDEBUG_C400_PWRITE	0x200000
#define NDEBUG_LISTS		0x400000
#define NDEBUG_ABORT		0x800000
#define NDEBUG_TAGS		0x1000000
#define NDEBUG_MERGING		0x2000000

#define NDEBUG_ANY		0xFFFFFFFFUL

/* 
 * The contents of the OUTPUT DATA register are asserted on the bus when
 * either arbitration is occurring or the phase-indicating signals (
 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
 * bit in the INITIATOR COMMAND register is set.
 */

#define OUTPUT_DATA_REG         0	/* wo DATA lines on SCSI bus */
#define CURRENT_SCSI_DATA_REG   0	/* ro same */

#define INITIATOR_COMMAND_REG	1	/* rw */
#define ICR_ASSERT_RST		0x80	/* rw Set to assert RST  */
#define ICR_ARBITRATION_PROGRESS 0x40	/* ro Indicates arbitration complete */
#define ICR_TRI_STATE		0x40	/* wo Set to tri-state drivers */
#define ICR_ARBITRATION_LOST	0x20	/* ro Indicates arbitration lost */
#define ICR_DIFF_ENABLE		0x20	/* wo Set to enable diff. drivers */
#define ICR_ASSERT_ACK		0x10	/* rw ini Set to assert ACK */
#define ICR_ASSERT_BSY		0x08	/* rw Set to assert BSY */
#define ICR_ASSERT_SEL 		0x04	/* rw Set to assert SEL */
#define ICR_ASSERT_ATN		0x02	/* rw Set to assert ATN */
#define ICR_ASSERT_DATA		0x01	/* rw SCSI_DATA_REG is asserted */

#ifdef DIFFERENTIAL
#define ICR_BASE		ICR_DIFF_ENABLE
#else
#define ICR_BASE		0
#endif

#define MODE_REG		2
/*
 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 
 * transfer, causing the chip to hog the bus.  You probably don't want 
 * this.
 */
#define MR_BLOCK_DMA_MODE	0x80	/* rw block mode DMA */
#define MR_TARGET		0x40	/* rw target mode */
#define MR_ENABLE_PAR_CHECK	0x20	/* rw enable parity checking */
#define MR_ENABLE_PAR_INTR	0x10	/* rw enable bad parity interrupt */
#define MR_ENABLE_EOP_INTR	0x08	/* rw enable eop interrupt */
#define MR_MONITOR_BSY		0x04	/* rw enable int on unexpected bsy fail */
#define MR_DMA_MODE		0x02	/* rw DMA / pseudo DMA mode */
#define MR_ARBITRATE		0x01	/* rw start arbitration */

#ifdef PARITY
#define MR_BASE			MR_ENABLE_PAR_CHECK
#else
#define MR_BASE			0
#endif

#define TARGET_COMMAND_REG	3
#define TCR_LAST_BYTE_SENT	0x80	/* ro DMA done */
#define TCR_ASSERT_REQ		0x08	/* tgt rw assert REQ */
#define TCR_ASSERT_MSG		0x04	/* tgt rw assert MSG */
#define TCR_ASSERT_CD		0x02	/* tgt rw assert CD */
#define TCR_ASSERT_IO		0x01	/* tgt rw assert IO */

#define STATUS_REG		4	/* ro */
/*
 * Note : a set bit indicates an active signal, driven by us or another 
 * device.
 */
#define SR_RST			0x80
#define SR_BSY			0x40
#define SR_REQ			0x20
#define SR_MSG			0x10
#define SR_CD			0x08
#define SR_IO			0x04
#define SR_SEL			0x02
#define SR_DBP			0x01

/*
 * Setting a bit in this register will cause an interrupt to be generated when 
 * BSY is false and SEL true and this bit is asserted  on the bus.
 */
#define SELECT_ENABLE_REG	4	/* wo */

#define BUS_AND_STATUS_REG	5	/* ro */
#define BASR_END_DMA_TRANSFER	0x80	/* ro set on end of transfer */
#define BASR_DRQ		0x40	/* ro mirror of DRQ pin */
#define BASR_PARITY_ERROR	0x20	/* ro parity error detected */
#define BASR_IRQ		0x10	/* ro mirror of IRQ pin */
#define BASR_PHASE_MATCH	0x08	/* ro Set when MSG CD IO match TCR */
#define BASR_BUSY_ERROR		0x04	/* ro Unexpected change to inactive state */
#define BASR_ATN 		0x02	/* ro BUS status */
#define BASR_ACK		0x01	/* ro BUS status */

/* Write any value to this register to start a DMA send */
#define START_DMA_SEND_REG	5	/* wo */

/* 
 * Used in DMA transfer mode, data is latched from the SCSI bus on
 * the falling edge of REQ (ini) or ACK (tgt)
 */
#define INPUT_DATA_REG			6	/* ro */

/* Write any value to this register to start a DMA receive */
#define START_DMA_TARGET_RECEIVE_REG	6	/* wo */

/* Read this register to clear interrupt conditions */
#define RESET_PARITY_INTERRUPT_REG	7	/* ro */

/* Write any value to this register to start an ini mode DMA receive */
#define START_DMA_INITIATOR_RECEIVE_REG 7	/* wo */

#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8	/* rw */

#define CSR_RESET              0x80	/* wo  Resets 53c400 */
#define CSR_53C80_REG          0x80	/* ro  5380 registers busy */
#define CSR_TRANS_DIR          0x40	/* rw  Data transfer direction */
#define CSR_SCSI_BUFF_INTR     0x20	/* rw  Enable int on transfer ready */
#define CSR_53C80_INTR         0x10	/* rw  Enable 53c80 interrupts */
#define CSR_SHARED_INTR        0x08	/* rw  Interrupt sharing */
#define CSR_HOST_BUF_NOT_RDY   0x04	/* ro  Is Host buffer ready */
#define CSR_SCSI_BUF_RDY       0x02	/* ro  SCSI buffer read */
#define CSR_GATED_53C80_IRQ    0x01	/* ro  Last block xferred */

#if 0
#define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
#else
#define CSR_BASE CSR_53C80_INTR
#endif

/* Number of 128-byte blocks to be transferred */
#define C400_BLOCK_COUNTER_REG   NCR53C400_register_offset-7	/* rw */

/* Resume transfer after disconnect */
#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6	/* wo */

/* Access to host buffer stack */
#define C400_HOST_BUFFER         NCR53C400_register_offset-4	/* rw */


/* Note : PHASE_* macros are based on the values of the STATUS register */
#define PHASE_MASK 	(SR_MSG | SR_CD | SR_IO)

#define PHASE_DATAOUT		0
#define PHASE_DATAIN		SR_IO
#define PHASE_CMDOUT		SR_CD
#define PHASE_STATIN		(SR_CD | SR_IO)
#define PHASE_MSGOUT		(SR_MSG | SR_CD)
#define PHASE_MSGIN		(SR_MSG | SR_CD | SR_IO)
#define PHASE_UNKNOWN		0xff

/* 
 * Convert status register phase to something we can use to set phase in 
 * the target register so we can get phase mismatch interrupts on DMA 
 * transfers.
 */

#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)

/* 
 * "Special" value for the (unsigned char) command tag, to indicate
 * I_T_L nexus instead of I_T_L_Q.
 */

#define TAG_NONE	0xff

/*
 * These are "special" values for the irq and dma_channel fields of the 
 * Scsi_Host structure
 */

#define DMA_NONE	255
#define IRQ_AUTO	254
#define DMA_AUTO	254
#define PORT_AUTO	0xffff	/* autoprobe io port for 53c400a */

#ifndef NO_IRQ
#define NO_IRQ		0
#endif

#define FLAG_HAS_LAST_BYTE_SENT		1	/* NCR53c81 or better */
#define FLAG_CHECK_LAST_BYTE_SENT	2	/* Only test once */
#define FLAG_NCR53C400			4	/* NCR53c400 */
#define FLAG_NO_PSEUDO_DMA		8	/* Inhibit DMA */
#define FLAG_DTC3181E			16	/* DTC3181E */
#define FLAG_LATE_DMA_SETUP		32	/* Setup NCR before DMA H/W */
#define FLAG_TAGGED_QUEUING		64	/* as X3T9.2 spelled it */
#define FLAG_TOSHIBA_DELAY		128	/* Allow for borken CD-ROMs */

#ifdef SUPPORT_TAGS
struct tag_alloc {
	DECLARE_BITMAP(allocated, MAX_TAGS);
	int nr_allocated;
	int queue_size;
};
#endif

struct NCR5380_hostdata {
	NCR5380_implementation_fields;		/* implementation specific */
	struct Scsi_Host *host;			/* Host backpointer */
	unsigned char id_mask, id_higher_mask;	/* 1 << id, all bits greater */
	volatile unsigned char busy[8];		/* index = target, bit = lun */
#if defined(REAL_DMA) || defined(REAL_DMA_POLL)
	volatile int dma_len;			/* requested length of DMA */
#endif
	volatile unsigned char last_message;	/* last message OUT */
	volatile struct scsi_cmnd *connected;	/* currently connected command */
	volatile struct scsi_cmnd *issue_queue;	/* waiting to be issued */
	volatile struct scsi_cmnd *disconnected_queue;	/* waiting for reconnect */
	int flags;
	struct scsi_eh_save ses;
	char info[256];
	int read_overruns;                /* number of bytes to cut from a
	                                   * transfer to handle chip overruns */
	int retain_dma_intr;
	struct work_struct main_task;
#ifdef SUPPORT_TAGS
	struct tag_alloc TagAlloc[8][8];	/* 8 targets and 8 LUNs */
#endif
#ifdef PSEUDO_DMA
	unsigned spin_max_r;
	unsigned spin_max_w;
#endif
	struct workqueue_struct *work_q;
	unsigned long accesses_per_ms;	/* chip register accesses per ms */
};

#ifdef __KERNEL__

#ifndef NDEBUG
#define NDEBUG (0)
#endif

#define dprintk(flg, fmt, ...) \
	do { if ((NDEBUG) & (flg)) \
		printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)

#if NDEBUG
#define NCR5380_dprint(flg, arg) \
	do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
#define NCR5380_dprint_phase(flg, arg) \
	do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
static void NCR5380_print_phase(struct Scsi_Host *instance);
static void NCR5380_print(struct Scsi_Host *instance);
#else
#define NCR5380_dprint(flg, arg)       do {} while (0)
#define NCR5380_dprint_phase(flg, arg) do {} while (0)
#endif

#if defined(AUTOPROBE_IRQ)
static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
#endif
static int NCR5380_init(struct Scsi_Host *instance, int flags);
static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
static void NCR5380_exit(struct Scsi_Host *instance);
static void NCR5380_information_transfer(struct Scsi_Host *instance);
#ifndef DONT_USE_INTR
static irqreturn_t NCR5380_intr(int irq, void *dev_id);
#endif
static void NCR5380_main(struct work_struct *work);
static const char *NCR5380_info(struct Scsi_Host *instance);
static void NCR5380_reselect(struct Scsi_Host *instance);
static int NCR5380_select(struct Scsi_Host *instance, struct scsi_cmnd *cmd);
#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
#endif
static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);

#if (defined(REAL_DMA) || defined(REAL_DMA_POLL))

#if defined(i386) || defined(__alpha__)

/**
 *	NCR5380_pc_dma_setup		-	setup ISA DMA
 *	@instance: adapter to set up
 *	@ptr: block to transfer (virtual address)
 *	@count: number of bytes to transfer
 *	@mode: DMA controller mode to use
 *
 *	Program the DMA controller ready to perform an ISA DMA transfer
 *	on this chip.
 *
 *	Locks: takes and releases the ISA DMA lock.
 */
 
static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
{
	unsigned limit;
	unsigned long bus_addr = virt_to_bus(ptr);
	unsigned long flags;

	if (instance->dma_channel <= 3) {
		if (count > 65536)
			count = 65536;
		limit = 65536 - (bus_addr & 0xFFFF);
	} else {
		if (count > 65536 * 2)
			count = 65536 * 2;
		limit = 65536 * 2 - (bus_addr & 0x1FFFF);
	}

	if (count > limit)
		count = limit;

	if ((count & 1) || (bus_addr & 1))
		panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
	
	flags=claim_dma_lock();
	disable_dma(instance->dma_channel);
	clear_dma_ff(instance->dma_channel);
	set_dma_addr(instance->dma_channel, bus_addr);
	set_dma_count(instance->dma_channel, count);
	set_dma_mode(instance->dma_channel, mode);
	enable_dma(instance->dma_channel);
	release_dma_lock(flags);
	
	return count;
}

/**
 *	NCR5380_pc_dma_write_setup		-	setup ISA DMA write
 *	@instance: adapter to set up
 *	@ptr: block to transfer (virtual address)
 *	@count: number of bytes to transfer
 *
 *	Program the DMA controller ready to perform an ISA DMA write to the
 *	SCSI controller.
 *
 *	Locks: called routines take and release the ISA DMA lock.
 */

static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
{
	return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
}

/**
 *	NCR5380_pc_dma_read_setup		-	setup ISA DMA read
 *	@instance: adapter to set up
 *	@ptr: block to transfer (virtual address)
 *	@count: number of bytes to transfer
 *
 *	Program the DMA controller ready to perform an ISA DMA read from the
 *	SCSI controller.
 *
 *	Locks: called routines take and release the ISA DMA lock.
 */

static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
{
	return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
}

/**
 *	NCR5380_pc_dma_residual		-	return bytes left 
 *	@instance: adapter
 *
 *	Reports the number of bytes left over after the DMA was terminated.
 *
 *	Locks: takes and releases the ISA DMA lock.
 */

static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
{
	unsigned long flags;
	int tmp;

	flags = claim_dma_lock();
	clear_dma_ff(instance->dma_channel);
	tmp = get_dma_residue(instance->dma_channel);
	release_dma_lock(flags);
	
	return tmp;
}
#endif				/* defined(i386) || defined(__alpha__) */
#endif				/* defined(REAL_DMA)  */
#endif				/* __KERNEL__ */
#endif				/* NCR5380_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* NCR 5380 defines
	3	*
	4	* Copyright 1993, Drew Eckhardt
	5	* Visionary Computing
	6	* (Unix consulting and custom programming)
	7	* drew@colorado.edu
	8	* +1 (303) 666-5836
	9	*
1da177e4 LT	10	* For more information, please consult
	11	*
	12	* NCR 5380 Family
	13	* SCSI Protocol Controller
	14	* Databook
	15	* NCR Microelectronics
	16	* 1635 Aeroplaza Drive
	17	* Colorado Springs, CO 80916
	18	* 1+ (719) 578-3400
	19	* 1+ (800) 334-5454
	20	*/
	21
1da177e4 LT	22	#ifndef NCR5380_H
	23	#define NCR5380_H
	24
	25	#include <linux/interrupt.h>
28424d3a	26	#include <scsi/scsi_eh.h>
28424d3a	27
1da177e4 LT	28	#define NDEBUG_ARBITRATION 0x1
	29	#define NDEBUG_AUTOSENSE 0x2
	30	#define NDEBUG_DMA 0x4
	31	#define NDEBUG_HANDSHAKE 0x8
	32	#define NDEBUG_INFORMATION 0x10
	33	#define NDEBUG_INIT 0x20
	34	#define NDEBUG_INTR 0x40
	35	#define NDEBUG_LINKED 0x80
	36	#define NDEBUG_MAIN 0x100
	37	#define NDEBUG_NO_DATAOUT 0x200
	38	#define NDEBUG_NO_WRITE 0x400
	39	#define NDEBUG_PIO 0x800
	40	#define NDEBUG_PSEUDO_DMA 0x1000
	41	#define NDEBUG_QUEUES 0x2000
	42	#define NDEBUG_RESELECTION 0x4000
	43	#define NDEBUG_SELECTION 0x8000
	44	#define NDEBUG_USLEEP 0x10000
	45	#define NDEBUG_LAST_BYTE_SENT 0x20000
	46	#define NDEBUG_RESTART_SELECT 0x40000
	47	#define NDEBUG_EXTENDED 0x80000
	48	#define NDEBUG_C400_PREAD 0x100000
	49	#define NDEBUG_C400_PWRITE 0x200000
	50	#define NDEBUG_LISTS 0x400000
9829e528 FT	51	#define NDEBUG_ABORT 0x800000
	52	#define NDEBUG_TAGS 0x1000000
	53	#define NDEBUG_MERGING 0x2000000
1da177e4 LT	54
	55	#define NDEBUG_ANY 0xFFFFFFFFUL
	56
	57	/*
	58	* The contents of the OUTPUT DATA register are asserted on the bus when
	59	* either arbitration is occurring or the phase-indicating signals (
	60	* IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
	61	* bit in the INITIATOR COMMAND register is set.
	62	*/
	63
	64	#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
	65	#define CURRENT_SCSI_DATA_REG 0 /* ro same */
	66
	67	#define INITIATOR_COMMAND_REG 1 /* rw */
	68	#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
	69	#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
	70	#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
	71	#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
	72	#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
	73	#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
	74	#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
	75	#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
	76	#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
	77	#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
	78
	79	#ifdef DIFFERENTIAL
	80	#define ICR_BASE ICR_DIFF_ENABLE
	81	#else
	82	#define ICR_BASE 0
	83	#endif
	84
	85	#define MODE_REG 2
	86	/*
	87	* Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
	88	* transfer, causing the chip to hog the bus. You probably don't want
	89	* this.
	90	*/
	91	#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
	92	#define MR_TARGET 0x40 /* rw target mode */
	93	#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
	94	#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
	95	#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
	96	#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
	97	#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
	98	#define MR_ARBITRATE 0x01 /* rw start arbitration */
	99
	100	#ifdef PARITY
	101	#define MR_BASE MR_ENABLE_PAR_CHECK
	102	#else
	103	#define MR_BASE 0
	104	#endif
	105
	106	#define TARGET_COMMAND_REG 3
	107	#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
	108	#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
	109	#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
	110	#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
	111	#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
	112
	113	#define STATUS_REG 4 /* ro */
	114	/*
	115	* Note : a set bit indicates an active signal, driven by us or another
	116	* device.
	117	*/
118	#define SR_RST 0x80
119	#define SR_BSY 0x40
120	#define SR_REQ 0x20
121	#define SR_MSG 0x10
122	#define SR_CD 0x08
123	#define SR_IO 0x04
124	#define SR_SEL 0x02
125	#define SR_DBP 0x01
126
127	/*
128	* Setting a bit in this register will cause an interrupt to be generated when
129	* BSY is false and SEL true and this bit is asserted on the bus.
130	*/
131	#define SELECT_ENABLE_REG 4 /* wo */
132
133	#define BUS_AND_STATUS_REG 5 /* ro */
134	#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
135	#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
136	#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
137	#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
138	#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
139	#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
140	#define BASR_ATN 0x02 /* ro BUS status */
141	#define BASR_ACK 0x01 /* ro BUS status */
142
143	/* Write any value to this register to start a DMA send */
144	#define START_DMA_SEND_REG 5 /* wo */
145
146	/*
147	* Used in DMA transfer mode, data is latched from the SCSI bus on
148	* the falling edge of REQ (ini) or ACK (tgt)
149	*/
150	#define INPUT_DATA_REG 6 /* ro */
151
152	/* Write any value to this register to start a DMA receive */
153	#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
154
155	/* Read this register to clear interrupt conditions */
156	#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
157
158	/* Write any value to this register to start an ini mode DMA receive */
159	#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
160
161	#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
162
163	#define CSR_RESET 0x80 /* wo Resets 53c400 */
164	#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
165	#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
166	#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
167	#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
168	#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
169	#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
170	#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
171	#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
172
173	#if 0
174	#define CSR_BASE CSR_SCSI_BUFF_INTR \| CSR_53C80_INTR
175	#else
176	#define CSR_BASE CSR_53C80_INTR
177	#endif
178
179	/* Number of 128-byte blocks to be transferred */
180	#define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
181
182	/* Resume transfer after disconnect */
183	#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
184
185	/* Access to host buffer stack */
186	#define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
187
188
189	/* Note : PHASE_* macros are based on the values of the STATUS register */
190	#define PHASE_MASK (SR_MSG \| SR_CD \| SR_IO)
191
192	#define PHASE_DATAOUT 0
193	#define PHASE_DATAIN SR_IO
194	#define PHASE_CMDOUT SR_CD
195	#define PHASE_STATIN (SR_CD \| SR_IO)
196	#define PHASE_MSGOUT (SR_MSG \| SR_CD)
197	#define PHASE_MSGIN (SR_MSG \| SR_CD \| SR_IO)
198	#define PHASE_UNKNOWN 0xff
199
200	/*
201	* Convert status register phase to something we can use to set phase in
202	* the target register so we can get phase mismatch interrupts on DMA
203	* transfers.
204	*/
205
206	#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
207
1da177e4	208	/*
76f13b93 FT	209	* "Special" value for the (unsigned char) command tag, to indicate
76f13b93 FT	210	* I_T_L nexus instead of I_T_L_Q.
1da177e4 LT	211	*/
1da177e4 LT	212
76f13b93	213	#define TAG_NONE 0xff
1da177e4 LT	214
	215	/*
	216	* These are "special" values for the irq and dma_channel fields of the
	217	* Scsi_Host structure
	218	*/
	219
1da177e4 LT	220	#define DMA_NONE 255
	221	#define IRQ_AUTO 254
	222	#define DMA_AUTO 254
	223	#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
	224
22f5f10d FT	225	#ifndef NO_IRQ
	226	#define NO_IRQ 0
	227	#endif
	228
1da177e4 LT	229	#define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
	230	#define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
	231	#define FLAG_NCR53C400 4 /* NCR53c400 */
	232	#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
	233	#define FLAG_DTC3181E 16 /* DTC3181E */
ef1081cb	234	#define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */
ca513fc9	235	#define FLAG_TAGGED_QUEUING 64 /* as X3T9.2 spelled it */
9c3f0e2b	236	#define FLAG_TOSHIBA_DELAY 128 /* Allow for borken CD-ROMs */
1da177e4	237
61d739a4 FT	238	#ifdef SUPPORT_TAGS
	239	struct tag_alloc {
	240	DECLARE_BITMAP(allocated, MAX_TAGS);
	241	int nr_allocated;
	242	int queue_size;
	243	};
	244	#endif
	245
1da177e4 LT	246	struct NCR5380_hostdata {
	247	NCR5380_implementation_fields; /* implementation specific */
	248	struct Scsi_Host host; / Host backpointer */
	249	unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
1da177e4 LT	250	volatile unsigned char busy[8]; /* index = target, bit = lun */
	251	#if defined(REAL_DMA) \|\| defined(REAL_DMA_POLL)
	252	volatile int dma_len; /* requested length of DMA */
	253	#endif
	254	volatile unsigned char last_message; /* last message OUT */
710ddd0d FT	255	volatile struct scsi_cmnd connected; / currently connected command */
	256	volatile struct scsi_cmnd issue_queue; / waiting to be issued */
	257	volatile struct scsi_cmnd disconnected_queue; / waiting for reconnect */
1da177e4	258	int flags;
28424d3a	259	struct scsi_eh_save ses;
8c32513b	260	char info[256];
ef1081cb FT	261	int read_overruns; /* number of bytes to cut from a
	262	* transfer to handle chip overruns */
	263	int retain_dma_intr;
a53a21e4	264	struct work_struct main_task;
61d739a4 FT	265	#ifdef SUPPORT_TAGS
	266	struct tag_alloc TagAlloc[8][8]; /* 8 targets and 8 LUNs */
	267	#endif
a9c2dc43 FT	268	#ifdef PSEUDO_DMA
	269	unsigned spin_max_r;
	270	unsigned spin_max_w;
	271	#endif
0ad0eff9	272	struct workqueue_struct *work_q;
2f854b82	273	unsigned long accesses_per_ms; /* chip register accesses per ms */
1da177e4 LT	274	};
	275
	276	#ifdef __KERNEL__
	277
9829e528 FT	278	#ifndef NDEBUG
	279	#define NDEBUG (0)
	280	#endif
	281
16b9d870	282	#define dprintk(flg, fmt, ...) \
d61c5427 FT	283	do { if ((NDEBUG) & (flg)) \
d61c5427 FT	284	printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
16b9d870	285
9829e528	286	#if NDEBUG
9829e528 FT	287	#define NCR5380_dprint(flg, arg) \
	288	do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
	289	#define NCR5380_dprint_phase(flg, arg) \
	290	do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
	291	static void NCR5380_print_phase(struct Scsi_Host *instance);
	292	static void NCR5380_print(struct Scsi_Host *instance);
	293	#else
52a6a1cb FT	294	#define NCR5380_dprint(flg, arg) do {} while (0)
52a6a1cb FT	295	#define NCR5380_dprint_phase(flg, arg) do {} while (0)
9829e528	296	#endif
1da177e4 LT	297
	298	#if defined(AUTOPROBE_IRQ)
	299	static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
	300	#endif
	301	static int NCR5380_init(struct Scsi_Host *instance, int flags);
b6488f97	302	static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
1da177e4 LT	303	static void NCR5380_exit(struct Scsi_Host *instance);
	304	static void NCR5380_information_transfer(struct Scsi_Host *instance);
	305	#ifndef DONT_USE_INTR
7d12e780	306	static irqreturn_t NCR5380_intr(int irq, void *dev_id);
1da177e4	307	#endif
c4028958	308	static void NCR5380_main(struct work_struct *work);
8c32513b	309	static const char NCR5380_info(struct Scsi_Host instance);
1da177e4	310	static void NCR5380_reselect(struct Scsi_Host *instance);
710ddd0d	311	static int NCR5380_select(struct Scsi_Host instance, struct scsi_cmnd cmd);
1da177e4 LT	312	#if defined(PSEUDO_DMA) \|\| defined(REAL_DMA) \|\| defined(REAL_DMA_POLL)
	313	static int NCR5380_transfer_dma(struct Scsi_Host instance, unsigned char phase, int count, unsigned char *data);
	314	#endif
	315	static int NCR5380_transfer_pio(struct Scsi_Host instance, unsigned char phase, int count, unsigned char *data);
	316
	317	#if (defined(REAL_DMA) \|\| defined(REAL_DMA_POLL))
	318
	319	#if defined(i386) \|\| defined(__alpha__)
	320
	321	/**
	322	* NCR5380_pc_dma_setup - setup ISA DMA
	323	* @instance: adapter to set up
	324	* @ptr: block to transfer (virtual address)
	325	* @count: number of bytes to transfer
	326	* @mode: DMA controller mode to use
	327	*
	328	* Program the DMA controller ready to perform an ISA DMA transfer
	329	* on this chip.
	330	*
	331	* Locks: takes and releases the ISA DMA lock.
	332	*/
	333
	334	static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host instance, unsigned char ptr, unsigned int count, unsigned char mode)
	335	{
	336	unsigned limit;
	337	unsigned long bus_addr = virt_to_bus(ptr);
	338	unsigned long flags;
	339
	340	if (instance->dma_channel <= 3) {
	341	if (count > 65536)
	342	count = 65536;
	343	limit = 65536 - (bus_addr & 0xFFFF);
	344	} else {
	345	if (count > 65536 * 2)
	346	count = 65536 * 2;
	347	limit = 65536 * 2 - (bus_addr & 0x1FFFF);
	348	}
	349
	350	if (count > limit)
	351	count = limit;
	352
	353	if ((count & 1) \|\| (bus_addr & 1))
	354	panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
	355
	356	flags=claim_dma_lock();
	357	disable_dma(instance->dma_channel);
	358	clear_dma_ff(instance->dma_channel);
	359	set_dma_addr(instance->dma_channel, bus_addr);
	360	set_dma_count(instance->dma_channel, count);
	361	set_dma_mode(instance->dma_channel, mode);
	362	enable_dma(instance->dma_channel);
	363	release_dma_lock(flags);
	364
	365	return count;
	366	}
	367
	368	/**
	369	* NCR5380_pc_dma_write_setup - setup ISA DMA write
	370	* @instance: adapter to set up
	371	* @ptr: block to transfer (virtual address)
	372	* @count: number of bytes to transfer
	373	*
	374	* Program the DMA controller ready to perform an ISA DMA write to the
	375	* SCSI controller.
376	*
377	* Locks: called routines take and release the ISA DMA lock.
378	*/
379
380	static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host instance, unsigned char src, unsigned int count)
381	{
382	return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
383	}
384
385	/**
386	* NCR5380_pc_dma_read_setup - setup ISA DMA read
387	* @instance: adapter to set up
388	* @ptr: block to transfer (virtual address)
389	* @count: number of bytes to transfer
390	*
391	* Program the DMA controller ready to perform an ISA DMA read from the
392	* SCSI controller.
393	*
394	* Locks: called routines take and release the ISA DMA lock.
395	*/
396
397	static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host instance, unsigned char src, unsigned int count)
398	{
399	return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
400	}
401
402	/**
403	* NCR5380_pc_dma_residual - return bytes left
404	* @instance: adapter
405	*
406	* Reports the number of bytes left over after the DMA was terminated.
407	*
408	* Locks: takes and releases the ISA DMA lock.
409	*/
410
411	static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
412	{
413	unsigned long flags;
414	int tmp;
415
416	flags = claim_dma_lock();
417	clear_dma_ff(instance->dma_channel);
418	tmp = get_dma_residue(instance->dma_channel);
419	release_dma_lock(flags);
420
421	return tmp;
422	}
423	#endif /* defined(i386) \|\| defined(__alpha__) */
424	#endif /* defined(REAL_DMA) */
425	#endif /* __KERNEL__ */
1da177e4	426	#endif /* NCR5380_H */