]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/sched.h> | |
87507cfd | 43 | #include <linux/dma-mapping.h> |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
47 | #include <linux/libata.h> |
48 | #include <asm/io.h> | |
49 | ||
50 | #define DRV_NAME "ahci" | |
af64371a | 51 | #define DRV_VERSION "1.3" |
1da177e4 LT |
52 | |
53 | ||
54 | enum { | |
55 | AHCI_PCI_BAR = 5, | |
56 | AHCI_MAX_SG = 168, /* hardware max is 64K */ | |
57 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
58 | AHCI_USE_CLUSTERING = 0, | |
12fad3f9 | 59 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 60 | AHCI_CMD_SZ = 32, |
12fad3f9 | 61 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 62 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 63 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
64 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
65 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
66 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
67 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
68 | AHCI_RX_FIS_SZ, |
69 | AHCI_IRQ_ON_SG = (1 << 31), | |
70 | AHCI_CMD_ATAPI = (1 << 5), | |
71 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 72 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
73 | AHCI_CMD_RESET = (1 << 8), |
74 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
75 | |
76 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
78cd52d0 | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
78 | |
79 | board_ahci = 0, | |
bf2af2a2 | 80 | board_ahci_vt8251 = 1, |
1da177e4 LT |
81 | |
82 | /* global controller registers */ | |
83 | HOST_CAP = 0x00, /* host capabilities */ | |
84 | HOST_CTL = 0x04, /* global host control */ | |
85 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
86 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
87 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
88 | ||
89 | /* HOST_CTL bits */ | |
90 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
91 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
92 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
93 | ||
94 | /* HOST_CAP bits */ | |
22b49985 | 95 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
979db803 | 96 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 97 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
98 | |
99 | /* registers for each SATA port */ | |
100 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
101 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
102 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
103 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
104 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
105 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
106 | PORT_CMD = 0x18, /* port command */ | |
107 | PORT_TFDATA = 0x20, /* taskfile data */ | |
108 | PORT_SIG = 0x24, /* device TF signature */ | |
109 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
110 | PORT_SCR = 0x28, /* SATA phy register block */ | |
111 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ | |
112 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
113 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
114 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
115 | ||
116 | /* PORT_IRQ_{STAT,MASK} bits */ | |
117 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
118 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
119 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
120 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
121 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
122 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
123 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
124 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
125 | ||
126 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
127 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
128 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
129 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
130 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
131 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
132 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
133 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
134 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
135 | ||
78cd52d0 TH |
136 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
137 | PORT_IRQ_IF_ERR | | |
138 | PORT_IRQ_CONNECT | | |
4296971d | 139 | PORT_IRQ_PHYRDY | |
78cd52d0 TH |
140 | PORT_IRQ_UNK_FIS, |
141 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | | |
142 | PORT_IRQ_TF_ERR | | |
143 | PORT_IRQ_HBUS_DATA_ERR, | |
144 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
145 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
146 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
147 | |
148 | /* PORT_CMD bits */ | |
02eaa666 | 149 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
1da177e4 LT |
150 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
151 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
152 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 153 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
154 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
155 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
156 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
157 | ||
158 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ | |
159 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
160 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 JG |
161 | |
162 | /* hpriv->flags bits */ | |
163 | AHCI_FLAG_MSI = (1 << 0), | |
bf2af2a2 BJ |
164 | |
165 | /* ap->flags bits */ | |
166 | AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24), | |
1da177e4 LT |
167 | }; |
168 | ||
169 | struct ahci_cmd_hdr { | |
170 | u32 opts; | |
171 | u32 status; | |
172 | u32 tbl_addr; | |
173 | u32 tbl_addr_hi; | |
174 | u32 reserved[4]; | |
175 | }; | |
176 | ||
177 | struct ahci_sg { | |
178 | u32 addr; | |
179 | u32 addr_hi; | |
180 | u32 reserved; | |
181 | u32 flags_size; | |
182 | }; | |
183 | ||
184 | struct ahci_host_priv { | |
185 | unsigned long flags; | |
186 | u32 cap; /* cache of HOST_CAP register */ | |
187 | u32 port_map; /* cache of HOST_PORTS_IMPL reg */ | |
188 | }; | |
189 | ||
190 | struct ahci_port_priv { | |
191 | struct ahci_cmd_hdr *cmd_slot; | |
192 | dma_addr_t cmd_slot_dma; | |
193 | void *cmd_tbl; | |
194 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
195 | void *rx_fis; |
196 | dma_addr_t rx_fis_dma; | |
197 | }; | |
198 | ||
199 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
200 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
201 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
9a3d9eb0 | 202 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 203 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs); |
1da177e4 | 204 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
205 | static int ahci_port_start(struct ata_port *ap); |
206 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
207 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
208 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
209 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
210 | static void ahci_freeze(struct ata_port *ap); |
211 | static void ahci_thaw(struct ata_port *ap); | |
212 | static void ahci_error_handler(struct ata_port *ap); | |
213 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); | |
907f4678 | 214 | static void ahci_remove_one (struct pci_dev *pdev); |
1da177e4 | 215 | |
193515d5 | 216 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
217 | .module = THIS_MODULE, |
218 | .name = DRV_NAME, | |
219 | .ioctl = ata_scsi_ioctl, | |
220 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
221 | .change_queue_depth = ata_scsi_change_queue_depth, |
222 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
223 | .this_id = ATA_SHT_THIS_ID, |
224 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
225 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
226 | .emulated = ATA_SHT_EMULATED, | |
227 | .use_clustering = AHCI_USE_CLUSTERING, | |
228 | .proc_name = DRV_NAME, | |
229 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
230 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 231 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 232 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
233 | }; |
234 | ||
057ace5e | 235 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
236 | .port_disable = ata_port_disable, |
237 | ||
238 | .check_status = ahci_check_status, | |
239 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
240 | .dev_select = ata_noop_dev_select, |
241 | ||
242 | .tf_read = ahci_tf_read, | |
243 | ||
1da177e4 LT |
244 | .qc_prep = ahci_qc_prep, |
245 | .qc_issue = ahci_qc_issue, | |
246 | ||
1da177e4 LT |
247 | .irq_handler = ahci_interrupt, |
248 | .irq_clear = ahci_irq_clear, | |
249 | ||
250 | .scr_read = ahci_scr_read, | |
251 | .scr_write = ahci_scr_write, | |
252 | ||
78cd52d0 TH |
253 | .freeze = ahci_freeze, |
254 | .thaw = ahci_thaw, | |
255 | ||
256 | .error_handler = ahci_error_handler, | |
257 | .post_internal_cmd = ahci_post_internal_cmd, | |
258 | ||
1da177e4 LT |
259 | .port_start = ahci_port_start, |
260 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
261 | }; |
262 | ||
98ac62de | 263 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
264 | /* board_ahci */ |
265 | { | |
266 | .sht = &ahci_sht, | |
267 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
4296971d TH |
268 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
269 | ATA_FLAG_SKIP_D2H_BSY, | |
7da79312 | 270 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 LT |
271 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
272 | .port_ops = &ahci_ops, | |
273 | }, | |
bf2af2a2 BJ |
274 | /* board_ahci_vt8251 */ |
275 | { | |
276 | .sht = &ahci_sht, | |
277 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
278 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
4296971d | 279 | ATA_FLAG_SKIP_D2H_BSY | |
bf2af2a2 BJ |
280 | AHCI_FLAG_RESET_NEEDS_CLO, |
281 | .pio_mask = 0x1f, /* pio0-4 */ | |
282 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
283 | .port_ops = &ahci_ops, | |
284 | }, | |
1da177e4 LT |
285 | }; |
286 | ||
3b7d697d | 287 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 288 | /* Intel */ |
1da177e4 LT |
289 | { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
290 | board_ahci }, /* ICH6 */ | |
291 | { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
292 | board_ahci }, /* ICH6M */ | |
293 | { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
294 | board_ahci }, /* ICH7 */ | |
295 | { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
296 | board_ahci }, /* ICH7M */ | |
297 | { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
298 | board_ahci }, /* ICH7R */ | |
299 | { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
300 | board_ahci }, /* ULi M5288 */ | |
680d3235 JG |
301 | { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
302 | board_ahci }, /* ESB2 */ | |
303 | { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
304 | board_ahci }, /* ESB2 */ | |
305 | { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
306 | board_ahci }, /* ESB2 */ | |
3db368f7 JG |
307 | { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
308 | board_ahci }, /* ICH7-M DH */ | |
f285757c JG |
309 | { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
310 | board_ahci }, /* ICH8 */ | |
311 | { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
312 | board_ahci }, /* ICH8 */ | |
313 | { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
314 | board_ahci }, /* ICH8 */ | |
315 | { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
316 | board_ahci }, /* ICH8M */ | |
317 | { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
318 | board_ahci }, /* ICH8M */ | |
fe7fa31a JG |
319 | |
320 | /* JMicron */ | |
bd12097c JG |
321 | { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
322 | board_ahci }, /* JMicron JMB360 */ | |
9220a2d0 JG |
323 | { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
324 | board_ahci }, /* JMicron JMB363 */ | |
fe7fa31a JG |
325 | |
326 | /* ATI */ | |
8b316a39 JG |
327 | { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
328 | board_ahci }, /* ATI SB600 non-raid */ | |
329 | { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
330 | board_ahci }, /* ATI SB600 raid */ | |
fe7fa31a JG |
331 | |
332 | /* VIA */ | |
bf2af2a2 BJ |
333 | { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
334 | board_ahci_vt8251 }, /* VIA VT8251 */ | |
fe7fa31a JG |
335 | |
336 | /* NVIDIA */ | |
337 | { PCI_VENDOR_ID_NVIDIA, 0x044c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
338 | board_ahci }, /* MCP65 */ | |
339 | { PCI_VENDOR_ID_NVIDIA, 0x044d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
340 | board_ahci }, /* MCP65 */ | |
341 | { PCI_VENDOR_ID_NVIDIA, 0x044e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
342 | board_ahci }, /* MCP65 */ | |
343 | { PCI_VENDOR_ID_NVIDIA, 0x044f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
344 | board_ahci }, /* MCP65 */ | |
345 | ||
1da177e4 LT |
346 | { } /* terminate list */ |
347 | }; | |
348 | ||
349 | ||
350 | static struct pci_driver ahci_pci_driver = { | |
351 | .name = DRV_NAME, | |
352 | .id_table = ahci_pci_tbl, | |
353 | .probe = ahci_init_one, | |
907f4678 | 354 | .remove = ahci_remove_one, |
1da177e4 LT |
355 | }; |
356 | ||
357 | ||
358 | static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port) | |
359 | { | |
360 | return base + 0x100 + (port * 0x80); | |
361 | } | |
362 | ||
ea6ba10b | 363 | static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port) |
1da177e4 | 364 | { |
ea6ba10b | 365 | return (void __iomem *) ahci_port_base_ul((unsigned long)base, port); |
1da177e4 LT |
366 | } |
367 | ||
1da177e4 LT |
368 | static int ahci_port_start(struct ata_port *ap) |
369 | { | |
370 | struct device *dev = ap->host_set->dev; | |
371 | struct ahci_host_priv *hpriv = ap->host_set->private_data; | |
372 | struct ahci_port_priv *pp; | |
ea6ba10b JG |
373 | void __iomem *mmio = ap->host_set->mmio_base; |
374 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
375 | void *mem; | |
1da177e4 | 376 | dma_addr_t mem_dma; |
6037d6bb | 377 | int rc; |
1da177e4 | 378 | |
1da177e4 | 379 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); |
0a139e79 TH |
380 | if (!pp) |
381 | return -ENOMEM; | |
1da177e4 LT |
382 | memset(pp, 0, sizeof(*pp)); |
383 | ||
6037d6bb JG |
384 | rc = ata_pad_alloc(ap, dev); |
385 | if (rc) { | |
cedc9a47 | 386 | kfree(pp); |
6037d6bb | 387 | return rc; |
cedc9a47 JG |
388 | } |
389 | ||
1da177e4 LT |
390 | mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); |
391 | if (!mem) { | |
6037d6bb | 392 | ata_pad_free(ap, dev); |
0a139e79 TH |
393 | kfree(pp); |
394 | return -ENOMEM; | |
1da177e4 LT |
395 | } |
396 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
397 | ||
398 | /* | |
399 | * First item in chunk of DMA memory: 32-slot command table, | |
400 | * 32 bytes each in size | |
401 | */ | |
402 | pp->cmd_slot = mem; | |
403 | pp->cmd_slot_dma = mem_dma; | |
404 | ||
405 | mem += AHCI_CMD_SLOT_SZ; | |
406 | mem_dma += AHCI_CMD_SLOT_SZ; | |
407 | ||
408 | /* | |
409 | * Second item: Received-FIS area | |
410 | */ | |
411 | pp->rx_fis = mem; | |
412 | pp->rx_fis_dma = mem_dma; | |
413 | ||
414 | mem += AHCI_RX_FIS_SZ; | |
415 | mem_dma += AHCI_RX_FIS_SZ; | |
416 | ||
417 | /* | |
418 | * Third item: data area for storing a single command | |
419 | * and its scatter-gather table | |
420 | */ | |
421 | pp->cmd_tbl = mem; | |
422 | pp->cmd_tbl_dma = mem_dma; | |
423 | ||
1da177e4 LT |
424 | ap->private_data = pp; |
425 | ||
426 | if (hpriv->cap & HOST_CAP_64) | |
427 | writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); | |
428 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
429 | readl(port_mmio + PORT_LST_ADDR); /* flush */ | |
430 | ||
431 | if (hpriv->cap & HOST_CAP_64) | |
432 | writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); | |
433 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
434 | readl(port_mmio + PORT_FIS_ADDR); /* flush */ | |
435 | ||
436 | writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | |
437 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | | |
438 | PORT_CMD_START, port_mmio + PORT_CMD); | |
439 | readl(port_mmio + PORT_CMD); /* flush */ | |
440 | ||
441 | return 0; | |
1da177e4 LT |
442 | } |
443 | ||
444 | ||
445 | static void ahci_port_stop(struct ata_port *ap) | |
446 | { | |
447 | struct device *dev = ap->host_set->dev; | |
448 | struct ahci_port_priv *pp = ap->private_data; | |
ea6ba10b JG |
449 | void __iomem *mmio = ap->host_set->mmio_base; |
450 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1da177e4 LT |
451 | u32 tmp; |
452 | ||
453 | tmp = readl(port_mmio + PORT_CMD); | |
454 | tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX); | |
455 | writel(tmp, port_mmio + PORT_CMD); | |
456 | readl(port_mmio + PORT_CMD); /* flush */ | |
457 | ||
458 | /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so | |
459 | * this is slightly incorrect. | |
460 | */ | |
461 | msleep(500); | |
462 | ||
463 | ap->private_data = NULL; | |
464 | dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, | |
465 | pp->cmd_slot, pp->cmd_slot_dma); | |
6037d6bb | 466 | ata_pad_free(ap, dev); |
1da177e4 | 467 | kfree(pp); |
1da177e4 LT |
468 | } |
469 | ||
470 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) | |
471 | { | |
472 | unsigned int sc_reg; | |
473 | ||
474 | switch (sc_reg_in) { | |
475 | case SCR_STATUS: sc_reg = 0; break; | |
476 | case SCR_CONTROL: sc_reg = 1; break; | |
477 | case SCR_ERROR: sc_reg = 2; break; | |
478 | case SCR_ACTIVE: sc_reg = 3; break; | |
479 | default: | |
480 | return 0xffffffffU; | |
481 | } | |
482 | ||
1e4f2a96 | 483 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
484 | } |
485 | ||
486 | ||
487 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |
488 | u32 val) | |
489 | { | |
490 | unsigned int sc_reg; | |
491 | ||
492 | switch (sc_reg_in) { | |
493 | case SCR_STATUS: sc_reg = 0; break; | |
494 | case SCR_CONTROL: sc_reg = 1; break; | |
495 | case SCR_ERROR: sc_reg = 2; break; | |
496 | case SCR_ACTIVE: sc_reg = 3; break; | |
497 | default: | |
498 | return; | |
499 | } | |
500 | ||
1e4f2a96 | 501 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
502 | } |
503 | ||
7c76d1e8 TH |
504 | static int ahci_stop_engine(struct ata_port *ap) |
505 | { | |
506 | void __iomem *mmio = ap->host_set->mmio_base; | |
507 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
508 | int work; | |
509 | u32 tmp; | |
510 | ||
511 | tmp = readl(port_mmio + PORT_CMD); | |
512 | tmp &= ~PORT_CMD_START; | |
513 | writel(tmp, port_mmio + PORT_CMD); | |
514 | ||
515 | /* wait for engine to stop. TODO: this could be | |
516 | * as long as 500 msec | |
517 | */ | |
518 | work = 1000; | |
519 | while (work-- > 0) { | |
520 | tmp = readl(port_mmio + PORT_CMD); | |
521 | if ((tmp & PORT_CMD_LIST_ON) == 0) | |
522 | return 0; | |
523 | udelay(10); | |
524 | } | |
525 | ||
526 | return -EIO; | |
527 | } | |
528 | ||
529 | static void ahci_start_engine(struct ata_port *ap) | |
530 | { | |
531 | void __iomem *mmio = ap->host_set->mmio_base; | |
532 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
533 | u32 tmp; | |
534 | ||
535 | tmp = readl(port_mmio + PORT_CMD); | |
536 | tmp |= PORT_CMD_START; | |
537 | writel(tmp, port_mmio + PORT_CMD); | |
538 | readl(port_mmio + PORT_CMD); /* flush */ | |
539 | } | |
540 | ||
422b7595 | 541 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 LT |
542 | { |
543 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
544 | struct ata_taskfile tf; | |
422b7595 TH |
545 | u32 tmp; |
546 | ||
547 | tmp = readl(port_mmio + PORT_SIG); | |
548 | tf.lbah = (tmp >> 24) & 0xff; | |
549 | tf.lbam = (tmp >> 16) & 0xff; | |
550 | tf.lbal = (tmp >> 8) & 0xff; | |
551 | tf.nsect = (tmp) & 0xff; | |
552 | ||
553 | return ata_dev_classify(&tf); | |
554 | } | |
555 | ||
12fad3f9 TH |
556 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
557 | u32 opts) | |
cc9278ed | 558 | { |
12fad3f9 TH |
559 | dma_addr_t cmd_tbl_dma; |
560 | ||
561 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
562 | ||
563 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
564 | pp->cmd_slot[tag].status = 0; | |
565 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
566 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
567 | } |
568 | ||
bf2af2a2 | 569 | static int ahci_clo(struct ata_port *ap) |
4658f79b | 570 | { |
bf2af2a2 | 571 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
4658f79b | 572 | struct ahci_host_priv *hpriv = ap->host_set->private_data; |
bf2af2a2 BJ |
573 | u32 tmp; |
574 | ||
575 | if (!(hpriv->cap & HOST_CAP_CLO)) | |
576 | return -EOPNOTSUPP; | |
577 | ||
578 | tmp = readl(port_mmio + PORT_CMD); | |
579 | tmp |= PORT_CMD_CLO; | |
580 | writel(tmp, port_mmio + PORT_CMD); | |
581 | ||
582 | tmp = ata_wait_register(port_mmio + PORT_CMD, | |
583 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
584 | if (tmp & PORT_CMD_CLO) | |
585 | return -EIO; | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
4296971d TH |
590 | static int ahci_prereset(struct ata_port *ap) |
591 | { | |
592 | if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) && | |
593 | (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) { | |
594 | /* ATA_BUSY hasn't cleared, so send a CLO */ | |
595 | ahci_clo(ap); | |
596 | } | |
597 | ||
598 | return ata_std_prereset(ap); | |
599 | } | |
600 | ||
bf2af2a2 BJ |
601 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) |
602 | { | |
4658f79b TH |
603 | struct ahci_port_priv *pp = ap->private_data; |
604 | void __iomem *mmio = ap->host_set->mmio_base; | |
605 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
606 | const u32 cmd_fis_len = 5; /* five dwords */ | |
607 | const char *reason = NULL; | |
608 | struct ata_taskfile tf; | |
75fe1806 | 609 | u32 tmp; |
4658f79b TH |
610 | u8 *fis; |
611 | int rc; | |
612 | ||
613 | DPRINTK("ENTER\n"); | |
614 | ||
81952c54 | 615 | if (ata_port_offline(ap)) { |
c2a65852 TH |
616 | DPRINTK("PHY reports no device\n"); |
617 | *class = ATA_DEV_NONE; | |
618 | return 0; | |
619 | } | |
620 | ||
4658f79b TH |
621 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
622 | rc = ahci_stop_engine(ap); | |
623 | if (rc) { | |
624 | reason = "failed to stop engine"; | |
625 | goto fail_restart; | |
626 | } | |
627 | ||
628 | /* check BUSY/DRQ, perform Command List Override if necessary */ | |
629 | ahci_tf_read(ap, &tf); | |
630 | if (tf.command & (ATA_BUSY | ATA_DRQ)) { | |
bf2af2a2 | 631 | rc = ahci_clo(ap); |
4658f79b | 632 | |
bf2af2a2 BJ |
633 | if (rc == -EOPNOTSUPP) { |
634 | reason = "port busy but CLO unavailable"; | |
635 | goto fail_restart; | |
636 | } else if (rc) { | |
637 | reason = "port busy but CLO failed"; | |
4658f79b TH |
638 | goto fail_restart; |
639 | } | |
640 | } | |
641 | ||
642 | /* restart engine */ | |
643 | ahci_start_engine(ap); | |
644 | ||
3373efd8 | 645 | ata_tf_init(ap->device, &tf); |
4658f79b TH |
646 | fis = pp->cmd_tbl; |
647 | ||
648 | /* issue the first D2H Register FIS */ | |
12fad3f9 TH |
649 | ahci_fill_cmd_slot(pp, 0, |
650 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); | |
4658f79b TH |
651 | |
652 | tf.ctl |= ATA_SRST; | |
653 | ata_tf_to_fis(&tf, fis, 0); | |
654 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
655 | ||
656 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
4658f79b | 657 | |
75fe1806 TH |
658 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
659 | if (tmp & 0x1) { | |
4658f79b TH |
660 | rc = -EIO; |
661 | reason = "1st FIS failed"; | |
662 | goto fail; | |
663 | } | |
664 | ||
665 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
666 | msleep(1); | |
667 | ||
668 | /* issue the second D2H Register FIS */ | |
12fad3f9 | 669 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
4658f79b TH |
670 | |
671 | tf.ctl &= ~ATA_SRST; | |
672 | ata_tf_to_fis(&tf, fis, 0); | |
673 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
674 | ||
675 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
676 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
677 | ||
678 | /* spec mandates ">= 2ms" before checking status. | |
679 | * We wait 150ms, because that was the magic delay used for | |
680 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time | |
681 | * between when the ATA command register is written, and then | |
682 | * status is checked. Because waiting for "a while" before | |
683 | * checking status is fine, post SRST, we perform this magic | |
684 | * delay here as well. | |
685 | */ | |
686 | msleep(150); | |
687 | ||
688 | *class = ATA_DEV_NONE; | |
81952c54 | 689 | if (ata_port_online(ap)) { |
4658f79b TH |
690 | if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { |
691 | rc = -EIO; | |
692 | reason = "device not ready"; | |
693 | goto fail; | |
694 | } | |
695 | *class = ahci_dev_classify(ap); | |
696 | } | |
697 | ||
698 | DPRINTK("EXIT, class=%u\n", *class); | |
699 | return 0; | |
700 | ||
701 | fail_restart: | |
702 | ahci_start_engine(ap); | |
703 | fail: | |
f15a1daf | 704 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
705 | return rc; |
706 | } | |
707 | ||
2bf2cb26 | 708 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class) |
422b7595 | 709 | { |
4296971d TH |
710 | struct ahci_port_priv *pp = ap->private_data; |
711 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
712 | struct ata_taskfile tf; | |
4bd00f6a TH |
713 | int rc; |
714 | ||
715 | DPRINTK("ENTER\n"); | |
1da177e4 | 716 | |
e0bfd149 | 717 | ahci_stop_engine(ap); |
4296971d TH |
718 | |
719 | /* clear D2H reception area to properly wait for D2H FIS */ | |
720 | ata_tf_init(ap->device, &tf); | |
721 | tf.command = 0xff; | |
722 | ata_tf_to_fis(&tf, d2h_fis, 0); | |
723 | ||
2bf2cb26 | 724 | rc = sata_std_hardreset(ap, class); |
4296971d | 725 | |
e0bfd149 | 726 | ahci_start_engine(ap); |
1da177e4 | 727 | |
81952c54 | 728 | if (rc == 0 && ata_port_online(ap)) |
4bd00f6a TH |
729 | *class = ahci_dev_classify(ap); |
730 | if (*class == ATA_DEV_UNKNOWN) | |
731 | *class = ATA_DEV_NONE; | |
1da177e4 | 732 | |
4bd00f6a TH |
733 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
734 | return rc; | |
735 | } | |
736 | ||
737 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) | |
738 | { | |
739 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
740 | u32 new_tmp, tmp; | |
741 | ||
742 | ata_std_postreset(ap, class); | |
02eaa666 JG |
743 | |
744 | /* Make sure port's ATAPI bit is set appropriately */ | |
745 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 746 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
747 | new_tmp |= PORT_CMD_ATAPI; |
748 | else | |
749 | new_tmp &= ~PORT_CMD_ATAPI; | |
750 | if (new_tmp != tmp) { | |
751 | writel(new_tmp, port_mmio + PORT_CMD); | |
752 | readl(port_mmio + PORT_CMD); /* flush */ | |
753 | } | |
1da177e4 LT |
754 | } |
755 | ||
756 | static u8 ahci_check_status(struct ata_port *ap) | |
757 | { | |
1e4f2a96 | 758 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
1da177e4 LT |
759 | |
760 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
761 | } | |
762 | ||
1da177e4 LT |
763 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
764 | { | |
765 | struct ahci_port_priv *pp = ap->private_data; | |
766 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
767 | ||
768 | ata_tf_from_fis(d2h_fis, tf); | |
769 | } | |
770 | ||
12fad3f9 | 771 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 772 | { |
cedc9a47 JG |
773 | struct scatterlist *sg; |
774 | struct ahci_sg *ahci_sg; | |
828d09de | 775 | unsigned int n_sg = 0; |
1da177e4 LT |
776 | |
777 | VPRINTK("ENTER\n"); | |
778 | ||
779 | /* | |
780 | * Next, the S/G list. | |
781 | */ | |
12fad3f9 | 782 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
783 | ata_for_each_sg(sg, qc) { |
784 | dma_addr_t addr = sg_dma_address(sg); | |
785 | u32 sg_len = sg_dma_len(sg); | |
786 | ||
787 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
788 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
789 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 790 | |
cedc9a47 | 791 | ahci_sg++; |
828d09de | 792 | n_sg++; |
1da177e4 | 793 | } |
828d09de JG |
794 | |
795 | return n_sg; | |
1da177e4 LT |
796 | } |
797 | ||
798 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
799 | { | |
a0ea7328 JG |
800 | struct ata_port *ap = qc->ap; |
801 | struct ahci_port_priv *pp = ap->private_data; | |
cc9278ed | 802 | int is_atapi = is_atapi_taskfile(&qc->tf); |
12fad3f9 | 803 | void *cmd_tbl; |
1da177e4 LT |
804 | u32 opts; |
805 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 806 | unsigned int n_elem; |
1da177e4 | 807 | |
1da177e4 LT |
808 | /* |
809 | * Fill in command table information. First, the header, | |
810 | * a SATA Register - Host to Device command FIS. | |
811 | */ | |
12fad3f9 TH |
812 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
813 | ||
814 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); | |
cc9278ed | 815 | if (is_atapi) { |
12fad3f9 TH |
816 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
817 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 818 | } |
1da177e4 | 819 | |
cc9278ed TH |
820 | n_elem = 0; |
821 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 822 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 823 | |
cc9278ed TH |
824 | /* |
825 | * Fill in command slot information. | |
826 | */ | |
827 | opts = cmd_fis_len | n_elem << 16; | |
828 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
829 | opts |= AHCI_CMD_WRITE; | |
830 | if (is_atapi) | |
4b10e559 | 831 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 832 | |
12fad3f9 | 833 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
834 | } |
835 | ||
78cd52d0 | 836 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 837 | { |
78cd52d0 TH |
838 | struct ahci_port_priv *pp = ap->private_data; |
839 | struct ata_eh_info *ehi = &ap->eh_info; | |
840 | unsigned int err_mask = 0, action = 0; | |
841 | struct ata_queued_cmd *qc; | |
842 | u32 serror; | |
1da177e4 | 843 | |
78cd52d0 | 844 | ata_ehi_clear_desc(ehi); |
1da177e4 | 845 | |
78cd52d0 TH |
846 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
847 | serror = ahci_scr_read(ap, SCR_ERROR); | |
848 | ahci_scr_write(ap, SCR_ERROR, serror); | |
1da177e4 | 849 | |
78cd52d0 TH |
850 | /* analyze @irq_stat */ |
851 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); | |
852 | ||
853 | if (irq_stat & PORT_IRQ_TF_ERR) | |
854 | err_mask |= AC_ERR_DEV; | |
855 | ||
856 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
857 | err_mask |= AC_ERR_HOST_BUS; | |
858 | action |= ATA_EH_SOFTRESET; | |
1da177e4 LT |
859 | } |
860 | ||
78cd52d0 TH |
861 | if (irq_stat & PORT_IRQ_IF_ERR) { |
862 | err_mask |= AC_ERR_ATA_BUS; | |
863 | action |= ATA_EH_SOFTRESET; | |
864 | ata_ehi_push_desc(ehi, ", interface fatal error"); | |
865 | } | |
1da177e4 | 866 | |
78cd52d0 | 867 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
4296971d | 868 | ata_ehi_hotplugged(ehi); |
78cd52d0 TH |
869 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
870 | "connection status changed" : "PHY RDY changed"); | |
871 | } | |
872 | ||
873 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
874 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1da177e4 | 875 | |
78cd52d0 TH |
876 | err_mask |= AC_ERR_HSM; |
877 | action |= ATA_EH_SOFTRESET; | |
878 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", | |
879 | unk[0], unk[1], unk[2], unk[3]); | |
880 | } | |
1da177e4 | 881 | |
78cd52d0 TH |
882 | /* okay, let's hand over to EH */ |
883 | ehi->serror |= serror; | |
884 | ehi->action |= action; | |
b8f6153e | 885 | |
1da177e4 | 886 | qc = ata_qc_from_tag(ap, ap->active_tag); |
78cd52d0 TH |
887 | if (qc) |
888 | qc->err_mask |= err_mask; | |
889 | else | |
890 | ehi->err_mask |= err_mask; | |
a72ec4ce | 891 | |
78cd52d0 TH |
892 | if (irq_stat & PORT_IRQ_FREEZE) |
893 | ata_port_freeze(ap); | |
894 | else | |
895 | ata_port_abort(ap); | |
1da177e4 LT |
896 | } |
897 | ||
78cd52d0 | 898 | static void ahci_host_intr(struct ata_port *ap) |
1da177e4 | 899 | { |
ea6ba10b JG |
900 | void __iomem *mmio = ap->host_set->mmio_base; |
901 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
12fad3f9 TH |
902 | struct ata_eh_info *ehi = &ap->eh_info; |
903 | u32 status, qc_active; | |
904 | int rc; | |
1da177e4 LT |
905 | |
906 | status = readl(port_mmio + PORT_IRQ_STAT); | |
907 | writel(status, port_mmio + PORT_IRQ_STAT); | |
908 | ||
78cd52d0 TH |
909 | if (unlikely(status & PORT_IRQ_ERROR)) { |
910 | ahci_error_intr(ap, status); | |
911 | return; | |
1da177e4 LT |
912 | } |
913 | ||
12fad3f9 TH |
914 | if (ap->sactive) |
915 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
916 | else | |
917 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
918 | ||
919 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
920 | if (rc > 0) | |
921 | return; | |
922 | if (rc < 0) { | |
923 | ehi->err_mask |= AC_ERR_HSM; | |
924 | ehi->action |= ATA_EH_SOFTRESET; | |
925 | ata_port_freeze(ap); | |
926 | return; | |
1da177e4 LT |
927 | } |
928 | ||
2a3917a8 TH |
929 | /* hmmm... a spurious interupt */ |
930 | ||
12fad3f9 TH |
931 | /* some devices send D2H reg with I bit set during NCQ command phase */ |
932 | if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS) | |
933 | return; | |
934 | ||
2a3917a8 TH |
935 | /* ignore interim PIO setup fis interrupts */ |
936 | if (ata_tag_valid(ap->active_tag)) { | |
937 | struct ata_queued_cmd *qc = | |
938 | ata_qc_from_tag(ap, ap->active_tag); | |
939 | ||
940 | if (qc && qc->tf.protocol == ATA_PROT_PIO && | |
941 | (status & PORT_IRQ_PIOS_FIS)) | |
942 | return; | |
943 | } | |
944 | ||
78cd52d0 TH |
945 | if (ata_ratelimit()) |
946 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " | |
12fad3f9 TH |
947 | "(irq_stat 0x%x active_tag %d sactive 0x%x)\n", |
948 | status, ap->active_tag, ap->sactive); | |
1da177e4 LT |
949 | } |
950 | ||
951 | static void ahci_irq_clear(struct ata_port *ap) | |
952 | { | |
953 | /* TODO */ | |
954 | } | |
955 | ||
12fad3f9 | 956 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs) |
1da177e4 LT |
957 | { |
958 | struct ata_host_set *host_set = dev_instance; | |
959 | struct ahci_host_priv *hpriv; | |
960 | unsigned int i, handled = 0; | |
ea6ba10b | 961 | void __iomem *mmio; |
1da177e4 LT |
962 | u32 irq_stat, irq_ack = 0; |
963 | ||
964 | VPRINTK("ENTER\n"); | |
965 | ||
966 | hpriv = host_set->private_data; | |
967 | mmio = host_set->mmio_base; | |
968 | ||
969 | /* sigh. 0xffffffff is a valid return from h/w */ | |
970 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
971 | irq_stat &= hpriv->port_map; | |
972 | if (!irq_stat) | |
973 | return IRQ_NONE; | |
974 | ||
975 | spin_lock(&host_set->lock); | |
976 | ||
977 | for (i = 0; i < host_set->n_ports; i++) { | |
978 | struct ata_port *ap; | |
1da177e4 | 979 | |
67846b30 JG |
980 | if (!(irq_stat & (1 << i))) |
981 | continue; | |
982 | ||
1da177e4 | 983 | ap = host_set->ports[i]; |
67846b30 | 984 | if (ap) { |
78cd52d0 | 985 | ahci_host_intr(ap); |
67846b30 JG |
986 | VPRINTK("port %u\n", i); |
987 | } else { | |
988 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f TH |
989 | if (ata_ratelimit()) |
990 | dev_printk(KERN_WARNING, host_set->dev, | |
a9524a76 | 991 | "interrupt on disabled port %u\n", i); |
1da177e4 | 992 | } |
67846b30 JG |
993 | |
994 | irq_ack |= (1 << i); | |
1da177e4 LT |
995 | } |
996 | ||
997 | if (irq_ack) { | |
998 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
999 | handled = 1; | |
1000 | } | |
1001 | ||
78cd52d0 | 1002 | spin_unlock(&host_set->lock); |
1da177e4 LT |
1003 | |
1004 | VPRINTK("EXIT\n"); | |
1005 | ||
1006 | return IRQ_RETVAL(handled); | |
1007 | } | |
1008 | ||
9a3d9eb0 | 1009 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1010 | { |
1011 | struct ata_port *ap = qc->ap; | |
ea6ba10b | 1012 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
1da177e4 | 1013 | |
12fad3f9 TH |
1014 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1015 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1016 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1017 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
78cd52d0 TH |
1022 | static void ahci_freeze(struct ata_port *ap) |
1023 | { | |
1024 | void __iomem *mmio = ap->host_set->mmio_base; | |
1025 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1026 | ||
1027 | /* turn IRQ off */ | |
1028 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1029 | } | |
1030 | ||
1031 | static void ahci_thaw(struct ata_port *ap) | |
1032 | { | |
1033 | void __iomem *mmio = ap->host_set->mmio_base; | |
1034 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1035 | u32 tmp; | |
1036 | ||
1037 | /* clear IRQ */ | |
1038 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1039 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1040 | writel(1 << ap->id, mmio + HOST_IRQ_STAT); | |
1041 | ||
1042 | /* turn IRQ back on */ | |
1043 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
1044 | } | |
1045 | ||
1046 | static void ahci_error_handler(struct ata_port *ap) | |
1047 | { | |
1048 | if (!(ap->flags & ATA_FLAG_FROZEN)) { | |
1049 | /* restart engine */ | |
1050 | ahci_stop_engine(ap); | |
1051 | ahci_start_engine(ap); | |
1052 | } | |
1053 | ||
1054 | /* perform recovery */ | |
4296971d | 1055 | ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset, |
f5914a46 | 1056 | ahci_postreset); |
78cd52d0 TH |
1057 | } |
1058 | ||
1059 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) | |
1060 | { | |
1061 | struct ata_port *ap = qc->ap; | |
1062 | ||
1063 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1064 | qc->err_mask |= AC_ERR_OTHER; | |
1065 | ||
1066 | if (qc->err_mask) { | |
1067 | /* make DMA engine forget about the failed command */ | |
1068 | ahci_stop_engine(ap); | |
1069 | ahci_start_engine(ap); | |
1070 | } | |
1071 | } | |
1072 | ||
1da177e4 LT |
1073 | static void ahci_setup_port(struct ata_ioports *port, unsigned long base, |
1074 | unsigned int port_idx) | |
1075 | { | |
1076 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); | |
1077 | base = ahci_port_base_ul(base, port_idx); | |
1078 | VPRINTK("base now==0x%lx\n", base); | |
1079 | ||
1080 | port->cmd_addr = base; | |
1081 | port->scr_addr = base + PORT_SCR; | |
1082 | ||
1083 | VPRINTK("EXIT\n"); | |
1084 | } | |
1085 | ||
1086 | static int ahci_host_init(struct ata_probe_ent *probe_ent) | |
1087 | { | |
1088 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1089 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
1090 | void __iomem *mmio = probe_ent->mmio_base; | |
1091 | u32 tmp, cap_save; | |
1da177e4 LT |
1092 | unsigned int i, j, using_dac; |
1093 | int rc; | |
1094 | void __iomem *port_mmio; | |
1095 | ||
1096 | cap_save = readl(mmio + HOST_CAP); | |
1097 | cap_save &= ( (1<<28) | (1<<17) ); | |
1098 | cap_save |= (1 << 27); | |
1099 | ||
1100 | /* global controller reset */ | |
1101 | tmp = readl(mmio + HOST_CTL); | |
1102 | if ((tmp & HOST_RESET) == 0) { | |
1103 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
1104 | readl(mmio + HOST_CTL); /* flush */ | |
1105 | } | |
1106 | ||
1107 | /* reset must complete within 1 second, or | |
1108 | * the hardware should be considered fried. | |
1109 | */ | |
1110 | ssleep(1); | |
1111 | ||
1112 | tmp = readl(mmio + HOST_CTL); | |
1113 | if (tmp & HOST_RESET) { | |
a9524a76 JG |
1114 | dev_printk(KERN_ERR, &pdev->dev, |
1115 | "controller reset failed (0x%x)\n", tmp); | |
1da177e4 LT |
1116 | return -EIO; |
1117 | } | |
1118 | ||
1119 | writel(HOST_AHCI_EN, mmio + HOST_CTL); | |
1120 | (void) readl(mmio + HOST_CTL); /* flush */ | |
1121 | writel(cap_save, mmio + HOST_CAP); | |
1122 | writel(0xf, mmio + HOST_PORTS_IMPL); | |
1123 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
1124 | ||
bd12097c JG |
1125 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
1126 | u16 tmp16; | |
1127 | ||
1128 | pci_read_config_word(pdev, 0x92, &tmp16); | |
1129 | tmp16 |= 0xf; | |
1130 | pci_write_config_word(pdev, 0x92, tmp16); | |
1131 | } | |
1da177e4 LT |
1132 | |
1133 | hpriv->cap = readl(mmio + HOST_CAP); | |
1134 | hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); | |
1135 | probe_ent->n_ports = (hpriv->cap & 0x1f) + 1; | |
1136 | ||
1137 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", | |
1138 | hpriv->cap, hpriv->port_map, probe_ent->n_ports); | |
1139 | ||
1140 | using_dac = hpriv->cap & HOST_CAP_64; | |
1141 | if (using_dac && | |
1142 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1143 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1144 | if (rc) { | |
1145 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1146 | if (rc) { | |
a9524a76 JG |
1147 | dev_printk(KERN_ERR, &pdev->dev, |
1148 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1149 | return rc; |
1150 | } | |
1151 | } | |
1da177e4 LT |
1152 | } else { |
1153 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1154 | if (rc) { | |
a9524a76 JG |
1155 | dev_printk(KERN_ERR, &pdev->dev, |
1156 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
1157 | return rc; |
1158 | } | |
1159 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1160 | if (rc) { | |
a9524a76 JG |
1161 | dev_printk(KERN_ERR, &pdev->dev, |
1162 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
1163 | return rc; |
1164 | } | |
1165 | } | |
1166 | ||
1167 | for (i = 0; i < probe_ent->n_ports; i++) { | |
1168 | #if 0 /* BIOSen initialize this incorrectly */ | |
1169 | if (!(hpriv->port_map & (1 << i))) | |
1170 | continue; | |
1171 | #endif | |
1172 | ||
1173 | port_mmio = ahci_port_base(mmio, i); | |
1174 | VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio); | |
1175 | ||
1176 | ahci_setup_port(&probe_ent->port[i], | |
1177 | (unsigned long) mmio, i); | |
1178 | ||
1179 | /* make sure port is not active */ | |
1180 | tmp = readl(port_mmio + PORT_CMD); | |
1181 | VPRINTK("PORT_CMD 0x%x\n", tmp); | |
1182 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
1183 | PORT_CMD_FIS_RX | PORT_CMD_START)) { | |
1184 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
1185 | PORT_CMD_FIS_RX | PORT_CMD_START); | |
1186 | writel(tmp, port_mmio + PORT_CMD); | |
1187 | readl(port_mmio + PORT_CMD); /* flush */ | |
1188 | ||
1189 | /* spec says 500 msecs for each bit, so | |
1190 | * this is slightly incorrect. | |
1191 | */ | |
1192 | msleep(500); | |
1193 | } | |
1194 | ||
1195 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); | |
1196 | ||
1197 | j = 0; | |
1198 | while (j < 100) { | |
1199 | msleep(10); | |
1200 | tmp = readl(port_mmio + PORT_SCR_STAT); | |
1201 | if ((tmp & 0xf) == 0x3) | |
1202 | break; | |
1203 | j++; | |
1204 | } | |
1205 | ||
1206 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
1207 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
1208 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
1209 | ||
1210 | /* ack any pending irq events for this port */ | |
1211 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1212 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
1213 | if (tmp) | |
1214 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1215 | ||
1216 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
1da177e4 LT |
1217 | } |
1218 | ||
1219 | tmp = readl(mmio + HOST_CTL); | |
1220 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1221 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
1222 | tmp = readl(mmio + HOST_CTL); | |
1223 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
1224 | ||
1225 | pci_set_master(pdev); | |
1226 | ||
1227 | return 0; | |
1228 | } | |
1229 | ||
1da177e4 LT |
1230 | static void ahci_print_info(struct ata_probe_ent *probe_ent) |
1231 | { | |
1232 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1233 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
ea6ba10b | 1234 | void __iomem *mmio = probe_ent->mmio_base; |
1da177e4 LT |
1235 | u32 vers, cap, impl, speed; |
1236 | const char *speed_s; | |
1237 | u16 cc; | |
1238 | const char *scc_s; | |
1239 | ||
1240 | vers = readl(mmio + HOST_VERSION); | |
1241 | cap = hpriv->cap; | |
1242 | impl = hpriv->port_map; | |
1243 | ||
1244 | speed = (cap >> 20) & 0xf; | |
1245 | if (speed == 1) | |
1246 | speed_s = "1.5"; | |
1247 | else if (speed == 2) | |
1248 | speed_s = "3"; | |
1249 | else | |
1250 | speed_s = "?"; | |
1251 | ||
1252 | pci_read_config_word(pdev, 0x0a, &cc); | |
1253 | if (cc == 0x0101) | |
1254 | scc_s = "IDE"; | |
1255 | else if (cc == 0x0106) | |
1256 | scc_s = "SATA"; | |
1257 | else if (cc == 0x0104) | |
1258 | scc_s = "RAID"; | |
1259 | else | |
1260 | scc_s = "unknown"; | |
1261 | ||
a9524a76 JG |
1262 | dev_printk(KERN_INFO, &pdev->dev, |
1263 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
1264 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
1265 | , | |
1da177e4 LT |
1266 | |
1267 | (vers >> 24) & 0xff, | |
1268 | (vers >> 16) & 0xff, | |
1269 | (vers >> 8) & 0xff, | |
1270 | vers & 0xff, | |
1271 | ||
1272 | ((cap >> 8) & 0x1f) + 1, | |
1273 | (cap & 0x1f) + 1, | |
1274 | speed_s, | |
1275 | impl, | |
1276 | scc_s); | |
1277 | ||
a9524a76 JG |
1278 | dev_printk(KERN_INFO, &pdev->dev, |
1279 | "flags: " | |
1da177e4 LT |
1280 | "%s%s%s%s%s%s" |
1281 | "%s%s%s%s%s%s%s\n" | |
1282 | , | |
1da177e4 LT |
1283 | |
1284 | cap & (1 << 31) ? "64bit " : "", | |
1285 | cap & (1 << 30) ? "ncq " : "", | |
1286 | cap & (1 << 28) ? "ilck " : "", | |
1287 | cap & (1 << 27) ? "stag " : "", | |
1288 | cap & (1 << 26) ? "pm " : "", | |
1289 | cap & (1 << 25) ? "led " : "", | |
1290 | ||
1291 | cap & (1 << 24) ? "clo " : "", | |
1292 | cap & (1 << 19) ? "nz " : "", | |
1293 | cap & (1 << 18) ? "only " : "", | |
1294 | cap & (1 << 17) ? "pmp " : "", | |
1295 | cap & (1 << 15) ? "pio " : "", | |
1296 | cap & (1 << 14) ? "slum " : "", | |
1297 | cap & (1 << 13) ? "part " : "" | |
1298 | ); | |
1299 | } | |
1300 | ||
1301 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1302 | { | |
1303 | static int printed_version; | |
1304 | struct ata_probe_ent *probe_ent = NULL; | |
1305 | struct ahci_host_priv *hpriv; | |
1306 | unsigned long base; | |
ea6ba10b | 1307 | void __iomem *mmio_base; |
1da177e4 | 1308 | unsigned int board_idx = (unsigned int) ent->driver_data; |
907f4678 | 1309 | int have_msi, pci_dev_busy = 0; |
1da177e4 LT |
1310 | int rc; |
1311 | ||
1312 | VPRINTK("ENTER\n"); | |
1313 | ||
12fad3f9 TH |
1314 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1315 | ||
1da177e4 | 1316 | if (!printed_version++) |
a9524a76 | 1317 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
1318 | |
1319 | rc = pci_enable_device(pdev); | |
1320 | if (rc) | |
1321 | return rc; | |
1322 | ||
1323 | rc = pci_request_regions(pdev, DRV_NAME); | |
1324 | if (rc) { | |
1325 | pci_dev_busy = 1; | |
1326 | goto err_out; | |
1327 | } | |
1328 | ||
907f4678 JG |
1329 | if (pci_enable_msi(pdev) == 0) |
1330 | have_msi = 1; | |
1331 | else { | |
1332 | pci_intx(pdev, 1); | |
1333 | have_msi = 0; | |
1334 | } | |
1da177e4 LT |
1335 | |
1336 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
1337 | if (probe_ent == NULL) { | |
1338 | rc = -ENOMEM; | |
907f4678 | 1339 | goto err_out_msi; |
1da177e4 LT |
1340 | } |
1341 | ||
1342 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
1343 | probe_ent->dev = pci_dev_to_dev(pdev); | |
1344 | INIT_LIST_HEAD(&probe_ent->node); | |
1345 | ||
374b1873 | 1346 | mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0); |
1da177e4 LT |
1347 | if (mmio_base == NULL) { |
1348 | rc = -ENOMEM; | |
1349 | goto err_out_free_ent; | |
1350 | } | |
1351 | base = (unsigned long) mmio_base; | |
1352 | ||
1353 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
1354 | if (!hpriv) { | |
1355 | rc = -ENOMEM; | |
1356 | goto err_out_iounmap; | |
1357 | } | |
1358 | memset(hpriv, 0, sizeof(*hpriv)); | |
1359 | ||
1360 | probe_ent->sht = ahci_port_info[board_idx].sht; | |
1361 | probe_ent->host_flags = ahci_port_info[board_idx].host_flags; | |
1362 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; | |
1363 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; | |
1364 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; | |
1365 | ||
1366 | probe_ent->irq = pdev->irq; | |
1367 | probe_ent->irq_flags = SA_SHIRQ; | |
1368 | probe_ent->mmio_base = mmio_base; | |
1369 | probe_ent->private_data = hpriv; | |
1370 | ||
4b0060f4 JG |
1371 | if (have_msi) |
1372 | hpriv->flags |= AHCI_FLAG_MSI; | |
907f4678 | 1373 | |
bd12097c JG |
1374 | /* JMicron-specific fixup: make sure we're in AHCI mode */ |
1375 | if (pdev->vendor == 0x197b) | |
1376 | pci_write_config_byte(pdev, 0x41, 0xa1); | |
1377 | ||
1da177e4 LT |
1378 | /* initialize adapter */ |
1379 | rc = ahci_host_init(probe_ent); | |
1380 | if (rc) | |
1381 | goto err_out_hpriv; | |
1382 | ||
12fad3f9 TH |
1383 | if (hpriv->cap & HOST_CAP_NCQ) |
1384 | probe_ent->host_flags |= ATA_FLAG_NCQ; | |
1385 | ||
1da177e4 LT |
1386 | ahci_print_info(probe_ent); |
1387 | ||
1388 | /* FIXME: check ata_device_add return value */ | |
1389 | ata_device_add(probe_ent); | |
1390 | kfree(probe_ent); | |
1391 | ||
1392 | return 0; | |
1393 | ||
1394 | err_out_hpriv: | |
1395 | kfree(hpriv); | |
1396 | err_out_iounmap: | |
374b1873 | 1397 | pci_iounmap(pdev, mmio_base); |
1da177e4 LT |
1398 | err_out_free_ent: |
1399 | kfree(probe_ent); | |
907f4678 JG |
1400 | err_out_msi: |
1401 | if (have_msi) | |
1402 | pci_disable_msi(pdev); | |
1403 | else | |
1404 | pci_intx(pdev, 0); | |
1da177e4 LT |
1405 | pci_release_regions(pdev); |
1406 | err_out: | |
1407 | if (!pci_dev_busy) | |
1408 | pci_disable_device(pdev); | |
1409 | return rc; | |
1410 | } | |
1411 | ||
907f4678 JG |
1412 | static void ahci_remove_one (struct pci_dev *pdev) |
1413 | { | |
1414 | struct device *dev = pci_dev_to_dev(pdev); | |
1415 | struct ata_host_set *host_set = dev_get_drvdata(dev); | |
1416 | struct ahci_host_priv *hpriv = host_set->private_data; | |
907f4678 JG |
1417 | unsigned int i; |
1418 | int have_msi; | |
1419 | ||
720ba126 TH |
1420 | for (i = 0; i < host_set->n_ports; i++) |
1421 | ata_port_detach(host_set->ports[i]); | |
907f4678 | 1422 | |
4b0060f4 | 1423 | have_msi = hpriv->flags & AHCI_FLAG_MSI; |
907f4678 | 1424 | free_irq(host_set->irq, host_set); |
907f4678 JG |
1425 | |
1426 | for (i = 0; i < host_set->n_ports; i++) { | |
720ba126 | 1427 | struct ata_port *ap = host_set->ports[i]; |
907f4678 JG |
1428 | |
1429 | ata_scsi_release(ap->host); | |
1430 | scsi_host_put(ap->host); | |
1431 | } | |
1432 | ||
e005f01d | 1433 | kfree(hpriv); |
374b1873 | 1434 | pci_iounmap(pdev, host_set->mmio_base); |
ead5de99 JG |
1435 | kfree(host_set); |
1436 | ||
907f4678 JG |
1437 | if (have_msi) |
1438 | pci_disable_msi(pdev); | |
1439 | else | |
1440 | pci_intx(pdev, 0); | |
1441 | pci_release_regions(pdev); | |
907f4678 JG |
1442 | pci_disable_device(pdev); |
1443 | dev_set_drvdata(dev, NULL); | |
1444 | } | |
1da177e4 LT |
1445 | |
1446 | static int __init ahci_init(void) | |
1447 | { | |
1448 | return pci_module_init(&ahci_pci_driver); | |
1449 | } | |
1450 | ||
1da177e4 LT |
1451 | static void __exit ahci_exit(void) |
1452 | { | |
1453 | pci_unregister_driver(&ahci_pci_driver); | |
1454 | } | |
1455 | ||
1456 | ||
1457 | MODULE_AUTHOR("Jeff Garzik"); | |
1458 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1459 | MODULE_LICENSE("GPL"); | |
1460 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1461 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
1462 | |
1463 | module_init(ahci_init); | |
1464 | module_exit(ahci_exit); |