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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
18 | * | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed AC |
40 | * Documentation |
41 | * Publically available from Intel web site. Errata documentation | |
42 | * is also publically available. As an aide to anyone hacking on this | |
43 | * driver the list of errata that are relevant is below.going back to | |
44 | * PIIX4. Older device documentation is now a bit tricky to find. | |
45 | * | |
46 | * The chipsets all follow very much the same design. The orginal Triton | |
47 | * series chipsets do _not_ support independant device timings, but this | |
48 | * is fixed in Triton II. With the odd mobile exception the chips then | |
49 | * change little except in gaining more modes until SATA arrives. This | |
50 | * driver supports only the chips with independant timing (that is those | |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix | |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
75 | * | |
76 | * Should have been BIOS fixed: | |
77 | * 450NX: errata #19 - DMA hangs on old 450NX | |
78 | * 450NX: errata #20 - DMA hangs on old 450NX | |
79 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
80 | * ICH3 errata #15 - IDE deadlock under high load | |
81 | * (BIOS must set dev 31 fn 0 bit 23) | |
82 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
83 | */ |
84 | ||
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/pci.h> | |
88 | #include <linux/init.h> | |
89 | #include <linux/blkdev.h> | |
90 | #include <linux/delay.h> | |
6248e647 | 91 | #include <linux/device.h> |
1da177e4 LT |
92 | #include <scsi/scsi_host.h> |
93 | #include <linux/libata.h> | |
94 | ||
95 | #define DRV_NAME "ata_piix" | |
7bdd7208 | 96 | #define DRV_VERSION "1.05" |
1da177e4 LT |
97 | |
98 | enum { | |
99 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
100 | ICH5_PMR = 0x90, /* port mapping register */ | |
101 | ICH5_PCS = 0x92, /* port control and status */ | |
7b6dbd68 | 102 | PIIX_SCC = 0x0A, /* sub-class code register */ |
1da177e4 | 103 | |
219e6214 | 104 | PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */ |
d4358048 | 105 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
ff0fc146 TH |
106 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
107 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ | |
108 | PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */ | |
109 | /* ICH6/7 use different scheme for map value */ | |
110 | PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30), | |
1da177e4 LT |
111 | |
112 | /* combined mode. if set, PATA is channel 0. | |
113 | * if clear, PATA is channel 1. | |
114 | */ | |
6a690df5 HR |
115 | PIIX_PORT_ENABLED = (1 << 0), |
116 | PIIX_PORT_PRESENT = (1 << 4), | |
1da177e4 LT |
117 | |
118 | PIIX_80C_PRI = (1 << 5) | (1 << 4), | |
119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
120 | ||
1d076e5b TH |
121 | /* controller IDs */ |
122 | piix4_pata = 0, | |
123 | ich5_pata = 1, | |
124 | ich5_sata = 2, | |
125 | esb_sata = 3, | |
126 | ich6_sata = 4, | |
127 | ich6_sata_ahci = 5, | |
128 | ich6m_sata_ahci = 6, | |
7b6dbd68 | 129 | |
d33f58b8 TH |
130 | /* constants for mapping table */ |
131 | P0 = 0, /* port 0 */ | |
132 | P1 = 1, /* port 1 */ | |
133 | P2 = 2, /* port 2 */ | |
134 | P3 = 3, /* port 3 */ | |
135 | IDE = -1, /* IDE */ | |
136 | NA = -2, /* not avaliable */ | |
137 | RV = -3, /* reserved */ | |
138 | ||
7b6dbd68 | 139 | PIIX_AHCI_DEVICE = 6, |
1da177e4 LT |
140 | }; |
141 | ||
d33f58b8 TH |
142 | struct piix_map_db { |
143 | const u32 mask; | |
144 | const int map[][4]; | |
145 | }; | |
146 | ||
1da177e4 LT |
147 | static int piix_init_one (struct pci_dev *pdev, |
148 | const struct pci_device_id *ent); | |
149 | ||
573db6b8 | 150 | static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes); |
ccbe6d5e | 151 | static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes); |
1da177e4 LT |
152 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
153 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
154 | ||
155 | static unsigned int in_module_init = 1; | |
156 | ||
3b7d697d | 157 | static const struct pci_device_id piix_pci_tbl[] = { |
1da177e4 LT |
158 | #ifdef ATA_ENABLE_PATA |
159 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata }, | |
160 | { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, | |
161 | { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, | |
162 | #endif | |
163 | ||
164 | /* NOTE: The following PCI ids must be kept in sync with the | |
165 | * list in drivers/pci/quirks.c. | |
166 | */ | |
167 | ||
1d076e5b | 168 | /* 82801EB (ICH5) */ |
1da177e4 | 169 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 170 | /* 82801EB (ICH5) */ |
1da177e4 | 171 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b TH |
172 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
173 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, | |
174 | /* 6300ESB pretending RAID */ | |
175 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, | |
176 | /* 82801FB/FW (ICH6/ICH6W) */ | |
1da177e4 | 177 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 178 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
1c24a412 | 179 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b TH |
180 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
181 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, | |
182 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ | |
1c24a412 | 183 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b TH |
184 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
185 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, | |
186 | /* Enterprise Southbridge 2 (where's the datasheet?) */ | |
1c24a412 | 187 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b | 188 | /* SATA Controller 1 IDE (ICH8, no datasheet yet) */ |
012b265f | 189 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b | 190 | /* SATA Controller 2 IDE (ICH8, ditto) */ |
012b265f | 191 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b TH |
192 | /* Mobile SATA Controller IDE (ICH8M, ditto) */ |
193 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, | |
1da177e4 LT |
194 | |
195 | { } /* terminate list */ | |
196 | }; | |
197 | ||
198 | static struct pci_driver piix_pci_driver = { | |
199 | .name = DRV_NAME, | |
200 | .id_table = piix_pci_tbl, | |
201 | .probe = piix_init_one, | |
202 | .remove = ata_pci_remove_one, | |
9b847548 JA |
203 | .suspend = ata_pci_device_suspend, |
204 | .resume = ata_pci_device_resume, | |
1da177e4 LT |
205 | }; |
206 | ||
193515d5 | 207 | static struct scsi_host_template piix_sht = { |
1da177e4 LT |
208 | .module = THIS_MODULE, |
209 | .name = DRV_NAME, | |
210 | .ioctl = ata_scsi_ioctl, | |
211 | .queuecommand = ata_scsi_queuecmd, | |
212 | .eh_strategy_handler = ata_scsi_error, | |
213 | .can_queue = ATA_DEF_QUEUE, | |
214 | .this_id = ATA_SHT_THIS_ID, | |
215 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
216 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
217 | .emulated = ATA_SHT_EMULATED, | |
218 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
219 | .proc_name = DRV_NAME, | |
220 | .dma_boundary = ATA_DMA_BOUNDARY, | |
221 | .slave_configure = ata_scsi_slave_config, | |
222 | .bios_param = ata_std_bios_param, | |
9b847548 JA |
223 | .resume = ata_scsi_device_resume, |
224 | .suspend = ata_scsi_device_suspend, | |
1da177e4 LT |
225 | }; |
226 | ||
057ace5e | 227 | static const struct ata_port_operations piix_pata_ops = { |
1da177e4 LT |
228 | .port_disable = ata_port_disable, |
229 | .set_piomode = piix_set_piomode, | |
230 | .set_dmamode = piix_set_dmamode, | |
231 | ||
232 | .tf_load = ata_tf_load, | |
233 | .tf_read = ata_tf_read, | |
234 | .check_status = ata_check_status, | |
235 | .exec_command = ata_exec_command, | |
236 | .dev_select = ata_std_dev_select, | |
237 | ||
573db6b8 | 238 | .probe_reset = piix_pata_probe_reset, |
1da177e4 LT |
239 | |
240 | .bmdma_setup = ata_bmdma_setup, | |
241 | .bmdma_start = ata_bmdma_start, | |
242 | .bmdma_stop = ata_bmdma_stop, | |
243 | .bmdma_status = ata_bmdma_status, | |
244 | .qc_prep = ata_qc_prep, | |
245 | .qc_issue = ata_qc_issue_prot, | |
246 | ||
247 | .eng_timeout = ata_eng_timeout, | |
248 | ||
249 | .irq_handler = ata_interrupt, | |
250 | .irq_clear = ata_bmdma_irq_clear, | |
251 | ||
252 | .port_start = ata_port_start, | |
253 | .port_stop = ata_port_stop, | |
aa8f0dc6 | 254 | .host_stop = ata_host_stop, |
1da177e4 LT |
255 | }; |
256 | ||
057ace5e | 257 | static const struct ata_port_operations piix_sata_ops = { |
1da177e4 LT |
258 | .port_disable = ata_port_disable, |
259 | ||
260 | .tf_load = ata_tf_load, | |
261 | .tf_read = ata_tf_read, | |
262 | .check_status = ata_check_status, | |
263 | .exec_command = ata_exec_command, | |
264 | .dev_select = ata_std_dev_select, | |
265 | ||
ccbe6d5e | 266 | .probe_reset = piix_sata_probe_reset, |
1da177e4 LT |
267 | |
268 | .bmdma_setup = ata_bmdma_setup, | |
269 | .bmdma_start = ata_bmdma_start, | |
270 | .bmdma_stop = ata_bmdma_stop, | |
271 | .bmdma_status = ata_bmdma_status, | |
272 | .qc_prep = ata_qc_prep, | |
273 | .qc_issue = ata_qc_issue_prot, | |
274 | ||
275 | .eng_timeout = ata_eng_timeout, | |
276 | ||
277 | .irq_handler = ata_interrupt, | |
278 | .irq_clear = ata_bmdma_irq_clear, | |
279 | ||
280 | .port_start = ata_port_start, | |
281 | .port_stop = ata_port_stop, | |
aa8f0dc6 | 282 | .host_stop = ata_host_stop, |
1da177e4 LT |
283 | }; |
284 | ||
d33f58b8 TH |
285 | static struct piix_map_db ich5_map_db = { |
286 | .mask = 0x7, | |
287 | .map = { | |
288 | /* PM PS SM SS MAP */ | |
289 | { P0, NA, P1, NA }, /* 000b */ | |
290 | { P1, NA, P0, NA }, /* 001b */ | |
291 | { RV, RV, RV, RV }, | |
292 | { RV, RV, RV, RV }, | |
293 | { P0, P1, IDE, IDE }, /* 100b */ | |
294 | { P1, P0, IDE, IDE }, /* 101b */ | |
295 | { IDE, IDE, P0, P1 }, /* 110b */ | |
296 | { IDE, IDE, P1, P0 }, /* 111b */ | |
297 | }, | |
298 | }; | |
299 | ||
300 | static struct piix_map_db ich6_map_db = { | |
301 | .mask = 0x3, | |
302 | .map = { | |
303 | /* PM PS SM SS MAP */ | |
304 | { P0, P1, P2, P3 }, /* 00b */ | |
305 | { IDE, IDE, P1, P3 }, /* 01b */ | |
306 | { P0, P2, IDE, IDE }, /* 10b */ | |
307 | { RV, RV, RV, RV }, | |
308 | }, | |
309 | }; | |
310 | ||
311 | static struct piix_map_db ich6m_map_db = { | |
312 | .mask = 0x3, | |
313 | .map = { | |
314 | /* PM PS SM SS MAP */ | |
315 | { P0, P1, P2, P3 }, /* 00b */ | |
316 | { RV, RV, RV, RV }, | |
317 | { P0, P2, IDE, IDE }, /* 10b */ | |
318 | { RV, RV, RV, RV }, | |
319 | }, | |
320 | }; | |
321 | ||
1da177e4 | 322 | static struct ata_port_info piix_port_info[] = { |
1d076e5b TH |
323 | /* piix4_pata */ |
324 | { | |
325 | .sht = &piix_sht, | |
326 | .host_flags = ATA_FLAG_SLAVE_POSS, | |
327 | .pio_mask = 0x1f, /* pio0-4 */ | |
328 | #if 0 | |
329 | .mwdma_mask = 0x06, /* mwdma1-2 */ | |
330 | #else | |
331 | .mwdma_mask = 0x00, /* mwdma broken */ | |
332 | #endif | |
333 | .udma_mask = ATA_UDMA_MASK_40C, | |
334 | .port_ops = &piix_pata_ops, | |
335 | }, | |
336 | ||
1da177e4 LT |
337 | /* ich5_pata */ |
338 | { | |
339 | .sht = &piix_sht, | |
573db6b8 | 340 | .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR, |
1da177e4 LT |
341 | .pio_mask = 0x1f, /* pio0-4 */ |
342 | #if 0 | |
343 | .mwdma_mask = 0x06, /* mwdma1-2 */ | |
344 | #else | |
345 | .mwdma_mask = 0x00, /* mwdma broken */ | |
346 | #endif | |
347 | .udma_mask = 0x3f, /* udma0-5 */ | |
348 | .port_ops = &piix_pata_ops, | |
349 | }, | |
350 | ||
351 | /* ich5_sata */ | |
352 | { | |
353 | .sht = &piix_sht, | |
ccbe6d5e TH |
354 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED | |
355 | PIIX_FLAG_CHECKINTR, | |
1da177e4 LT |
356 | .pio_mask = 0x1f, /* pio0-4 */ |
357 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
358 | .udma_mask = 0x7f, /* udma0-6 */ | |
359 | .port_ops = &piix_sata_ops, | |
d33f58b8 | 360 | .private_data = &ich5_map_db, |
1da177e4 LT |
361 | }, |
362 | ||
1d076e5b | 363 | /* i6300esb_sata */ |
1da177e4 LT |
364 | { |
365 | .sht = &piix_sht, | |
1d076e5b | 366 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED | |
219e6214 | 367 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS, |
1da177e4 | 368 | .pio_mask = 0x1f, /* pio0-4 */ |
1d076e5b TH |
369 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
370 | .udma_mask = 0x7f, /* udma0-6 */ | |
371 | .port_ops = &piix_sata_ops, | |
d33f58b8 | 372 | .private_data = &ich5_map_db, |
1da177e4 LT |
373 | }, |
374 | ||
375 | /* ich6_sata */ | |
376 | { | |
377 | .sht = &piix_sht, | |
ccbe6d5e | 378 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 | |
d33f58b8 | 379 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR, |
1da177e4 LT |
380 | .pio_mask = 0x1f, /* pio0-4 */ |
381 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
382 | .udma_mask = 0x7f, /* udma0-6 */ | |
383 | .port_ops = &piix_sata_ops, | |
d33f58b8 | 384 | .private_data = &ich6_map_db, |
1da177e4 LT |
385 | }, |
386 | ||
1c24a412 | 387 | /* ich6_sata_ahci */ |
c368ca4e JG |
388 | { |
389 | .sht = &piix_sht, | |
ccbe6d5e | 390 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 | |
d33f58b8 TH |
391 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
392 | PIIX_FLAG_AHCI, | |
c368ca4e JG |
393 | .pio_mask = 0x1f, /* pio0-4 */ |
394 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
395 | .udma_mask = 0x7f, /* udma0-6 */ | |
396 | .port_ops = &piix_sata_ops, | |
d33f58b8 | 397 | .private_data = &ich6_map_db, |
c368ca4e | 398 | }, |
1d076e5b TH |
399 | |
400 | /* ich6m_sata_ahci */ | |
401 | { | |
402 | .sht = &piix_sht, | |
403 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 | | |
d33f58b8 TH |
404 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
405 | PIIX_FLAG_AHCI, | |
1d076e5b TH |
406 | .pio_mask = 0x1f, /* pio0-4 */ |
407 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
408 | .udma_mask = 0x7f, /* udma0-6 */ | |
409 | .port_ops = &piix_sata_ops, | |
d33f58b8 | 410 | .private_data = &ich6m_map_db, |
1d076e5b | 411 | }, |
1da177e4 LT |
412 | }; |
413 | ||
414 | static struct pci_bits piix_enable_bits[] = { | |
415 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
416 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
417 | }; | |
418 | ||
419 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
420 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
421 | MODULE_LICENSE("GPL"); | |
422 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
423 | MODULE_VERSION(DRV_VERSION); | |
424 | ||
425 | /** | |
426 | * piix_pata_cbl_detect - Probe host controller cable detect info | |
427 | * @ap: Port for which cable detect info is desired | |
428 | * | |
429 | * Read 80c cable indicator from ATA PCI device's PCI config | |
430 | * register. This register is normally set by firmware (BIOS). | |
431 | * | |
432 | * LOCKING: | |
433 | * None (inherited from caller). | |
434 | */ | |
435 | static void piix_pata_cbl_detect(struct ata_port *ap) | |
436 | { | |
437 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
438 | u8 tmp, mask; | |
439 | ||
440 | /* no 80c support in host controller? */ | |
441 | if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0) | |
442 | goto cbl40; | |
443 | ||
444 | /* check BIOS cable detect results */ | |
445 | mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; | |
446 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); | |
447 | if ((tmp & mask) == 0) | |
448 | goto cbl40; | |
449 | ||
450 | ap->cbl = ATA_CBL_PATA80; | |
451 | return; | |
452 | ||
453 | cbl40: | |
454 | ap->cbl = ATA_CBL_PATA40; | |
455 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
456 | } | |
457 | ||
458 | /** | |
573db6b8 TH |
459 | * piix_pata_probeinit - probeinit for PATA host controller |
460 | * @ap: Target port | |
1da177e4 | 461 | * |
573db6b8 | 462 | * Probeinit including cable detection. |
1da177e4 LT |
463 | * |
464 | * LOCKING: | |
465 | * None (inherited from caller). | |
466 | */ | |
573db6b8 TH |
467 | static void piix_pata_probeinit(struct ata_port *ap) |
468 | { | |
469 | piix_pata_cbl_detect(ap); | |
470 | ata_std_probeinit(ap); | |
471 | } | |
1da177e4 | 472 | |
573db6b8 TH |
473 | /** |
474 | * piix_pata_probe_reset - Perform reset on PATA port and classify | |
475 | * @ap: Port to reset | |
476 | * @classes: Resulting classes of attached devices | |
477 | * | |
478 | * Reset PATA phy and classify attached devices. | |
479 | * | |
480 | * LOCKING: | |
481 | * None (inherited from caller). | |
482 | */ | |
483 | static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes) | |
1da177e4 LT |
484 | { |
485 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
486 | ||
487 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) { | |
1da177e4 | 488 | printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id); |
573db6b8 | 489 | return 0; |
1da177e4 LT |
490 | } |
491 | ||
573db6b8 TH |
492 | return ata_drive_probe_reset(ap, piix_pata_probeinit, |
493 | ata_std_softreset, NULL, | |
494 | ata_std_postreset, classes); | |
1da177e4 LT |
495 | } |
496 | ||
497 | /** | |
498 | * piix_sata_probe - Probe PCI device for present SATA devices | |
499 | * @ap: Port associated with the PCI device we wish to probe | |
500 | * | |
d133ecab TH |
501 | * Reads and configures SATA PCI device's PCI config register |
502 | * Port Configuration and Status (PCS) to determine port and | |
503 | * device availability. | |
1da177e4 LT |
504 | * |
505 | * LOCKING: | |
506 | * None (inherited from caller). | |
507 | * | |
508 | * RETURNS: | |
d133ecab | 509 | * Mask of avaliable devices on the port. |
1da177e4 | 510 | */ |
d133ecab | 511 | static unsigned int piix_sata_probe (struct ata_port *ap) |
1da177e4 LT |
512 | { |
513 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
d133ecab TH |
514 | const unsigned int *map = ap->host_set->private_data; |
515 | int base = 2 * ap->hard_port_no; | |
516 | unsigned int present_mask = 0; | |
517 | int port, i; | |
1da177e4 LT |
518 | u8 pcs; |
519 | ||
1da177e4 | 520 | pci_read_config_byte(pdev, ICH5_PCS, &pcs); |
d133ecab TH |
521 | DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base); |
522 | ||
523 | /* enable all ports on this ap and wait for them to settle */ | |
524 | for (i = 0; i < 2; i++) { | |
525 | port = map[base + i]; | |
526 | if (port >= 0) | |
527 | pcs |= 1 << port; | |
528 | } | |
1da177e4 | 529 | |
d133ecab TH |
530 | pci_write_config_byte(pdev, ICH5_PCS, pcs); |
531 | msleep(100); | |
1da177e4 | 532 | |
d133ecab TH |
533 | /* let's see which devices are present */ |
534 | pci_read_config_byte(pdev, ICH5_PCS, &pcs); | |
535 | ||
536 | for (i = 0; i < 2; i++) { | |
537 | port = map[base + i]; | |
538 | if (port < 0) | |
539 | continue; | |
219e6214 | 540 | if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port)) |
d133ecab TH |
541 | present_mask |= 1 << i; |
542 | else | |
543 | pcs &= ~(1 << port); | |
1da177e4 LT |
544 | } |
545 | ||
d133ecab TH |
546 | /* disable offline ports on non-AHCI controllers */ |
547 | if (!(ap->flags & PIIX_FLAG_AHCI)) | |
548 | pci_write_config_byte(pdev, ICH5_PCS, pcs); | |
549 | ||
550 | DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n", | |
551 | ap->id, pcs, present_mask); | |
552 | ||
553 | return present_mask; | |
1da177e4 LT |
554 | } |
555 | ||
556 | /** | |
ccbe6d5e TH |
557 | * piix_sata_probe_reset - Perform reset on SATA port and classify |
558 | * @ap: Port to reset | |
559 | * @classes: Resulting classes of attached devices | |
1da177e4 | 560 | * |
ccbe6d5e | 561 | * Reset SATA phy and classify attached devices. |
1da177e4 LT |
562 | * |
563 | * LOCKING: | |
564 | * None (inherited from caller). | |
565 | */ | |
ccbe6d5e | 566 | static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes) |
1da177e4 LT |
567 | { |
568 | if (!piix_sata_probe(ap)) { | |
1da177e4 | 569 | printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id); |
ccbe6d5e | 570 | return 0; |
1da177e4 LT |
571 | } |
572 | ||
ccbe6d5e TH |
573 | return ata_drive_probe_reset(ap, ata_std_probeinit, |
574 | ata_std_softreset, NULL, | |
575 | ata_std_postreset, classes); | |
1da177e4 LT |
576 | } |
577 | ||
578 | /** | |
579 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
580 | * @ap: Port whose timings we are configuring | |
581 | * @adev: um | |
1da177e4 LT |
582 | * |
583 | * Set PIO mode for device, in host controller PCI config space. | |
584 | * | |
585 | * LOCKING: | |
586 | * None (inherited from caller). | |
587 | */ | |
588 | ||
589 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
590 | { | |
591 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
592 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); | |
593 | unsigned int is_slave = (adev->devno != 0); | |
594 | unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40; | |
595 | unsigned int slave_port = 0x44; | |
596 | u16 master_data; | |
597 | u8 slave_data; | |
598 | ||
599 | static const /* ISP RTC */ | |
600 | u8 timings[][2] = { { 0, 0 }, | |
601 | { 0, 0 }, | |
602 | { 1, 0 }, | |
603 | { 2, 1 }, | |
604 | { 2, 3 }, }; | |
605 | ||
606 | pci_read_config_word(dev, master_port, &master_data); | |
607 | if (is_slave) { | |
608 | master_data |= 0x4000; | |
609 | /* enable PPE, IE and TIME */ | |
610 | master_data |= 0x0070; | |
611 | pci_read_config_byte(dev, slave_port, &slave_data); | |
612 | slave_data &= (ap->hard_port_no ? 0x0f : 0xf0); | |
613 | slave_data |= | |
614 | (timings[pio][0] << 2) | | |
615 | (timings[pio][1] << (ap->hard_port_no ? 4 : 0)); | |
616 | } else { | |
617 | master_data &= 0xccf8; | |
618 | /* enable PPE, IE and TIME */ | |
619 | master_data |= 0x0007; | |
620 | master_data |= | |
621 | (timings[pio][0] << 12) | | |
622 | (timings[pio][1] << 8); | |
623 | } | |
624 | pci_write_config_word(dev, master_port, master_data); | |
625 | if (is_slave) | |
626 | pci_write_config_byte(dev, slave_port, slave_data); | |
627 | } | |
628 | ||
629 | /** | |
630 | * piix_set_dmamode - Initialize host controller PATA PIO timings | |
631 | * @ap: Port whose timings we are configuring | |
632 | * @adev: um | |
633 | * @udma: udma mode, 0 - 6 | |
634 | * | |
635 | * Set UDMA mode for device, in host controller PCI config space. | |
636 | * | |
637 | * LOCKING: | |
638 | * None (inherited from caller). | |
639 | */ | |
640 | ||
641 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
642 | { | |
643 | unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */ | |
644 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); | |
645 | u8 maslave = ap->hard_port_no ? 0x42 : 0x40; | |
646 | u8 speed = udma; | |
647 | unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno; | |
648 | int a_speed = 3 << (drive_dn * 4); | |
649 | int u_flag = 1 << drive_dn; | |
650 | int v_flag = 0x01 << drive_dn; | |
651 | int w_flag = 0x10 << drive_dn; | |
652 | int u_speed = 0; | |
653 | int sitre; | |
654 | u16 reg4042, reg4a; | |
655 | u8 reg48, reg54, reg55; | |
656 | ||
657 | pci_read_config_word(dev, maslave, ®4042); | |
658 | DPRINTK("reg4042 = 0x%04x\n", reg4042); | |
659 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
660 | pci_read_config_byte(dev, 0x48, ®48); | |
661 | pci_read_config_word(dev, 0x4a, ®4a); | |
662 | pci_read_config_byte(dev, 0x54, ®54); | |
663 | pci_read_config_byte(dev, 0x55, ®55); | |
664 | ||
665 | switch(speed) { | |
666 | case XFER_UDMA_4: | |
667 | case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break; | |
668 | case XFER_UDMA_6: | |
669 | case XFER_UDMA_5: | |
670 | case XFER_UDMA_3: | |
671 | case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break; | |
672 | case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break; | |
673 | case XFER_MW_DMA_2: | |
674 | case XFER_MW_DMA_1: break; | |
675 | default: | |
676 | BUG(); | |
677 | return; | |
678 | } | |
679 | ||
680 | if (speed >= XFER_UDMA_0) { | |
681 | if (!(reg48 & u_flag)) | |
682 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
683 | if (speed == XFER_UDMA_5) { | |
684 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
685 | } else { | |
686 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
687 | } | |
688 | if ((reg4a & a_speed) != u_speed) | |
689 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
690 | if (speed > XFER_UDMA_2) { | |
691 | if (!(reg54 & v_flag)) | |
692 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
693 | } else | |
694 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
695 | } else { | |
696 | if (reg48 & u_flag) | |
697 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
698 | if (reg4a & a_speed) | |
699 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
700 | if (reg54 & v_flag) | |
701 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
702 | if (reg55 & w_flag) | |
703 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
704 | } | |
705 | } | |
706 | ||
1da177e4 LT |
707 | #define AHCI_PCI_BAR 5 |
708 | #define AHCI_GLOBAL_CTL 0x04 | |
709 | #define AHCI_ENABLE (1 << 31) | |
710 | static int piix_disable_ahci(struct pci_dev *pdev) | |
711 | { | |
ea6ba10b | 712 | void __iomem *mmio; |
1da177e4 LT |
713 | u32 tmp; |
714 | int rc = 0; | |
715 | ||
716 | /* BUG: pci_enable_device has not yet been called. This | |
717 | * works because this device is usually set up by BIOS. | |
718 | */ | |
719 | ||
374b1873 JG |
720 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
721 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 722 | return 0; |
7b6dbd68 | 723 | |
374b1873 | 724 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
725 | if (!mmio) |
726 | return -ENOMEM; | |
7b6dbd68 | 727 | |
1da177e4 LT |
728 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
729 | if (tmp & AHCI_ENABLE) { | |
730 | tmp &= ~AHCI_ENABLE; | |
731 | writel(tmp, mmio + AHCI_GLOBAL_CTL); | |
732 | ||
733 | tmp = readl(mmio + AHCI_GLOBAL_CTL); | |
734 | if (tmp & AHCI_ENABLE) | |
735 | rc = -EIO; | |
736 | } | |
7b6dbd68 | 737 | |
374b1873 | 738 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
739 | return rc; |
740 | } | |
741 | ||
c621b140 AC |
742 | /** |
743 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 744 | * @ata_dev: the PCI device to check |
c621b140 AC |
745 | * |
746 | * Check for the present of 450NX errata #19 and errata #25. If | |
747 | * they are found return an error code so we can turn off DMA | |
748 | */ | |
749 | ||
750 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
751 | { | |
752 | struct pci_dev *pdev = NULL; | |
753 | u16 cfg; | |
754 | u8 rev; | |
755 | int no_piix_dma = 0; | |
756 | ||
757 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) | |
758 | { | |
759 | /* Look for 450NX PXB. Check for problem configurations | |
760 | A PCI quirk checks bit 6 already */ | |
761 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
762 | pci_read_config_word(pdev, 0x41, &cfg); | |
763 | /* Only on the original revision: IDE DMA can hang */ | |
764 | if(rev == 0x00) | |
765 | no_piix_dma = 1; | |
766 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
767 | else if(cfg & (1<<14) && rev < 5) | |
768 | no_piix_dma = 2; | |
769 | } | |
770 | if(no_piix_dma) | |
771 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); | |
772 | if(no_piix_dma == 2) | |
773 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); | |
774 | return no_piix_dma; | |
775 | } | |
776 | ||
d33f58b8 TH |
777 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
778 | struct ata_port_info *pinfo) | |
779 | { | |
780 | struct piix_map_db *map_db = pinfo[0].private_data; | |
781 | const unsigned int *map; | |
782 | int i, invalid_map = 0; | |
783 | u8 map_value; | |
784 | ||
785 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
786 | ||
787 | map = map_db->map[map_value & map_db->mask]; | |
788 | ||
789 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); | |
790 | for (i = 0; i < 4; i++) { | |
791 | switch (map[i]) { | |
792 | case RV: | |
793 | invalid_map = 1; | |
794 | printk(" XX"); | |
795 | break; | |
796 | ||
797 | case NA: | |
798 | printk(" --"); | |
799 | break; | |
800 | ||
801 | case IDE: | |
802 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
803 | pinfo[i / 2] = piix_port_info[ich5_pata]; | |
804 | i++; | |
805 | printk(" IDE IDE"); | |
806 | break; | |
807 | ||
808 | default: | |
809 | printk(" P%d", map[i]); | |
810 | if (i & 1) | |
811 | pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS; | |
812 | break; | |
813 | } | |
814 | } | |
815 | printk(" ]\n"); | |
816 | ||
817 | if (invalid_map) | |
818 | dev_printk(KERN_ERR, &pdev->dev, | |
819 | "invalid MAP value %u\n", map_value); | |
820 | ||
821 | pinfo[0].private_data = (void *)map; | |
822 | pinfo[1].private_data = (void *)map; | |
823 | } | |
824 | ||
1da177e4 LT |
825 | /** |
826 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
827 | * @pdev: PCI device to register | |
828 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
829 | * | |
830 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
831 | * and then hand over control to libata, for it to do the rest. | |
832 | * | |
833 | * LOCKING: | |
834 | * Inherited from PCI layer (may sleep). | |
835 | * | |
836 | * RETURNS: | |
837 | * Zero on success, or -ERRNO value. | |
838 | */ | |
839 | ||
840 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
841 | { | |
842 | static int printed_version; | |
d33f58b8 TH |
843 | struct ata_port_info port_info[2]; |
844 | struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] }; | |
ff0fc146 | 845 | unsigned long host_flags; |
1da177e4 LT |
846 | |
847 | if (!printed_version++) | |
6248e647 JG |
848 | dev_printk(KERN_DEBUG, &pdev->dev, |
849 | "version " DRV_VERSION "\n"); | |
1da177e4 LT |
850 | |
851 | /* no hotplugging support (FIXME) */ | |
852 | if (!in_module_init) | |
853 | return -ENODEV; | |
854 | ||
d33f58b8 TH |
855 | port_info[0] = piix_port_info[ent->driver_data]; |
856 | port_info[1] = piix_port_info[ent->driver_data]; | |
1da177e4 | 857 | |
d33f58b8 | 858 | host_flags = port_info[0].host_flags; |
ff0fc146 TH |
859 | |
860 | if (host_flags & PIIX_FLAG_AHCI) { | |
8a60a071 JG |
861 | u8 tmp; |
862 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); | |
863 | if (tmp == PIIX_AHCI_DEVICE) { | |
864 | int rc = piix_disable_ahci(pdev); | |
865 | if (rc) | |
866 | return rc; | |
867 | } | |
1da177e4 LT |
868 | } |
869 | ||
d33f58b8 TH |
870 | /* Initialize SATA map */ |
871 | if (host_flags & ATA_FLAG_SATA) | |
872 | piix_init_sata_map(pdev, port_info); | |
1da177e4 LT |
873 | |
874 | /* On ICH5, some BIOSen disable the interrupt using the | |
875 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
876 | * On ICH6, this bit has the same effect, but only when | |
877 | * MSI is disabled (and it is disabled, as we don't use | |
878 | * message-signalled interrupts currently). | |
879 | */ | |
ff0fc146 | 880 | if (host_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 881 | pci_intx(pdev, 1); |
1da177e4 | 882 | |
c621b140 AC |
883 | if (piix_check_450nx_errata(pdev)) { |
884 | /* This writes into the master table but it does not | |
885 | really matter for this errata as we will apply it to | |
886 | all the PIIX devices on the board */ | |
d33f58b8 TH |
887 | port_info[0].mwdma_mask = 0; |
888 | port_info[0].udma_mask = 0; | |
889 | port_info[1].mwdma_mask = 0; | |
890 | port_info[1].udma_mask = 0; | |
c621b140 | 891 | } |
d33f58b8 | 892 | return ata_pci_init_one(pdev, ppinfo, 2); |
1da177e4 LT |
893 | } |
894 | ||
1da177e4 LT |
895 | static int __init piix_init(void) |
896 | { | |
897 | int rc; | |
898 | ||
899 | DPRINTK("pci_module_init\n"); | |
900 | rc = pci_module_init(&piix_pci_driver); | |
901 | if (rc) | |
902 | return rc; | |
903 | ||
904 | in_module_init = 0; | |
905 | ||
906 | DPRINTK("done\n"); | |
907 | return 0; | |
908 | } | |
909 | ||
1da177e4 LT |
910 | static void __exit piix_exit(void) |
911 | { | |
912 | pci_unregister_driver(&piix_pci_driver); | |
913 | } | |
914 | ||
915 | module_init(piix_init); | |
916 | module_exit(piix_exit); | |
917 |