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92f61e3b JG |
1 | /* |
2 | * Copyright (c) 2017 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include "hisi_sas.h" | |
12 | #define DRV_NAME "hisi_sas_v3_hw" | |
13 | ||
c94d8ca2 XC |
14 | /* global registers need init*/ |
15 | #define DLVRY_QUEUE_ENABLE 0x0 | |
16 | #define IOST_BASE_ADDR_LO 0x8 | |
17 | #define IOST_BASE_ADDR_HI 0xc | |
18 | #define ITCT_BASE_ADDR_LO 0x10 | |
19 | #define ITCT_BASE_ADDR_HI 0x14 | |
20 | #define IO_BROKEN_MSG_ADDR_LO 0x18 | |
21 | #define IO_BROKEN_MSG_ADDR_HI 0x1c | |
3975f605 XC |
22 | #define PHY_CONTEXT 0x20 |
23 | #define PHY_STATE 0x24 | |
24 | #define PHY_PORT_NUM_MA 0x28 | |
25 | #define PHY_CONN_RATE 0x30 | |
182e7222 XC |
26 | #define ITCT_CLR 0x44 |
27 | #define ITCT_CLR_EN_OFF 16 | |
28 | #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) | |
29 | #define ITCT_DEV_OFF 0 | |
30 | #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) | |
c94d8ca2 XC |
31 | #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 |
32 | #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c | |
33 | #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 | |
34 | #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 | |
35 | #define CFG_MAX_TAG 0x68 | |
36 | #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 | |
37 | #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 | |
38 | #define HGC_GET_ITV_TIME 0x90 | |
39 | #define DEVICE_MSG_WORK_MODE 0x94 | |
40 | #define OPENA_WT_CONTI_TIME 0x9c | |
41 | #define I_T_NEXUS_LOSS_TIME 0xa0 | |
42 | #define MAX_CON_TIME_LIMIT_TIME 0xa4 | |
43 | #define BUS_INACTIVE_LIMIT_TIME 0xa8 | |
44 | #define REJECT_TO_OPEN_LIMIT_TIME 0xac | |
6cc8d8f2 | 45 | #define CQ_INT_CONVERGE_EN 0xb0 |
c94d8ca2 XC |
46 | #define CFG_AGING_TIME 0xbc |
47 | #define HGC_DFX_CFG2 0xc0 | |
48 | #define CFG_ABT_SET_QUERY_IPTT 0xd4 | |
49 | #define CFG_SET_ABORTED_IPTT_OFF 0 | |
50 | #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) | |
d30ff263 XC |
51 | #define CFG_SET_ABORTED_EN_OFF 12 |
52 | #define CFG_ABT_SET_IPTT_DONE 0xd8 | |
53 | #define CFG_ABT_SET_IPTT_DONE_OFF 0 | |
54 | #define HGC_IOMB_PROC1_STATUS 0x104 | |
3975f605 | 55 | #define CHNL_INT_STATUS 0x148 |
fa231408 XT |
56 | #define HGC_AXI_FIFO_ERR_INFO 0x154 |
57 | #define AXI_ERR_INFO_OFF 0 | |
58 | #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) | |
59 | #define FIFO_ERR_INFO_OFF 8 | |
60 | #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) | |
c94d8ca2 XC |
61 | #define INT_COAL_EN 0x19c |
62 | #define OQ_INT_COAL_TIME 0x1a0 | |
63 | #define OQ_INT_COAL_CNT 0x1a4 | |
64 | #define ENT_INT_COAL_TIME 0x1a8 | |
65 | #define ENT_INT_COAL_CNT 0x1ac | |
66 | #define OQ_INT_SRC 0x1b0 | |
67 | #define OQ_INT_SRC_MSK 0x1b4 | |
68 | #define ENT_INT_SRC1 0x1b8 | |
69 | #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 | |
70 | #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) | |
71 | #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 | |
72 | #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) | |
73 | #define ENT_INT_SRC2 0x1bc | |
74 | #define ENT_INT_SRC3 0x1c0 | |
75 | #define ENT_INT_SRC3_WP_DEPTH_OFF 8 | |
76 | #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 | |
77 | #define ENT_INT_SRC3_RP_DEPTH_OFF 10 | |
78 | #define ENT_INT_SRC3_AXI_OFF 11 | |
79 | #define ENT_INT_SRC3_FIFO_OFF 12 | |
80 | #define ENT_INT_SRC3_LM_OFF 14 | |
81 | #define ENT_INT_SRC3_ITC_INT_OFF 15 | |
82 | #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) | |
83 | #define ENT_INT_SRC3_ABT_OFF 16 | |
84 | #define ENT_INT_SRC_MSK1 0x1c4 | |
85 | #define ENT_INT_SRC_MSK2 0x1c8 | |
86 | #define ENT_INT_SRC_MSK3 0x1cc | |
3975f605 | 87 | #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 |
c94d8ca2 XC |
88 | #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 |
89 | #define CHNL_ENT_INT_MSK 0x1d4 | |
90 | #define HGC_COM_INT_MSK 0x1d8 | |
3975f605 | 91 | #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) |
c94d8ca2 XC |
92 | #define SAS_ECC_INTR 0x1e8 |
93 | #define SAS_ECC_INTR_MSK 0x1ec | |
94 | #define HGC_ERR_STAT_EN 0x238 | |
1a7068b3 | 95 | #define CQE_SEND_CNT 0x248 |
c94d8ca2 XC |
96 | #define DLVRY_Q_0_BASE_ADDR_LO 0x260 |
97 | #define DLVRY_Q_0_BASE_ADDR_HI 0x264 | |
98 | #define DLVRY_Q_0_DEPTH 0x268 | |
99 | #define DLVRY_Q_0_WR_PTR 0x26c | |
100 | #define DLVRY_Q_0_RD_PTR 0x270 | |
101 | #define HYPER_STREAM_ID_EN_CFG 0xc80 | |
102 | #define OQ0_INT_SRC_MSK 0xc90 | |
103 | #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 | |
104 | #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 | |
105 | #define COMPL_Q_0_DEPTH 0x4e8 | |
106 | #define COMPL_Q_0_WR_PTR 0x4ec | |
107 | #define COMPL_Q_0_RD_PTR 0x4f0 | |
108 | #define AWQOS_AWCACHE_CFG 0xc84 | |
109 | #define ARQOS_ARCACHE_CFG 0xc88 | |
70230be3 | 110 | #define HILINK_ERR_DFX 0xe04 |
e24fe507 XT |
111 | #define SAS_GPIO_CFG_0 0x1000 |
112 | #define SAS_GPIO_CFG_1 0x1004 | |
113 | #define SAS_GPIO_TX_0_1 0x1040 | |
114 | #define SAS_CFG_DRIVE_VLD 0x1070 | |
c94d8ca2 XC |
115 | |
116 | /* phy registers requiring init */ | |
117 | #define PORT_BASE (0x2000) | |
3975f605 XC |
118 | #define PHY_CFG (PORT_BASE + 0x0) |
119 | #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) | |
120 | #define PHY_CFG_ENA_OFF 0 | |
121 | #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) | |
122 | #define PHY_CFG_DC_OPT_OFF 2 | |
123 | #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) | |
17d59a57 XT |
124 | #define PHY_CFG_PHY_RST_OFF 3 |
125 | #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) | |
c94d8ca2 XC |
126 | #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) |
127 | #define PHY_CTRL (PORT_BASE + 0x14) | |
128 | #define PHY_CTRL_RESET_OFF 0 | |
129 | #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) | |
3e5d03c7 XC |
130 | #define CMD_HDR_PIR_OFF 8 |
131 | #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) | |
c94d8ca2 | 132 | #define SL_CFG (PORT_BASE + 0x84) |
7ab742dc | 133 | #define AIP_LIMIT (PORT_BASE + 0x90) |
3975f605 XC |
134 | #define SL_CONTROL (PORT_BASE + 0x94) |
135 | #define SL_CONTROL_NOTIFY_EN_OFF 0 | |
136 | #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) | |
137 | #define SL_CTA_OFF 17 | |
138 | #define SL_CTA_MSK (0x1 << SL_CTA_OFF) | |
45651175 XT |
139 | #define RX_PRIMS_STATUS (PORT_BASE + 0x98) |
140 | #define RX_BCAST_CHG_OFF 1 | |
141 | #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) | |
3975f605 XC |
142 | #define TX_ID_DWORD0 (PORT_BASE + 0x9c) |
143 | #define TX_ID_DWORD1 (PORT_BASE + 0xa0) | |
144 | #define TX_ID_DWORD2 (PORT_BASE + 0xa4) | |
145 | #define TX_ID_DWORD3 (PORT_BASE + 0xa8) | |
146 | #define TX_ID_DWORD4 (PORT_BASE + 0xaC) | |
147 | #define TX_ID_DWORD5 (PORT_BASE + 0xb0) | |
148 | #define TX_ID_DWORD6 (PORT_BASE + 0xb4) | |
149 | #define TXID_AUTO (PORT_BASE + 0xb8) | |
150 | #define CT3_OFF 1 | |
151 | #define CT3_MSK (0x1 << CT3_OFF) | |
402cd9f0 XC |
152 | #define TX_HARDRST_OFF 2 |
153 | #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) | |
3975f605 | 154 | #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) |
c94d8ca2 | 155 | #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) |
81036731 | 156 | #define STP_LINK_TIMER (PORT_BASE + 0x120) |
066312f6 | 157 | #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) |
d40bfb0d | 158 | #define CON_CFG_DRIVER (PORT_BASE + 0x130) |
c94d8ca2 XC |
159 | #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) |
160 | #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) | |
161 | #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) | |
162 | #define CHL_INT0 (PORT_BASE + 0x1b4) | |
163 | #define CHL_INT0_HOTPLUG_TOUT_OFF 0 | |
164 | #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) | |
165 | #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 | |
166 | #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) | |
167 | #define CHL_INT0_SL_PHY_ENABLE_OFF 2 | |
168 | #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) | |
169 | #define CHL_INT0_NOT_RDY_OFF 4 | |
170 | #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) | |
171 | #define CHL_INT0_PHY_RDY_OFF 5 | |
172 | #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) | |
173 | #define CHL_INT1 (PORT_BASE + 0x1b8) | |
174 | #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 | |
175 | #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) | |
176 | #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 | |
177 | #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) | |
4a6125c5 XT |
178 | #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 |
179 | #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 | |
180 | #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 | |
181 | #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 | |
c94d8ca2 | 182 | #define CHL_INT2 (PORT_BASE + 0x1bc) |
066312f6 | 183 | #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 |
70230be3 | 184 | #define CHL_INT2_RX_INVLD_DW_OFF 30 |
066312f6 | 185 | #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 |
c94d8ca2 XC |
186 | #define CHL_INT0_MSK (PORT_BASE + 0x1c0) |
187 | #define CHL_INT1_MSK (PORT_BASE + 0x1c4) | |
188 | #define CHL_INT2_MSK (PORT_BASE + 0x1c8) | |
189 | #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) | |
2b9174ae | 190 | #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) |
c94d8ca2 XC |
191 | #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) |
192 | #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) | |
193 | #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) | |
194 | #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) | |
195 | #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) | |
196 | #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) | |
a25d0d3d XC |
197 | #define DMA_TX_STATUS (PORT_BASE + 0x2d0) |
198 | #define DMA_TX_STATUS_BUSY_OFF 0 | |
199 | #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) | |
200 | #define DMA_RX_STATUS (PORT_BASE + 0x2e8) | |
201 | #define DMA_RX_STATUS_BUSY_OFF 0 | |
202 | #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) | |
2b9174ae XT |
203 | |
204 | #define COARSETUNE_TIME (PORT_BASE + 0x304) | |
ffc8f149 XT |
205 | #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) |
206 | #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) | |
207 | #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) | |
208 | #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) | |
a25d0d3d | 209 | |
a25d0d3d XC |
210 | #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ |
211 | #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) | |
212 | #error Max ITCT exceeded | |
213 | #endif | |
214 | ||
215 | #define AXI_MASTER_CFG_BASE (0x5000) | |
216 | #define AM_CTRL_GLOBAL (0x0) | |
1d51757d XT |
217 | #define AM_CTRL_SHUTDOWN_REQ_OFF 0 |
218 | #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) | |
a25d0d3d XC |
219 | #define AM_CURR_TRANS_RETURN (0x150) |
220 | ||
221 | #define AM_CFG_MAX_TRANS (0x5010) | |
222 | #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) | |
223 | #define AXI_CFG (0x5100) | |
224 | #define AM_ROB_ECC_ERR_ADDR (0x510c) | |
225 | #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 | |
226 | #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) | |
227 | #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 | |
228 | #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) | |
c94d8ca2 | 229 | |
56b72168 XT |
230 | /* RAS registers need init */ |
231 | #define RAS_BASE (0x6000) | |
232 | #define SAS_RAS_INTR0 (RAS_BASE) | |
233 | #define SAS_RAS_INTR1 (RAS_BASE + 0x04) | |
234 | #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) | |
235 | #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) | |
c13c7ac5 XT |
236 | #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) |
237 | #define SAS_RAS_INTR2 (RAS_BASE + 0x20) | |
238 | #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) | |
56b72168 | 239 | |
a2204723 XC |
240 | /* HW dma structures */ |
241 | /* Delivery queue header */ | |
242 | /* dw0 */ | |
4de0ca69 XC |
243 | #define CMD_HDR_ABORT_FLAG_OFF 0 |
244 | #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) | |
245 | #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 | |
246 | #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | |
a2204723 XC |
247 | #define CMD_HDR_RESP_REPORT_OFF 5 |
248 | #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) | |
249 | #define CMD_HDR_TLR_CTRL_OFF 6 | |
250 | #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) | |
251 | #define CMD_HDR_PORT_OFF 18 | |
252 | #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) | |
253 | #define CMD_HDR_PRIORITY_OFF 27 | |
254 | #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) | |
255 | #define CMD_HDR_CMD_OFF 29 | |
256 | #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) | |
257 | /* dw1 */ | |
ce60689e | 258 | #define CMD_HDR_UNCON_CMD_OFF 3 |
a2204723 XC |
259 | #define CMD_HDR_DIR_OFF 5 |
260 | #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) | |
ce60689e XC |
261 | #define CMD_HDR_RESET_OFF 7 |
262 | #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) | |
a2204723 XC |
263 | #define CMD_HDR_VDTL_OFF 10 |
264 | #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) | |
265 | #define CMD_HDR_FRAME_TYPE_OFF 11 | |
266 | #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) | |
267 | #define CMD_HDR_DEV_ID_OFF 16 | |
268 | #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) | |
269 | /* dw2 */ | |
270 | #define CMD_HDR_CFL_OFF 0 | |
271 | #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) | |
ce60689e XC |
272 | #define CMD_HDR_NCQ_TAG_OFF 10 |
273 | #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) | |
a2204723 XC |
274 | #define CMD_HDR_MRFL_OFF 15 |
275 | #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) | |
276 | #define CMD_HDR_SG_MOD_OFF 24 | |
277 | #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) | |
fa913de2 XC |
278 | /* dw3 */ |
279 | #define CMD_HDR_IPTT_OFF 0 | |
280 | #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) | |
a2204723 XC |
281 | /* dw6 */ |
282 | #define CMD_HDR_DIF_SGL_LEN_OFF 0 | |
283 | #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) | |
284 | #define CMD_HDR_DATA_SGL_LEN_OFF 16 | |
285 | #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) | |
4de0ca69 XC |
286 | /* dw7 */ |
287 | #define CMD_HDR_ADDR_MODE_SEL_OFF 15 | |
288 | #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) | |
289 | #define CMD_HDR_ABORT_IPTT_OFF 16 | |
290 | #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) | |
a2204723 | 291 | |
60b4a5ee XC |
292 | /* Completion header */ |
293 | /* dw0 */ | |
294 | #define CMPLT_HDR_CMPLT_OFF 0 | |
295 | #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) | |
296 | #define CMPLT_HDR_ERROR_PHASE_OFF 2 | |
297 | #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) | |
298 | #define CMPLT_HDR_RSPNS_XFRD_OFF 10 | |
299 | #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) | |
300 | #define CMPLT_HDR_ERX_OFF 12 | |
301 | #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) | |
302 | #define CMPLT_HDR_ABORT_STAT_OFF 13 | |
303 | #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) | |
304 | /* abort_stat */ | |
305 | #define STAT_IO_NOT_VALID 0x1 | |
306 | #define STAT_IO_NO_DEVICE 0x2 | |
307 | #define STAT_IO_COMPLETE 0x3 | |
308 | #define STAT_IO_ABORTED 0x4 | |
309 | /* dw1 */ | |
310 | #define CMPLT_HDR_IPTT_OFF 0 | |
311 | #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) | |
312 | #define CMPLT_HDR_DEV_ID_OFF 16 | |
313 | #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) | |
314 | /* dw3 */ | |
315 | #define CMPLT_HDR_IO_IN_TARGET_OFF 17 | |
316 | #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) | |
317 | ||
182e7222 XC |
318 | /* ITCT header */ |
319 | /* qw0 */ | |
320 | #define ITCT_HDR_DEV_TYPE_OFF 0 | |
321 | #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) | |
322 | #define ITCT_HDR_VALID_OFF 2 | |
323 | #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) | |
324 | #define ITCT_HDR_MCR_OFF 5 | |
325 | #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) | |
326 | #define ITCT_HDR_VLN_OFF 9 | |
327 | #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) | |
328 | #define ITCT_HDR_SMP_TIMEOUT_OFF 16 | |
329 | #define ITCT_HDR_AWT_CONTINUE_OFF 25 | |
330 | #define ITCT_HDR_PORT_ID_OFF 28 | |
331 | #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) | |
332 | /* qw2 */ | |
333 | #define ITCT_HDR_INLT_OFF 0 | |
334 | #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) | |
335 | #define ITCT_HDR_RTOLT_OFF 48 | |
336 | #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) | |
337 | ||
3e5d03c7 XC |
338 | struct hisi_sas_protect_iu_v3_hw { |
339 | u32 dw0; | |
340 | u32 lbrtcv; | |
341 | u32 lbrtgv; | |
342 | u32 dw3; | |
343 | u32 dw4; | |
344 | u32 dw5; | |
345 | u32 rsv; | |
346 | }; | |
347 | ||
c94d8ca2 XC |
348 | struct hisi_sas_complete_v3_hdr { |
349 | __le32 dw0; | |
350 | __le32 dw1; | |
351 | __le32 act; | |
352 | __le32 dw3; | |
353 | }; | |
354 | ||
60b4a5ee XC |
355 | struct hisi_sas_err_record_v3 { |
356 | /* dw0 */ | |
357 | __le32 trans_tx_fail_type; | |
358 | ||
359 | /* dw1 */ | |
360 | __le32 trans_rx_fail_type; | |
361 | ||
362 | /* dw2 */ | |
363 | __le16 dma_tx_err_type; | |
364 | __le16 sipc_rx_err_type; | |
365 | ||
366 | /* dw3 */ | |
367 | __le32 dma_rx_err_type; | |
368 | }; | |
369 | ||
370 | #define RX_DATA_LEN_UNDERFLOW_OFF 6 | |
371 | #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) | |
372 | ||
c94d8ca2 | 373 | #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 |
3975f605 XC |
374 | #define HISI_SAS_MSI_COUNT_V3_HW 32 |
375 | ||
a2204723 XC |
376 | #define DIR_NO_DATA 0 |
377 | #define DIR_TO_INI 1 | |
378 | #define DIR_TO_DEVICE 2 | |
379 | #define DIR_RESERVED 3 | |
380 | ||
ed80f9c4 XC |
381 | #define FIS_CMD_IS_UNCONSTRAINED(fis) \ |
382 | ((fis.command == ATA_CMD_READ_LOG_EXT) || \ | |
383 | (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ | |
384 | ((fis.command == ATA_CMD_DEV_RESET) && \ | |
385 | ((fis.control & ATA_SRST) != 0))) | |
ce60689e | 386 | |
3e5d03c7 XC |
387 | #define T10_INSRT_EN_OFF 0 |
388 | #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) | |
389 | #define T10_RMV_EN_OFF 1 | |
390 | #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) | |
391 | #define T10_RPLC_EN_OFF 2 | |
392 | #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) | |
393 | #define T10_CHK_EN_OFF 3 | |
394 | #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) | |
395 | #define INCR_LBRT_OFF 5 | |
396 | #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) | |
397 | #define USR_DATA_BLOCK_SZ_OFF 20 | |
398 | #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) | |
399 | #define T10_CHK_MSK_OFF 16 | |
400 | ||
6cc8d8f2 XC |
401 | static bool hisi_sas_intr_conv; |
402 | MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); | |
403 | ||
3e5d03c7 XC |
404 | /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ |
405 | static int prot_mask; | |
406 | module_param(prot_mask, int, 0); | |
407 | MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); | |
408 | ||
54edeee1 XC |
409 | static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) |
410 | { | |
411 | void __iomem *regs = hisi_hba->regs + off; | |
412 | ||
413 | return readl(regs); | |
414 | } | |
415 | ||
a2204723 XC |
416 | static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) |
417 | { | |
418 | void __iomem *regs = hisi_hba->regs + off; | |
419 | ||
420 | return readl_relaxed(regs); | |
421 | } | |
422 | ||
c94d8ca2 XC |
423 | static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) |
424 | { | |
425 | void __iomem *regs = hisi_hba->regs + off; | |
426 | ||
427 | writel(val, regs); | |
428 | } | |
429 | ||
430 | static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, | |
431 | u32 off, u32 val) | |
432 | { | |
433 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; | |
434 | ||
435 | writel(val, regs); | |
436 | } | |
437 | ||
3975f605 XC |
438 | static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, |
439 | int phy_no, u32 off) | |
440 | { | |
441 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; | |
442 | ||
443 | return readl(regs); | |
444 | } | |
445 | ||
70bfdcae JG |
446 | #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ |
447 | timeout_us) \ | |
448 | ({ \ | |
449 | void __iomem *regs = hisi_hba->regs + off; \ | |
450 | readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ | |
451 | }) | |
452 | ||
453 | #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ | |
454 | timeout_us) \ | |
455 | ({ \ | |
456 | void __iomem *regs = hisi_hba->regs + off; \ | |
457 | readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ | |
458 | }) | |
459 | ||
c94d8ca2 XC |
460 | static void init_reg_v3_hw(struct hisi_hba *hisi_hba) |
461 | { | |
c13c7ac5 | 462 | struct pci_dev *pdev = hisi_hba->pci_dev; |
c94d8ca2 XC |
463 | int i; |
464 | ||
465 | /* Global registers init */ | |
466 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, | |
467 | (u32)((1ULL << hisi_hba->queue_count) - 1)); | |
3297ded1 | 468 | hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); |
c94d8ca2 | 469 | hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); |
7ab742dc | 470 | hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); |
c94d8ca2 XC |
471 | hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); |
472 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); | |
473 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); | |
6cc8d8f2 XC |
474 | hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, |
475 | hisi_sas_intr_conv); | |
c94d8ca2 XC |
476 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); |
477 | hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); | |
478 | hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); | |
479 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); | |
480 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); | |
481 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); | |
c13c7ac5 | 482 | if (pdev->revision >= 0x21) |
f0b06432 | 483 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff); |
c13c7ac5 XT |
484 | else |
485 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); | |
c94d8ca2 XC |
486 | hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); |
487 | hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); | |
488 | hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); | |
056e4cc6 | 489 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); |
c94d8ca2 XC |
490 | hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); |
491 | hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); | |
492 | for (i = 0; i < hisi_hba->queue_count; i++) | |
493 | hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); | |
494 | ||
c94d8ca2 | 495 | hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); |
c94d8ca2 XC |
496 | |
497 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
f385b4ff XC |
498 | struct hisi_sas_phy *phy = &hisi_hba->phy[i]; |
499 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
500 | u32 prog_phy_link_rate = 0x800; | |
501 | ||
502 | if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < | |
503 | SAS_LINK_RATE_1_5_GBPS)) { | |
504 | prog_phy_link_rate = 0x855; | |
505 | } else { | |
506 | enum sas_linkrate max = sas_phy->phy->maximum_linkrate; | |
507 | ||
508 | prog_phy_link_rate = | |
509 | hisi_sas_get_prog_phy_linkrate_mask(max) | | |
510 | 0x800; | |
511 | } | |
512 | hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, | |
513 | prog_phy_link_rate); | |
2b9174ae | 514 | hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); |
c94d8ca2 XC |
515 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); |
516 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); | |
517 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); | |
518 | hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); | |
c13c7ac5 XT |
519 | if (pdev->revision >= 0x21) |
520 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, | |
521 | 0xffffffff); | |
522 | else | |
523 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, | |
524 | 0xff87ffff); | |
066312f6 | 525 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); |
c94d8ca2 XC |
526 | hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); |
527 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); | |
528 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); | |
529 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); | |
530 | hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); | |
2b9174ae XT |
531 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); |
532 | hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); | |
fe058330 | 533 | hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); |
806561bf | 534 | hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); |
2b9174ae XT |
535 | /* used for 12G negotiate */ |
536 | hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); | |
7ab742dc | 537 | hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); |
c94d8ca2 | 538 | } |
2b9174ae | 539 | |
c94d8ca2 XC |
540 | for (i = 0; i < hisi_hba->queue_count; i++) { |
541 | /* Delivery queue */ | |
542 | hisi_sas_write32(hisi_hba, | |
543 | DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), | |
544 | upper_32_bits(hisi_hba->cmd_hdr_dma[i])); | |
545 | ||
546 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), | |
547 | lower_32_bits(hisi_hba->cmd_hdr_dma[i])); | |
548 | ||
549 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), | |
550 | HISI_SAS_QUEUE_SLOTS); | |
551 | ||
552 | /* Completion queue */ | |
553 | hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), | |
554 | upper_32_bits(hisi_hba->complete_hdr_dma[i])); | |
555 | ||
556 | hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), | |
557 | lower_32_bits(hisi_hba->complete_hdr_dma[i])); | |
558 | ||
559 | hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), | |
560 | HISI_SAS_QUEUE_SLOTS); | |
561 | } | |
562 | ||
563 | /* itct */ | |
564 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, | |
565 | lower_32_bits(hisi_hba->itct_dma)); | |
566 | ||
567 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, | |
568 | upper_32_bits(hisi_hba->itct_dma)); | |
569 | ||
570 | /* iost */ | |
571 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, | |
572 | lower_32_bits(hisi_hba->iost_dma)); | |
573 | ||
574 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, | |
575 | upper_32_bits(hisi_hba->iost_dma)); | |
576 | ||
577 | /* breakpoint */ | |
578 | hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, | |
579 | lower_32_bits(hisi_hba->breakpoint_dma)); | |
580 | ||
581 | hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, | |
582 | upper_32_bits(hisi_hba->breakpoint_dma)); | |
583 | ||
584 | /* SATA broken msg */ | |
585 | hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, | |
586 | lower_32_bits(hisi_hba->sata_breakpoint_dma)); | |
587 | ||
588 | hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, | |
589 | upper_32_bits(hisi_hba->sata_breakpoint_dma)); | |
590 | ||
591 | /* SATA initial fis */ | |
592 | hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, | |
593 | lower_32_bits(hisi_hba->initial_fis_dma)); | |
594 | ||
595 | hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, | |
596 | upper_32_bits(hisi_hba->initial_fis_dma)); | |
56b72168 XT |
597 | |
598 | /* RAS registers init */ | |
599 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); | |
600 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); | |
c13c7ac5 XT |
601 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); |
602 | hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); | |
e24fe507 XT |
603 | |
604 | /* LED registers init */ | |
605 | hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); | |
606 | hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); | |
607 | hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); | |
608 | /* Configure blink generator rate A to 1Hz and B to 4Hz */ | |
609 | hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); | |
610 | hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); | |
c94d8ca2 XC |
611 | } |
612 | ||
3975f605 XC |
613 | static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
614 | { | |
615 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
616 | ||
617 | cfg &= ~PHY_CFG_DC_OPT_MSK; | |
618 | cfg |= 1 << PHY_CFG_DC_OPT_OFF; | |
619 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
620 | } | |
621 | ||
622 | static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) | |
623 | { | |
624 | struct sas_identify_frame identify_frame; | |
625 | u32 *identify_buffer; | |
626 | ||
627 | memset(&identify_frame, 0, sizeof(identify_frame)); | |
628 | identify_frame.dev_type = SAS_END_DEVICE; | |
629 | identify_frame.frame_type = 0; | |
630 | identify_frame._un1 = 1; | |
631 | identify_frame.initiator_bits = SAS_PROTOCOL_ALL; | |
632 | identify_frame.target_bits = SAS_PROTOCOL_NONE; | |
633 | memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); | |
634 | memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); | |
635 | identify_frame.phy_id = phy_no; | |
636 | identify_buffer = (u32 *)(&identify_frame); | |
637 | ||
638 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, | |
639 | __swab32(identify_buffer[0])); | |
640 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, | |
641 | __swab32(identify_buffer[1])); | |
642 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, | |
643 | __swab32(identify_buffer[2])); | |
644 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, | |
645 | __swab32(identify_buffer[3])); | |
646 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, | |
647 | __swab32(identify_buffer[4])); | |
648 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, | |
649 | __swab32(identify_buffer[5])); | |
650 | } | |
651 | ||
182e7222 XC |
652 | static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, |
653 | struct hisi_sas_device *sas_dev) | |
654 | { | |
655 | struct domain_device *device = sas_dev->sas_device; | |
656 | struct device *dev = hisi_hba->dev; | |
657 | u64 qw0, device_id = sas_dev->device_id; | |
658 | struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; | |
659 | struct domain_device *parent_dev = device->parent; | |
660 | struct asd_sas_port *sas_port = device->port; | |
661 | struct hisi_sas_port *port = to_hisi_sas_port(sas_port); | |
b8438c40 | 662 | u64 sas_addr; |
182e7222 XC |
663 | |
664 | memset(itct, 0, sizeof(*itct)); | |
665 | ||
666 | /* qw0 */ | |
667 | qw0 = 0; | |
668 | switch (sas_dev->dev_type) { | |
669 | case SAS_END_DEVICE: | |
670 | case SAS_EDGE_EXPANDER_DEVICE: | |
671 | case SAS_FANOUT_EXPANDER_DEVICE: | |
672 | qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; | |
673 | break; | |
674 | case SAS_SATA_DEV: | |
675 | case SAS_SATA_PENDING: | |
676 | if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) | |
677 | qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; | |
678 | else | |
679 | qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; | |
680 | break; | |
681 | default: | |
682 | dev_warn(dev, "setup itct: unsupported dev type (%d)\n", | |
683 | sas_dev->dev_type); | |
684 | } | |
685 | ||
686 | qw0 |= ((1 << ITCT_HDR_VALID_OFF) | | |
687 | (device->linkrate << ITCT_HDR_MCR_OFF) | | |
688 | (1 << ITCT_HDR_VLN_OFF) | | |
689 | (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | | |
690 | (1 << ITCT_HDR_AWT_CONTINUE_OFF) | | |
691 | (port->id << ITCT_HDR_PORT_ID_OFF)); | |
692 | itct->qw0 = cpu_to_le64(qw0); | |
693 | ||
694 | /* qw1 */ | |
b8438c40 JG |
695 | memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); |
696 | itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); | |
182e7222 XC |
697 | |
698 | /* qw2 */ | |
699 | if (!dev_is_sata(device)) | |
700 | itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | | |
701 | (0x1ULL << ITCT_HDR_RTOLT_OFF)); | |
702 | } | |
703 | ||
f39943ee | 704 | static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, |
182e7222 XC |
705 | struct hisi_sas_device *sas_dev) |
706 | { | |
13cd5ed6 | 707 | DECLARE_COMPLETION_ONSTACK(completion); |
182e7222 | 708 | u64 dev_id = sas_dev->device_id; |
182e7222 XC |
709 | struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; |
710 | u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); | |
711 | ||
13cd5ed6 XC |
712 | sas_dev->completion = &completion; |
713 | ||
182e7222 XC |
714 | /* clear the itct interrupt state */ |
715 | if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) | |
716 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, | |
717 | ENT_INT_SRC3_ITC_INT_MSK); | |
718 | ||
719 | /* clear the itct table*/ | |
13cd5ed6 | 720 | reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); |
182e7222 XC |
721 | hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); |
722 | ||
13cd5ed6 XC |
723 | wait_for_completion(sas_dev->completion); |
724 | memset(itct, 0, sizeof(struct hisi_sas_itct)); | |
182e7222 XC |
725 | } |
726 | ||
d30ff263 XC |
727 | static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, |
728 | struct domain_device *device) | |
729 | { | |
730 | struct hisi_sas_slot *slot, *slot2; | |
731 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
732 | u32 cfg_abt_set_query_iptt; | |
733 | ||
734 | cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, | |
735 | CFG_ABT_SET_QUERY_IPTT); | |
736 | list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { | |
737 | cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; | |
738 | cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | | |
739 | (slot->idx << CFG_SET_ABORTED_IPTT_OFF); | |
740 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, | |
741 | cfg_abt_set_query_iptt); | |
742 | } | |
743 | cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); | |
744 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, | |
745 | cfg_abt_set_query_iptt); | |
746 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, | |
747 | 1 << CFG_ABT_SET_IPTT_DONE_OFF); | |
748 | } | |
749 | ||
a25d0d3d XC |
750 | static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) |
751 | { | |
752 | struct device *dev = hisi_hba->dev; | |
753 | int ret; | |
754 | u32 val; | |
755 | ||
756 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); | |
757 | ||
758 | /* Disable all of the PHYs */ | |
759 | hisi_sas_stop_phys(hisi_hba); | |
760 | udelay(50); | |
761 | ||
762 | /* Ensure axi bus idle */ | |
70bfdcae JG |
763 | ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, |
764 | 20000, 1000000); | |
a25d0d3d XC |
765 | if (ret) { |
766 | dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); | |
767 | return -EIO; | |
768 | } | |
769 | ||
770 | if (ACPI_HANDLE(dev)) { | |
771 | acpi_status s; | |
772 | ||
773 | s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); | |
774 | if (ACPI_FAILURE(s)) { | |
775 | dev_err(dev, "Reset failed\n"); | |
776 | return -EIO; | |
777 | } | |
bcbc7f1c | 778 | } else { |
a25d0d3d | 779 | dev_err(dev, "no reset method!\n"); |
bcbc7f1c XC |
780 | return -EINVAL; |
781 | } | |
a25d0d3d XC |
782 | |
783 | return 0; | |
784 | } | |
785 | ||
c94d8ca2 XC |
786 | static int hw_init_v3_hw(struct hisi_hba *hisi_hba) |
787 | { | |
a25d0d3d XC |
788 | struct device *dev = hisi_hba->dev; |
789 | int rc; | |
790 | ||
791 | rc = reset_hw_v3_hw(hisi_hba); | |
792 | if (rc) { | |
793 | dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); | |
794 | return rc; | |
795 | } | |
796 | ||
797 | msleep(100); | |
c94d8ca2 XC |
798 | init_reg_v3_hw(hisi_hba); |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
3975f605 XC |
803 | static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
804 | { | |
805 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
806 | ||
807 | cfg |= PHY_CFG_ENA_MSK; | |
17d59a57 | 808 | cfg &= ~PHY_CFG_PHY_RST_MSK; |
3975f605 XC |
809 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); |
810 | } | |
811 | ||
402cd9f0 XC |
812 | static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
813 | { | |
814 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
17d59a57 | 815 | u32 state; |
402cd9f0 XC |
816 | |
817 | cfg &= ~PHY_CFG_ENA_MSK; | |
818 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
17d59a57 XT |
819 | |
820 | mdelay(50); | |
821 | ||
822 | state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
823 | if (state & BIT(phy_no)) { | |
824 | cfg |= PHY_CFG_PHY_RST_MSK; | |
825 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
826 | } | |
402cd9f0 XC |
827 | } |
828 | ||
3975f605 XC |
829 | static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
830 | { | |
831 | config_id_frame_v3_hw(hisi_hba, phy_no); | |
832 | config_phy_opt_mode_v3_hw(hisi_hba, phy_no); | |
833 | enable_phy_v3_hw(hisi_hba, phy_no); | |
834 | } | |
835 | ||
402cd9f0 XC |
836 | static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
837 | { | |
838 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
839 | u32 txid_auto; | |
840 | ||
a25d0d3d | 841 | disable_phy_v3_hw(hisi_hba, phy_no); |
402cd9f0 XC |
842 | if (phy->identify.device_type == SAS_END_DEVICE) { |
843 | txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); | |
844 | hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, | |
845 | txid_auto | TX_HARDRST_MSK); | |
846 | } | |
847 | msleep(100); | |
848 | start_phy_v3_hw(hisi_hba, phy_no); | |
849 | } | |
850 | ||
bcbc7f1c | 851 | static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) |
402cd9f0 XC |
852 | { |
853 | return SAS_LINK_RATE_12_0_GBPS; | |
854 | } | |
855 | ||
3975f605 XC |
856 | static void phys_init_v3_hw(struct hisi_hba *hisi_hba) |
857 | { | |
a25d0d3d XC |
858 | int i; |
859 | ||
860 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
861 | struct hisi_sas_phy *phy = &hisi_hba->phy[i]; | |
862 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
863 | ||
864 | if (!sas_phy->phy->enabled) | |
865 | continue; | |
866 | ||
867 | start_phy_v3_hw(hisi_hba, i); | |
868 | } | |
3975f605 XC |
869 | } |
870 | ||
a2b61737 | 871 | static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
3975f605 XC |
872 | { |
873 | u32 sl_control; | |
874 | ||
875 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
876 | sl_control |= SL_CONTROL_NOTIFY_EN_MSK; | |
877 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); | |
878 | msleep(1); | |
879 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
880 | sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; | |
881 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); | |
882 | } | |
883 | ||
f771d3b0 XC |
884 | static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) |
885 | { | |
886 | int i, bitmap = 0; | |
887 | u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
0e3231fc | 888 | u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); |
f771d3b0 XC |
889 | |
890 | for (i = 0; i < hisi_hba->n_phy; i++) | |
0e3231fc XT |
891 | if (phy_state & BIT(i)) |
892 | if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) | |
893 | bitmap |= BIT(i); | |
f771d3b0 XC |
894 | |
895 | return bitmap; | |
896 | } | |
897 | ||
a2204723 XC |
898 | /** |
899 | * The callpath to this function and upto writing the write | |
900 | * queue pointer should be safe from interruption. | |
901 | */ | |
902 | static int | |
903 | get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) | |
904 | { | |
905 | struct device *dev = hisi_hba->dev; | |
906 | int queue = dq->id; | |
907 | u32 r, w; | |
908 | ||
909 | w = dq->wr_point; | |
910 | r = hisi_sas_read32_relaxed(hisi_hba, | |
911 | DLVRY_Q_0_RD_PTR + (queue * 0x14)); | |
912 | if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { | |
c58ec824 | 913 | dev_warn(dev, "full queue=%d r=%d w=%d\n", |
a2204723 XC |
914 | queue, r, w); |
915 | return -EAGAIN; | |
916 | } | |
917 | ||
c58ec824 XC |
918 | dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; |
919 | ||
920 | return w; | |
a2204723 XC |
921 | } |
922 | ||
923 | static void start_delivery_v3_hw(struct hisi_sas_dq *dq) | |
924 | { | |
925 | struct hisi_hba *hisi_hba = dq->hisi_hba; | |
5a61a535 | 926 | struct hisi_sas_slot *s, *s1, *s2 = NULL; |
c58ec824 | 927 | int dlvry_queue = dq->id; |
5a61a535 | 928 | int wp; |
c58ec824 | 929 | |
c58ec824 XC |
930 | list_for_each_entry_safe(s, s1, &dq->list, delivery) { |
931 | if (!s->ready) | |
932 | break; | |
5a61a535 | 933 | s2 = s; |
c58ec824 XC |
934 | list_del(&s->delivery); |
935 | } | |
936 | ||
5a61a535 | 937 | if (!s2) |
c58ec824 | 938 | return; |
a2204723 | 939 | |
5a61a535 XT |
940 | /* |
941 | * Ensure that memories for slots built on other CPUs is observed. | |
942 | */ | |
943 | smp_rmb(); | |
944 | wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; | |
945 | ||
c58ec824 | 946 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); |
a2204723 XC |
947 | } |
948 | ||
81d115ec | 949 | static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, |
a2204723 XC |
950 | struct hisi_sas_slot *slot, |
951 | struct hisi_sas_cmd_hdr *hdr, | |
952 | struct scatterlist *scatter, | |
953 | int n_elem) | |
954 | { | |
f557e32c | 955 | struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); |
a2204723 XC |
956 | struct scatterlist *sg; |
957 | int i; | |
958 | ||
a2204723 | 959 | for_each_sg(scatter, sg, n_elem, i) { |
f557e32c | 960 | struct hisi_sas_sge *entry = &sge_page->sge[i]; |
a2204723 XC |
961 | |
962 | entry->addr = cpu_to_le64(sg_dma_address(sg)); | |
963 | entry->page_ctrl_0 = entry->page_ctrl_1 = 0; | |
964 | entry->data_len = cpu_to_le32(sg_dma_len(sg)); | |
965 | entry->data_off = 0; | |
966 | } | |
967 | ||
f557e32c XT |
968 | hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); |
969 | ||
a2204723 | 970 | hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); |
a2204723 XC |
971 | } |
972 | ||
3e5d03c7 XC |
973 | static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) |
974 | { | |
975 | unsigned char prot_flags = scsi_cmnd->prot_flags; | |
976 | ||
977 | if (prot_flags & SCSI_PROT_TRANSFER_PI) { | |
978 | if (prot_flags & SCSI_PROT_REF_CHECK) | |
979 | return 0xc << 16; | |
980 | return 0xfc << 16; | |
981 | } | |
982 | return 0; | |
983 | } | |
984 | ||
985 | static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, | |
986 | struct hisi_sas_protect_iu_v3_hw *prot) | |
987 | { | |
988 | unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); | |
989 | unsigned int interval = scsi_prot_interval(scsi_cmnd); | |
990 | u32 lbrt_chk_val = scsi_prot_ref_tag(scsi_cmnd); | |
991 | ||
992 | switch (prot_op) { | |
993 | case SCSI_PROT_READ_STRIP: | |
994 | prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); | |
995 | prot->lbrtcv = lbrt_chk_val; | |
996 | prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); | |
997 | break; | |
998 | case SCSI_PROT_WRITE_INSERT: | |
999 | prot->dw0 |= T10_INSRT_EN_MSK; | |
1000 | prot->lbrtgv = lbrt_chk_val; | |
1001 | break; | |
1002 | default: | |
1003 | WARN(1, "prot_op(0x%x) is not valid\n", prot_op); | |
1004 | break; | |
1005 | } | |
1006 | ||
1007 | switch (interval) { | |
1008 | case 512: | |
1009 | break; | |
1010 | case 4096: | |
1011 | prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); | |
1012 | break; | |
1013 | case 520: | |
1014 | prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); | |
1015 | break; | |
1016 | default: | |
1017 | WARN(1, "protection interval (0x%x) invalid\n", | |
1018 | interval); | |
1019 | break; | |
1020 | } | |
1021 | ||
1022 | prot->dw0 |= INCR_LBRT_MSK; | |
1023 | } | |
1024 | ||
81d115ec | 1025 | static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, |
9a98d728 | 1026 | struct hisi_sas_slot *slot) |
a2204723 XC |
1027 | { |
1028 | struct sas_task *task = slot->task; | |
1029 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1030 | struct domain_device *device = task->dev; | |
1031 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
1032 | struct hisi_sas_port *port = slot->port; | |
1033 | struct sas_ssp_task *ssp_task = &task->ssp_task; | |
1034 | struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; | |
9a98d728 | 1035 | struct hisi_sas_tmf_task *tmf = slot->tmf; |
3e5d03c7 | 1036 | unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); |
9a98d728 | 1037 | int has_data = 0, priority = !!tmf; |
a2204723 | 1038 | u8 *buf_cmd; |
3e5d03c7 | 1039 | u32 dw1 = 0, dw2 = 0, len = 0; |
a2204723 XC |
1040 | |
1041 | hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | | |
1042 | (2 << CMD_HDR_TLR_CTRL_OFF) | | |
1043 | (port->id << CMD_HDR_PORT_OFF) | | |
1044 | (priority << CMD_HDR_PRIORITY_OFF) | | |
1045 | (1 << CMD_HDR_CMD_OFF)); /* ssp */ | |
1046 | ||
1047 | dw1 = 1 << CMD_HDR_VDTL_OFF; | |
9a98d728 | 1048 | if (tmf) { |
a2204723 XC |
1049 | dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; |
1050 | dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; | |
1051 | } else { | |
1052 | dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; | |
1053 | switch (scsi_cmnd->sc_data_direction) { | |
1054 | case DMA_TO_DEVICE: | |
1055 | has_data = 1; | |
1056 | dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; | |
1057 | break; | |
1058 | case DMA_FROM_DEVICE: | |
1059 | has_data = 1; | |
1060 | dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; | |
1061 | break; | |
1062 | default: | |
1063 | dw1 &= ~CMD_HDR_DIR_MSK; | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | /* map itct entry */ | |
1068 | dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; | |
a2204723 XC |
1069 | |
1070 | dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) | |
1071 | + 3) / 4) << CMD_HDR_CFL_OFF) | | |
1072 | ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | | |
1073 | (2 << CMD_HDR_SG_MOD_OFF); | |
1074 | hdr->dw2 = cpu_to_le32(dw2); | |
1075 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1076 | ||
81d115ec XC |
1077 | if (has_data) |
1078 | prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, | |
a2204723 | 1079 | slot->n_elem); |
a2204723 | 1080 | |
f557e32c XT |
1081 | hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); |
1082 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); | |
a2204723 | 1083 | |
f557e32c XT |
1084 | buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + |
1085 | sizeof(struct ssp_frame_hdr); | |
a2204723 | 1086 | |
f557e32c | 1087 | memcpy(buf_cmd, &task->ssp_task.LUN, 8); |
9a98d728 | 1088 | if (!tmf) { |
a2204723 XC |
1089 | buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); |
1090 | memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); | |
1091 | } else { | |
1092 | buf_cmd[10] = tmf->tmf; | |
1093 | switch (tmf->tmf) { | |
1094 | case TMF_ABORT_TASK: | |
1095 | case TMF_QUERY_TASK: | |
1096 | buf_cmd[12] = | |
1097 | (tmf->tag_of_task_to_be_managed >> 8) & 0xff; | |
1098 | buf_cmd[13] = | |
1099 | tmf->tag_of_task_to_be_managed & 0xff; | |
1100 | break; | |
1101 | default: | |
1102 | break; | |
1103 | } | |
1104 | } | |
3e5d03c7 XC |
1105 | |
1106 | if (has_data && (prot_op != SCSI_PROT_NORMAL)) { | |
1107 | struct hisi_sas_protect_iu_v3_hw prot; | |
1108 | u8 *buf_cmd_prot; | |
1109 | ||
1110 | hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); | |
1111 | dw1 |= CMD_HDR_PIR_MSK; | |
1112 | buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + | |
1113 | sizeof(struct ssp_frame_hdr) + | |
1114 | sizeof(struct ssp_command_iu); | |
1115 | ||
1116 | memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); | |
1117 | fill_prot_v3_hw(scsi_cmnd, &prot); | |
1118 | memcpy(buf_cmd_prot, &prot, | |
1119 | sizeof(struct hisi_sas_protect_iu_v3_hw)); | |
1120 | ||
1121 | /* | |
1122 | * For READ, we need length of info read to memory, while for | |
1123 | * WRITE we need length of data written to the disk. | |
1124 | */ | |
1125 | if (prot_op == SCSI_PROT_WRITE_INSERT) { | |
1126 | unsigned int interval = scsi_prot_interval(scsi_cmnd); | |
1127 | unsigned int ilog2_interval = ilog2(interval); | |
1128 | ||
1129 | len = (task->total_xfer_len >> ilog2_interval) * 8; | |
1130 | } | |
1131 | ||
1132 | } | |
1133 | ||
1134 | hdr->dw1 = cpu_to_le32(dw1); | |
1135 | ||
1136 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); | |
a2204723 XC |
1137 | } |
1138 | ||
81d115ec | 1139 | static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, |
fa913de2 XC |
1140 | struct hisi_sas_slot *slot) |
1141 | { | |
1142 | struct sas_task *task = slot->task; | |
1143 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1144 | struct domain_device *device = task->dev; | |
fa913de2 | 1145 | struct hisi_sas_port *port = slot->port; |
8118ae07 | 1146 | struct scatterlist *sg_req; |
fa913de2 XC |
1147 | struct hisi_sas_device *sas_dev = device->lldd_dev; |
1148 | dma_addr_t req_dma_addr; | |
8118ae07 | 1149 | unsigned int req_len; |
fa913de2 | 1150 | |
fa913de2 XC |
1151 | /* req */ |
1152 | sg_req = &task->smp_task.smp_req; | |
fa913de2 XC |
1153 | req_len = sg_dma_len(sg_req); |
1154 | req_dma_addr = sg_dma_address(sg_req); | |
1155 | ||
fa913de2 XC |
1156 | /* create header */ |
1157 | /* dw0 */ | |
1158 | hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | | |
1159 | (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ | |
1160 | (2 << CMD_HDR_CMD_OFF)); /* smp */ | |
1161 | ||
1162 | /* map itct entry */ | |
1163 | hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | | |
1164 | (1 << CMD_HDR_FRAME_TYPE_OFF) | | |
1165 | (DIR_NO_DATA << CMD_HDR_DIR_OFF)); | |
1166 | ||
1167 | /* dw2 */ | |
1168 | hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | | |
1169 | (HISI_SAS_MAX_SMP_RESP_SZ / 4 << | |
1170 | CMD_HDR_MRFL_OFF)); | |
1171 | ||
1172 | hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); | |
1173 | ||
1174 | hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); | |
f557e32c | 1175 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); |
fa913de2 | 1176 | |
fa913de2 XC |
1177 | } |
1178 | ||
81d115ec | 1179 | static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, |
ce60689e XC |
1180 | struct hisi_sas_slot *slot) |
1181 | { | |
1182 | struct sas_task *task = slot->task; | |
1183 | struct domain_device *device = task->dev; | |
1184 | struct domain_device *parent_dev = device->parent; | |
1185 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
1186 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1187 | struct asd_sas_port *sas_port = device->port; | |
1188 | struct hisi_sas_port *port = to_hisi_sas_port(sas_port); | |
1189 | u8 *buf_cmd; | |
81d115ec | 1190 | int has_data = 0, hdr_tag = 0; |
ce60689e XC |
1191 | u32 dw1 = 0, dw2 = 0; |
1192 | ||
1193 | hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); | |
1194 | if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) | |
1195 | hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); | |
1196 | else | |
1197 | hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); | |
1198 | ||
1199 | switch (task->data_dir) { | |
1200 | case DMA_TO_DEVICE: | |
1201 | has_data = 1; | |
1202 | dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; | |
1203 | break; | |
1204 | case DMA_FROM_DEVICE: | |
1205 | has_data = 1; | |
1206 | dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; | |
1207 | break; | |
1208 | default: | |
1209 | dw1 &= ~CMD_HDR_DIR_MSK; | |
1210 | } | |
1211 | ||
1212 | if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && | |
1213 | (task->ata_task.fis.control & ATA_SRST)) | |
1214 | dw1 |= 1 << CMD_HDR_RESET_OFF; | |
1215 | ||
1216 | dw1 |= (hisi_sas_get_ata_protocol( | |
ba0bb2be | 1217 | &task->ata_task.fis, task->data_dir)) |
ce60689e XC |
1218 | << CMD_HDR_FRAME_TYPE_OFF; |
1219 | dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; | |
1220 | ||
ed80f9c4 | 1221 | if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) |
ce60689e XC |
1222 | dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; |
1223 | ||
1224 | hdr->dw1 = cpu_to_le32(dw1); | |
1225 | ||
1226 | /* dw2 */ | |
ac458c64 XC |
1227 | if (task->ata_task.use_ncq) { |
1228 | struct ata_queued_cmd *qc = task->uldd_task; | |
1229 | ||
1230 | hdr_tag = qc->tag; | |
ce60689e XC |
1231 | task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); |
1232 | dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; | |
1233 | } | |
1234 | ||
1235 | dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | | |
1236 | 2 << CMD_HDR_SG_MOD_OFF; | |
1237 | hdr->dw2 = cpu_to_le32(dw2); | |
1238 | ||
1239 | /* dw3 */ | |
1240 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1241 | ||
81d115ec XC |
1242 | if (has_data) |
1243 | prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, | |
ce60689e | 1244 | slot->n_elem); |
ce60689e XC |
1245 | |
1246 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); | |
f557e32c XT |
1247 | hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); |
1248 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); | |
ce60689e | 1249 | |
f557e32c | 1250 | buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); |
ce60689e XC |
1251 | |
1252 | if (likely(!task->ata_task.device_control_reg_update)) | |
1253 | task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ | |
1254 | /* fill in command FIS */ | |
1255 | memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); | |
ce60689e XC |
1256 | } |
1257 | ||
81d115ec | 1258 | static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, |
4de0ca69 XC |
1259 | struct hisi_sas_slot *slot, |
1260 | int device_id, int abort_flag, int tag_to_abort) | |
1261 | { | |
1262 | struct sas_task *task = slot->task; | |
1263 | struct domain_device *dev = task->dev; | |
1264 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1265 | struct hisi_sas_port *port = slot->port; | |
1266 | ||
1267 | /* dw0 */ | |
1268 | hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ | |
1269 | (port->id << CMD_HDR_PORT_OFF) | | |
bcbc7f1c | 1270 | (dev_is_sata(dev) |
4de0ca69 XC |
1271 | << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | |
1272 | (abort_flag | |
1273 | << CMD_HDR_ABORT_FLAG_OFF)); | |
1274 | ||
1275 | /* dw1 */ | |
1276 | hdr->dw1 = cpu_to_le32(device_id | |
1277 | << CMD_HDR_DEV_ID_OFF); | |
1278 | ||
1279 | /* dw7 */ | |
1280 | hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); | |
1281 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1282 | ||
4de0ca69 XC |
1283 | } |
1284 | ||
bcbc7f1c | 1285 | static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 | 1286 | { |
bcbc7f1c | 1287 | int i, res; |
c57eb4e4 | 1288 | u32 context, port_id, link_rate; |
54edeee1 XC |
1289 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; |
1290 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1291 | struct device *dev = hisi_hba->dev; | |
cca25cbc | 1292 | unsigned long flags; |
54edeee1 XC |
1293 | |
1294 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); | |
1295 | ||
1296 | port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
1297 | port_id = (port_id >> (4 * phy_no)) & 0xf; | |
1298 | link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); | |
1299 | link_rate = (link_rate >> (phy_no * 4)) & 0xf; | |
1300 | ||
1301 | if (port_id == 0xf) { | |
1302 | dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); | |
1303 | res = IRQ_NONE; | |
1304 | goto end; | |
1305 | } | |
1306 | sas_phy->linkrate = link_rate; | |
54edeee1 XC |
1307 | phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); |
1308 | ||
1309 | /* Check for SATA dev */ | |
1310 | context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); | |
1311 | if (context & (1 << phy_no)) { | |
1312 | struct hisi_sas_initial_fis *initial_fis; | |
1313 | struct dev_to_host_fis *fis; | |
1314 | u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; | |
1315 | ||
081a1608 | 1316 | dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); |
54edeee1 XC |
1317 | initial_fis = &hisi_hba->initial_fis[phy_no]; |
1318 | fis = &initial_fis->fis; | |
a2d76b6b XC |
1319 | |
1320 | /* check ERR bit of Status Register */ | |
1321 | if (fis->status & ATA_ERR) { | |
1322 | dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", | |
1323 | phy_no, fis->status); | |
1324 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1325 | res = IRQ_NONE; | |
1326 | goto end; | |
1327 | } | |
1328 | ||
54edeee1 XC |
1329 | sas_phy->oob_mode = SATA_OOB_MODE; |
1330 | attached_sas_addr[0] = 0x50; | |
1331 | attached_sas_addr[7] = phy_no; | |
1332 | memcpy(sas_phy->attached_sas_addr, | |
1333 | attached_sas_addr, | |
1334 | SAS_ADDR_SIZE); | |
1335 | memcpy(sas_phy->frame_rcvd, fis, | |
1336 | sizeof(struct dev_to_host_fis)); | |
1337 | phy->phy_type |= PORT_TYPE_SATA; | |
1338 | phy->identify.device_type = SAS_SATA_DEV; | |
1339 | phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); | |
1340 | phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; | |
1341 | } else { | |
1342 | u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; | |
1343 | struct sas_identify_frame *id = | |
1344 | (struct sas_identify_frame *)frame_rcvd; | |
1345 | ||
1346 | dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); | |
1347 | for (i = 0; i < 6; i++) { | |
1348 | u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1349 | RX_IDAF_DWORD0 + (i * 4)); | |
1350 | frame_rcvd[i] = __swab32(idaf); | |
1351 | } | |
1352 | sas_phy->oob_mode = SAS_OOB_MODE; | |
1353 | memcpy(sas_phy->attached_sas_addr, | |
1354 | &id->sas_addr, | |
1355 | SAS_ADDR_SIZE); | |
1356 | phy->phy_type |= PORT_TYPE_SAS; | |
1357 | phy->identify.device_type = id->dev_type; | |
1358 | phy->frame_rcvd_size = sizeof(struct sas_identify_frame); | |
1359 | if (phy->identify.device_type == SAS_END_DEVICE) | |
1360 | phy->identify.target_port_protocols = | |
1361 | SAS_PROTOCOL_SSP; | |
1362 | else if (phy->identify.device_type != SAS_PHY_UNUSED) | |
1363 | phy->identify.target_port_protocols = | |
1364 | SAS_PROTOCOL_SMP; | |
1365 | } | |
1366 | ||
1367 | phy->port_id = port_id; | |
1368 | phy->phy_attached = 1; | |
320cd6f1 | 1369 | hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); |
bcbc7f1c | 1370 | res = IRQ_HANDLED; |
cca25cbc XC |
1371 | spin_lock_irqsave(&phy->lock, flags); |
1372 | if (phy->reset_completion) { | |
1373 | phy->in_reset = 0; | |
1374 | complete(phy->reset_completion); | |
1375 | } | |
1376 | spin_unlock_irqrestore(&phy->lock, flags); | |
54edeee1 XC |
1377 | end: |
1378 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, | |
1379 | CHL_INT0_SL_PHY_ENABLE_MSK); | |
1380 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); | |
1381 | ||
1382 | return res; | |
1383 | } | |
1384 | ||
bcbc7f1c | 1385 | static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 | 1386 | { |
54edeee1 XC |
1387 | u32 phy_state, sl_ctrl, txid_auto; |
1388 | struct device *dev = hisi_hba->dev; | |
1389 | ||
1390 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); | |
1391 | ||
1392 | phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
1393 | dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); | |
1394 | hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); | |
1395 | ||
1396 | sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
1397 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, | |
1398 | sl_ctrl&(~SL_CTA_MSK)); | |
1399 | ||
1400 | txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); | |
1401 | hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, | |
1402 | txid_auto | CT3_MSK); | |
1403 | ||
1404 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); | |
1405 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); | |
1406 | ||
bcbc7f1c | 1407 | return IRQ_HANDLED; |
54edeee1 XC |
1408 | } |
1409 | ||
bcbc7f1c | 1410 | static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 XC |
1411 | { |
1412 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
1413 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1414 | struct sas_ha_struct *sas_ha = &hisi_hba->sha; | |
45651175 | 1415 | u32 bcast_status; |
54edeee1 XC |
1416 | |
1417 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); | |
45651175 | 1418 | bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); |
df48a904 XT |
1419 | if ((bcast_status & RX_BCAST_CHG_MSK) && |
1420 | !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) | |
45651175 | 1421 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); |
54edeee1 XC |
1422 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, |
1423 | CHL_INT0_SL_RX_BCST_ACK_MSK); | |
1424 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); | |
bcbc7f1c XC |
1425 | |
1426 | return IRQ_HANDLED; | |
54edeee1 XC |
1427 | } |
1428 | ||
1429 | static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) | |
1430 | { | |
1431 | struct hisi_hba *hisi_hba = p; | |
1432 | u32 irq_msk; | |
1433 | int phy_no = 0; | |
1434 | irqreturn_t res = IRQ_NONE; | |
1435 | ||
1436 | irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) | |
1437 | & 0x11111111; | |
1438 | while (irq_msk) { | |
1439 | if (irq_msk & 1) { | |
1440 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1441 | CHL_INT0); | |
1442 | u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
1443 | int rdy = phy_state & (1 << phy_no); | |
1444 | ||
1445 | if (rdy) { | |
1446 | if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) | |
1447 | /* phy up */ | |
1448 | if (phy_up_v3_hw(phy_no, hisi_hba) | |
1449 | == IRQ_HANDLED) | |
1450 | res = IRQ_HANDLED; | |
1451 | if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) | |
1452 | /* phy bcast */ | |
bcbc7f1c XC |
1453 | if (phy_bcast_v3_hw(phy_no, hisi_hba) |
1454 | == IRQ_HANDLED) | |
1455 | res = IRQ_HANDLED; | |
54edeee1 XC |
1456 | } else { |
1457 | if (irq_value & CHL_INT0_NOT_RDY_MSK) | |
1458 | /* phy down */ | |
1459 | if (phy_down_v3_hw(phy_no, hisi_hba) | |
1460 | == IRQ_HANDLED) | |
1461 | res = IRQ_HANDLED; | |
1462 | } | |
1463 | } | |
1464 | irq_msk >>= 4; | |
1465 | phy_no++; | |
1466 | } | |
1467 | ||
1468 | return res; | |
1469 | } | |
1470 | ||
4a6125c5 XT |
1471 | static const struct hisi_sas_hw_error port_axi_error[] = { |
1472 | { | |
1473 | .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), | |
1474 | .msg = "dma_tx_axi_wr_err", | |
1475 | }, | |
1476 | { | |
1477 | .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), | |
1478 | .msg = "dma_tx_axi_rd_err", | |
1479 | }, | |
1480 | { | |
1481 | .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), | |
1482 | .msg = "dma_rx_axi_wr_err", | |
1483 | }, | |
1484 | { | |
1485 | .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), | |
1486 | .msg = "dma_rx_axi_rd_err", | |
1487 | }, | |
1488 | }; | |
1489 | ||
cdb76c15 | 1490 | static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
54edeee1 | 1491 | { |
cdb76c15 XT |
1492 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); |
1493 | u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); | |
54edeee1 | 1494 | struct device *dev = hisi_hba->dev; |
cdb76c15 XT |
1495 | int i; |
1496 | ||
1497 | irq_value &= ~irq_msk; | |
1498 | if (!irq_value) | |
1499 | return; | |
1500 | ||
1501 | for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { | |
1502 | const struct hisi_sas_hw_error *error = &port_axi_error[i]; | |
1503 | ||
1504 | if (!(irq_value & error->irq_msk)) | |
1505 | continue; | |
1506 | ||
1507 | dev_err(dev, "%s error (phy%d 0x%x) found!\n", | |
1508 | error->msg, phy_no, irq_value); | |
1509 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
1510 | } | |
1511 | ||
1512 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); | |
1513 | } | |
1514 | ||
1515 | static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) | |
1516 | { | |
1517 | u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); | |
1518 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); | |
1519 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
70230be3 | 1520 | struct pci_dev *pci_dev = hisi_hba->pci_dev; |
cdb76c15 XT |
1521 | struct device *dev = hisi_hba->dev; |
1522 | ||
1523 | irq_value &= ~irq_msk; | |
1524 | if (!irq_value) | |
1525 | return; | |
1526 | ||
1527 | if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { | |
1528 | dev_warn(dev, "phy%d identify timeout\n", phy_no); | |
1529 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1530 | } | |
1531 | ||
1532 | if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { | |
1533 | u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1534 | STP_LINK_TIMEOUT_STATE); | |
1535 | ||
1536 | dev_warn(dev, "phy%d stp link timeout (0x%x)\n", | |
1537 | phy_no, reg_value); | |
1538 | if (reg_value & BIT(4)) | |
1539 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1540 | } | |
1541 | ||
cdb76c15 XT |
1542 | if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && |
1543 | (pci_dev->revision == 0x20)) { | |
1544 | u32 reg_value; | |
1545 | int rc; | |
1546 | ||
1547 | rc = hisi_sas_read32_poll_timeout_atomic( | |
1548 | HILINK_ERR_DFX, reg_value, | |
1549 | !((reg_value >> 8) & BIT(phy_no)), | |
1550 | 1000, 10000); | |
17d59a57 XT |
1551 | if (rc) |
1552 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
cdb76c15 | 1553 | } |
17d59a57 XT |
1554 | |
1555 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); | |
cdb76c15 XT |
1556 | } |
1557 | ||
1558 | static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) | |
1559 | { | |
1560 | struct hisi_hba *hisi_hba = p; | |
ab39f052 | 1561 | u32 irq_msk; |
54edeee1 XC |
1562 | int phy_no = 0; |
1563 | ||
54edeee1 XC |
1564 | irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) |
1565 | & 0xeeeeeeee; | |
1566 | ||
1567 | while (irq_msk) { | |
1568 | u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1569 | CHL_INT0); | |
066312f6 | 1570 | |
cdb76c15 XT |
1571 | if (irq_msk & (4 << (phy_no * 4))) |
1572 | handle_chl_int1_v3_hw(hisi_hba, phy_no); | |
066312f6 | 1573 | |
cdb76c15 XT |
1574 | if (irq_msk & (8 << (phy_no * 4))) |
1575 | handle_chl_int2_v3_hw(hisi_hba, phy_no); | |
54edeee1 XC |
1576 | |
1577 | if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { | |
1578 | hisi_sas_phy_write32(hisi_hba, phy_no, | |
1579 | CHL_INT0, irq_value0 | |
4f73575a | 1580 | & (~CHL_INT0_SL_RX_BCST_ACK_MSK) |
54edeee1 XC |
1581 | & (~CHL_INT0_SL_PHY_ENABLE_MSK) |
1582 | & (~CHL_INT0_NOT_RDY_MSK)); | |
1583 | } | |
1584 | irq_msk &= ~(0xe << (phy_no * 4)); | |
1585 | phy_no++; | |
1586 | } | |
1587 | ||
54edeee1 XC |
1588 | return IRQ_HANDLED; |
1589 | } | |
1590 | ||
fa231408 XT |
1591 | static const struct hisi_sas_hw_error axi_error[] = { |
1592 | { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, | |
1593 | { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, | |
1594 | { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, | |
1595 | { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, | |
1596 | { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, | |
1597 | { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, | |
1598 | { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, | |
1599 | { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, | |
1600 | {}, | |
1601 | }; | |
1602 | ||
1603 | static const struct hisi_sas_hw_error fifo_error[] = { | |
1604 | { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, | |
1605 | { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, | |
1606 | { .msk = BIT(10), .msg = "GETDQE_FIFO" }, | |
1607 | { .msk = BIT(11), .msg = "CMDP_FIFO" }, | |
1608 | { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, | |
1609 | {}, | |
1610 | }; | |
1611 | ||
1612 | static const struct hisi_sas_hw_error fatal_axi_error[] = { | |
1613 | { | |
1614 | .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), | |
1615 | .msg = "write pointer and depth", | |
1616 | }, | |
1617 | { | |
1618 | .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), | |
1619 | .msg = "iptt no match slot", | |
1620 | }, | |
1621 | { | |
1622 | .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), | |
1623 | .msg = "read pointer and depth", | |
1624 | }, | |
1625 | { | |
1626 | .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), | |
1627 | .reg = HGC_AXI_FIFO_ERR_INFO, | |
1628 | .sub = axi_error, | |
1629 | }, | |
1630 | { | |
1631 | .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), | |
1632 | .reg = HGC_AXI_FIFO_ERR_INFO, | |
1633 | .sub = fifo_error, | |
1634 | }, | |
1635 | { | |
1636 | .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), | |
1637 | .msg = "LM add/fetch list", | |
1638 | }, | |
1639 | { | |
1640 | .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), | |
1641 | .msg = "SAS_HGC_ABT fetch LM list", | |
1642 | }, | |
1643 | }; | |
1644 | ||
1645 | static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) | |
1646 | { | |
1647 | u32 irq_value, irq_msk; | |
1648 | struct hisi_hba *hisi_hba = p; | |
1649 | struct device *dev = hisi_hba->dev; | |
9a31daaf | 1650 | struct pci_dev *pdev = hisi_hba->pci_dev; |
fa231408 XT |
1651 | int i; |
1652 | ||
1653 | irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); | |
1654 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); | |
1655 | ||
1656 | irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); | |
c13c7ac5 | 1657 | irq_value &= ~irq_msk; |
fa231408 XT |
1658 | |
1659 | for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { | |
1660 | const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; | |
1661 | ||
1662 | if (!(irq_value & error->irq_msk)) | |
1663 | continue; | |
1664 | ||
1665 | if (error->sub) { | |
1666 | const struct hisi_sas_hw_error *sub = error->sub; | |
1667 | u32 err_value = hisi_sas_read32(hisi_hba, error->reg); | |
1668 | ||
1669 | for (; sub->msk || sub->msg; sub++) { | |
1670 | if (!(err_value & sub->msk)) | |
1671 | continue; | |
1672 | ||
081a1608 | 1673 | dev_err(dev, "%s error (0x%x) found!\n", |
fa231408 XT |
1674 | sub->msg, irq_value); |
1675 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
1676 | } | |
1677 | } else { | |
081a1608 | 1678 | dev_err(dev, "%s error (0x%x) found!\n", |
fa231408 XT |
1679 | error->msg, irq_value); |
1680 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
1681 | } | |
9a31daaf XC |
1682 | |
1683 | if (pdev->revision < 0x21) { | |
1684 | u32 reg_val; | |
1685 | ||
1686 | reg_val = hisi_sas_read32(hisi_hba, | |
1687 | AXI_MASTER_CFG_BASE + | |
1688 | AM_CTRL_GLOBAL); | |
1689 | reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; | |
1690 | hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + | |
1691 | AM_CTRL_GLOBAL, reg_val); | |
1692 | } | |
fa231408 XT |
1693 | } |
1694 | ||
1695 | if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { | |
1696 | u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); | |
1697 | u32 dev_id = reg_val & ITCT_DEV_MSK; | |
1698 | struct hisi_sas_device *sas_dev = | |
1699 | &hisi_hba->devices[dev_id]; | |
1700 | ||
1701 | hisi_sas_write32(hisi_hba, ITCT_CLR, 0); | |
1702 | dev_dbg(dev, "clear ITCT ok\n"); | |
1703 | complete(sas_dev->completion); | |
1704 | } | |
1705 | ||
1706 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); | |
1707 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); | |
1708 | ||
1709 | return IRQ_HANDLED; | |
1710 | } | |
1711 | ||
60b4a5ee XC |
1712 | static void |
1713 | slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, | |
1714 | struct hisi_sas_slot *slot) | |
1715 | { | |
1716 | struct task_status_struct *ts = &task->task_status; | |
1717 | struct hisi_sas_complete_v3_hdr *complete_queue = | |
1718 | hisi_hba->complete_hdr[slot->cmplt_queue]; | |
1719 | struct hisi_sas_complete_v3_hdr *complete_hdr = | |
1720 | &complete_queue[slot->cmplt_queue_slot]; | |
f557e32c XT |
1721 | struct hisi_sas_err_record_v3 *record = |
1722 | hisi_sas_status_buf_addr_mem(slot); | |
b8438c40 JG |
1723 | u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); |
1724 | u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); | |
1725 | u32 dw3 = le32_to_cpu(complete_hdr->dw3); | |
60b4a5ee XC |
1726 | |
1727 | switch (task->task_proto) { | |
1728 | case SAS_PROTOCOL_SSP: | |
1729 | if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { | |
1730 | ts->residual = trans_tx_fail_type; | |
1731 | ts->stat = SAS_DATA_UNDERRUN; | |
b8438c40 | 1732 | } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { |
60b4a5ee XC |
1733 | ts->stat = SAS_QUEUE_FULL; |
1734 | slot->abort = 1; | |
1735 | } else { | |
1736 | ts->stat = SAS_OPEN_REJECT; | |
1737 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1738 | } | |
1739 | break; | |
1740 | case SAS_PROTOCOL_SATA: | |
1741 | case SAS_PROTOCOL_STP: | |
1742 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: | |
1743 | if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { | |
1744 | ts->residual = trans_tx_fail_type; | |
1745 | ts->stat = SAS_DATA_UNDERRUN; | |
b8438c40 | 1746 | } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { |
60b4a5ee XC |
1747 | ts->stat = SAS_PHY_DOWN; |
1748 | slot->abort = 1; | |
1749 | } else { | |
1750 | ts->stat = SAS_OPEN_REJECT; | |
1751 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1752 | } | |
1753 | hisi_sas_sata_done(task, slot); | |
1754 | break; | |
1755 | case SAS_PROTOCOL_SMP: | |
1756 | ts->stat = SAM_STAT_CHECK_CONDITION; | |
1757 | break; | |
1758 | default: | |
1759 | break; | |
1760 | } | |
1761 | } | |
1762 | ||
1763 | static int | |
1764 | slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) | |
1765 | { | |
1766 | struct sas_task *task = slot->task; | |
1767 | struct hisi_sas_device *sas_dev; | |
1768 | struct device *dev = hisi_hba->dev; | |
1769 | struct task_status_struct *ts; | |
1770 | struct domain_device *device; | |
68e6bace | 1771 | struct sas_ha_struct *ha; |
60b4a5ee XC |
1772 | enum exec_status sts; |
1773 | struct hisi_sas_complete_v3_hdr *complete_queue = | |
1774 | hisi_hba->complete_hdr[slot->cmplt_queue]; | |
1775 | struct hisi_sas_complete_v3_hdr *complete_hdr = | |
1776 | &complete_queue[slot->cmplt_queue_slot]; | |
60b4a5ee | 1777 | unsigned long flags; |
68e6bace | 1778 | bool is_internal = slot->is_internal; |
b8438c40 | 1779 | u32 dw0, dw1, dw3; |
60b4a5ee XC |
1780 | |
1781 | if (unlikely(!task || !task->lldd_task || !task->dev)) | |
1782 | return -EINVAL; | |
1783 | ||
1784 | ts = &task->task_status; | |
1785 | device = task->dev; | |
68e6bace | 1786 | ha = device->port->ha; |
60b4a5ee XC |
1787 | sas_dev = device->lldd_dev; |
1788 | ||
1789 | spin_lock_irqsave(&task->task_state_lock, flags); | |
60b4a5ee XC |
1790 | task->task_state_flags &= |
1791 | ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); | |
1792 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
1793 | ||
1794 | memset(ts, 0, sizeof(*ts)); | |
1795 | ts->resp = SAS_TASK_COMPLETE; | |
60b4a5ee XC |
1796 | |
1797 | if (unlikely(!sas_dev)) { | |
1798 | dev_dbg(dev, "slot complete: port has not device\n"); | |
1799 | ts->stat = SAS_PHY_DOWN; | |
1800 | goto out; | |
1801 | } | |
1802 | ||
b8438c40 JG |
1803 | dw0 = le32_to_cpu(complete_hdr->dw0); |
1804 | dw1 = le32_to_cpu(complete_hdr->dw1); | |
1805 | dw3 = le32_to_cpu(complete_hdr->dw3); | |
1806 | ||
60b4a5ee XC |
1807 | /* |
1808 | * Use SAS+TMF status codes | |
1809 | */ | |
b8438c40 | 1810 | switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { |
60b4a5ee XC |
1811 | case STAT_IO_ABORTED: |
1812 | /* this IO has been aborted by abort command */ | |
1813 | ts->stat = SAS_ABORTED_TASK; | |
1814 | goto out; | |
1815 | case STAT_IO_COMPLETE: | |
1816 | /* internal abort command complete */ | |
1817 | ts->stat = TMF_RESP_FUNC_SUCC; | |
1818 | goto out; | |
1819 | case STAT_IO_NO_DEVICE: | |
1820 | ts->stat = TMF_RESP_FUNC_COMPLETE; | |
1821 | goto out; | |
1822 | case STAT_IO_NOT_VALID: | |
1823 | /* | |
1824 | * abort single IO, the controller can't find the IO | |
1825 | */ | |
1826 | ts->stat = TMF_RESP_FUNC_FAILED; | |
1827 | goto out; | |
1828 | default: | |
1829 | break; | |
1830 | } | |
1831 | ||
1832 | /* check for erroneous completion */ | |
b8438c40 | 1833 | if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { |
081a1608 XC |
1834 | u32 *error_info = hisi_sas_status_buf_addr_mem(slot); |
1835 | ||
60b4a5ee | 1836 | slot_err_v3_hw(hisi_hba, task, slot); |
081a1608 | 1837 | if (ts->stat != SAS_DATA_UNDERRUN) |
ab2d8bd6 | 1838 | dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " |
081a1608 XC |
1839 | "CQ hdr: 0x%x 0x%x 0x%x 0x%x " |
1840 | "Error info: 0x%x 0x%x 0x%x 0x%x\n", | |
ab2d8bd6 | 1841 | slot->idx, task, sas_dev->device_id, |
b8438c40 | 1842 | dw0, dw1, complete_hdr->act, dw3, |
081a1608 XC |
1843 | error_info[0], error_info[1], |
1844 | error_info[2], error_info[3]); | |
60b4a5ee XC |
1845 | if (unlikely(slot->abort)) |
1846 | return ts->stat; | |
1847 | goto out; | |
1848 | } | |
1849 | ||
1850 | switch (task->task_proto) { | |
1851 | case SAS_PROTOCOL_SSP: { | |
f557e32c XT |
1852 | struct ssp_response_iu *iu = |
1853 | hisi_sas_status_buf_addr_mem(slot) + | |
60b4a5ee XC |
1854 | sizeof(struct hisi_sas_err_record); |
1855 | ||
1856 | sas_ssp_task_response(dev, task, iu); | |
1857 | break; | |
1858 | } | |
1859 | case SAS_PROTOCOL_SMP: { | |
1860 | struct scatterlist *sg_resp = &task->smp_task.smp_resp; | |
1861 | void *to; | |
1862 | ||
1863 | ts->stat = SAM_STAT_GOOD; | |
1864 | to = kmap_atomic(sg_page(sg_resp)); | |
1865 | ||
1866 | dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, | |
1867 | DMA_FROM_DEVICE); | |
1868 | dma_unmap_sg(dev, &task->smp_task.smp_req, 1, | |
1869 | DMA_TO_DEVICE); | |
1870 | memcpy(to + sg_resp->offset, | |
f557e32c | 1871 | hisi_sas_status_buf_addr_mem(slot) + |
60b4a5ee XC |
1872 | sizeof(struct hisi_sas_err_record), |
1873 | sg_dma_len(sg_resp)); | |
1874 | kunmap_atomic(to); | |
1875 | break; | |
1876 | } | |
1877 | case SAS_PROTOCOL_SATA: | |
1878 | case SAS_PROTOCOL_STP: | |
1879 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: | |
1880 | ts->stat = SAM_STAT_GOOD; | |
1881 | hisi_sas_sata_done(task, slot); | |
1882 | break; | |
1883 | default: | |
1884 | ts->stat = SAM_STAT_CHECK_CONDITION; | |
1885 | break; | |
1886 | } | |
1887 | ||
1888 | if (!slot->port->port_attached) { | |
081a1608 | 1889 | dev_warn(dev, "slot complete: port %d has removed\n", |
60b4a5ee XC |
1890 | slot->port->sas_port.id); |
1891 | ts->stat = SAS_PHY_DOWN; | |
1892 | } | |
1893 | ||
1894 | out: | |
52ed2bba | 1895 | sts = ts->stat; |
60b4a5ee | 1896 | spin_lock_irqsave(&task->task_state_lock, flags); |
52ed2bba XC |
1897 | if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { |
1898 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
1899 | dev_info(dev, "slot complete: task(%p) aborted\n", task); | |
1900 | return SAS_ABORTED_TASK; | |
1901 | } | |
60b4a5ee XC |
1902 | task->task_state_flags |= SAS_TASK_STATE_DONE; |
1903 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
bb03e124 | 1904 | hisi_sas_slot_task_free(hisi_hba, task, slot); |
60b4a5ee | 1905 | |
68e6bace XC |
1906 | if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { |
1907 | spin_lock_irqsave(&device->done_lock, flags); | |
1908 | if (test_bit(SAS_HA_FROZEN, &ha->state)) { | |
1909 | spin_unlock_irqrestore(&device->done_lock, flags); | |
1910 | dev_info(dev, "slot complete: task(%p) ignored\n ", | |
1911 | task); | |
1912 | return sts; | |
1913 | } | |
1914 | spin_unlock_irqrestore(&device->done_lock, flags); | |
1915 | } | |
1916 | ||
60b4a5ee XC |
1917 | if (task->task_done) |
1918 | task->task_done(task); | |
1919 | ||
1920 | return sts; | |
1921 | } | |
1922 | ||
1923 | static void cq_tasklet_v3_hw(unsigned long val) | |
1924 | { | |
1925 | struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; | |
1926 | struct hisi_hba *hisi_hba = cq->hisi_hba; | |
1927 | struct hisi_sas_slot *slot; | |
60b4a5ee | 1928 | struct hisi_sas_complete_v3_hdr *complete_queue; |
ee076d5b | 1929 | u32 rd_point = cq->rd_point, wr_point; |
60b4a5ee | 1930 | int queue = cq->id; |
60b4a5ee XC |
1931 | |
1932 | complete_queue = hisi_hba->complete_hdr[queue]; | |
1933 | ||
60b4a5ee XC |
1934 | wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + |
1935 | (0x14 * queue)); | |
1936 | ||
1937 | while (rd_point != wr_point) { | |
1938 | struct hisi_sas_complete_v3_hdr *complete_hdr; | |
e812cf8c | 1939 | struct device *dev = hisi_hba->dev; |
b8438c40 | 1940 | u32 dw1; |
60b4a5ee XC |
1941 | int iptt; |
1942 | ||
1943 | complete_hdr = &complete_queue[rd_point]; | |
b8438c40 | 1944 | dw1 = le32_to_cpu(complete_hdr->dw1); |
60b4a5ee | 1945 | |
b8438c40 | 1946 | iptt = dw1 & CMPLT_HDR_IPTT_MSK; |
e812cf8c XT |
1947 | if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { |
1948 | slot = &hisi_hba->slot_info[iptt]; | |
1949 | slot->cmplt_queue_slot = rd_point; | |
1950 | slot->cmplt_queue = queue; | |
1951 | slot_complete_v3_hw(hisi_hba, slot); | |
1952 | } else | |
1953 | dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); | |
60b4a5ee XC |
1954 | |
1955 | if (++rd_point >= HISI_SAS_QUEUE_SLOTS) | |
1956 | rd_point = 0; | |
1957 | } | |
1958 | ||
1959 | /* update rd_point */ | |
1960 | cq->rd_point = rd_point; | |
1961 | hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); | |
60b4a5ee XC |
1962 | } |
1963 | ||
1964 | static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) | |
1965 | { | |
1966 | struct hisi_sas_cq *cq = p; | |
1967 | struct hisi_hba *hisi_hba = cq->hisi_hba; | |
1968 | int queue = cq->id; | |
1969 | ||
1970 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); | |
1971 | ||
1972 | tasklet_schedule(&cq->tasklet); | |
1973 | ||
1974 | return IRQ_HANDLED; | |
1975 | } | |
1976 | ||
54edeee1 XC |
1977 | static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) |
1978 | { | |
1979 | struct device *dev = hisi_hba->dev; | |
1980 | struct pci_dev *pdev = hisi_hba->pci_dev; | |
1981 | int vectors, rc; | |
60b4a5ee | 1982 | int i, k; |
54edeee1 XC |
1983 | int max_msi = HISI_SAS_MSI_COUNT_V3_HW; |
1984 | ||
1985 | vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, | |
1986 | max_msi, PCI_IRQ_MSI); | |
1987 | if (vectors < max_msi) { | |
1988 | dev_err(dev, "could not allocate all msi (%d)\n", vectors); | |
1989 | return -ENOENT; | |
1990 | } | |
1991 | ||
1992 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), | |
1993 | int_phy_up_down_bcast_v3_hw, 0, | |
1994 | DRV_NAME " phy", hisi_hba); | |
1995 | if (rc) { | |
1996 | dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); | |
1997 | rc = -ENOENT; | |
1998 | goto free_irq_vectors; | |
1999 | } | |
2000 | ||
2001 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), | |
2002 | int_chnl_int_v3_hw, 0, | |
2003 | DRV_NAME " channel", hisi_hba); | |
2004 | if (rc) { | |
2005 | dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); | |
2006 | rc = -ENOENT; | |
2007 | goto free_phy_irq; | |
2008 | } | |
2009 | ||
fa231408 XT |
2010 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), |
2011 | fatal_axi_int_v3_hw, 0, | |
2012 | DRV_NAME " fatal", hisi_hba); | |
2013 | if (rc) { | |
2014 | dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); | |
2015 | rc = -ENOENT; | |
2016 | goto free_chnl_interrupt; | |
2017 | } | |
2018 | ||
60b4a5ee XC |
2019 | /* Init tasklets for cq only */ |
2020 | for (i = 0; i < hisi_hba->queue_count; i++) { | |
2021 | struct hisi_sas_cq *cq = &hisi_hba->cq[i]; | |
2022 | struct tasklet_struct *t = &cq->tasklet; | |
6cc8d8f2 XC |
2023 | int nr = hisi_sas_intr_conv ? 16 : 16 + i; |
2024 | unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; | |
60b4a5ee | 2025 | |
6cc8d8f2 XC |
2026 | rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), |
2027 | cq_interrupt_v3_hw, irqflags, | |
2028 | DRV_NAME " cq", cq); | |
60b4a5ee XC |
2029 | if (rc) { |
2030 | dev_err(dev, | |
2031 | "could not request cq%d interrupt, rc=%d\n", | |
2032 | i, rc); | |
2033 | rc = -ENOENT; | |
2034 | goto free_cq_irqs; | |
2035 | } | |
2036 | ||
2037 | tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); | |
2038 | } | |
54edeee1 XC |
2039 | |
2040 | return 0; | |
2041 | ||
60b4a5ee XC |
2042 | free_cq_irqs: |
2043 | for (k = 0; k < i; k++) { | |
2044 | struct hisi_sas_cq *cq = &hisi_hba->cq[k]; | |
6cc8d8f2 | 2045 | int nr = hisi_sas_intr_conv ? 16 : 16 + k; |
60b4a5ee | 2046 | |
6cc8d8f2 | 2047 | free_irq(pci_irq_vector(pdev, nr), cq); |
60b4a5ee | 2048 | } |
fa231408 XT |
2049 | free_irq(pci_irq_vector(pdev, 11), hisi_hba); |
2050 | free_chnl_interrupt: | |
60b4a5ee | 2051 | free_irq(pci_irq_vector(pdev, 2), hisi_hba); |
54edeee1 XC |
2052 | free_phy_irq: |
2053 | free_irq(pci_irq_vector(pdev, 1), hisi_hba); | |
2054 | free_irq_vectors: | |
2055 | pci_free_irq_vectors(pdev); | |
2056 | return rc; | |
2057 | } | |
2058 | ||
c94d8ca2 XC |
2059 | static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) |
2060 | { | |
2061 | int rc; | |
2062 | ||
2063 | rc = hw_init_v3_hw(hisi_hba); | |
2064 | if (rc) | |
2065 | return rc; | |
2066 | ||
54edeee1 XC |
2067 | rc = interrupt_init_v3_hw(hisi_hba); |
2068 | if (rc) | |
2069 | return rc; | |
2070 | ||
c94d8ca2 XC |
2071 | return 0; |
2072 | } | |
2073 | ||
2400620c XC |
2074 | static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, |
2075 | struct sas_phy_linkrates *r) | |
2076 | { | |
5193a533 | 2077 | enum sas_linkrate max = r->maximum_linkrate; |
f385b4ff | 2078 | u32 prog_phy_link_rate = 0x800; |
2400620c | 2079 | |
f385b4ff | 2080 | prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); |
2400620c | 2081 | hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, |
5193a533 | 2082 | prog_phy_link_rate); |
2400620c XC |
2083 | } |
2084 | ||
a25d0d3d XC |
2085 | static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) |
2086 | { | |
2087 | struct pci_dev *pdev = hisi_hba->pci_dev; | |
2088 | int i; | |
2089 | ||
2090 | synchronize_irq(pci_irq_vector(pdev, 1)); | |
2091 | synchronize_irq(pci_irq_vector(pdev, 2)); | |
2092 | synchronize_irq(pci_irq_vector(pdev, 11)); | |
2093 | for (i = 0; i < hisi_hba->queue_count; i++) { | |
2094 | hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); | |
2095 | synchronize_irq(pci_irq_vector(pdev, i + 16)); | |
2096 | } | |
2097 | ||
2098 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); | |
2099 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); | |
2100 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); | |
2101 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); | |
2102 | ||
2103 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
2104 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); | |
2105 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); | |
2106 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); | |
2107 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); | |
2108 | hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); | |
2109 | } | |
2110 | } | |
2111 | ||
2112 | static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) | |
2113 | { | |
2114 | return hisi_sas_read32(hisi_hba, PHY_STATE); | |
2115 | } | |
2116 | ||
ffc8f149 XT |
2117 | static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
2118 | { | |
2119 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
2120 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
2121 | struct sas_phy *sphy = sas_phy->phy; | |
2122 | u32 reg_value; | |
2123 | ||
2124 | /* loss dword sync */ | |
2125 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); | |
2126 | sphy->loss_of_dword_sync_count += reg_value; | |
2127 | ||
2128 | /* phy reset problem */ | |
2129 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); | |
2130 | sphy->phy_reset_problem_count += reg_value; | |
2131 | ||
2132 | /* invalid dword */ | |
2133 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); | |
2134 | sphy->invalid_dword_count += reg_value; | |
2135 | ||
2136 | /* disparity err */ | |
2137 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); | |
2138 | sphy->running_disparity_error_count += reg_value; | |
2139 | ||
2140 | } | |
2141 | ||
1d51757d | 2142 | static int disable_host_v3_hw(struct hisi_hba *hisi_hba) |
a25d0d3d XC |
2143 | { |
2144 | struct device *dev = hisi_hba->dev; | |
1d51757d | 2145 | u32 status, reg_val; |
a25d0d3d | 2146 | int rc; |
a25d0d3d XC |
2147 | |
2148 | interrupt_disable_v3_hw(hisi_hba); | |
2149 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); | |
571295f8 | 2150 | hisi_sas_kill_tasklets(hisi_hba); |
a25d0d3d XC |
2151 | |
2152 | hisi_sas_stop_phys(hisi_hba); | |
2153 | ||
2154 | mdelay(10); | |
2155 | ||
1d51757d XT |
2156 | reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + |
2157 | AM_CTRL_GLOBAL); | |
2158 | reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; | |
2159 | hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + | |
2160 | AM_CTRL_GLOBAL, reg_val); | |
a25d0d3d XC |
2161 | |
2162 | /* wait until bus idle */ | |
70bfdcae JG |
2163 | rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + |
2164 | AM_CURR_TRANS_RETURN, status, | |
2165 | status == 0x3, 10, 100); | |
a25d0d3d | 2166 | if (rc) { |
1d51757d XT |
2167 | dev_err(dev, "axi bus is not idle, rc=%d\n", rc); |
2168 | return rc; | |
2169 | } | |
2170 | ||
2171 | return 0; | |
2172 | } | |
2173 | ||
2174 | static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) | |
2175 | { | |
2176 | struct device *dev = hisi_hba->dev; | |
2177 | int rc; | |
2178 | ||
2179 | rc = disable_host_v3_hw(hisi_hba); | |
2180 | if (rc) { | |
2181 | dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); | |
a25d0d3d XC |
2182 | return rc; |
2183 | } | |
2184 | ||
2185 | hisi_sas_init_mem(hisi_hba); | |
2186 | ||
2187 | return hw_init_v3_hw(hisi_hba); | |
2188 | } | |
2189 | ||
e24fe507 XT |
2190 | static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, |
2191 | u8 reg_index, u8 reg_count, u8 *write_data) | |
2192 | { | |
2193 | struct device *dev = hisi_hba->dev; | |
2194 | u32 *data = (u32 *)write_data; | |
2195 | int i; | |
2196 | ||
2197 | switch (reg_type) { | |
2198 | case SAS_GPIO_REG_TX: | |
2199 | if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { | |
2200 | dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", | |
2201 | reg_index, reg_index + reg_count - 1); | |
2202 | return -EINVAL; | |
2203 | } | |
2204 | ||
2205 | for (i = 0; i < reg_count; i++) | |
2206 | hisi_sas_write32(hisi_hba, | |
2207 | SAS_GPIO_TX_0_1 + (reg_index + i) * 4, | |
2208 | data[i]); | |
2209 | break; | |
2210 | default: | |
2211 | dev_err(dev, "write gpio: unsupported or bad reg type %d\n", | |
2212 | reg_type); | |
2213 | return -EINVAL; | |
2214 | } | |
2215 | ||
2216 | return 0; | |
2217 | } | |
2218 | ||
1a7068b3 XT |
2219 | static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, |
2220 | int delay_ms, int timeout_ms) | |
2221 | { | |
2222 | struct device *dev = hisi_hba->dev; | |
2223 | int entries, entries_old = 0, time; | |
2224 | ||
2225 | for (time = 0; time < timeout_ms; time += delay_ms) { | |
2226 | entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); | |
2227 | if (entries == entries_old) | |
2228 | break; | |
2229 | ||
2230 | entries_old = entries; | |
2231 | msleep(delay_ms); | |
2232 | } | |
2233 | ||
2234 | dev_dbg(dev, "wait commands complete %dms\n", time); | |
2235 | } | |
2236 | ||
6cc8d8f2 XC |
2237 | static ssize_t intr_conv_v3_hw_show(struct device *dev, |
2238 | struct device_attribute *attr, char *buf) | |
2239 | { | |
2240 | return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); | |
2241 | } | |
2242 | static DEVICE_ATTR_RO(intr_conv_v3_hw); | |
2243 | ||
3e45e10b XC |
2244 | static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) |
2245 | { | |
2246 | /* config those registers between enable and disable PHYs */ | |
2247 | hisi_sas_stop_phys(hisi_hba); | |
2248 | ||
2249 | if (hisi_hba->intr_coal_ticks == 0 || | |
2250 | hisi_hba->intr_coal_count == 0) { | |
2251 | hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); | |
2252 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); | |
2253 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); | |
2254 | } else { | |
2255 | hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); | |
2256 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, | |
2257 | hisi_hba->intr_coal_ticks); | |
2258 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, | |
2259 | hisi_hba->intr_coal_count); | |
2260 | } | |
2261 | phys_init_v3_hw(hisi_hba); | |
2262 | } | |
2263 | ||
2264 | static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, | |
2265 | struct device_attribute *attr, | |
2266 | char *buf) | |
2267 | { | |
2268 | struct Scsi_Host *shost = class_to_shost(dev); | |
2269 | struct hisi_hba *hisi_hba = shost_priv(shost); | |
2270 | ||
2271 | return scnprintf(buf, PAGE_SIZE, "%u\n", | |
2272 | hisi_hba->intr_coal_ticks); | |
2273 | } | |
2274 | ||
2275 | static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, | |
2276 | struct device_attribute *attr, | |
2277 | const char *buf, size_t count) | |
2278 | { | |
2279 | struct Scsi_Host *shost = class_to_shost(dev); | |
2280 | struct hisi_hba *hisi_hba = shost_priv(shost); | |
2281 | u32 intr_coal_ticks; | |
2282 | int ret; | |
2283 | ||
2284 | ret = kstrtou32(buf, 10, &intr_coal_ticks); | |
2285 | if (ret) { | |
2286 | dev_err(dev, "Input data of interrupt coalesce unmatch\n"); | |
2287 | return -EINVAL; | |
2288 | } | |
2289 | ||
2290 | if (intr_coal_ticks >= BIT(24)) { | |
2291 | dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); | |
2292 | return -EINVAL; | |
2293 | } | |
2294 | ||
2295 | hisi_hba->intr_coal_ticks = intr_coal_ticks; | |
2296 | ||
2297 | config_intr_coal_v3_hw(hisi_hba); | |
2298 | ||
2299 | return count; | |
2300 | } | |
2301 | static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); | |
2302 | ||
2303 | static ssize_t intr_coal_count_v3_hw_show(struct device *dev, | |
2304 | struct device_attribute | |
2305 | *attr, char *buf) | |
2306 | { | |
2307 | struct Scsi_Host *shost = class_to_shost(dev); | |
2308 | struct hisi_hba *hisi_hba = shost_priv(shost); | |
2309 | ||
2310 | return scnprintf(buf, PAGE_SIZE, "%u\n", | |
2311 | hisi_hba->intr_coal_count); | |
2312 | } | |
2313 | ||
2314 | static ssize_t intr_coal_count_v3_hw_store(struct device *dev, | |
2315 | struct device_attribute | |
2316 | *attr, const char *buf, size_t count) | |
2317 | { | |
2318 | struct Scsi_Host *shost = class_to_shost(dev); | |
2319 | struct hisi_hba *hisi_hba = shost_priv(shost); | |
2320 | u32 intr_coal_count; | |
2321 | int ret; | |
2322 | ||
2323 | ret = kstrtou32(buf, 10, &intr_coal_count); | |
2324 | if (ret) { | |
2325 | dev_err(dev, "Input data of interrupt coalesce unmatch\n"); | |
2326 | return -EINVAL; | |
2327 | } | |
2328 | ||
2329 | if (intr_coal_count >= BIT(8)) { | |
2330 | dev_err(dev, "intr_coal_count must be less than 2^8!\n"); | |
2331 | return -EINVAL; | |
2332 | } | |
2333 | ||
2334 | hisi_hba->intr_coal_count = intr_coal_count; | |
2335 | ||
2336 | config_intr_coal_v3_hw(hisi_hba); | |
2337 | ||
2338 | return count; | |
2339 | } | |
2340 | static DEVICE_ATTR_RW(intr_coal_count_v3_hw); | |
2341 | ||
b8438c40 | 2342 | static struct device_attribute *host_attrs_v3_hw[] = { |
4659b074 | 2343 | &dev_attr_phy_event_threshold, |
6cc8d8f2 | 2344 | &dev_attr_intr_conv_v3_hw, |
3e45e10b XC |
2345 | &dev_attr_intr_coal_ticks_v3_hw, |
2346 | &dev_attr_intr_coal_count_v3_hw, | |
4659b074 XC |
2347 | NULL |
2348 | }; | |
2349 | ||
b1793064 XC |
2350 | static struct scsi_host_template sht_v3_hw = { |
2351 | .name = DRV_NAME, | |
2352 | .module = THIS_MODULE, | |
2353 | .queuecommand = sas_queuecommand, | |
2354 | .target_alloc = sas_target_alloc, | |
2355 | .slave_configure = hisi_sas_slave_configure, | |
2356 | .scan_finished = hisi_sas_scan_finished, | |
2357 | .scan_start = hisi_sas_scan_start, | |
2358 | .change_queue_depth = sas_change_queue_depth, | |
2359 | .bios_param = sas_bios_param, | |
b1793064 | 2360 | .this_id = -1, |
3c42dba0 | 2361 | .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, |
b1793064 XC |
2362 | .max_sectors = SCSI_DEFAULT_MAX_SECTORS, |
2363 | .use_clustering = ENABLE_CLUSTERING, | |
2364 | .eh_device_reset_handler = sas_eh_device_reset_handler, | |
2365 | .eh_target_reset_handler = sas_eh_target_reset_handler, | |
2366 | .target_destroy = sas_target_destroy, | |
2367 | .ioctl = sas_ioctl, | |
4659b074 | 2368 | .shost_attrs = host_attrs_v3_hw, |
8041484f | 2369 | .tag_alloc_policy = BLK_TAG_ALLOC_RR, |
b1793064 XC |
2370 | }; |
2371 | ||
e21fe3a5 | 2372 | static const struct hisi_sas_hw hisi_sas_v3_hw = { |
c94d8ca2 | 2373 | .hw_init = hisi_sas_v3_init, |
182e7222 | 2374 | .setup_itct = setup_itct_v3_hw, |
c94d8ca2 | 2375 | .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, |
f771d3b0 | 2376 | .get_wideport_bitmap = get_wideport_bitmap_v3_hw, |
c94d8ca2 | 2377 | .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), |
f39943ee | 2378 | .clear_itct = clear_itct_v3_hw, |
a2b61737 | 2379 | .sl_notify_ssp = sl_notify_ssp_v3_hw, |
a2204723 | 2380 | .prep_ssp = prep_ssp_v3_hw, |
fa913de2 | 2381 | .prep_smp = prep_smp_v3_hw, |
ce60689e | 2382 | .prep_stp = prep_ata_v3_hw, |
4de0ca69 | 2383 | .prep_abort = prep_abort_v3_hw, |
a2204723 XC |
2384 | .get_free_slot = get_free_slot_v3_hw, |
2385 | .start_delivery = start_delivery_v3_hw, | |
2386 | .slot_complete = slot_complete_v3_hw, | |
3975f605 | 2387 | .phys_init = phys_init_v3_hw, |
1eb8eeac | 2388 | .phy_start = start_phy_v3_hw, |
402cd9f0 XC |
2389 | .phy_disable = disable_phy_v3_hw, |
2390 | .phy_hard_reset = phy_hard_reset_v3_hw, | |
2391 | .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, | |
2400620c | 2392 | .phy_set_linkrate = phy_set_linkrate_v3_hw, |
d30ff263 | 2393 | .dereg_device = dereg_device_v3_hw, |
a25d0d3d XC |
2394 | .soft_reset = soft_reset_v3_hw, |
2395 | .get_phys_state = get_phys_state_v3_hw, | |
ffc8f149 | 2396 | .get_events = phy_get_events_v3_hw, |
e24fe507 | 2397 | .write_gpio = write_gpio_v3_hw, |
1a7068b3 | 2398 | .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, |
e21fe3a5 JG |
2399 | }; |
2400 | ||
2401 | static struct Scsi_Host * | |
2402 | hisi_sas_shost_alloc_pci(struct pci_dev *pdev) | |
2403 | { | |
2404 | struct Scsi_Host *shost; | |
2405 | struct hisi_hba *hisi_hba; | |
2406 | struct device *dev = &pdev->dev; | |
2407 | ||
b1793064 | 2408 | shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); |
76aae5f6 JG |
2409 | if (!shost) { |
2410 | dev_err(dev, "shost alloc failed\n"); | |
2411 | return NULL; | |
2412 | } | |
e21fe3a5 JG |
2413 | hisi_hba = shost_priv(shost); |
2414 | ||
b4241f0f | 2415 | INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); |
e21fe3a5 JG |
2416 | hisi_hba->hw = &hisi_sas_v3_hw; |
2417 | hisi_hba->pci_dev = pdev; | |
2418 | hisi_hba->dev = dev; | |
2419 | hisi_hba->shost = shost; | |
2420 | SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; | |
2421 | ||
3e5d03c7 XC |
2422 | if (prot_mask & ~HISI_SAS_PROT_MASK) |
2423 | dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", | |
2424 | prot_mask); | |
2425 | else | |
2426 | hisi_hba->prot_mask = prot_mask; | |
2427 | ||
77570eed | 2428 | timer_setup(&hisi_hba->timer, NULL, 0); |
e21fe3a5 JG |
2429 | |
2430 | if (hisi_sas_get_fw_info(hisi_hba) < 0) | |
2431 | goto err_out; | |
2432 | ||
2433 | if (hisi_sas_alloc(hisi_hba, shost)) { | |
2434 | hisi_sas_free(hisi_hba); | |
2435 | goto err_out; | |
2436 | } | |
2437 | ||
2438 | return shost; | |
2439 | err_out: | |
76aae5f6 | 2440 | scsi_host_put(shost); |
e21fe3a5 JG |
2441 | dev_err(dev, "shost alloc failed\n"); |
2442 | return NULL; | |
2443 | } | |
2444 | ||
92f61e3b JG |
2445 | static int |
2446 | hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
2447 | { | |
e21fe3a5 JG |
2448 | struct Scsi_Host *shost; |
2449 | struct hisi_hba *hisi_hba; | |
2450 | struct device *dev = &pdev->dev; | |
2451 | struct asd_sas_phy **arr_phy; | |
2452 | struct asd_sas_port **arr_port; | |
2453 | struct sas_ha_struct *sha; | |
2454 | int rc, phy_nr, port_nr, i; | |
2455 | ||
2456 | rc = pci_enable_device(pdev); | |
2457 | if (rc) | |
2458 | goto err_out; | |
2459 | ||
2460 | pci_set_master(pdev); | |
2461 | ||
2462 | rc = pci_request_regions(pdev, DRV_NAME); | |
2463 | if (rc) | |
2464 | goto err_out_disable_device; | |
2465 | ||
745d4335 CH |
2466 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) || |
2467 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { | |
2468 | dev_err(dev, "No usable DMA addressing method\n"); | |
2469 | rc = -EIO; | |
2470 | goto err_out_regions; | |
e21fe3a5 JG |
2471 | } |
2472 | ||
2473 | shost = hisi_sas_shost_alloc_pci(pdev); | |
2474 | if (!shost) { | |
2475 | rc = -ENOMEM; | |
2476 | goto err_out_regions; | |
2477 | } | |
2478 | ||
2479 | sha = SHOST_TO_SAS_HA(shost); | |
2480 | hisi_hba = shost_priv(shost); | |
2481 | dev_set_drvdata(dev, sha); | |
2482 | ||
2483 | hisi_hba->regs = pcim_iomap(pdev, 5, 0); | |
2484 | if (!hisi_hba->regs) { | |
2485 | dev_err(dev, "cannot map register.\n"); | |
2486 | rc = -ENOMEM; | |
2487 | goto err_out_ha; | |
2488 | } | |
2489 | ||
2490 | phy_nr = port_nr = hisi_hba->n_phy; | |
2491 | ||
2492 | arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); | |
2493 | arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); | |
2494 | if (!arr_phy || !arr_port) { | |
2495 | rc = -ENOMEM; | |
2496 | goto err_out_ha; | |
2497 | } | |
2498 | ||
2499 | sha->sas_phy = arr_phy; | |
2500 | sha->sas_port = arr_port; | |
2501 | sha->core.shost = shost; | |
2502 | sha->lldd_ha = hisi_hba; | |
2503 | ||
2504 | shost->transportt = hisi_sas_stt; | |
2505 | shost->max_id = HISI_SAS_MAX_DEVICES; | |
2506 | shost->max_lun = ~0; | |
2507 | shost->max_channel = 1; | |
2508 | shost->max_cmd_len = 16; | |
8041484f XC |
2509 | shost->can_queue = hisi_hba->hw->max_command_entries - |
2510 | HISI_SAS_RESERVED_IPTT_CNT; | |
2511 | shost->cmd_per_lun = hisi_hba->hw->max_command_entries - | |
2512 | HISI_SAS_RESERVED_IPTT_CNT; | |
e21fe3a5 JG |
2513 | |
2514 | sha->sas_ha_name = DRV_NAME; | |
2515 | sha->dev = dev; | |
2516 | sha->lldd_module = THIS_MODULE; | |
2517 | sha->sas_addr = &hisi_hba->sas_addr[0]; | |
2518 | sha->num_phys = hisi_hba->n_phy; | |
2519 | sha->core.shost = hisi_hba->shost; | |
2520 | ||
2521 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
2522 | sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; | |
2523 | sha->sas_port[i] = &hisi_hba->port[i].sas_port; | |
2524 | } | |
2525 | ||
e21fe3a5 JG |
2526 | rc = scsi_add_host(shost, dev); |
2527 | if (rc) | |
2528 | goto err_out_ha; | |
2529 | ||
2530 | rc = sas_register_ha(sha); | |
2531 | if (rc) | |
2532 | goto err_out_register_ha; | |
2533 | ||
2534 | rc = hisi_hba->hw->hw_init(hisi_hba); | |
2535 | if (rc) | |
2536 | goto err_out_register_ha; | |
2537 | ||
3e5d03c7 XC |
2538 | if (hisi_hba->prot_mask) { |
2539 | dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", | |
2540 | prot_mask); | |
2541 | scsi_host_set_prot(hisi_hba->shost, prot_mask); | |
2542 | } | |
2543 | ||
e21fe3a5 JG |
2544 | scsi_scan_host(shost); |
2545 | ||
92f61e3b | 2546 | return 0; |
e21fe3a5 JG |
2547 | |
2548 | err_out_register_ha: | |
2549 | scsi_remove_host(shost); | |
2550 | err_out_ha: | |
76aae5f6 | 2551 | scsi_host_put(shost); |
e21fe3a5 JG |
2552 | err_out_regions: |
2553 | pci_release_regions(pdev); | |
2554 | err_out_disable_device: | |
2555 | pci_disable_device(pdev); | |
2556 | err_out: | |
2557 | return rc; | |
92f61e3b JG |
2558 | } |
2559 | ||
54edeee1 XC |
2560 | static void |
2561 | hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) | |
2562 | { | |
60b4a5ee XC |
2563 | int i; |
2564 | ||
54edeee1 XC |
2565 | free_irq(pci_irq_vector(pdev, 1), hisi_hba); |
2566 | free_irq(pci_irq_vector(pdev, 2), hisi_hba); | |
fa231408 | 2567 | free_irq(pci_irq_vector(pdev, 11), hisi_hba); |
60b4a5ee XC |
2568 | for (i = 0; i < hisi_hba->queue_count; i++) { |
2569 | struct hisi_sas_cq *cq = &hisi_hba->cq[i]; | |
6cc8d8f2 | 2570 | int nr = hisi_sas_intr_conv ? 16 : 16 + i; |
60b4a5ee | 2571 | |
6cc8d8f2 | 2572 | free_irq(pci_irq_vector(pdev, nr), cq); |
60b4a5ee | 2573 | } |
54edeee1 XC |
2574 | pci_free_irq_vectors(pdev); |
2575 | } | |
2576 | ||
92f61e3b JG |
2577 | static void hisi_sas_v3_remove(struct pci_dev *pdev) |
2578 | { | |
e21fe3a5 JG |
2579 | struct device *dev = &pdev->dev; |
2580 | struct sas_ha_struct *sha = dev_get_drvdata(dev); | |
2581 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
76aae5f6 | 2582 | struct Scsi_Host *shost = sha->core.shost; |
e21fe3a5 | 2583 | |
a417a9c1 XC |
2584 | if (timer_pending(&hisi_hba->timer)) |
2585 | del_timer(&hisi_hba->timer); | |
2586 | ||
e21fe3a5 JG |
2587 | sas_unregister_ha(sha); |
2588 | sas_remove_host(sha->core.shost); | |
2589 | ||
54edeee1 | 2590 | hisi_sas_v3_destroy_irqs(pdev, hisi_hba); |
571295f8 | 2591 | hisi_sas_kill_tasklets(hisi_hba); |
e21fe3a5 JG |
2592 | pci_release_regions(pdev); |
2593 | pci_disable_device(pdev); | |
76aae5f6 JG |
2594 | hisi_sas_free(hisi_hba); |
2595 | scsi_host_put(shost); | |
92f61e3b JG |
2596 | } |
2597 | ||
56b72168 XT |
2598 | static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { |
2599 | { .irq_msk = BIT(19), .msg = "HILINK_INT" }, | |
2600 | { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, | |
2601 | { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, | |
2602 | { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, | |
2603 | { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, | |
2604 | { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, | |
2605 | { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, | |
2606 | { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, | |
2607 | { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, | |
2608 | { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, | |
2609 | { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, | |
2610 | { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, | |
2611 | { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, | |
2612 | }; | |
2613 | ||
2614 | static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { | |
2615 | { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, | |
2616 | { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, | |
2617 | { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, | |
2618 | { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, | |
2619 | { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, | |
2620 | { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, | |
2621 | { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, | |
2622 | { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, | |
2623 | { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, | |
2624 | { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, | |
2625 | { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, | |
2626 | { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, | |
2627 | { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, | |
2628 | { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, | |
2629 | { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, | |
2630 | { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, | |
2631 | { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, | |
2632 | { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, | |
2633 | { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, | |
2634 | { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, | |
2635 | { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, | |
2636 | { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, | |
2637 | { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, | |
2638 | { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, | |
2639 | { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, | |
2640 | { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, | |
2641 | { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, | |
2642 | { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, | |
2643 | { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, | |
2644 | { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, | |
2645 | { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, | |
2646 | }; | |
2647 | ||
c13c7ac5 XT |
2648 | static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { |
2649 | { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, | |
2650 | { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, | |
2651 | { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, | |
2652 | { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, | |
2653 | { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, | |
2654 | { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, | |
2655 | { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, | |
2656 | { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, | |
2657 | { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, | |
2658 | { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, | |
2659 | { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, | |
2660 | { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, | |
2661 | { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, | |
2662 | { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, | |
2663 | { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, | |
2664 | { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, | |
2665 | { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, | |
2666 | { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, | |
2667 | { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, | |
2668 | { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, | |
2669 | }; | |
2670 | ||
56b72168 XT |
2671 | static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) |
2672 | { | |
2673 | struct device *dev = hisi_hba->dev; | |
2674 | const struct hisi_sas_hw_error *ras_error; | |
2675 | bool need_reset = false; | |
2676 | u32 irq_value; | |
2677 | int i; | |
2678 | ||
2679 | irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); | |
2680 | for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { | |
2681 | ras_error = &sas_ras_intr0_nfe[i]; | |
2682 | if (ras_error->irq_msk & irq_value) { | |
2683 | dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", | |
2684 | ras_error->msg, irq_value); | |
2685 | need_reset = true; | |
2686 | } | |
2687 | } | |
2688 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); | |
2689 | ||
2690 | irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); | |
2691 | for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { | |
2692 | ras_error = &sas_ras_intr1_nfe[i]; | |
2693 | if (ras_error->irq_msk & irq_value) { | |
2694 | dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", | |
2695 | ras_error->msg, irq_value); | |
2696 | need_reset = true; | |
2697 | } | |
2698 | } | |
2699 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); | |
2700 | ||
c13c7ac5 XT |
2701 | irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); |
2702 | for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { | |
2703 | ras_error = &sas_ras_intr2_nfe[i]; | |
2704 | if (ras_error->irq_msk & irq_value) { | |
2705 | dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", | |
2706 | ras_error->msg, irq_value); | |
2707 | need_reset = true; | |
2708 | } | |
2709 | } | |
2710 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); | |
2711 | ||
56b72168 XT |
2712 | return need_reset; |
2713 | } | |
2714 | ||
2715 | static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, | |
2716 | pci_channel_state_t state) | |
2717 | { | |
2718 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2719 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2720 | struct device *dev = hisi_hba->dev; | |
2721 | ||
2722 | dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); | |
2723 | if (state == pci_channel_io_perm_failure) | |
2724 | return PCI_ERS_RESULT_DISCONNECT; | |
2725 | ||
2726 | if (process_non_fatal_error_v3_hw(hisi_hba)) | |
2727 | return PCI_ERS_RESULT_NEED_RESET; | |
2728 | ||
2729 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2730 | } | |
2731 | ||
2732 | static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) | |
2733 | { | |
2734 | return PCI_ERS_RESULT_RECOVERED; | |
2735 | } | |
2736 | ||
2737 | static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) | |
2738 | { | |
2739 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2740 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2741 | struct device *dev = hisi_hba->dev; | |
2742 | HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); | |
2743 | ||
2744 | dev_info(dev, "PCI error: slot reset callback!!\n"); | |
2745 | queue_work(hisi_hba->wq, &r.work); | |
2746 | wait_for_completion(r.completion); | |
2747 | if (r.done) | |
2748 | return PCI_ERS_RESULT_RECOVERED; | |
2749 | ||
2750 | return PCI_ERS_RESULT_DISCONNECT; | |
2751 | } | |
2752 | ||
e851852b XT |
2753 | static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) |
2754 | { | |
2755 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2756 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2757 | struct device *dev = hisi_hba->dev; | |
2758 | int rc; | |
2759 | ||
2760 | dev_info(dev, "FLR prepare\n"); | |
2761 | set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
2762 | hisi_sas_controller_reset_prepare(hisi_hba); | |
2763 | ||
2764 | rc = disable_host_v3_hw(hisi_hba); | |
2765 | if (rc) | |
2766 | dev_err(dev, "FLR: disable host failed rc=%d\n", rc); | |
2767 | } | |
2768 | ||
2769 | static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) | |
2770 | { | |
2771 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2772 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2773 | struct device *dev = hisi_hba->dev; | |
2774 | int rc; | |
2775 | ||
2776 | hisi_sas_init_mem(hisi_hba); | |
2777 | ||
2778 | rc = hw_init_v3_hw(hisi_hba); | |
2779 | if (rc) { | |
2780 | dev_err(dev, "FLR: hw init failed rc=%d\n", rc); | |
2781 | return; | |
2782 | } | |
2783 | ||
2784 | hisi_sas_controller_reset_done(hisi_hba); | |
2785 | dev_info(dev, "FLR done\n"); | |
2786 | } | |
2787 | ||
92f61e3b JG |
2788 | enum { |
2789 | /* instances of the controller */ | |
2790 | hip08, | |
2791 | }; | |
2792 | ||
33623483 XC |
2793 | static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) |
2794 | { | |
2795 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2796 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2797 | struct device *dev = hisi_hba->dev; | |
2798 | struct Scsi_Host *shost = hisi_hba->shost; | |
b8438c40 | 2799 | pci_power_t device_state; |
33623483 | 2800 | int rc; |
33623483 XC |
2801 | |
2802 | if (!pdev->pm_cap) { | |
2803 | dev_err(dev, "PCI PM not supported\n"); | |
2804 | return -ENODEV; | |
2805 | } | |
2806 | ||
84b58ff9 XT |
2807 | if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) |
2808 | return -1; | |
2809 | ||
33623483 XC |
2810 | scsi_block_requests(shost); |
2811 | set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); | |
2812 | flush_workqueue(hisi_hba->wq); | |
33623483 | 2813 | |
1d51757d | 2814 | rc = disable_host_v3_hw(hisi_hba); |
33623483 | 2815 | if (rc) { |
1d51757d | 2816 | dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); |
33623483 XC |
2817 | clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); |
2818 | clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
2819 | scsi_unblock_requests(shost); | |
2820 | return rc; | |
2821 | } | |
2822 | ||
2823 | hisi_sas_init_mem(hisi_hba); | |
2824 | ||
2825 | device_state = pci_choose_state(pdev, state); | |
2826 | dev_warn(dev, "entering operating state [D%d]\n", | |
2827 | device_state); | |
2828 | pci_save_state(pdev); | |
2829 | pci_disable_device(pdev); | |
2830 | pci_set_power_state(pdev, device_state); | |
2831 | ||
33623483 | 2832 | hisi_sas_release_tasks(hisi_hba); |
33623483 XC |
2833 | |
2834 | sas_suspend_ha(sha); | |
2835 | return 0; | |
2836 | } | |
2837 | ||
2838 | static int hisi_sas_v3_resume(struct pci_dev *pdev) | |
2839 | { | |
2840 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2841 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2842 | struct Scsi_Host *shost = hisi_hba->shost; | |
2843 | struct device *dev = hisi_hba->dev; | |
2844 | unsigned int rc; | |
b8438c40 | 2845 | pci_power_t device_state = pdev->current_state; |
33623483 XC |
2846 | |
2847 | dev_warn(dev, "resuming from operating state [D%d]\n", | |
2848 | device_state); | |
2849 | pci_set_power_state(pdev, PCI_D0); | |
2850 | pci_enable_wake(pdev, PCI_D0, 0); | |
2851 | pci_restore_state(pdev); | |
2852 | rc = pci_enable_device(pdev); | |
2853 | if (rc) | |
2854 | dev_err(dev, "enable device failed during resume (%d)\n", rc); | |
2855 | ||
2856 | pci_set_master(pdev); | |
2857 | scsi_unblock_requests(shost); | |
2858 | clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); | |
2859 | ||
2860 | sas_prep_resume_ha(sha); | |
2861 | init_reg_v3_hw(hisi_hba); | |
2862 | hisi_hba->hw->phys_init(hisi_hba); | |
2863 | sas_resume_ha(sha); | |
2864 | clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
2865 | ||
2866 | return 0; | |
2867 | } | |
2868 | ||
92f61e3b JG |
2869 | static const struct pci_device_id sas_v3_pci_table[] = { |
2870 | { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, | |
2871 | {} | |
2872 | }; | |
a48c4524 | 2873 | MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); |
92f61e3b | 2874 | |
56b72168 XT |
2875 | static const struct pci_error_handlers hisi_sas_err_handler = { |
2876 | .error_detected = hisi_sas_error_detected_v3_hw, | |
2877 | .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, | |
2878 | .slot_reset = hisi_sas_slot_reset_v3_hw, | |
e851852b XT |
2879 | .reset_prepare = hisi_sas_reset_prepare_v3_hw, |
2880 | .reset_done = hisi_sas_reset_done_v3_hw, | |
56b72168 XT |
2881 | }; |
2882 | ||
92f61e3b JG |
2883 | static struct pci_driver sas_v3_pci_driver = { |
2884 | .name = DRV_NAME, | |
2885 | .id_table = sas_v3_pci_table, | |
2886 | .probe = hisi_sas_v3_probe, | |
2887 | .remove = hisi_sas_v3_remove, | |
33623483 XC |
2888 | .suspend = hisi_sas_v3_suspend, |
2889 | .resume = hisi_sas_v3_resume, | |
56b72168 | 2890 | .err_handler = &hisi_sas_err_handler, |
92f61e3b JG |
2891 | }; |
2892 | ||
2893 | module_pci_driver(sas_v3_pci_driver); | |
6cc8d8f2 | 2894 | module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); |
92f61e3b | 2895 | |
92f61e3b JG |
2896 | MODULE_LICENSE("GPL"); |
2897 | MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); | |
2898 | MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); | |
a48c4524 | 2899 | MODULE_ALIAS("pci:" DRV_NAME); |