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scsi: lpfc: Fix counters so outstandng NVME IO count is accurate
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / lpfc / lpfc.h
CommitLineData
dea3101e
JB		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
d080abe0
JS		 4 * Copyright (C) 2017 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e
JB		 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e
JB		 22 *******************************************************************/
23
2e0fef85 24#include <scsi/scsi_host.h>
895427bd 25#include <linux/ktime.h>
88a2cfbb
JS		 26
27#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
28#define CONFIG_SCSI_LPFC_DEBUG_FS
29#endif
30
dea3101e
JB		 31struct lpfc_sli2_slim;
32
5402a315
JS		 33#define ELX_MODEL_NAME_SIZE 80
34
3772a991
JS		 35#define LPFC_PCI_DEV_LP 0x1
36#define LPFC_PCI_DEV_OC 0x2
37
38#define LPFC_SLI_REV2 2
39#define LPFC_SLI_REV3 3
40#define LPFC_SLI_REV4 4
41
97eab634 42#define LPFC_MAX_TARGET 4096 /* max number of targets supported */
e17da18e
JS		 43#define LPFC_MAX_DISC_THREADS 64 /* max outstanding discovery els
44 requests */
45#define LPFC_MAX_NS_RETRY 3 /* Number of retry attempts to contact
46 the NameServer before giving up. */
445cf4f4 47#define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */
81301a9b 48#define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */
e2aed29f
JS		 49#define LPFC_DEFAULT_MENLO_SG_SEG_CNT 128 /* sg element count per scsi
50 cmnd for menlo needs nearly twice as for firmware
51 downloads using bsg */
96f7077f
JS		 52
53#define LPFC_MIN_SG_SLI4_BUF_SZ 0x800 /* based on LPFC_DEFAULT_SG_SEG_CNT */
54#define LPFC_MAX_SG_SLI4_SEG_CNT_DIF 128 /* sg element count per scsi cmnd */
55#define LPFC_MAX_SG_SEG_CNT_DIF 512 /* sg element count per scsi cmnd */
81301a9b 56#define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */
09294d46
JS		 57#define LPFC_MAX_SGL_SEG_CNT 512 /* SGL element count per scsi cmnd */
58#define LPFC_MAX_BPL_SEG_CNT 4096 /* BPL element count per scsi cmnd */
4d4c4a4a 59#define LPFC_MAX_NVME_SEG_CNT 128 /* max SGL element cnt per NVME cmnd */
09294d46 60
0558056c 61#define LPFC_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
dea3101e 62#define LPFC_IOCB_LIST_CNT 2250 /* list of IOCBs for fast-path usage. */
445cf4f4 63#define LPFC_Q_RAMP_UP_INTERVAL 120 /* lun q_depth ramp up interval */
495a714c 64#define LPFC_VNAME_LEN 100 /* vport symbolic name length */
977b5a0a
JS		 65#define LPFC_TGTQ_INTERVAL 40000 /* Min amount of time between tgt
66 queue depth change in millisecs */
67#define LPFC_TGTQ_RAMPUP_PCENT 5 /* Target queue rampup in percentage */
7dc517df 68#define LPFC_MIN_TGT_QDEPTH 10
977b5a0a 69#define LPFC_MAX_TGT_QDEPTH 0xFFFF
dea3101e 70
ea2151b4
JS		 71#define LPFC_MAX_BUCKET_COUNT 20 /* Maximum no. of buckets for stat data
72 collection. */
92d7f7b0
JS		 73/*
74 * Following time intervals are used of adjusting SCSI device
75 * queue depths when there are driver resource error or Firmware
76 * resource error.
77 */
256ec0d0
JS		 78/* 1 Second */
79#define QUEUE_RAMP_DOWN_INTERVAL (msecs_to_jiffies(1000 * 1))
92d7f7b0
JS		 80
81/* Number of exchanges reserved for discovery to complete */
82#define LPFC_DISC_IOCB_BUFF_COUNT 20
83
858c9f6c 84#define LPFC_HB_MBOX_INTERVAL 5 /* Heart beat interval in seconds. */
311464ec 85#define LPFC_HB_MBOX_TIMEOUT 30 /* Heart beat timeout in seconds. */
858c9f6c 86
ba20c853
JS		 87#define LPFC_LOOK_AHEAD_OFF 0 /* Look ahead logic is turned off */
88
9399627f
JS		 89/* Error Attention event polling interval */
90#define LPFC_ERATT_POLL_INTERVAL 5 /* EATT poll interval in seconds */
91
dea3101e
JB		 92/* Define macros for 64 bit support */
93#define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
94#define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
95#define getPaddr(high, low) ((dma_addr_t)( \
96 (( (u64)(high)<<16 ) << 16)|( (u64)(low))))
97/* Provide maximum configuration definitions. */
98#define LPFC_DRVR_TIMEOUT 16 /* driver iocb timeout value in sec */
dea3101e
JB		 99#define FC_MAX_ADPTMSG 64
100
101#define MAX_HBAEVT 32
96418b5e 102#define MAX_HBAS_NO_RESET 16
dea3101e 103
9399627f
JS		 104/* Number of MSI-X vectors the driver uses */
105#define LPFC_MSIX_VECTORS 2
106
5e9d9b82 107/* lpfc wait event data ready flag */
2ade92ae 108#define LPFC_DATA_READY 0 /* bit 0 */
5e9d9b82 109
809c7536
JS		 110/* queue dump line buffer size */
111#define LPFC_LBUF_SZ 128
112
618a5230
JS		 113/* mailbox system shutdown options */
114#define LPFC_MBX_NO_WAIT 0
115#define LPFC_MBX_WAIT 1
116
875fbdfe
JSEC		 117enum lpfc_polling_flags {
118 ENABLE_FCP_RING_POLLING = 0x1,
119 DISABLE_FCP_RING_INT = 0x2
120};
121
895427bd
JS		 122struct perf_prof {
123 uint16_t cmd_cpu[40];
124 uint16_t rsp_cpu[40];
125 uint16_t qh_cpu[40];
126 uint16_t wqidx[40];
127};
128
01649561
JS		 129/*
130 * Provide for FC4 TYPE x28 - NVME. The
131 * bit mask for FCP and NVME is 0x8 identically
132 * because they are 32 bit positions distance.
133 */
a0f2d3ef
JS		 134#define LPFC_FC4_TYPE_BITMASK 0x00000100
135
dea3101e
JB		 136/* Provide DMA memory definitions the driver uses per port instance. */
137struct lpfc_dmabuf {
138 struct list_head list;
139 void *virt; /* virtual address ptr */
140 dma_addr_t phys; /* mapped address */
76bb24ef 141 uint32_t buffer_tag; /* used for tagged queue ring */
dea3101e
JB		 142};
143
6c621a22
JS		 144struct lpfc_nvmet_ctxbuf {
145 struct list_head list;
146 struct lpfc_nvmet_rcv_ctx *context;
147 struct lpfc_iocbq *iocbq;
148 struct lpfc_sglq *sglq;
149};
150
dea3101e
JB		 151struct lpfc_dma_pool {
152 struct lpfc_dmabuf *elements;
153 uint32_t max_count;
154 uint32_t current_count;
155};
156
ed957684 157struct hbq_dmabuf {
da0436e9 158 struct lpfc_dmabuf hbuf;
ed957684 159 struct lpfc_dmabuf dbuf;
895427bd
JS		 160 uint16_t total_size;
161 uint16_t bytes_recv;
ed957684 162 uint32_t tag;
4d9ab994 163 struct lpfc_cq_event cq_event;
45ed1190 164 unsigned long time_stamp;
895427bd
JS		 165 void *context;
166};
167
168struct rqb_dmabuf {
169 struct lpfc_dmabuf hbuf;
170 struct lpfc_dmabuf dbuf;
171 uint16_t total_size;
172 uint16_t bytes_recv;
a8cf5dfe 173 uint16_t idx;
895427bd
JS		 174 struct lpfc_queue *hrq; /* ptr to associated Header RQ */
175 struct lpfc_queue *drq; /* ptr to associated Data RQ */
ed957684
JS		 176};
177
dea3101e
JB		 178/* Priority bit. Set value to exceed low water mark in lpfc_mem. */
179#define MEM_PRI 0x100
180
181
182/****************************************************************************/
183/* Device VPD save area */
184/****************************************************************************/
185typedef struct lpfc_vpd {
186 uint32_t status; /* vpd status value */
187 uint32_t length; /* number of bytes actually returned */
188 struct {
189 uint32_t rsvd1; /* Revision numbers */
190 uint32_t biuRev;
191 uint32_t smRev;
192 uint32_t smFwRev;
193 uint32_t endecRev;
194 uint16_t rBit;
195 uint8_t fcphHigh;
196 uint8_t fcphLow;
197 uint8_t feaLevelHigh;
198 uint8_t feaLevelLow;
199 uint32_t postKernRev;
200 uint32_t opFwRev;
201 uint8_t opFwName[16];
202 uint32_t sli1FwRev;
203 uint8_t sli1FwName[16];
204 uint32_t sli2FwRev;
205 uint8_t sli2FwName[16];
206 } rev;
92d7f7b0
JS		 207 struct {
208#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 209 uint32_t rsvd3 :19; /* Reserved */
210 uint32_t cdss : 1; /* Configure Data Security SLI */
211 uint32_t rsvd2 : 3; /* Reserved */
212 uint32_t cbg : 1; /* Configure BlockGuard */
92d7f7b0
JS		 213 uint32_t cmv : 1; /* Configure Max VPIs */
214 uint32_t ccrp : 1; /* Config Command Ring Polling */
215 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
216 uint32_t chbs : 1; /* Cofigure Host Backing store */
217 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
218 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
219 uint32_t cmx : 1; /* Configure Max XRIs */
220 uint32_t cmr : 1; /* Configure Max RPIs */
221#else /* __LITTLE_ENDIAN */
222 uint32_t cmr : 1; /* Configure Max RPIs */
223 uint32_t cmx : 1; /* Configure Max XRIs */
224 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
225 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
226 uint32_t chbs : 1; /* Cofigure Host Backing store */
227 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
228 uint32_t ccrp : 1; /* Config Command Ring Polling */
229 uint32_t cmv : 1; /* Configure Max VPIs */
da0436e9
JS		 230 uint32_t cbg : 1; /* Configure BlockGuard */
231 uint32_t rsvd2 : 3; /* Reserved */
232 uint32_t cdss : 1; /* Configure Data Security SLI */
233 uint32_t rsvd3 :19; /* Reserved */
92d7f7b0
JS		 234#endif
235 } sli3Feat;
dea3101e
JB		 236} lpfc_vpd_t;
237
238struct lpfc_scsi_buf;
239
240
241/*
242 * lpfc stat counters
243 */
244struct lpfc_stats {
245 /* Statistics for ELS commands */
246 uint32_t elsLogiCol;
247 uint32_t elsRetryExceeded;
248 uint32_t elsXmitRetry;
249 uint32_t elsDelayRetry;
250 uint32_t elsRcvDrop;
251 uint32_t elsRcvFrame;
252 uint32_t elsRcvRSCN;
253 uint32_t elsRcvRNID;
254 uint32_t elsRcvFARP;
255 uint32_t elsRcvFARPR;
256 uint32_t elsRcvFLOGI;
257 uint32_t elsRcvPLOGI;
258 uint32_t elsRcvADISC;
259 uint32_t elsRcvPDISC;
260 uint32_t elsRcvFAN;
261 uint32_t elsRcvLOGO;
262 uint32_t elsRcvPRLO;
263 uint32_t elsRcvPRLI;
7bb3b137 264 uint32_t elsRcvLIRR;
12265f68 265 uint32_t elsRcvRLS;
7bb3b137
JW		 266 uint32_t elsRcvRPS;
267 uint32_t elsRcvRPL;
5ffc266e 268 uint32_t elsRcvRRQ;
12265f68
JS		 269 uint32_t elsRcvRTV;
270 uint32_t elsRcvECHO;
8b017a30 271 uint32_t elsRcvLCB;
86478875 272 uint32_t elsRcvRDP;
dea3101e 273 uint32_t elsXmitFLOGI;
92d7f7b0 274 uint32_t elsXmitFDISC;
dea3101e
JB		 275 uint32_t elsXmitPLOGI;
276 uint32_t elsXmitPRLI;
277 uint32_t elsXmitADISC;
278 uint32_t elsXmitLOGO;
279 uint32_t elsXmitSCR;
280 uint32_t elsXmitRNID;
281 uint32_t elsXmitFARP;
282 uint32_t elsXmitFARPR;
283 uint32_t elsXmitACC;
284 uint32_t elsXmitLSRJT;
285
286 uint32_t frameRcvBcast;
287 uint32_t frameRcvMulti;
288 uint32_t strayXmitCmpl;
289 uint32_t frameXmitDelay;
290 uint32_t xriCmdCmpl;
291 uint32_t xriStatErr;
292 uint32_t LinkUp;
293 uint32_t LinkDown;
294 uint32_t LinkMultiEvent;
295 uint32_t NoRcvBuf;
296 uint32_t fcpCmd;
297 uint32_t fcpCmpl;
298 uint32_t fcpRspErr;
299 uint32_t fcpRemoteStop;
300 uint32_t fcpPortRjt;
301 uint32_t fcpPortBusy;
302 uint32_t fcpError;
303 uint32_t fcpLocalErr;
304};
305
2e0fef85
JS		 306struct lpfc_hba;
307
92d7f7b0 308
2e0fef85 309enum discovery_state {
92d7f7b0
JS		 310 LPFC_VPORT_UNKNOWN = 0, /* vport state is unknown */
311 LPFC_VPORT_FAILED = 1, /* vport has failed */
312 LPFC_LOCAL_CFG_LINK = 6, /* local NPORT Id configured */
313 LPFC_FLOGI = 7, /* FLOGI sent to Fabric */
314 LPFC_FDISC = 8, /* FDISC sent for vport */
315 LPFC_FABRIC_CFG_LINK = 9, /* Fabric assigned NPORT Id
316 * configured */
317 LPFC_NS_REG = 10, /* Register with NameServer */
318 LPFC_NS_QRY = 11, /* Query NameServer for NPort ID list */
319 LPFC_BUILD_DISC_LIST = 12, /* Build ADISC and PLOGI lists for
320 * device authentication / discovery */
321 LPFC_DISC_AUTH = 13, /* Processing ADISC list */
322 LPFC_VPORT_READY = 32,
2e0fef85
JS		 323};
324
325enum hba_state {
326 LPFC_LINK_UNKNOWN = 0, /* HBA state is unknown */
327 LPFC_WARM_START = 1, /* HBA state after selective reset */
328 LPFC_INIT_START = 2, /* Initial state after board reset */
329 LPFC_INIT_MBX_CMDS = 3, /* Initialize HBA with mbox commands */
330 LPFC_LINK_DOWN = 4, /* HBA initialized, link is down */
331 LPFC_LINK_UP = 5, /* Link is up - issue READ_LA */
92d7f7b0 332 LPFC_CLEAR_LA = 6, /* authentication cmplt - issue
2e0fef85 333 * CLEAR_LA */
92d7f7b0 334 LPFC_HBA_READY = 32,
2e0fef85
JS		 335 LPFC_HBA_ERROR = -1
336};
337
338struct lpfc_vport {
2e0fef85 339 struct lpfc_hba *phba;
3772a991 340 struct list_head listentry;
2e0fef85
JS		 341 uint8_t port_type;
342#define LPFC_PHYSICAL_PORT 1
343#define LPFC_NPIV_PORT 2
344#define LPFC_FABRIC_PORT 3
345 enum discovery_state port_state;
346
92d7f7b0 347 uint16_t vpi;
da0436e9 348 uint16_t vfi;
c868595d
JS		 349 uint8_t vpi_state;
350#define LPFC_VPI_REGISTERED 0x1
2e0fef85
JS		 351
352 uint32_t fc_flag; /* FC flags */
353/* Several of these flags are HBA centric and should be moved to
354 * phba->link_flag (e.g. FC_PTP, FC_PUBLIC_LOOP)
355 */
92d7f7b0
JS		 356#define FC_PT2PT 0x1 /* pt2pt with no fabric */
357#define FC_PT2PT_PLOGI 0x2 /* pt2pt initiate PLOGI */
358#define FC_DISC_TMO 0x4 /* Discovery timer running */
359#define FC_PUBLIC_LOOP 0x8 /* Public loop */
360#define FC_LBIT 0x10 /* LOGIN bit in loopinit set */
361#define FC_RSCN_MODE 0x20 /* RSCN cmd rcv'ed */
362#define FC_NLP_MORE 0x40 /* More node to process in node tbl */
363#define FC_OFFLINE_MODE 0x80 /* Interface is offline for diag */
364#define FC_FABRIC 0x100 /* We are fabric attached */
4b40c59e 365#define FC_VPORT_LOGO_RCVD 0x200 /* LOGO received on vport */
92d7f7b0 366#define FC_RSCN_DISCOVERY 0x400 /* Auth all devices after RSCN */
4b40c59e 367#define FC_LOGO_RCVD_DID_CHNG 0x800 /* FDISC on phys port detect DID chng*/
92d7f7b0
JS		 368#define FC_SCSI_SCAN_TMO 0x4000 /* scsi scan timer running */
369#define FC_ABORT_DISCOVERY 0x8000 /* we want to abort discovery */
370#define FC_NDISC_ACTIVE 0x10000 /* NPort discovery active */
371#define FC_BYPASSED_MODE 0x20000 /* NPort is in bypassed mode */
92d7f7b0
JS		 372#define FC_VPORT_NEEDS_REG_VPI 0x80000 /* Needs to have its vpi registered */
373#define FC_RSCN_DEFERRED 0x100000 /* A deferred RSCN being processed */
1c6834a7 374#define FC_VPORT_NEEDS_INIT_VPI 0x200000 /* Need to INIT_VPI before FDISC */
695a814e
JS		 375#define FC_VPORT_CVL_RCVD 0x400000 /* VLink failed due to CVL */
376#define FC_VFI_REGISTERED 0x800000 /* VFI is registered */
377#define FC_FDISC_COMPLETED 0x1000000/* FDISC completed */
92494144 378#define FC_DISC_DELAYED 0x2000000/* Delay NPort discovery */
2e0fef85 379
7ee5d43e
JS		 380 uint32_t ct_flags;
381#define FC_CT_RFF_ID 0x1 /* RFF_ID accepted by switch */
382#define FC_CT_RNN_ID 0x2 /* RNN_ID accepted by switch */
383#define FC_CT_RSNN_NN 0x4 /* RSNN_NN accepted by switch */
384#define FC_CT_RSPN_ID 0x8 /* RSPN_ID accepted by switch */
385#define FC_CT_RFT_ID 0x10 /* RFT_ID accepted by switch */
386
2e0fef85
JS		 387 struct list_head fc_nodes;
388
389 /* Keep counters for the number of entries in each list. */
390 uint16_t fc_plogi_cnt;
391 uint16_t fc_adisc_cnt;
392 uint16_t fc_reglogin_cnt;
393 uint16_t fc_prli_cnt;
394 uint16_t fc_unmap_cnt;
395 uint16_t fc_map_cnt;
396 uint16_t fc_npr_cnt;
397 uint16_t fc_unused_cnt;
398 struct serv_parm fc_sparam; /* buffer for our service parameters */
399
400 uint32_t fc_myDID; /* fibre channel S_ID */
401 uint32_t fc_prevDID; /* previous fibre channel S_ID */
92494144
JS		 402 struct lpfc_name fabric_portname;
403 struct lpfc_name fabric_nodename;
2e0fef85
JS		 404
405 int32_t stopped; /* HBA has not been restarted since last ERATT */
406 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
407
a0f2d3ef
JS		 408 uint32_t num_disc_nodes; /* in addition to hba_state */
409 uint32_t gidft_inp; /* cnt of outstanding GID_FTs */
2e0fef85
JS		 410
411 uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
412 uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
7f5f3d0d 413 uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
2e0fef85
JS		 414 struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
415 struct lpfc_name fc_nodename; /* fc nodename */
416 struct lpfc_name fc_portname; /* fc portname */
417
418 struct lpfc_work_evt disc_timeout_evt;
419
420 struct timer_list fc_disctmo; /* Discovery rescue timer */
421 uint8_t fc_ns_retry; /* retries for fabric nameserver */
422 uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */
423
424 spinlock_t work_port_lock;
425 uint32_t work_port_events; /* Timeout to be handled */
858c9f6c
JS		 426#define WORKER_DISC_TMO 0x1 /* vport: Discovery timeout */
427#define WORKER_ELS_TMO 0x2 /* vport: ELS timeout */
92494144 428#define WORKER_DELAYED_DISC_TMO 0x8 /* vport: delayed discovery */
858c9f6c
JS		 429
430#define WORKER_MBOX_TMO 0x100 /* hba: MBOX timeout */
431#define WORKER_HB_TMO 0x200 /* hba: Heart beat timeout */
b1c11812 432#define WORKER_FABRIC_BLOCK_TMO 0x400 /* hba: fabric block timeout */
858c9f6c
JS		 433#define WORKER_RAMP_DOWN_QUEUE 0x800 /* hba: Decrease Q depth */
434#define WORKER_RAMP_UP_QUEUE 0x1000 /* hba: Increase Q depth */
2a9bf3d0 435#define WORKER_SERVICE_TXQ 0x2000 /* hba: IOCBs on the txq */
2e0fef85 436
2e0fef85 437 struct timer_list els_tmofunc;
92494144 438 struct timer_list delayed_disc_tmo;
2e0fef85
JS		 439
440 int unreg_vpi_cmpl;
441
442 uint8_t load_flag;
443#define FC_LOADING 0x1 /* HBA in process of loading drvr */
444#define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */
4258e98e 445#define FC_ALLOW_FDMI 0x4 /* port is ready for FDMI requests */
3de2a653
JS		 446 /* Vport Config Parameters */
447 uint32_t cfg_scan_down;
448 uint32_t cfg_lun_queue_depth;
449 uint32_t cfg_nodev_tmo;
450 uint32_t cfg_devloss_tmo;
451 uint32_t cfg_restrict_login;
452 uint32_t cfg_peer_port_login;
453 uint32_t cfg_fcp_class;
454 uint32_t cfg_use_adisc;
3de2a653 455 uint32_t cfg_discovery_threads;
e8b62011 456 uint32_t cfg_log_verbose;
3de2a653 457 uint32_t cfg_max_luns;
7ee5d43e 458 uint32_t cfg_enable_da_id;
977b5a0a 459 uint32_t cfg_max_scsicmpl_time;
7dc517df 460 uint32_t cfg_tgt_queue_depth;
3cb01c57 461 uint32_t cfg_first_burst_size;
3de2a653 462 uint32_t dev_loss_tmo_changed;
51ef4c26
JS		 463
464 struct fc_vport *fc_vport;
465
923e4b6a 466#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
51ef4c26
JS		 467 struct dentry *debug_disc_trc;
468 struct dentry *debug_nodelist;
bd2cdd5e
JS		 469 struct dentry *debug_nvmestat;
470 struct dentry *debug_nvmektime;
471 struct dentry *debug_cpucheck;
51ef4c26
JS		 472 struct dentry *vport_debugfs_root;
473 struct lpfc_debugfs_trc *disc_trc;
474 atomic_t disc_trc_cnt;
475#endif
ea2151b4
JS		 476 uint8_t stat_data_enabled;
477 uint8_t stat_data_blocked;
da0436e9 478 struct list_head rcv_buffer_list;
45ed1190 479 unsigned long rcv_buffer_time_stamp;
da0436e9
JS		 480 uint32_t vport_flag;
481#define STATIC_VPORT 1
aeb3c817
JS		 482#define FAWWPN_SET 2
483#define FAWWPN_PARAM_CHG 4
4258e98e
JS		 484
485 uint16_t fdmi_num_disc;
486 uint32_t fdmi_hba_mask;
487 uint32_t fdmi_port_mask;
895427bd
JS		 488
489 /* There is a single nvme instance per vport. */
490 struct nvme_fc_local_port *localport;
491 uint8_t nvmei_support; /* driver supports NVME Initiator */
492 uint32_t last_fcp_wqidx;
2e0fef85
JS		 493};
494
ed957684
JS		 495struct hbq_s {
496 uint16_t entry_count; /* Current number of HBQ slots */
a8adb832 497 uint16_t buffer_count; /* Current number of buffers posted */
ed957684
JS		 498 uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */
499 uint32_t hbqPutIdx; /* HBQ slot to use */
500 uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */
51ef4c26
JS		 501 void *hbq_virt; /* Virtual ptr to this hbq */
502 struct list_head hbq_buffer_list; /* buffers assigned to this HBQ */
503 /* Callback for HBQ buffer allocation */
504 struct hbq_dmabuf *(*hbq_alloc_buffer) (struct lpfc_hba *);
505 /* Callback for HBQ buffer free */
506 void (*hbq_free_buffer) (struct lpfc_hba *,
507 struct hbq_dmabuf *);
ed957684
JS		 508};
509
51ef4c26 510/* this matches the position in the lpfc_hbq_defs array */
92d7f7b0 511#define LPFC_ELS_HBQ 0
895427bd 512#define LPFC_MAX_HBQS 1
ed957684 513
7af67051
JS		 514enum hba_temp_state {
515 HBA_NORMAL_TEMP,
516 HBA_OVER_TEMP
517};
518
db2378e0
JS		 519enum intr_type_t {
520 NONE = 0,
521 INTx,
522 MSI,
523 MSIX,
524};
525
6dd9e31c 526#define LPFC_CT_CTX_MAX 64
f1c3b0fc
JS		 527struct unsol_rcv_ct_ctx {
528 uint32_t ctxt_id;
529 uint32_t SID;
6dd9e31c
JS		 530 uint32_t valid;
531#define UNSOL_INVALID 0
532#define UNSOL_VALID 1
7851fe2c
JS		 533 uint16_t oxid;
534 uint16_t rxid;
f1c3b0fc
JS		 535};
536
76a95d75
JS		 537#define LPFC_USER_LINK_SPEED_AUTO 0 /* auto select (default)*/
538#define LPFC_USER_LINK_SPEED_1G 1 /* 1 Gigabaud */
539#define LPFC_USER_LINK_SPEED_2G 2 /* 2 Gigabaud */
540#define LPFC_USER_LINK_SPEED_4G 4 /* 4 Gigabaud */
541#define LPFC_USER_LINK_SPEED_8G 8 /* 8 Gigabaud */
542#define LPFC_USER_LINK_SPEED_10G 10 /* 10 Gigabaud */
543#define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */
d38dd52c
JS		 544#define LPFC_USER_LINK_SPEED_32G 32 /* 32 Gigabaud */
545#define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_32G
546#define LPFC_USER_LINK_SPEED_BITMAP ((1ULL << LPFC_USER_LINK_SPEED_32G) | \
547 (1 << LPFC_USER_LINK_SPEED_16G) | \
76a95d75
JS		 548 (1 << LPFC_USER_LINK_SPEED_10G) | \
549 (1 << LPFC_USER_LINK_SPEED_8G) | \
550 (1 << LPFC_USER_LINK_SPEED_4G) | \
551 (1 << LPFC_USER_LINK_SPEED_2G) | \
552 (1 << LPFC_USER_LINK_SPEED_1G) | \
553 (1 << LPFC_USER_LINK_SPEED_AUTO))
d38dd52c 554#define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16, 32"
76a95d75 555
7ad20aa9
JS		 556enum nemb_type {
557 nemb_mse = 1,
558 nemb_hbd
559};
560
561enum mbox_type {
562 mbox_rd = 1,
563 mbox_wr
564};
565
566enum dma_type {
567 dma_mbox = 1,
568 dma_ebuf
569};
570
571enum sta_type {
572 sta_pre_addr = 1,
573 sta_pos_addr
574};
575
576struct lpfc_mbox_ext_buf_ctx {
577 uint32_t state;
578#define LPFC_BSG_MBOX_IDLE 0
579#define LPFC_BSG_MBOX_HOST 1
580#define LPFC_BSG_MBOX_PORT 2
581#define LPFC_BSG_MBOX_DONE 3
582#define LPFC_BSG_MBOX_ABTS 4
583 enum nemb_type nembType;
584 enum mbox_type mboxType;
585 uint32_t numBuf;
586 uint32_t mbxTag;
587 uint32_t seqNum;
588 struct lpfc_dmabuf *mbx_dmabuf;
589 struct list_head ext_dmabuf_list;
590};
591
dea3101e 592struct lpfc_hba {
3772a991
JS		 593 /* SCSI interface function jump table entries */
594 int (*lpfc_new_scsi_buf)
595 (struct lpfc_vport *, int);
596 struct lpfc_scsi_buf * (*lpfc_get_scsi_buf)
19ca7609 597 (struct lpfc_hba *, struct lpfc_nodelist *);
3772a991
JS		 598 int (*lpfc_scsi_prep_dma_buf)
599 (struct lpfc_hba *, struct lpfc_scsi_buf *);
600 void (*lpfc_scsi_unprep_dma_buf)
601 (struct lpfc_hba *, struct lpfc_scsi_buf *);
602 void (*lpfc_release_scsi_buf)
603 (struct lpfc_hba *, struct lpfc_scsi_buf *);
604 void (*lpfc_rampdown_queue_depth)
605 (struct lpfc_hba *);
606 void (*lpfc_scsi_prep_cmnd)
607 (struct lpfc_vport *, struct lpfc_scsi_buf *,
608 struct lpfc_nodelist *);
acd6859b 609
3772a991
JS		 610 /* IOCB interface function jump table entries */
611 int (*__lpfc_sli_issue_iocb)
612 (struct lpfc_hba *, uint32_t,
613 struct lpfc_iocbq *, uint32_t);
614 void (*__lpfc_sli_release_iocbq)(struct lpfc_hba *,
615 struct lpfc_iocbq *);
616 int (*lpfc_hba_down_post)(struct lpfc_hba *phba);
3772a991
JS		 617 IOCB_t * (*lpfc_get_iocb_from_iocbq)
618 (struct lpfc_iocbq *);
619 void (*lpfc_scsi_cmd_iocb_cmpl)
620 (struct lpfc_hba *, struct lpfc_iocbq *, struct lpfc_iocbq *);
621
622 /* MBOX interface function jump table entries */
623 int (*lpfc_sli_issue_mbox)
624 (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t);
acd6859b 625
3772a991
JS		 626 /* Slow-path IOCB process function jump table entries */
627 void (*lpfc_sli_handle_slow_ring_event)
628 (struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
629 uint32_t mask);
acd6859b 630
3772a991
JS		 631 /* INIT device interface function jump table entries */
632 int (*lpfc_sli_hbq_to_firmware)
633 (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *);
634 int (*lpfc_sli_brdrestart)
635 (struct lpfc_hba *);
636 int (*lpfc_sli_brdready)
637 (struct lpfc_hba *, uint32_t);
638 void (*lpfc_handle_eratt)
639 (struct lpfc_hba *);
640 void (*lpfc_stop_port)
641 (struct lpfc_hba *);
84d1b006 642 int (*lpfc_hba_init_link)
6e7288d9 643 (struct lpfc_hba *, uint32_t);
84d1b006 644 int (*lpfc_hba_down_link)
6e7288d9 645 (struct lpfc_hba *, uint32_t);
7f86059a
JS		 646 int (*lpfc_selective_reset)
647 (struct lpfc_hba *);
3772a991 648
acd6859b
JS		 649 int (*lpfc_bg_scsi_prep_dma_buf)
650 (struct lpfc_hba *, struct lpfc_scsi_buf *);
651 /* Add new entries here */
652
3772a991
JS		 653 /* SLI4 specific HBA data structure */
654 struct lpfc_sli4_hba sli4_hba;
655
dea3101e 656 struct lpfc_sli sli;
3772a991
JS		 657 uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */
658 uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */
ed957684 659 uint32_t sli3_options; /* Mask of enabled SLI3 options */
34b02dcd
JS		 660#define LPFC_SLI3_HBQ_ENABLED 0x01
661#define LPFC_SLI3_NPIV_ENABLED 0x02
662#define LPFC_SLI3_VPORT_TEARDOWN 0x04
663#define LPFC_SLI3_CRP_ENABLED 0x08
81301a9b 664#define LPFC_SLI3_BG_ENABLED 0x20
da0436e9 665#define LPFC_SLI3_DSS_ENABLED 0x40
fedd3b7b
JS		 666#define LPFC_SLI4_PERFH_ENABLED 0x80
667#define LPFC_SLI4_PHWQ_ENABLED 0x100
ed957684
JS		 668 uint32_t iocb_cmd_size;
669 uint32_t iocb_rsp_size;
2e0fef85
JS		 670
671 enum hba_state link_state;
672 uint32_t link_flag; /* link state flags */
311464ec 673#define LS_LOOPBACK_MODE 0x1 /* NPort is in Loopback mode */
2e0fef85
JS		 674 /* This flag is set while issuing */
675 /* INIT_LINK mailbox command */
92d7f7b0 676#define LS_NPIV_FAB_SUPPORTED 0x2 /* Fabric supports NPIV */
1b32f6aa 677#define LS_IGNORE_ERATT 0x4 /* intr handler should ignore ERATT */
ae9e28f3
JS		 678#define LS_MDS_LINK_DOWN 0x8 /* MDS Diagnostics Link Down */
679#define LS_MDS_LOOPBACK 0x16 /* MDS Diagnostics Link Up (Loopback) */
2e0fef85 680
9399627f
JS		 681 uint32_t hba_flag; /* hba generic flags */
682#define HBA_ERATT_HANDLED 0x1 /* This flag is set when eratt handled */
da0436e9 683#define DEFER_ERATT 0x2 /* Deferred error attention in progress */
76a95d75 684#define HBA_FCOE_MODE 0x4 /* HBA function in FCoE Mode */
45ed1190 685#define HBA_SP_QUEUE_EVT 0x8 /* Slow-path qevt posted to worker thread*/
da0436e9
JS		 686#define HBA_POST_RECEIVE_BUFFER 0x10 /* Rcv buffers need to be posted */
687#define FCP_XRI_ABORT_EVENT 0x20
688#define ELS_XRI_ABORT_EVENT 0x40
689#define ASYNC_EVENT 0x80
a0c87cbd 690#define LINK_DISABLED 0x100 /* Link disabled by user */
a93ff37a
JS		 691#define FCF_TS_INPROG 0x200 /* FCF table scan in progress */
692#define FCF_RR_INPROG 0x400 /* FCF roundrobin flogi in progress */
693#define HBA_FIP_SUPPORT 0x800 /* FIP support in HBA */
694#define HBA_AER_ENABLED 0x1000 /* AER enabled with HBA */
695#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
19ca7609 696#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
4f2e66c6 697#define HBA_FCP_IOQ_FLUSH 0x8000 /* FCP I/O queues being flushed */
0293635e 698#define HBA_FW_DUMP_OP 0x10000 /* Skips fn reset before FW dump */
65791f1f 699#define HBA_RECOVERABLE_UE 0x20000 /* Firmware supports recoverable UE */
c691816e
JS		 700#define HBA_FORCED_LINK_SPEED 0x40000 /*
701 * Firmware supports Forced Link Speed
702 * capability
703 */
895427bd 704#define HBA_NVME_IOQ_FLUSH 0x80000 /* NVME IO queues flushed. */
318083ad 705#define NVME_XRI_ABORT_EVENT 0x100000
895427bd 706
45ed1190 707 uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
34b02dcd
JS		 708 struct lpfc_dmabuf slim2p;
709
710 MAILBOX_t *mbox;
7a470277 711 uint32_t *mbox_ext;
7ad20aa9 712 struct lpfc_mbox_ext_buf_ctx mbox_ext_buf_ctx;
9399627f 713 uint32_t ha_copy;
34b02dcd
JS		 714 struct _PCB *pcb;
715 struct _IOCB *IOCBs;
2e0fef85 716
34b02dcd 717 struct lpfc_dmabuf hbqslimp;
2e0fef85 718
dea3101e
JB		 719 uint16_t pci_cfg_value;
720
dea3101e
JB		 721 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
722
723 uint32_t fc_eventTag; /* event tag for link attention */
4d9ab994 724 uint32_t link_events;
dea3101e 725
dea3101e 726 /* These fields used to be binfo */
dea3101e 727 uint32_t fc_pref_DID; /* preferred D_ID */
92d7f7b0 728 uint8_t fc_pref_ALPA; /* preferred AL_PA */
12265f68 729 uint32_t fc_edtovResol; /* E_D_TOV timer resolution */
dea3101e
JB		 730 uint32_t fc_edtov; /* E_D_TOV timer value */
731 uint32_t fc_arbtov; /* ARB_TOV timer value */
732 uint32_t fc_ratov; /* R_A_TOV timer value */
733 uint32_t fc_rttov; /* R_T_TOV timer value */
734 uint32_t fc_altov; /* AL_TOV timer value */
735 uint32_t fc_crtov; /* C_R_TOV timer value */
736 uint32_t fc_citov; /* C_I_TOV timer value */
dea3101e 737
dea3101e
JB		 738 struct serv_parm fc_fabparam; /* fabric service parameters buffer */
739 uint8_t alpa_map[128]; /* AL_PA map from READ_LA */
740
dea3101e 741 uint32_t lmt;
dea3101e
JB		 742
743 uint32_t fc_topology; /* link topology, from LINK INIT */
e74c03c8 744 uint32_t fc_topology_changed; /* link topology, from LINK INIT */
dea3101e
JB		 745
746 struct lpfc_stats fc_stat;
747
dea3101e
JB		 748 struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
749 uint32_t nport_event_cnt; /* timestamp for nlplist entry */
750
2e0fef85
JS		 751 uint8_t wwnn[8];
752 uint8_t wwpn[8];
dea3101e 753 uint32_t RandomData[7];
7bdedb34 754 uint8_t fcp_embed_io;
895427bd
JS		 755 uint8_t nvme_support; /* Firmware supports NVME */
756 uint8_t nvmet_support; /* driver supports NVMET */
f358dd0c 757#define LPFC_NVMET_MAX_PORTS 32
7bdedb34 758 uint8_t mds_diags_support;
dea3101e 759
3de2a653 760 /* HBA Config Parameters */
dea3101e 761 uint32_t cfg_ack0;
78b2d852 762 uint32_t cfg_enable_npiv;
19ca7609 763 uint32_t cfg_enable_rrq;
dea3101e 764 uint32_t cfg_topology;
dea3101e 765 uint32_t cfg_link_speed;
7d791df7
JS		 766#define LPFC_FCF_FOV 1 /* Fast fcf failover */
767#define LPFC_FCF_PRIORITY 2 /* Priority fcf failover */
768 uint32_t cfg_fcf_failover_policy;
49aa143d 769 uint32_t cfg_fcp_io_sched;
a6571c6e 770 uint32_t cfg_fcp2_no_tgt_reset;
dea3101e
JB		 771 uint32_t cfg_cr_delay;
772 uint32_t cfg_cr_count;
cf5bf97e 773 uint32_t cfg_multi_ring_support;
a4bc3379
JS		 774 uint32_t cfg_multi_ring_rctl;
775 uint32_t cfg_multi_ring_type;
875fbdfe
JSEC		 776 uint32_t cfg_poll;
777 uint32_t cfg_poll_tmo;
0c411222 778 uint32_t cfg_task_mgmt_tmo;
4ff43246 779 uint32_t cfg_use_msi;
da0436e9 780 uint32_t cfg_fcp_imax;
7bb03bbf 781 uint32_t cfg_fcp_cpu_map;
67d12733 782 uint32_t cfg_fcp_io_channel;
f358dd0c 783 uint32_t cfg_suppress_rsp;
895427bd
JS		 784 uint32_t cfg_nvme_oas;
785 uint32_t cfg_nvme_io_channel;
2d7dbc4c 786 uint32_t cfg_nvmet_mrq;
f358dd0c 787 uint32_t cfg_enable_nvmet;
895427bd 788 uint32_t cfg_nvme_enable_fb;
2d7dbc4c 789 uint32_t cfg_nvmet_fb_size;
96f7077f 790 uint32_t cfg_total_seg_cnt;
dea3101e 791 uint32_t cfg_sg_seg_cnt;
4d4c4a4a 792 uint32_t cfg_nvme_seg_cnt;
dea3101e 793 uint32_t cfg_sg_dma_buf_size;
352e5fd1
JS		 794 uint64_t cfg_soft_wwnn;
795 uint64_t cfg_soft_wwpn;
3de2a653 796 uint32_t cfg_hba_queue_depth;
13815c83
JS		 797 uint32_t cfg_enable_hba_reset;
798 uint32_t cfg_enable_hba_heartbeat;
1ba981fd
JS		 799 uint32_t cfg_fof;
800 uint32_t cfg_EnableXLane;
801 uint8_t cfg_oas_tgt_wwpn[8];
802 uint8_t cfg_oas_vpt_wwpn[8];
803 uint32_t cfg_oas_lun_state;
804#define OAS_LUN_ENABLE 1
805#define OAS_LUN_DISABLE 0
806 uint32_t cfg_oas_lun_status;
807#define OAS_LUN_STATUS_EXISTS 0x01
808 uint32_t cfg_oas_flags;
809#define OAS_FIND_ANY_VPORT 0x01
810#define OAS_FIND_ANY_TARGET 0x02
811#define OAS_LUN_VALID 0x04
c92c841c 812 uint32_t cfg_oas_priority;
1ba981fd 813 uint32_t cfg_XLanePriority;
81301a9b 814 uint32_t cfg_enable_bg;
b3b98b74
JS		 815 uint32_t cfg_prot_mask;
816 uint32_t cfg_prot_guard;
7a470277 817 uint32_t cfg_hostmem_hgp;
da0436e9 818 uint32_t cfg_log_verbose;
0d878419 819 uint32_t cfg_aer_support;
912e3acd 820 uint32_t cfg_sriov_nr_virtfn;
c71ab861 821 uint32_t cfg_request_firmware_upgrade;
2a9bf3d0 822 uint32_t cfg_iocb_cnt;
84d1b006 823 uint32_t cfg_suppress_link_up;
cff261f6 824 uint32_t cfg_rrq_xri_bitmap_sz;
8eb8b960 825 uint32_t cfg_delay_discovery;
12247e81 826 uint32_t cfg_sli_mode;
e40a02c1
JS		 827#define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */
828#define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */
829#define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */
ab56dc2e 830 uint32_t cfg_enable_dss;
4258e98e
JS		 831 uint32_t cfg_fdmi_on;
832#define LPFC_FDMI_NO_SUPPORT 0 /* FDMI not supported */
833#define LPFC_FDMI_SUPPORT 1 /* FDMI supported? */
4258e98e 834 uint32_t cfg_enable_SmartSAN;
7bdedb34 835 uint32_t cfg_enable_mds_diags;
895427bd
JS		 836 uint32_t cfg_enable_fc4_type;
837 uint32_t cfg_xri_split;
838#define LPFC_ENABLE_FCP 1
839#define LPFC_ENABLE_NVME 2
840#define LPFC_ENABLE_BOTH 3
841 uint32_t io_channel_irqs; /* number of irqs for io channels */
f358dd0c 842 struct nvmet_fc_target_port *targetport;
dea3101e
JB		 843 lpfc_vpd_t vpd; /* vital product data */
844
dea3101e
JB		 845 struct pci_dev *pcidev;
846 struct list_head work_list;
847 uint32_t work_ha; /* Host Attention Bits for WT */
848 uint32_t work_ha_mask; /* HA Bits owned by WT */
849 uint32_t work_hs; /* HS stored in case of ERRAT */
850 uint32_t work_status[2]; /* Extra status from SLIM */
dea3101e 851
5e9d9b82 852 wait_queue_head_t work_waitq;
dea3101e 853 struct task_struct *worker_thread;
d7c255b2 854 unsigned long data_flags;
dea3101e 855
3163f725 856 uint32_t hbq_in_use; /* HBQs in use flag */
ed957684 857 uint32_t hbq_count; /* Count of configured HBQs */
92d7f7b0 858 struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
ed957684 859
895427bd
JS		 860 atomic_t fcp_qidx; /* next FCP WQ (RR Policy) */
861 atomic_t nvme_qidx; /* next NVME WQ (RR Policy) */
8fa38513 862
115a4124
JS		 863 phys_addr_t pci_bar0_map; /* Physical address for PCI BAR0 */
864 phys_addr_t pci_bar1_map; /* Physical address for PCI BAR1 */
865 phys_addr_t pci_bar2_map; /* Physical address for PCI BAR2 */
dea3101e
JB		 866 void __iomem *slim_memmap_p; /* Kernel memory mapped address for
867 PCI BAR0 */
868 void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
869 PCI BAR2 */
870
962bc51b
JS		 871 void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
872 PCI BAR0 with dual-ULP support */
873 void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
874 PCI BAR2 with dual-ULP support */
875 void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
876 PCI BAR4 with dual-ULP support */
877#define PCI_64BIT_BAR0 0
878#define PCI_64BIT_BAR2 2
879#define PCI_64BIT_BAR4 4
dea3101e
JB		 880 void __iomem *MBslimaddr; /* virtual address for mbox cmds */
881 void __iomem *HAregaddr; /* virtual address for host attn reg */
882 void __iomem *CAregaddr; /* virtual address for chip attn reg */
883 void __iomem *HSregaddr; /* virtual address for host status
884 reg */
885 void __iomem *HCregaddr; /* virtual address for host ctl reg */
886
ed957684 887 struct lpfc_hgp __iomem *host_gp; /* Host side get/put pointers */
34b02dcd 888 struct lpfc_pgp *port_gp;
ed957684 889 uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */
92d7f7b0 890 uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */
ed957684 891
dea3101e 892 int brd_no; /* FC board number */
dea3101e
JB		 893 char SerialNumber[32]; /* adapter Serial Number */
894 char OptionROMVersion[32]; /* adapter BIOS / Fcode version */
895 char ModelDesc[256]; /* Model Description */
896 char ModelName[80]; /* Model Name */
897 char ProgramType[256]; /* Program Type */
898 char Port[20]; /* Port No */
899 uint8_t vpd_flag; /* VPD data flag */
900
901#define VPD_MODEL_DESC 0x1 /* valid vpd model description */
902#define VPD_MODEL_NAME 0x2 /* valid vpd model name */
903#define VPD_PROGRAM_TYPE 0x4 /* valid vpd program type */
904#define VPD_PORT 0x8 /* valid vpd port data */
905#define VPD_MASK 0xf /* mask for any vpd data */
906
352e5fd1
JS		 907 uint8_t soft_wwn_enable;
908
875fbdfe 909 struct timer_list fcp_poll_timer;
9399627f 910 struct timer_list eratt_poll;
65791f1f 911 uint32_t eratt_poll_interval;
875fbdfe 912
dea3101e
JB		 913 /*
914 * stat counters
915 */
2cee7808
JS		 916 atomic_t fc4ScsiInputRequests;
917 atomic_t fc4ScsiOutputRequests;
918 atomic_t fc4ScsiControlRequests;
919 atomic_t fc4ScsiIoCmpls;
920 atomic_t fc4NvmeInputRequests;
921 atomic_t fc4NvmeOutputRequests;
922 atomic_t fc4NvmeControlRequests;
923 atomic_t fc4NvmeIoCmpls;
924 atomic_t fc4NvmeLsRequests;
925 atomic_t fc4NvmeLsCmpls;
895427bd 926
81301a9b
JS		 927 uint64_t bg_guard_err_cnt;
928 uint64_t bg_apptag_err_cnt;
929 uint64_t bg_reftag_err_cnt;
dea3101e 930
dea3101e 931 /* fastpath list. */
a40fc5f0
JS		 932 spinlock_t scsi_buf_list_get_lock; /* SCSI buf alloc list lock */
933 spinlock_t scsi_buf_list_put_lock; /* SCSI buf free list lock */
934 struct list_head lpfc_scsi_buf_list_get;
935 struct list_head lpfc_scsi_buf_list_put;
dea3101e 936 uint32_t total_scsi_bufs;
895427bd
JS		 937 spinlock_t nvme_buf_list_get_lock; /* NVME buf alloc list lock */
938 spinlock_t nvme_buf_list_put_lock; /* NVME buf free list lock */
939 struct list_head lpfc_nvme_buf_list_get;
940 struct list_head lpfc_nvme_buf_list_put;
941 uint32_t total_nvme_bufs;
dea3101e
JB		 942 struct list_head lpfc_iocb_list;
943 uint32_t total_iocbq_bufs;
19ca7609 944 struct list_head active_rrq_list;
2e0fef85 945 spinlock_t hbalock;
dea3101e
JB		 946
947 /* pci_mem_pools */
895427bd 948 struct pci_pool *lpfc_sg_dma_buf_pool;
dea3101e 949 struct pci_pool *lpfc_mbuf_pool;
da0436e9
JS		 950 struct pci_pool *lpfc_hrb_pool; /* header receive buffer pool */
951 struct pci_pool *lpfc_drb_pool; /* data receive buffer pool */
3c603be9 952 struct pci_pool *lpfc_nvmet_drb_pool; /* data receive buffer pool */
8568a4d2 953 struct pci_pool *lpfc_hbq_pool; /* SLI3 hbq buffer pool */
895427bd 954 struct pci_pool *txrdy_payload_pool;
dea3101e
JB		 955 struct lpfc_dma_pool lpfc_mbuf_safety_pool;
956
957 mempool_t *mbox_mem_pool;
958 mempool_t *nlp_mem_pool;
19ca7609 959 mempool_t *rrq_pool;
cff261f6 960 mempool_t *active_rrq_pool;
f888ba3c
JSEC		 961
962 struct fc_host_statistics link_stats;
db2378e0 963 enum intr_type_t intr_type;
5b75da2f
JS		 964 uint32_t intr_mode;
965#define LPFC_INTR_ERROR 0xFFFFFFFF
2e0fef85 966 struct list_head port_list;
549e55cd
JS		 967 struct lpfc_vport *pport; /* physical lpfc_vport pointer */
968 uint16_t max_vpi; /* Maximum virtual nports */
09372820 969#define LPFC_MAX_VPI 0xFFFF /* Max number of VPI supported */
da0436e9
JS		 970 uint16_t max_vports; /*
971 * For IOV HBAs max_vpi can change
972 * after a reset. max_vports is max
973 * number of vports present. This can
974 * be greater than max_vpi.
975 */
976 uint16_t vpi_base;
977 uint16_t vfi_base;
549e55cd 978 unsigned long *vpi_bmask; /* vpi allocation table */
6d368e53
JS		 979 uint16_t *vpi_ids;
980 uint16_t vpi_count;
981 struct list_head lpfc_vpi_blk_list;
92d7f7b0
JS		 982
983 /* Data structure used by fabric iocb scheduler */
984 struct list_head fabric_iocb_list;
985 atomic_t fabric_iocb_count;
986 struct timer_list fabric_block_timer;
987 unsigned long bit_flags;
988#define FABRIC_COMANDS_BLOCKED 0
989 atomic_t num_rsrc_err;
990 atomic_t num_cmd_success;
991 unsigned long last_rsrc_error_time;
992 unsigned long last_ramp_down_time;
923e4b6a 993#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
858c9f6c
JS		 994 struct dentry *hba_debugfs_root;
995 atomic_t debugfs_vport_count;
78b2d852 996 struct dentry *debug_hbqinfo;
c95d6c6c
JS		 997 struct dentry *debug_dumpHostSlim;
998 struct dentry *debug_dumpHBASlim;
f9bb2da1
JS		 999 struct dentry *debug_dumpData; /* BlockGuard BPL */
1000 struct dentry *debug_dumpDif; /* BlockGuard BPL */
1001 struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
4ac9b226
JS		 1002 struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
1003 struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
f9bb2da1
JS		 1004 struct dentry *debug_writeGuard; /* inject write guard_tag errors */
1005 struct dentry *debug_writeApp; /* inject write app_tag errors */
1006 struct dentry *debug_writeRef; /* inject write ref_tag errors */
acd6859b 1007 struct dentry *debug_readGuard; /* inject read guard_tag errors */
f9bb2da1
JS		 1008 struct dentry *debug_readApp; /* inject read app_tag errors */
1009 struct dentry *debug_readRef; /* inject read ref_tag errors */
1010
bd2cdd5e
JS		 1011 struct dentry *debug_nvmeio_trc;
1012 struct lpfc_debugfs_nvmeio_trc *nvmeio_trc;
1013 atomic_t nvmeio_trc_cnt;
1014 uint32_t nvmeio_trc_size;
1015 uint32_t nvmeio_trc_output_idx;
1016
f9bb2da1
JS		 1017 /* T10 DIF error injection */
1018 uint32_t lpfc_injerr_wgrd_cnt;
1019 uint32_t lpfc_injerr_wapp_cnt;
1020 uint32_t lpfc_injerr_wref_cnt;
acd6859b 1021 uint32_t lpfc_injerr_rgrd_cnt;
f9bb2da1
JS		 1022 uint32_t lpfc_injerr_rapp_cnt;
1023 uint32_t lpfc_injerr_rref_cnt;
4ac9b226
JS		 1024 uint32_t lpfc_injerr_nportid;
1025 struct lpfc_name lpfc_injerr_wwpn;
f9bb2da1 1026 sector_t lpfc_injerr_lba;
acd6859b 1027#define LPFC_INJERR_LBA_OFF (sector_t)(-1)
f9bb2da1 1028
a58cbd52
JS		 1029 struct dentry *debug_slow_ring_trc;
1030 struct lpfc_debugfs_trc *slow_ring_trc;
1031 atomic_t slow_ring_trc_cnt;
2a622bfb
JS		 1032 /* iDiag debugfs sub-directory */
1033 struct dentry *idiag_root;
1034 struct dentry *idiag_pci_cfg;
b76f2dc9 1035 struct dentry *idiag_bar_acc;
2a622bfb 1036 struct dentry *idiag_que_info;
86a80846
JS		 1037 struct dentry *idiag_que_acc;
1038 struct dentry *idiag_drb_acc;
b76f2dc9
JS		 1039 struct dentry *idiag_ctl_acc;
1040 struct dentry *idiag_mbx_acc;
1041 struct dentry *idiag_ext_acc;
07bcd98e 1042 uint8_t lpfc_idiag_last_eq;
858c9f6c 1043#endif
bd2cdd5e 1044 uint16_t nvmeio_trc_on;
858c9f6c 1045
0ff10d46
JS		 1046 /* Used for deferred freeing of ELS data buffers */
1047 struct list_head elsbuf;
1048 int elsbuf_cnt;
1049 int elsbuf_prev_cnt;
1050
57127f15 1051 uint8_t temp_sensor_support;
858c9f6c
JS		 1052 /* Fields used for heart beat. */
1053 unsigned long last_completion_time;
bc73905a 1054 unsigned long skipped_hb;
858c9f6c
JS		 1055 struct timer_list hb_tmofunc;
1056 uint8_t hb_outstanding;
19ca7609 1057 struct timer_list rrq_tmr;
84774a4d 1058 enum hba_temp_state over_temp_state;
e47c9093
JS		 1059 /* ndlp reference management */
1060 spinlock_t ndlp_lock;
76bb24ef
JS		 1061 /*
1062 * Following bit will be set for all buffer tags which are not
1063 * associated with any HBQ.
1064 */
1065#define QUE_BUFTAG_BIT (1<<31)
1066 uint32_t buffer_tag_count;
84774a4d
JS		 1067 int wait_4_mlo_maint_flg;
1068 wait_queue_head_t wait_4_mlo_m_q;
ea2151b4
JS		 1069 /* data structure used for latency data collection */
1070#define LPFC_NO_BUCKET 0
1071#define LPFC_LINEAR_BUCKET 1
1072#define LPFC_POWER2_BUCKET 2
1073 uint8_t bucket_type;
1074 uint32_t bucket_base;
1075 uint32_t bucket_step;
1076
1077/* Maximum number of events that can be outstanding at any time*/
1078#define LPFC_MAX_EVT_COUNT 512
1079 atomic_t fast_event_count;
32b9793f
JS		 1080 uint32_t fcoe_eventtag;
1081 uint32_t fcoe_eventtag_at_fcf_scan;
80c17849
JS		 1082 uint32_t fcoe_cvl_eventtag;
1083 uint32_t fcoe_cvl_eventtag_attn;
da0436e9
JS		 1084 struct lpfc_fcf fcf;
1085 uint8_t fc_map[3];
1086 uint8_t valid_vlan;
1087 uint16_t vlan_id;
1088 struct list_head fcf_conn_rec_list;
f1c3b0fc 1089
4fede78f 1090 spinlock_t ct_ev_lock; /* synchronize access to ct_ev_waiters */
f1c3b0fc 1091 struct list_head ct_ev_waiters;
6dd9e31c 1092 struct unsol_rcv_ct_ctx ct_ctx[LPFC_CT_CTX_MAX];
f1c3b0fc 1093 uint32_t ctx_idx;
e2aed29f
JS		 1094
1095 uint8_t menlo_flag; /* menlo generic flags */
1096#define HBA_MENLO_SUPPORT 0x1 /* HBA supports menlo commands */
2a9bf3d0
JS		 1097 uint32_t iocb_cnt;
1098 uint32_t iocb_max;
d7c47992 1099 atomic_t sdev_cnt;
bc73905a
JS		 1100 uint8_t fips_spec_rev;
1101 uint8_t fips_level;
1ba981fd
JS		 1102 spinlock_t devicelock; /* lock for luns list */
1103 mempool_t *device_data_mem_pool;
1104 struct list_head luns;
310429ef
JS		 1105#define LPFC_TRANSGRESSION_HIGH_TEMPERATURE 0x0080
1106#define LPFC_TRANSGRESSION_LOW_TEMPERATURE 0x0040
1107#define LPFC_TRANSGRESSION_HIGH_VOLTAGE 0x0020
1108#define LPFC_TRANSGRESSION_LOW_VOLTAGE 0x0010
1109#define LPFC_TRANSGRESSION_HIGH_TXBIAS 0x0008
1110#define LPFC_TRANSGRESSION_LOW_TXBIAS 0x0004
1111#define LPFC_TRANSGRESSION_HIGH_TXPOWER 0x0002
1112#define LPFC_TRANSGRESSION_LOW_TXPOWER 0x0001
1113#define LPFC_TRANSGRESSION_HIGH_RXPOWER 0x8000
1114#define LPFC_TRANSGRESSION_LOW_RXPOWER 0x4000
1115 uint16_t sfp_alarm;
1116 uint16_t sfp_warning;
bd2cdd5e
JS		 1117
1118#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
1119#define LPFC_CHECK_CPU_CNT 32
1120 uint32_t cpucheck_rcv_io[LPFC_CHECK_CPU_CNT];
1121 uint32_t cpucheck_xmt_io[LPFC_CHECK_CPU_CNT];
1122 uint32_t cpucheck_cmpl_io[LPFC_CHECK_CPU_CNT];
1123 uint32_t cpucheck_ccmpl_io[LPFC_CHECK_CPU_CNT];
1124 uint16_t cpucheck_on;
1125#define LPFC_CHECK_OFF 0
1126#define LPFC_CHECK_NVME_IO 1
f358dd0c
JS		 1127#define LPFC_CHECK_NVMET_RCV 2
1128#define LPFC_CHECK_NVMET_IO 4
bd2cdd5e
JS		 1129 uint16_t ktime_on;
1130 uint64_t ktime_data_samples;
1131 uint64_t ktime_status_samples;
1132 uint64_t ktime_last_cmd;
1133 uint64_t ktime_seg1_total;
1134 uint64_t ktime_seg1_min;
1135 uint64_t ktime_seg1_max;
1136 uint64_t ktime_seg2_total;
1137 uint64_t ktime_seg2_min;
1138 uint64_t ktime_seg2_max;
1139 uint64_t ktime_seg3_total;
1140 uint64_t ktime_seg3_min;
1141 uint64_t ktime_seg3_max;
1142 uint64_t ktime_seg4_total;
1143 uint64_t ktime_seg4_min;
1144 uint64_t ktime_seg4_max;
1145 uint64_t ktime_seg5_total;
1146 uint64_t ktime_seg5_min;
1147 uint64_t ktime_seg5_max;
1148 uint64_t ktime_seg6_total;
1149 uint64_t ktime_seg6_min;
1150 uint64_t ktime_seg6_max;
1151 uint64_t ktime_seg7_total;
1152 uint64_t ktime_seg7_min;
1153 uint64_t ktime_seg7_max;
1154 uint64_t ktime_seg8_total;
1155 uint64_t ktime_seg8_min;
1156 uint64_t ktime_seg8_max;
1157 uint64_t ktime_seg9_total;
1158 uint64_t ktime_seg9_min;
1159 uint64_t ktime_seg9_max;
1160 uint64_t ktime_seg10_total;
1161 uint64_t ktime_seg10_min;
1162 uint64_t ktime_seg10_max;
1163#endif
dea3101e
JB		 1164};
1165
2e0fef85
JS		 1166static inline struct Scsi_Host *
1167lpfc_shost_from_vport(struct lpfc_vport *vport)
1168{
1169 return container_of((void *) vport, struct Scsi_Host, hostdata[0]);
1170}
1171
5b8bd0c9 1172static inline void
2e0fef85
JS		 1173lpfc_set_loopback_flag(struct lpfc_hba *phba)
1174{
5b8bd0c9 1175 if (phba->cfg_topology == FLAGS_LOCAL_LB)
2e0fef85 1176 phba->link_flag |= LS_LOOPBACK_MODE;
5b8bd0c9 1177 else
2e0fef85
JS		 1178 phba->link_flag &= ~LS_LOOPBACK_MODE;
1179}
1180
1181static inline int
1182lpfc_is_link_up(struct lpfc_hba *phba)
1183{
1184 return phba->link_state == LPFC_LINK_UP ||
92d7f7b0
JS		 1185 phba->link_state == LPFC_CLEAR_LA ||
1186 phba->link_state == LPFC_HBA_READY;
5b8bd0c9 1187}
dea3101e 1188
5e9d9b82
JS		 1189static inline void
1190lpfc_worker_wake_up(struct lpfc_hba *phba)
1191{
1192 /* Set the lpfc data pending flag */
1193 set_bit(LPFC_DATA_READY, &phba->data_flags);
1194
1195 /* Wake up worker thread */
1196 wake_up(&phba->work_waitq);
1197 return;
1198}
1199
9940b97b
JS		 1200static inline int
1201lpfc_readl(void __iomem *addr, uint32_t *data)
1202{
1203 uint32_t temp;
1204 temp = readl(addr);
1205 if (temp == 0xffffffff)
1206 return -EIO;
1207 *data = temp;
1208 return 0;
1209}
1210
1211static inline int
9399627f
JS		 1212lpfc_sli_read_hs(struct lpfc_hba *phba)
1213{
1214 /*
1215 * There was a link/board error. Read the status register to retrieve
1216 * the error event and process it.
1217 */
1218 phba->sli.slistat.err_attn_event++;
1219
9940b97b
JS		 1220 /* Save status info and check for unplug error */
1221 if (lpfc_readl(phba->HSregaddr, &phba->work_hs) ||
1222 lpfc_readl(phba->MBslimaddr + 0xa8, &phba->work_status[0]) ||
1223 lpfc_readl(phba->MBslimaddr + 0xac, &phba->work_status[1])) {
1224 return -EIO;
1225 }
9399627f
JS		 1226
1227 /* Clear chip Host Attention error bit */
1228 writel(HA_ERATT, phba->HAregaddr);
1229 readl(phba->HAregaddr); /* flush */
1230 phba->pport->stopped = 1;
1231
9940b97b 1232 return 0;
9399627f 1233}
895427bd
JS		 1234
1235static inline struct lpfc_sli_ring *
1236lpfc_phba_elsring(struct lpfc_hba *phba)
1237{
0c9c6a75
JS		 1238 if (phba->sli_rev == LPFC_SLI_REV4) {
1239 if (phba->sli4_hba.els_wq)
1240 return phba->sli4_hba.els_wq->pring;
1241 else
1242 return NULL;
1243 }
895427bd
JS		 1244 return &phba->sli.sli3_ring[LPFC_ELS_RING];
1245}
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