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20f733e7 BR |
1 | /* |
2 | * sata_mv.c - Marvell SATA support | |
3 | * | |
8b260248 | 4 | * Copyright 2005: EMC Corporation, all rights reserved. |
20f733e7 BR |
5 | * |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/blkdev.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/dma-mapping.h> | |
a9524a76 | 32 | #include <linux/device.h> |
20f733e7 | 33 | #include <scsi/scsi_host.h> |
193515d5 | 34 | #include <scsi/scsi_cmnd.h> |
20f733e7 BR |
35 | #include <linux/libata.h> |
36 | #include <asm/io.h> | |
37 | ||
38 | #define DRV_NAME "sata_mv" | |
7e6c1208 | 39 | #define DRV_VERSION "0.25" |
20f733e7 BR |
40 | |
41 | enum { | |
42 | /* BAR's are enumerated in terms of pci_resource_start() terms */ | |
43 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ | |
44 | MV_IO_BAR = 2, /* offset 0x18: IO space */ | |
45 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ | |
46 | ||
47 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ | |
48 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ | |
49 | ||
50 | MV_PCI_REG_BASE = 0, | |
51 | MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ | |
52 | MV_SATAHC0_REG_BASE = 0x20000, | |
bca1c4eb JG |
53 | MV_GPIO_PORT_CTL = 0x104f0, |
54 | MV_RESET_CFG = 0x180d8, | |
20f733e7 BR |
55 | |
56 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
57 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
58 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ | |
59 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, | |
60 | ||
31961943 | 61 | MV_USE_Q_DEPTH = ATA_DEF_QUEUE, |
20f733e7 | 62 | |
31961943 BR |
63 | MV_MAX_Q_DEPTH = 32, |
64 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, | |
65 | ||
66 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB | |
67 | * CRPB needs alignment on a 256B boundary. Size == 256B | |
68 | * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB | |
69 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B | |
70 | */ | |
71 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), | |
72 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), | |
73 | MV_MAX_SG_CT = 176, | |
74 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), | |
75 | MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), | |
76 | ||
20f733e7 BR |
77 | MV_PORTS_PER_HC = 4, |
78 | /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ | |
79 | MV_PORT_HC_SHIFT = 2, | |
31961943 | 80 | /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ |
20f733e7 BR |
81 | MV_PORT_MASK = 3, |
82 | ||
83 | /* Host Flags */ | |
84 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ | |
85 | MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ | |
31961943 BR |
86 | MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */ |
87 | MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
88 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO), | |
8b260248 | 89 | MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE | |
31961943 | 90 | MV_FLAG_GLBL_SFT_RST), |
20f733e7 BR |
91 | |
92 | chip_504x = 0, | |
93 | chip_508x = 1, | |
94 | chip_604x = 2, | |
95 | chip_608x = 3, | |
96 | ||
31961943 BR |
97 | CRQB_FLAG_READ = (1 << 0), |
98 | CRQB_TAG_SHIFT = 1, | |
99 | CRQB_CMD_ADDR_SHIFT = 8, | |
100 | CRQB_CMD_CS = (0x2 << 11), | |
101 | CRQB_CMD_LAST = (1 << 15), | |
102 | ||
103 | CRPB_FLAG_STATUS_SHIFT = 8, | |
104 | ||
105 | EPRD_FLAG_END_OF_TBL = (1 << 31), | |
106 | ||
20f733e7 BR |
107 | /* PCI interface registers */ |
108 | ||
31961943 BR |
109 | PCI_COMMAND_OFS = 0xc00, |
110 | ||
20f733e7 BR |
111 | PCI_MAIN_CMD_STS_OFS = 0xd30, |
112 | STOP_PCI_MASTER = (1 << 2), | |
113 | PCI_MASTER_EMPTY = (1 << 3), | |
114 | GLOB_SFT_RST = (1 << 4), | |
115 | ||
116 | PCI_IRQ_CAUSE_OFS = 0x1d58, | |
117 | PCI_IRQ_MASK_OFS = 0x1d5c, | |
118 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ | |
119 | ||
120 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, | |
121 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, | |
122 | PORT0_ERR = (1 << 0), /* shift by port # */ | |
123 | PORT0_DONE = (1 << 1), /* shift by port # */ | |
124 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ | |
125 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ | |
126 | PCI_ERR = (1 << 18), | |
127 | TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ | |
128 | TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ | |
129 | PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ | |
130 | GPIO_INT = (1 << 22), | |
131 | SELF_INT = (1 << 23), | |
132 | TWSI_INT = (1 << 24), | |
133 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ | |
8b260248 | 134 | HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | |
20f733e7 BR |
135 | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | |
136 | HC_MAIN_RSVD), | |
137 | ||
138 | /* SATAHC registers */ | |
139 | HC_CFG_OFS = 0, | |
140 | ||
141 | HC_IRQ_CAUSE_OFS = 0x14, | |
31961943 | 142 | CRPB_DMA_DONE = (1 << 0), /* shift by port # */ |
20f733e7 BR |
143 | HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ |
144 | DEV_IRQ = (1 << 8), /* shift by port # */ | |
145 | ||
146 | /* Shadow block registers */ | |
31961943 BR |
147 | SHD_BLK_OFS = 0x100, |
148 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ | |
20f733e7 BR |
149 | |
150 | /* SATA registers */ | |
151 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ | |
152 | SATA_ACTIVE_OFS = 0x350, | |
bca1c4eb JG |
153 | PHY_MODE4 = 0x314, |
154 | PHY_MODE2 = 0x330, | |
155 | SATA_INTERFACE_CTL = 0x050, | |
156 | ||
157 | MV_M2_PREAMP_MASK = 0x7e0, | |
20f733e7 BR |
158 | |
159 | /* Port registers */ | |
160 | EDMA_CFG_OFS = 0, | |
31961943 BR |
161 | EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */ |
162 | EDMA_CFG_NCQ = (1 << 5), | |
163 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ | |
164 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ | |
165 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ | |
20f733e7 BR |
166 | |
167 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, | |
168 | EDMA_ERR_IRQ_MASK_OFS = 0xc, | |
169 | EDMA_ERR_D_PAR = (1 << 0), | |
170 | EDMA_ERR_PRD_PAR = (1 << 1), | |
171 | EDMA_ERR_DEV = (1 << 2), | |
172 | EDMA_ERR_DEV_DCON = (1 << 3), | |
173 | EDMA_ERR_DEV_CON = (1 << 4), | |
174 | EDMA_ERR_SERR = (1 << 5), | |
175 | EDMA_ERR_SELF_DIS = (1 << 7), | |
176 | EDMA_ERR_BIST_ASYNC = (1 << 8), | |
177 | EDMA_ERR_CRBQ_PAR = (1 << 9), | |
178 | EDMA_ERR_CRPB_PAR = (1 << 10), | |
179 | EDMA_ERR_INTRL_PAR = (1 << 11), | |
180 | EDMA_ERR_IORDY = (1 << 12), | |
181 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), | |
182 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), | |
183 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), | |
184 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), | |
185 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), | |
186 | EDMA_ERR_TRANS_PROTO = (1 << 31), | |
8b260248 | 187 | EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
20f733e7 BR |
188 | EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | |
189 | EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | | |
8b260248 | 190 | EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | |
20f733e7 | 191 | EDMA_ERR_LNK_DATA_RX | |
8b260248 | 192 | EDMA_ERR_LNK_DATA_TX | |
20f733e7 BR |
193 | EDMA_ERR_TRANS_PROTO), |
194 | ||
31961943 BR |
195 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
196 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ | |
31961943 BR |
197 | |
198 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, | |
199 | EDMA_REQ_Q_PTR_SHIFT = 5, | |
200 | ||
201 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, | |
202 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, | |
203 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ | |
31961943 BR |
204 | EDMA_RSP_Q_PTR_SHIFT = 3, |
205 | ||
20f733e7 BR |
206 | EDMA_CMD_OFS = 0x28, |
207 | EDMA_EN = (1 << 0), | |
208 | EDMA_DS = (1 << 1), | |
209 | ATA_RST = (1 << 2), | |
210 | ||
bca1c4eb JG |
211 | EDMA_ARB_CFG = 0x38, |
212 | EDMA_NO_SNOOP = (1 << 6), | |
213 | ||
31961943 BR |
214 | /* Host private flags (hp_flags) */ |
215 | MV_HP_FLAG_MSI = (1 << 0), | |
bca1c4eb JG |
216 | MV_HP_ERRATA_60X1A1 = (1 << 1), |
217 | MV_HP_ERRATA_60X1B0 = (1 << 2), | |
218 | MV_HP_ERRATA_50XXB0 = (1 << 3), | |
219 | MV_HP_ERRATA_50XXB1 = (1 << 4), | |
220 | MV_HP_ERRATA_50XXB2 = (1 << 5), | |
221 | MV_HP_50XX = (1 << 6), | |
20f733e7 | 222 | |
31961943 BR |
223 | /* Port private flags (pp_flags) */ |
224 | MV_PP_FLAG_EDMA_EN = (1 << 0), | |
225 | MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), | |
20f733e7 BR |
226 | }; |
227 | ||
bca1c4eb JG |
228 | #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX) |
229 | #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0) | |
230 | ||
095fec88 JG |
231 | enum { |
232 | /* Our DMA boundary is determined by an ePRD being unable to handle | |
233 | * anything larger than 64KB | |
234 | */ | |
235 | MV_DMA_BOUNDARY = 0xffffU, | |
236 | ||
237 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, | |
238 | ||
239 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, | |
240 | }; | |
241 | ||
31961943 BR |
242 | /* Command ReQuest Block: 32B */ |
243 | struct mv_crqb { | |
244 | u32 sg_addr; | |
245 | u32 sg_addr_hi; | |
246 | u16 ctrl_flags; | |
247 | u16 ata_cmd[11]; | |
248 | }; | |
20f733e7 | 249 | |
31961943 BR |
250 | /* Command ResPonse Block: 8B */ |
251 | struct mv_crpb { | |
252 | u16 id; | |
253 | u16 flags; | |
254 | u32 tmstmp; | |
20f733e7 BR |
255 | }; |
256 | ||
31961943 BR |
257 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
258 | struct mv_sg { | |
259 | u32 addr; | |
260 | u32 flags_size; | |
261 | u32 addr_hi; | |
262 | u32 reserved; | |
263 | }; | |
20f733e7 | 264 | |
31961943 BR |
265 | struct mv_port_priv { |
266 | struct mv_crqb *crqb; | |
267 | dma_addr_t crqb_dma; | |
268 | struct mv_crpb *crpb; | |
269 | dma_addr_t crpb_dma; | |
270 | struct mv_sg *sg_tbl; | |
271 | dma_addr_t sg_tbl_dma; | |
272 | ||
273 | unsigned req_producer; /* cp of req_in_ptr */ | |
274 | unsigned rsp_consumer; /* cp of rsp_out_ptr */ | |
275 | u32 pp_flags; | |
276 | }; | |
277 | ||
bca1c4eb JG |
278 | struct mv_port_signal { |
279 | u32 amps; | |
280 | u32 pre; | |
281 | }; | |
282 | ||
31961943 BR |
283 | struct mv_host_priv { |
284 | u32 hp_flags; | |
bca1c4eb | 285 | struct mv_port_signal signal[8]; |
20f733e7 BR |
286 | }; |
287 | ||
288 | static void mv_irq_clear(struct ata_port *ap); | |
289 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); | |
290 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | |
291 | static void mv_phy_reset(struct ata_port *ap); | |
31961943 BR |
292 | static void mv_host_stop(struct ata_host_set *host_set); |
293 | static int mv_port_start(struct ata_port *ap); | |
294 | static void mv_port_stop(struct ata_port *ap); | |
295 | static void mv_qc_prep(struct ata_queued_cmd *qc); | |
296 | static int mv_qc_issue(struct ata_queued_cmd *qc); | |
20f733e7 BR |
297 | static irqreturn_t mv_interrupt(int irq, void *dev_instance, |
298 | struct pt_regs *regs); | |
31961943 | 299 | static void mv_eng_timeout(struct ata_port *ap); |
20f733e7 BR |
300 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
301 | ||
193515d5 | 302 | static struct scsi_host_template mv_sht = { |
20f733e7 BR |
303 | .module = THIS_MODULE, |
304 | .name = DRV_NAME, | |
305 | .ioctl = ata_scsi_ioctl, | |
306 | .queuecommand = ata_scsi_queuecmd, | |
307 | .eh_strategy_handler = ata_scsi_error, | |
31961943 | 308 | .can_queue = MV_USE_Q_DEPTH, |
20f733e7 | 309 | .this_id = ATA_SHT_THIS_ID, |
31961943 | 310 | .sg_tablesize = MV_MAX_SG_CT, |
20f733e7 BR |
311 | .max_sectors = ATA_MAX_SECTORS, |
312 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
313 | .emulated = ATA_SHT_EMULATED, | |
31961943 | 314 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
20f733e7 BR |
315 | .proc_name = DRV_NAME, |
316 | .dma_boundary = MV_DMA_BOUNDARY, | |
317 | .slave_configure = ata_scsi_slave_config, | |
318 | .bios_param = ata_std_bios_param, | |
319 | .ordered_flush = 1, | |
320 | }; | |
321 | ||
057ace5e | 322 | static const struct ata_port_operations mv_ops = { |
20f733e7 BR |
323 | .port_disable = ata_port_disable, |
324 | ||
325 | .tf_load = ata_tf_load, | |
326 | .tf_read = ata_tf_read, | |
327 | .check_status = ata_check_status, | |
328 | .exec_command = ata_exec_command, | |
329 | .dev_select = ata_std_dev_select, | |
330 | ||
331 | .phy_reset = mv_phy_reset, | |
332 | ||
31961943 BR |
333 | .qc_prep = mv_qc_prep, |
334 | .qc_issue = mv_qc_issue, | |
20f733e7 | 335 | |
31961943 | 336 | .eng_timeout = mv_eng_timeout, |
20f733e7 BR |
337 | |
338 | .irq_handler = mv_interrupt, | |
339 | .irq_clear = mv_irq_clear, | |
340 | ||
341 | .scr_read = mv_scr_read, | |
342 | .scr_write = mv_scr_write, | |
343 | ||
31961943 BR |
344 | .port_start = mv_port_start, |
345 | .port_stop = mv_port_stop, | |
346 | .host_stop = mv_host_stop, | |
20f733e7 BR |
347 | }; |
348 | ||
349 | static struct ata_port_info mv_port_info[] = { | |
350 | { /* chip_504x */ | |
351 | .sht = &mv_sht, | |
31961943 BR |
352 | .host_flags = MV_COMMON_FLAGS, |
353 | .pio_mask = 0x1f, /* pio0-4 */ | |
354 | .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */ | |
20f733e7 BR |
355 | .port_ops = &mv_ops, |
356 | }, | |
357 | { /* chip_508x */ | |
358 | .sht = &mv_sht, | |
31961943 BR |
359 | .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), |
360 | .pio_mask = 0x1f, /* pio0-4 */ | |
361 | .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */ | |
20f733e7 BR |
362 | .port_ops = &mv_ops, |
363 | }, | |
364 | { /* chip_604x */ | |
365 | .sht = &mv_sht, | |
31961943 BR |
366 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), |
367 | .pio_mask = 0x1f, /* pio0-4 */ | |
368 | .udma_mask = 0x7f, /* udma0-6 */ | |
20f733e7 BR |
369 | .port_ops = &mv_ops, |
370 | }, | |
371 | { /* chip_608x */ | |
372 | .sht = &mv_sht, | |
8b260248 | 373 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
31961943 BR |
374 | MV_FLAG_DUAL_HC), |
375 | .pio_mask = 0x1f, /* pio0-4 */ | |
376 | .udma_mask = 0x7f, /* udma0-6 */ | |
20f733e7 BR |
377 | .port_ops = &mv_ops, |
378 | }, | |
379 | }; | |
380 | ||
3b7d697d | 381 | static const struct pci_device_id mv_pci_tbl[] = { |
bca1c4eb | 382 | #if 0 /* unusably broken right now */ |
20f733e7 BR |
383 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x}, |
384 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x}, | |
385 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x}, | |
386 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x}, | |
bca1c4eb | 387 | #endif |
20f733e7 BR |
388 | |
389 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x}, | |
390 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x}, | |
391 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x}, | |
392 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x}, | |
29179539 JG |
393 | |
394 | {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x}, | |
20f733e7 BR |
395 | {} /* terminate list */ |
396 | }; | |
397 | ||
398 | static struct pci_driver mv_pci_driver = { | |
399 | .name = DRV_NAME, | |
400 | .id_table = mv_pci_tbl, | |
401 | .probe = mv_init_one, | |
402 | .remove = ata_pci_remove_one, | |
403 | }; | |
404 | ||
405 | /* | |
406 | * Functions | |
407 | */ | |
408 | ||
409 | static inline void writelfl(unsigned long data, void __iomem *addr) | |
410 | { | |
411 | writel(data, addr); | |
412 | (void) readl(addr); /* flush to avoid PCI posted write */ | |
413 | } | |
414 | ||
20f733e7 BR |
415 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
416 | { | |
417 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); | |
418 | } | |
419 | ||
420 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) | |
421 | { | |
422 | return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) + | |
8b260248 | 423 | MV_SATAHC_ARBTR_REG_SZ + |
20f733e7 BR |
424 | ((port & MV_PORT_MASK) * MV_PORT_REG_SZ)); |
425 | } | |
426 | ||
427 | static inline void __iomem *mv_ap_base(struct ata_port *ap) | |
428 | { | |
429 | return mv_port_base(ap->host_set->mmio_base, ap->port_no); | |
430 | } | |
431 | ||
bca1c4eb | 432 | static inline int mv_get_hc_count(unsigned long host_flags) |
31961943 | 433 | { |
bca1c4eb | 434 | return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
31961943 BR |
435 | } |
436 | ||
437 | static void mv_irq_clear(struct ata_port *ap) | |
20f733e7 | 438 | { |
20f733e7 BR |
439 | } |
440 | ||
05b308e1 BR |
441 | /** |
442 | * mv_start_dma - Enable eDMA engine | |
443 | * @base: port base address | |
444 | * @pp: port private data | |
445 | * | |
446 | * Verify the local cache of the eDMA state is accurate with an | |
447 | * assert. | |
448 | * | |
449 | * LOCKING: | |
450 | * Inherited from caller. | |
451 | */ | |
afb0edd9 | 452 | static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp) |
20f733e7 | 453 | { |
afb0edd9 BR |
454 | if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) { |
455 | writelfl(EDMA_EN, base + EDMA_CMD_OFS); | |
456 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; | |
457 | } | |
458 | assert(EDMA_EN & readl(base + EDMA_CMD_OFS)); | |
20f733e7 BR |
459 | } |
460 | ||
05b308e1 BR |
461 | /** |
462 | * mv_stop_dma - Disable eDMA engine | |
463 | * @ap: ATA channel to manipulate | |
464 | * | |
465 | * Verify the local cache of the eDMA state is accurate with an | |
466 | * assert. | |
467 | * | |
468 | * LOCKING: | |
469 | * Inherited from caller. | |
470 | */ | |
31961943 | 471 | static void mv_stop_dma(struct ata_port *ap) |
20f733e7 | 472 | { |
31961943 BR |
473 | void __iomem *port_mmio = mv_ap_base(ap); |
474 | struct mv_port_priv *pp = ap->private_data; | |
31961943 BR |
475 | u32 reg; |
476 | int i; | |
477 | ||
afb0edd9 BR |
478 | if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) { |
479 | /* Disable EDMA if active. The disable bit auto clears. | |
31961943 | 480 | */ |
31961943 BR |
481 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
482 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
afb0edd9 BR |
483 | } else { |
484 | assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); | |
485 | } | |
8b260248 | 486 | |
31961943 BR |
487 | /* now properly wait for the eDMA to stop */ |
488 | for (i = 1000; i > 0; i--) { | |
489 | reg = readl(port_mmio + EDMA_CMD_OFS); | |
490 | if (!(EDMA_EN & reg)) { | |
491 | break; | |
492 | } | |
493 | udelay(100); | |
494 | } | |
495 | ||
31961943 BR |
496 | if (EDMA_EN & reg) { |
497 | printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id); | |
afb0edd9 | 498 | /* FIXME: Consider doing a reset here to recover */ |
31961943 | 499 | } |
20f733e7 BR |
500 | } |
501 | ||
8a70f8dc | 502 | #ifdef ATA_DEBUG |
31961943 | 503 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
20f733e7 | 504 | { |
31961943 BR |
505 | int b, w; |
506 | for (b = 0; b < bytes; ) { | |
507 | DPRINTK("%p: ", start + b); | |
508 | for (w = 0; b < bytes && w < 4; w++) { | |
509 | printk("%08x ",readl(start + b)); | |
510 | b += sizeof(u32); | |
511 | } | |
512 | printk("\n"); | |
513 | } | |
31961943 | 514 | } |
8a70f8dc JG |
515 | #endif |
516 | ||
31961943 BR |
517 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
518 | { | |
519 | #ifdef ATA_DEBUG | |
520 | int b, w; | |
521 | u32 dw; | |
522 | for (b = 0; b < bytes; ) { | |
523 | DPRINTK("%02x: ", b); | |
524 | for (w = 0; b < bytes && w < 4; w++) { | |
525 | (void) pci_read_config_dword(pdev,b,&dw); | |
526 | printk("%08x ",dw); | |
527 | b += sizeof(u32); | |
528 | } | |
529 | printk("\n"); | |
530 | } | |
531 | #endif | |
532 | } | |
533 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, | |
534 | struct pci_dev *pdev) | |
535 | { | |
536 | #ifdef ATA_DEBUG | |
8b260248 | 537 | void __iomem *hc_base = mv_hc_base(mmio_base, |
31961943 BR |
538 | port >> MV_PORT_HC_SHIFT); |
539 | void __iomem *port_base; | |
540 | int start_port, num_ports, p, start_hc, num_hcs, hc; | |
541 | ||
542 | if (0 > port) { | |
543 | start_hc = start_port = 0; | |
544 | num_ports = 8; /* shld be benign for 4 port devs */ | |
545 | num_hcs = 2; | |
546 | } else { | |
547 | start_hc = port >> MV_PORT_HC_SHIFT; | |
548 | start_port = port; | |
549 | num_ports = num_hcs = 1; | |
550 | } | |
8b260248 | 551 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
31961943 BR |
552 | num_ports > 1 ? num_ports - 1 : start_port); |
553 | ||
554 | if (NULL != pdev) { | |
555 | DPRINTK("PCI config space regs:\n"); | |
556 | mv_dump_pci_cfg(pdev, 0x68); | |
557 | } | |
558 | DPRINTK("PCI regs:\n"); | |
559 | mv_dump_mem(mmio_base+0xc00, 0x3c); | |
560 | mv_dump_mem(mmio_base+0xd00, 0x34); | |
561 | mv_dump_mem(mmio_base+0xf00, 0x4); | |
562 | mv_dump_mem(mmio_base+0x1d00, 0x6c); | |
563 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { | |
564 | hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT); | |
565 | DPRINTK("HC regs (HC %i):\n", hc); | |
566 | mv_dump_mem(hc_base, 0x1c); | |
567 | } | |
568 | for (p = start_port; p < start_port + num_ports; p++) { | |
569 | port_base = mv_port_base(mmio_base, p); | |
570 | DPRINTK("EDMA regs (port %i):\n",p); | |
571 | mv_dump_mem(port_base, 0x54); | |
572 | DPRINTK("SATA regs (port %i):\n",p); | |
573 | mv_dump_mem(port_base+0x300, 0x60); | |
574 | } | |
575 | #endif | |
20f733e7 BR |
576 | } |
577 | ||
578 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) | |
579 | { | |
580 | unsigned int ofs; | |
581 | ||
582 | switch (sc_reg_in) { | |
583 | case SCR_STATUS: | |
584 | case SCR_CONTROL: | |
585 | case SCR_ERROR: | |
586 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); | |
587 | break; | |
588 | case SCR_ACTIVE: | |
589 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ | |
590 | break; | |
591 | default: | |
592 | ofs = 0xffffffffU; | |
593 | break; | |
594 | } | |
595 | return ofs; | |
596 | } | |
597 | ||
598 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | |
599 | { | |
600 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
601 | ||
602 | if (0xffffffffU != ofs) { | |
603 | return readl(mv_ap_base(ap) + ofs); | |
604 | } else { | |
605 | return (u32) ofs; | |
606 | } | |
607 | } | |
608 | ||
609 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | |
610 | { | |
611 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
612 | ||
613 | if (0xffffffffU != ofs) { | |
614 | writelfl(val, mv_ap_base(ap) + ofs); | |
615 | } | |
616 | } | |
617 | ||
05b308e1 BR |
618 | /** |
619 | * mv_global_soft_reset - Perform the 6xxx global soft reset | |
620 | * @mmio_base: base address of the HBA | |
621 | * | |
622 | * This routine only applies to 6xxx parts. | |
623 | * | |
624 | * LOCKING: | |
625 | * Inherited from caller. | |
626 | */ | |
31961943 | 627 | static int mv_global_soft_reset(void __iomem *mmio_base) |
20f733e7 BR |
628 | { |
629 | void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS; | |
630 | int i, rc = 0; | |
631 | u32 t; | |
632 | ||
20f733e7 BR |
633 | /* Following procedure defined in PCI "main command and status |
634 | * register" table. | |
635 | */ | |
636 | t = readl(reg); | |
637 | writel(t | STOP_PCI_MASTER, reg); | |
638 | ||
31961943 BR |
639 | for (i = 0; i < 1000; i++) { |
640 | udelay(1); | |
20f733e7 BR |
641 | t = readl(reg); |
642 | if (PCI_MASTER_EMPTY & t) { | |
643 | break; | |
644 | } | |
645 | } | |
646 | if (!(PCI_MASTER_EMPTY & t)) { | |
31961943 BR |
647 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); |
648 | rc = 1; | |
20f733e7 BR |
649 | goto done; |
650 | } | |
651 | ||
652 | /* set reset */ | |
653 | i = 5; | |
654 | do { | |
655 | writel(t | GLOB_SFT_RST, reg); | |
656 | t = readl(reg); | |
657 | udelay(1); | |
658 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); | |
659 | ||
660 | if (!(GLOB_SFT_RST & t)) { | |
31961943 BR |
661 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); |
662 | rc = 1; | |
20f733e7 BR |
663 | goto done; |
664 | } | |
665 | ||
31961943 | 666 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ |
20f733e7 BR |
667 | i = 5; |
668 | do { | |
31961943 | 669 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); |
20f733e7 BR |
670 | t = readl(reg); |
671 | udelay(1); | |
672 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); | |
673 | ||
674 | if (GLOB_SFT_RST & t) { | |
31961943 BR |
675 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); |
676 | rc = 1; | |
20f733e7 | 677 | } |
31961943 | 678 | done: |
20f733e7 BR |
679 | return rc; |
680 | } | |
681 | ||
05b308e1 BR |
682 | /** |
683 | * mv_host_stop - Host specific cleanup/stop routine. | |
684 | * @host_set: host data structure | |
685 | * | |
686 | * Disable ints, cleanup host memory, call general purpose | |
687 | * host_stop. | |
688 | * | |
689 | * LOCKING: | |
690 | * Inherited from caller. | |
691 | */ | |
31961943 | 692 | static void mv_host_stop(struct ata_host_set *host_set) |
20f733e7 | 693 | { |
31961943 BR |
694 | struct mv_host_priv *hpriv = host_set->private_data; |
695 | struct pci_dev *pdev = to_pci_dev(host_set->dev); | |
696 | ||
697 | if (hpriv->hp_flags & MV_HP_FLAG_MSI) { | |
698 | pci_disable_msi(pdev); | |
699 | } else { | |
700 | pci_intx(pdev, 0); | |
701 | } | |
702 | kfree(hpriv); | |
703 | ata_host_stop(host_set); | |
704 | } | |
705 | ||
6037d6bb JG |
706 | static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev) |
707 | { | |
708 | dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma); | |
709 | } | |
710 | ||
05b308e1 BR |
711 | /** |
712 | * mv_port_start - Port specific init/start routine. | |
713 | * @ap: ATA channel to manipulate | |
714 | * | |
715 | * Allocate and point to DMA memory, init port private memory, | |
716 | * zero indices. | |
717 | * | |
718 | * LOCKING: | |
719 | * Inherited from caller. | |
720 | */ | |
31961943 BR |
721 | static int mv_port_start(struct ata_port *ap) |
722 | { | |
723 | struct device *dev = ap->host_set->dev; | |
bca1c4eb | 724 | struct mv_host_priv *hpriv = ap->host_set->private_data; |
31961943 BR |
725 | struct mv_port_priv *pp; |
726 | void __iomem *port_mmio = mv_ap_base(ap); | |
727 | void *mem; | |
728 | dma_addr_t mem_dma; | |
6037d6bb | 729 | int rc = -ENOMEM; |
31961943 BR |
730 | |
731 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
6037d6bb JG |
732 | if (!pp) |
733 | goto err_out; | |
31961943 BR |
734 | memset(pp, 0, sizeof(*pp)); |
735 | ||
8b260248 | 736 | mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, |
31961943 | 737 | GFP_KERNEL); |
6037d6bb JG |
738 | if (!mem) |
739 | goto err_out_pp; | |
31961943 BR |
740 | memset(mem, 0, MV_PORT_PRIV_DMA_SZ); |
741 | ||
6037d6bb JG |
742 | rc = ata_pad_alloc(ap, dev); |
743 | if (rc) | |
744 | goto err_out_priv; | |
745 | ||
8b260248 | 746 | /* First item in chunk of DMA memory: |
31961943 BR |
747 | * 32-slot command request table (CRQB), 32 bytes each in size |
748 | */ | |
749 | pp->crqb = mem; | |
750 | pp->crqb_dma = mem_dma; | |
751 | mem += MV_CRQB_Q_SZ; | |
752 | mem_dma += MV_CRQB_Q_SZ; | |
753 | ||
8b260248 | 754 | /* Second item: |
31961943 BR |
755 | * 32-slot command response table (CRPB), 8 bytes each in size |
756 | */ | |
757 | pp->crpb = mem; | |
758 | pp->crpb_dma = mem_dma; | |
759 | mem += MV_CRPB_Q_SZ; | |
760 | mem_dma += MV_CRPB_Q_SZ; | |
761 | ||
762 | /* Third item: | |
763 | * Table of scatter-gather descriptors (ePRD), 16 bytes each | |
764 | */ | |
765 | pp->sg_tbl = mem; | |
766 | pp->sg_tbl_dma = mem_dma; | |
767 | ||
8b260248 | 768 | writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT | |
31961943 BR |
769 | EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS); |
770 | ||
771 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); | |
8b260248 | 772 | writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, |
31961943 BR |
773 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
774 | ||
775 | writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); | |
776 | writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); | |
777 | ||
778 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); | |
8b260248 | 779 | writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, |
31961943 BR |
780 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
781 | ||
bca1c4eb JG |
782 | if (hpriv->hp_flags & MV_HP_ERRATA_60X1A1) { |
783 | u32 new_tmp, tmp; | |
784 | ||
785 | new_tmp = tmp = readl(port_mmio + EDMA_ARB_CFG); | |
786 | new_tmp &= ~EDMA_NO_SNOOP; | |
787 | if (new_tmp != tmp) | |
788 | writel(new_tmp, port_mmio + EDMA_ARB_CFG); | |
789 | } | |
790 | ||
31961943 BR |
791 | pp->req_producer = pp->rsp_consumer = 0; |
792 | ||
793 | /* Don't turn on EDMA here...do it before DMA commands only. Else | |
794 | * we'll be unable to send non-data, PIO, etc due to restricted access | |
795 | * to shadow regs. | |
796 | */ | |
797 | ap->private_data = pp; | |
798 | return 0; | |
6037d6bb JG |
799 | |
800 | err_out_priv: | |
801 | mv_priv_free(pp, dev); | |
802 | err_out_pp: | |
803 | kfree(pp); | |
804 | err_out: | |
805 | return rc; | |
31961943 BR |
806 | } |
807 | ||
05b308e1 BR |
808 | /** |
809 | * mv_port_stop - Port specific cleanup/stop routine. | |
810 | * @ap: ATA channel to manipulate | |
811 | * | |
812 | * Stop DMA, cleanup port memory. | |
813 | * | |
814 | * LOCKING: | |
815 | * This routine uses the host_set lock to protect the DMA stop. | |
816 | */ | |
31961943 BR |
817 | static void mv_port_stop(struct ata_port *ap) |
818 | { | |
819 | struct device *dev = ap->host_set->dev; | |
820 | struct mv_port_priv *pp = ap->private_data; | |
afb0edd9 | 821 | unsigned long flags; |
31961943 | 822 | |
afb0edd9 | 823 | spin_lock_irqsave(&ap->host_set->lock, flags); |
31961943 | 824 | mv_stop_dma(ap); |
afb0edd9 | 825 | spin_unlock_irqrestore(&ap->host_set->lock, flags); |
31961943 BR |
826 | |
827 | ap->private_data = NULL; | |
6037d6bb JG |
828 | ata_pad_free(ap, dev); |
829 | mv_priv_free(pp, dev); | |
31961943 BR |
830 | kfree(pp); |
831 | } | |
832 | ||
05b308e1 BR |
833 | /** |
834 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries | |
835 | * @qc: queued command whose SG list to source from | |
836 | * | |
837 | * Populate the SG list and mark the last entry. | |
838 | * | |
839 | * LOCKING: | |
840 | * Inherited from caller. | |
841 | */ | |
31961943 BR |
842 | static void mv_fill_sg(struct ata_queued_cmd *qc) |
843 | { | |
844 | struct mv_port_priv *pp = qc->ap->private_data; | |
972c26bd JG |
845 | unsigned int i = 0; |
846 | struct scatterlist *sg; | |
31961943 | 847 | |
972c26bd | 848 | ata_for_each_sg(sg, qc) { |
31961943 BR |
849 | u32 sg_len; |
850 | dma_addr_t addr; | |
851 | ||
972c26bd JG |
852 | addr = sg_dma_address(sg); |
853 | sg_len = sg_dma_len(sg); | |
31961943 BR |
854 | |
855 | pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff); | |
856 | pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
857 | assert(0 == (sg_len & ~MV_DMA_BOUNDARY)); | |
858 | pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len); | |
972c26bd JG |
859 | if (ata_sg_is_last(sg, qc)) |
860 | pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); | |
861 | ||
862 | i++; | |
31961943 BR |
863 | } |
864 | } | |
865 | ||
866 | static inline unsigned mv_inc_q_index(unsigned *index) | |
867 | { | |
868 | *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK; | |
869 | return *index; | |
870 | } | |
871 | ||
872 | static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last) | |
873 | { | |
874 | *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | | |
875 | (last ? CRQB_CMD_LAST : 0); | |
876 | } | |
877 | ||
05b308e1 BR |
878 | /** |
879 | * mv_qc_prep - Host specific command preparation. | |
880 | * @qc: queued command to prepare | |
881 | * | |
882 | * This routine simply redirects to the general purpose routine | |
883 | * if command is not DMA. Else, it handles prep of the CRQB | |
884 | * (command request block), does some sanity checking, and calls | |
885 | * the SG load routine. | |
886 | * | |
887 | * LOCKING: | |
888 | * Inherited from caller. | |
889 | */ | |
31961943 BR |
890 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
891 | { | |
892 | struct ata_port *ap = qc->ap; | |
893 | struct mv_port_priv *pp = ap->private_data; | |
894 | u16 *cw; | |
895 | struct ata_taskfile *tf; | |
896 | u16 flags = 0; | |
897 | ||
898 | if (ATA_PROT_DMA != qc->tf.protocol) { | |
899 | return; | |
900 | } | |
20f733e7 | 901 | |
31961943 | 902 | /* the req producer index should be the same as we remember it */ |
8b260248 | 903 | assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> |
31961943 BR |
904 | EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == |
905 | pp->req_producer); | |
906 | ||
907 | /* Fill in command request block | |
908 | */ | |
909 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
910 | flags |= CRQB_FLAG_READ; | |
911 | } | |
912 | assert(MV_MAX_Q_DEPTH > qc->tag); | |
913 | flags |= qc->tag << CRQB_TAG_SHIFT; | |
914 | ||
8b260248 | 915 | pp->crqb[pp->req_producer].sg_addr = |
31961943 | 916 | cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); |
8b260248 | 917 | pp->crqb[pp->req_producer].sg_addr_hi = |
31961943 BR |
918 | cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); |
919 | pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags); | |
920 | ||
921 | cw = &pp->crqb[pp->req_producer].ata_cmd[0]; | |
922 | tf = &qc->tf; | |
923 | ||
924 | /* Sadly, the CRQB cannot accomodate all registers--there are | |
925 | * only 11 bytes...so we must pick and choose required | |
926 | * registers based on the command. So, we drop feature and | |
927 | * hob_feature for [RW] DMA commands, but they are needed for | |
928 | * NCQ. NCQ will drop hob_nsect. | |
20f733e7 | 929 | */ |
31961943 BR |
930 | switch (tf->command) { |
931 | case ATA_CMD_READ: | |
932 | case ATA_CMD_READ_EXT: | |
933 | case ATA_CMD_WRITE: | |
934 | case ATA_CMD_WRITE_EXT: | |
935 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); | |
936 | break; | |
937 | #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ | |
938 | case ATA_CMD_FPDMA_READ: | |
939 | case ATA_CMD_FPDMA_WRITE: | |
8b260248 | 940 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
31961943 BR |
941 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
942 | break; | |
943 | #endif /* FIXME: remove this line when NCQ added */ | |
944 | default: | |
945 | /* The only other commands EDMA supports in non-queued and | |
946 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none | |
947 | * of which are defined/used by Linux. If we get here, this | |
948 | * driver needs work. | |
949 | * | |
950 | * FIXME: modify libata to give qc_prep a return value and | |
951 | * return error here. | |
952 | */ | |
953 | BUG_ON(tf->command); | |
954 | break; | |
955 | } | |
956 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); | |
957 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); | |
958 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); | |
959 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); | |
960 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); | |
961 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); | |
962 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); | |
963 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); | |
964 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ | |
965 | ||
966 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) { | |
967 | return; | |
968 | } | |
969 | mv_fill_sg(qc); | |
970 | } | |
971 | ||
05b308e1 BR |
972 | /** |
973 | * mv_qc_issue - Initiate a command to the host | |
974 | * @qc: queued command to start | |
975 | * | |
976 | * This routine simply redirects to the general purpose routine | |
977 | * if command is not DMA. Else, it sanity checks our local | |
978 | * caches of the request producer/consumer indices then enables | |
979 | * DMA and bumps the request producer index. | |
980 | * | |
981 | * LOCKING: | |
982 | * Inherited from caller. | |
983 | */ | |
31961943 BR |
984 | static int mv_qc_issue(struct ata_queued_cmd *qc) |
985 | { | |
986 | void __iomem *port_mmio = mv_ap_base(qc->ap); | |
987 | struct mv_port_priv *pp = qc->ap->private_data; | |
988 | u32 in_ptr; | |
989 | ||
990 | if (ATA_PROT_DMA != qc->tf.protocol) { | |
991 | /* We're about to send a non-EDMA capable command to the | |
992 | * port. Turn off EDMA so there won't be problems accessing | |
993 | * shadow block, etc registers. | |
994 | */ | |
995 | mv_stop_dma(qc->ap); | |
996 | return ata_qc_issue_prot(qc); | |
997 | } | |
998 | ||
999 | in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | |
1000 | ||
1001 | /* the req producer index should be the same as we remember it */ | |
1002 | assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == | |
1003 | pp->req_producer); | |
1004 | /* until we do queuing, the queue should be empty at this point */ | |
1005 | assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == | |
8b260248 | 1006 | ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >> |
31961943 BR |
1007 | EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); |
1008 | ||
1009 | mv_inc_q_index(&pp->req_producer); /* now incr producer index */ | |
1010 | ||
afb0edd9 | 1011 | mv_start_dma(port_mmio, pp); |
31961943 BR |
1012 | |
1013 | /* and write the request in pointer to kick the EDMA to life */ | |
1014 | in_ptr &= EDMA_REQ_Q_BASE_LO_MASK; | |
1015 | in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT; | |
1016 | writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
05b308e1 BR |
1021 | /** |
1022 | * mv_get_crpb_status - get status from most recently completed cmd | |
1023 | * @ap: ATA channel to manipulate | |
1024 | * | |
1025 | * This routine is for use when the port is in DMA mode, when it | |
1026 | * will be using the CRPB (command response block) method of | |
1027 | * returning command completion information. We assert indices | |
1028 | * are good, grab status, and bump the response consumer index to | |
1029 | * prove that we're up to date. | |
1030 | * | |
1031 | * LOCKING: | |
1032 | * Inherited from caller. | |
1033 | */ | |
31961943 BR |
1034 | static u8 mv_get_crpb_status(struct ata_port *ap) |
1035 | { | |
1036 | void __iomem *port_mmio = mv_ap_base(ap); | |
1037 | struct mv_port_priv *pp = ap->private_data; | |
1038 | u32 out_ptr; | |
1039 | ||
1040 | out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | |
1041 | ||
1042 | /* the response consumer index should be the same as we remember it */ | |
8b260248 | 1043 | assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == |
31961943 BR |
1044 | pp->rsp_consumer); |
1045 | ||
1046 | /* increment our consumer index... */ | |
1047 | pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer); | |
8b260248 | 1048 | |
31961943 | 1049 | /* and, until we do NCQ, there should only be 1 CRPB waiting */ |
8b260248 JG |
1050 | assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >> |
1051 | EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == | |
31961943 BR |
1052 | pp->rsp_consumer); |
1053 | ||
1054 | /* write out our inc'd consumer index so EDMA knows we're caught up */ | |
1055 | out_ptr &= EDMA_RSP_Q_BASE_LO_MASK; | |
1056 | out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT; | |
1057 | writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | |
1058 | ||
1059 | /* Return ATA status register for completed CRPB */ | |
1060 | return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT); | |
1061 | } | |
1062 | ||
05b308e1 BR |
1063 | /** |
1064 | * mv_err_intr - Handle error interrupts on the port | |
1065 | * @ap: ATA channel to manipulate | |
1066 | * | |
1067 | * In most cases, just clear the interrupt and move on. However, | |
1068 | * some cases require an eDMA reset, which is done right before | |
1069 | * the COMRESET in mv_phy_reset(). The SERR case requires a | |
1070 | * clear of pending errors in the SATA SERROR register. Finally, | |
1071 | * if the port disabled DMA, update our cached copy to match. | |
1072 | * | |
1073 | * LOCKING: | |
1074 | * Inherited from caller. | |
1075 | */ | |
31961943 BR |
1076 | static void mv_err_intr(struct ata_port *ap) |
1077 | { | |
1078 | void __iomem *port_mmio = mv_ap_base(ap); | |
1079 | u32 edma_err_cause, serr = 0; | |
20f733e7 BR |
1080 | |
1081 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1082 | ||
1083 | if (EDMA_ERR_SERR & edma_err_cause) { | |
1084 | serr = scr_read(ap, SCR_ERROR); | |
1085 | scr_write_flush(ap, SCR_ERROR, serr); | |
1086 | } | |
afb0edd9 BR |
1087 | if (EDMA_ERR_SELF_DIS & edma_err_cause) { |
1088 | struct mv_port_priv *pp = ap->private_data; | |
1089 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
1090 | } | |
1091 | DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x " | |
1092 | "SERR: 0x%08x\n", ap->id, edma_err_cause, serr); | |
20f733e7 BR |
1093 | |
1094 | /* Clear EDMA now that SERR cleanup done */ | |
1095 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1096 | ||
1097 | /* check for fatal here and recover if needed */ | |
1098 | if (EDMA_ERR_FATAL & edma_err_cause) { | |
1099 | mv_phy_reset(ap); | |
1100 | } | |
1101 | } | |
1102 | ||
05b308e1 BR |
1103 | /** |
1104 | * mv_host_intr - Handle all interrupts on the given host controller | |
1105 | * @host_set: host specific structure | |
1106 | * @relevant: port error bits relevant to this host controller | |
1107 | * @hc: which host controller we're to look at | |
1108 | * | |
1109 | * Read then write clear the HC interrupt status then walk each | |
1110 | * port connected to the HC and see if it needs servicing. Port | |
1111 | * success ints are reported in the HC interrupt status reg, the | |
1112 | * port error ints are reported in the higher level main | |
1113 | * interrupt status register and thus are passed in via the | |
1114 | * 'relevant' argument. | |
1115 | * | |
1116 | * LOCKING: | |
1117 | * Inherited from caller. | |
1118 | */ | |
20f733e7 BR |
1119 | static void mv_host_intr(struct ata_host_set *host_set, u32 relevant, |
1120 | unsigned int hc) | |
1121 | { | |
1122 | void __iomem *mmio = host_set->mmio_base; | |
1123 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); | |
1124 | struct ata_port *ap; | |
1125 | struct ata_queued_cmd *qc; | |
1126 | u32 hc_irq_cause; | |
31961943 | 1127 | int shift, port, port0, hard_port, handled; |
a7dac447 | 1128 | unsigned int err_mask; |
31961943 | 1129 | u8 ata_status = 0; |
20f733e7 BR |
1130 | |
1131 | if (hc == 0) { | |
1132 | port0 = 0; | |
1133 | } else { | |
1134 | port0 = MV_PORTS_PER_HC; | |
1135 | } | |
1136 | ||
1137 | /* we'll need the HC success int register in most cases */ | |
1138 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); | |
1139 | if (hc_irq_cause) { | |
31961943 | 1140 | writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
20f733e7 BR |
1141 | } |
1142 | ||
1143 | VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", | |
1144 | hc,relevant,hc_irq_cause); | |
1145 | ||
1146 | for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) { | |
1147 | ap = host_set->ports[port]; | |
1148 | hard_port = port & MV_PORT_MASK; /* range 0-3 */ | |
31961943 | 1149 | handled = 0; /* ensure ata_status is set if handled++ */ |
20f733e7 | 1150 | |
31961943 BR |
1151 | if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) { |
1152 | /* new CRPB on the queue; just one at a time until NCQ | |
1153 | */ | |
1154 | ata_status = mv_get_crpb_status(ap); | |
1155 | handled++; | |
1156 | } else if ((DEV_IRQ << hard_port) & hc_irq_cause) { | |
1157 | /* received ATA IRQ; read the status reg to clear INTRQ | |
20f733e7 BR |
1158 | */ |
1159 | ata_status = readb((void __iomem *) | |
1160 | ap->ioaddr.status_addr); | |
31961943 | 1161 | handled++; |
20f733e7 BR |
1162 | } |
1163 | ||
a7dac447 JG |
1164 | err_mask = ac_err_mask(ata_status); |
1165 | ||
31961943 | 1166 | shift = port << 1; /* (port * 2) */ |
20f733e7 BR |
1167 | if (port >= MV_PORTS_PER_HC) { |
1168 | shift++; /* skip bit 8 in the HC Main IRQ reg */ | |
1169 | } | |
1170 | if ((PORT0_ERR << shift) & relevant) { | |
1171 | mv_err_intr(ap); | |
a7dac447 | 1172 | err_mask |= AC_ERR_OTHER; |
31961943 | 1173 | handled++; |
20f733e7 | 1174 | } |
8b260248 | 1175 | |
31961943 | 1176 | if (handled && ap) { |
20f733e7 BR |
1177 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1178 | if (NULL != qc) { | |
1179 | VPRINTK("port %u IRQ found for qc, " | |
1180 | "ata_status 0x%x\n", port,ata_status); | |
20f733e7 | 1181 | /* mark qc status appropriately */ |
a7dac447 | 1182 | ata_qc_complete(qc, err_mask); |
20f733e7 BR |
1183 | } |
1184 | } | |
1185 | } | |
1186 | VPRINTK("EXIT\n"); | |
1187 | } | |
1188 | ||
05b308e1 | 1189 | /** |
8b260248 | 1190 | * mv_interrupt - |
05b308e1 BR |
1191 | * @irq: unused |
1192 | * @dev_instance: private data; in this case the host structure | |
1193 | * @regs: unused | |
1194 | * | |
1195 | * Read the read only register to determine if any host | |
1196 | * controllers have pending interrupts. If so, call lower level | |
1197 | * routine to handle. Also check for PCI errors which are only | |
1198 | * reported here. | |
1199 | * | |
8b260248 | 1200 | * LOCKING: |
05b308e1 BR |
1201 | * This routine holds the host_set lock while processing pending |
1202 | * interrupts. | |
1203 | */ | |
20f733e7 BR |
1204 | static irqreturn_t mv_interrupt(int irq, void *dev_instance, |
1205 | struct pt_regs *regs) | |
1206 | { | |
1207 | struct ata_host_set *host_set = dev_instance; | |
1208 | unsigned int hc, handled = 0, n_hcs; | |
31961943 | 1209 | void __iomem *mmio = host_set->mmio_base; |
20f733e7 BR |
1210 | u32 irq_stat; |
1211 | ||
20f733e7 | 1212 | irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS); |
20f733e7 BR |
1213 | |
1214 | /* check the cases where we either have nothing pending or have read | |
1215 | * a bogus register value which can indicate HW removal or PCI fault | |
1216 | */ | |
1217 | if (!irq_stat || (0xffffffffU == irq_stat)) { | |
1218 | return IRQ_NONE; | |
1219 | } | |
1220 | ||
31961943 | 1221 | n_hcs = mv_get_hc_count(host_set->ports[0]->flags); |
20f733e7 BR |
1222 | spin_lock(&host_set->lock); |
1223 | ||
1224 | for (hc = 0; hc < n_hcs; hc++) { | |
1225 | u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); | |
1226 | if (relevant) { | |
1227 | mv_host_intr(host_set, relevant, hc); | |
31961943 | 1228 | handled++; |
20f733e7 BR |
1229 | } |
1230 | } | |
1231 | if (PCI_ERR & irq_stat) { | |
31961943 BR |
1232 | printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n", |
1233 | readl(mmio + PCI_IRQ_CAUSE_OFS)); | |
1234 | ||
afb0edd9 | 1235 | DPRINTK("All regs @ PCI error\n"); |
31961943 | 1236 | mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev)); |
20f733e7 | 1237 | |
31961943 BR |
1238 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); |
1239 | handled++; | |
1240 | } | |
20f733e7 BR |
1241 | spin_unlock(&host_set->lock); |
1242 | ||
1243 | return IRQ_RETVAL(handled); | |
1244 | } | |
1245 | ||
ba3fe8fb JG |
1246 | static void mv_cfg_signal5(struct mv_host_priv *hpriv, int idx, |
1247 | void __iomem *mmio) | |
1248 | { | |
1249 | /* FIXME */ | |
1250 | } | |
1251 | ||
1252 | static void mv_enable_leds5(struct mv_host_priv *hpriv, void __iomem *mmio) | |
1253 | { | |
1254 | /* FIXME */ | |
1255 | } | |
1256 | ||
bca1c4eb JG |
1257 | static void mv_phy_errata5(struct ata_port *ap) |
1258 | { | |
1259 | /* FIXME */ | |
1260 | } | |
1261 | ||
ba3fe8fb JG |
1262 | static void mv_cfg_signal6(struct mv_host_priv *hpriv, int idx, |
1263 | void __iomem *mmio) | |
1264 | { | |
1265 | void __iomem *port_mmio; | |
1266 | u32 tmp; | |
1267 | ||
1268 | if (hpriv->hp_flags & MV_HP_ERRATA_60X1A1) { | |
1269 | hpriv->signal[idx].amps = 0x5 << 8; | |
1270 | hpriv->signal[idx].pre = 0x3 << 5; | |
1271 | return; | |
1272 | } | |
1273 | ||
1274 | assert (hpriv->hp_flags & MV_HP_ERRATA_60X1B0); | |
1275 | ||
1276 | tmp = readl(mmio + MV_RESET_CFG); | |
1277 | if ((tmp & (1 << 0)) == 0) { | |
1278 | hpriv->signal[idx].amps = 0x4 << 8; | |
1279 | hpriv->signal[idx].pre = 0x1 << 5; | |
1280 | return; | |
1281 | } | |
1282 | ||
1283 | port_mmio = mv_port_base(mmio, idx); | |
1284 | tmp = readl(port_mmio + PHY_MODE2); | |
1285 | ||
1286 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
1287 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
1288 | } | |
1289 | ||
1290 | static void mv_enable_leds6(struct mv_host_priv *hpriv, void __iomem *mmio) | |
1291 | { | |
1292 | if (hpriv->hp_flags & MV_HP_ERRATA_60X1A1) | |
1293 | writel(0x00020060, mmio + MV_GPIO_PORT_CTL); | |
1294 | ||
1295 | else if (hpriv->hp_flags & MV_HP_ERRATA_60X1B0) | |
1296 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL); | |
1297 | } | |
1298 | ||
bca1c4eb JG |
1299 | static void mv_phy_errata6(struct ata_port *ap) |
1300 | { | |
1301 | struct mv_host_priv *hpriv = ap->host_set->private_data; | |
1302 | u32 hp_flags = hpriv->hp_flags; | |
1303 | void __iomem *port_mmio = mv_ap_base(ap); | |
1304 | int fix_phy_mode4 = | |
1305 | hp_flags & (MV_HP_ERRATA_60X1A1 | MV_HP_ERRATA_60X1B0); | |
1306 | u32 m2; | |
1307 | ||
1308 | if (fix_phy_mode4) { | |
1309 | u32 tmp, m4; | |
1310 | ||
1311 | m4 = readl(port_mmio + PHY_MODE4); | |
1312 | tmp = readl(port_mmio + 0x310); | |
1313 | ||
1314 | m4 = (m4 & ~(1 << 1)) | (1 << 0); | |
1315 | ||
1316 | writel(m4, port_mmio + PHY_MODE4); | |
1317 | writel(tmp, port_mmio + 0x310); | |
1318 | } | |
1319 | ||
1320 | /* Revert values of pre-emphasis and signal amps to the saved ones */ | |
1321 | m2 = readl(port_mmio + PHY_MODE2); | |
1322 | ||
1323 | m2 &= ~MV_M2_PREAMP_MASK; | |
1324 | m2 |= hpriv->signal[ap->port_no].amps; | |
1325 | m2 |= hpriv->signal[ap->port_no].pre; | |
1326 | ||
1327 | writel(m2, port_mmio + PHY_MODE2); | |
1328 | } | |
1329 | ||
1330 | static void mv_phy_errata(struct ata_port *ap) | |
1331 | { | |
1332 | struct mv_host_priv *hpriv = ap->host_set->private_data; | |
1333 | ||
1334 | if (IS_50XX(hpriv)) | |
1335 | mv_phy_errata5(ap); | |
1336 | else | |
1337 | mv_phy_errata6(ap); | |
1338 | } | |
1339 | ||
05b308e1 BR |
1340 | /** |
1341 | * mv_phy_reset - Perform eDMA reset followed by COMRESET | |
1342 | * @ap: ATA channel to manipulate | |
1343 | * | |
1344 | * Part of this is taken from __sata_phy_reset and modified to | |
1345 | * not sleep since this routine gets called from interrupt level. | |
1346 | * | |
1347 | * LOCKING: | |
1348 | * Inherited from caller. This is coded to safe to call at | |
1349 | * interrupt level, i.e. it does not sleep. | |
31961943 | 1350 | */ |
20f733e7 BR |
1351 | static void mv_phy_reset(struct ata_port *ap) |
1352 | { | |
095fec88 | 1353 | struct mv_port_priv *pp = ap->private_data; |
bca1c4eb | 1354 | struct mv_host_priv *hpriv = ap->host_set->private_data; |
20f733e7 BR |
1355 | void __iomem *port_mmio = mv_ap_base(ap); |
1356 | struct ata_taskfile tf; | |
1357 | struct ata_device *dev = &ap->device[0]; | |
31961943 | 1358 | unsigned long timeout; |
20f733e7 BR |
1359 | |
1360 | VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); | |
1361 | ||
31961943 | 1362 | mv_stop_dma(ap); |
20f733e7 | 1363 | |
31961943 | 1364 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); |
bca1c4eb JG |
1365 | |
1366 | if (IS_60XX(hpriv)) { | |
1367 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); | |
1368 | ifctl |= (1 << 12) | (1 << 7); | |
1369 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); | |
1370 | } | |
1371 | ||
20f733e7 BR |
1372 | udelay(25); /* allow reset propagation */ |
1373 | ||
1374 | /* Spec never mentions clearing the bit. Marvell's driver does | |
1375 | * clear the bit, however. | |
1376 | */ | |
31961943 | 1377 | writelfl(0, port_mmio + EDMA_CMD_OFS); |
20f733e7 | 1378 | |
bca1c4eb JG |
1379 | mv_phy_errata(ap); |
1380 | ||
095fec88 | 1381 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " |
31961943 BR |
1382 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
1383 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | |
20f733e7 BR |
1384 | |
1385 | /* proceed to init communications via the scr_control reg */ | |
31961943 BR |
1386 | scr_write_flush(ap, SCR_CONTROL, 0x301); |
1387 | mdelay(1); | |
1388 | scr_write_flush(ap, SCR_CONTROL, 0x300); | |
1389 | timeout = jiffies + (HZ * 1); | |
1390 | do { | |
1391 | mdelay(10); | |
1392 | if ((scr_read(ap, SCR_STATUS) & 0xf) != 1) | |
1393 | break; | |
1394 | } while (time_before(jiffies, timeout)); | |
20f733e7 | 1395 | |
095fec88 JG |
1396 | mv_scr_write(ap, SCR_ERROR, mv_scr_read(ap, SCR_ERROR)); |
1397 | ||
1398 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " | |
31961943 BR |
1399 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
1400 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | |
1401 | ||
1402 | if (sata_dev_present(ap)) { | |
1403 | ata_port_probe(ap); | |
1404 | } else { | |
1405 | printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n", | |
1406 | ap->id, scr_read(ap, SCR_STATUS)); | |
1407 | ata_port_disable(ap); | |
20f733e7 BR |
1408 | return; |
1409 | } | |
31961943 | 1410 | ap->cbl = ATA_CBL_SATA; |
20f733e7 BR |
1411 | |
1412 | tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr); | |
1413 | tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr); | |
1414 | tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr); | |
1415 | tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr); | |
1416 | ||
1417 | dev->class = ata_dev_classify(&tf); | |
1418 | if (!ata_dev_present(dev)) { | |
1419 | VPRINTK("Port disabled post-sig: No device present.\n"); | |
1420 | ata_port_disable(ap); | |
1421 | } | |
095fec88 JG |
1422 | |
1423 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1424 | ||
1425 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
1426 | ||
bca1c4eb | 1427 | VPRINTK("EXIT\n"); |
20f733e7 BR |
1428 | } |
1429 | ||
05b308e1 BR |
1430 | /** |
1431 | * mv_eng_timeout - Routine called by libata when SCSI times out I/O | |
1432 | * @ap: ATA channel to manipulate | |
1433 | * | |
1434 | * Intent is to clear all pending error conditions, reset the | |
1435 | * chip/bus, fail the command, and move on. | |
1436 | * | |
1437 | * LOCKING: | |
1438 | * This routine holds the host_set lock while failing the command. | |
1439 | */ | |
31961943 BR |
1440 | static void mv_eng_timeout(struct ata_port *ap) |
1441 | { | |
1442 | struct ata_queued_cmd *qc; | |
1443 | unsigned long flags; | |
1444 | ||
1445 | printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id); | |
1446 | DPRINTK("All regs @ start of eng_timeout\n"); | |
8b260248 | 1447 | mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no, |
31961943 BR |
1448 | to_pci_dev(ap->host_set->dev)); |
1449 | ||
1450 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
1451 | printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", | |
8b260248 | 1452 | ap->host_set->mmio_base, ap, qc, qc->scsicmd, |
31961943 BR |
1453 | &qc->scsicmd->cmnd); |
1454 | ||
1455 | mv_err_intr(ap); | |
1456 | mv_phy_reset(ap); | |
1457 | ||
1458 | if (!qc) { | |
1459 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | |
1460 | ap->id); | |
1461 | } else { | |
1462 | /* hack alert! We cannot use the supplied completion | |
1463 | * function from inside the ->eh_strategy_handler() thread. | |
1464 | * libata is the only user of ->eh_strategy_handler() in | |
1465 | * any kernel, so the default scsi_done() assumes it is | |
1466 | * not being called from the SCSI EH. | |
1467 | */ | |
1468 | spin_lock_irqsave(&ap->host_set->lock, flags); | |
1469 | qc->scsidone = scsi_finish_command; | |
a7dac447 | 1470 | ata_qc_complete(qc, AC_ERR_OTHER); |
31961943 BR |
1471 | spin_unlock_irqrestore(&ap->host_set->lock, flags); |
1472 | } | |
1473 | } | |
1474 | ||
05b308e1 BR |
1475 | /** |
1476 | * mv_port_init - Perform some early initialization on a single port. | |
1477 | * @port: libata data structure storing shadow register addresses | |
1478 | * @port_mmio: base address of the port | |
1479 | * | |
1480 | * Initialize shadow register mmio addresses, clear outstanding | |
1481 | * interrupts on the port, and unmask interrupts for the future | |
1482 | * start of the port. | |
1483 | * | |
1484 | * LOCKING: | |
1485 | * Inherited from caller. | |
1486 | */ | |
31961943 | 1487 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
20f733e7 | 1488 | { |
31961943 BR |
1489 | unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS; |
1490 | unsigned serr_ofs; | |
1491 | ||
8b260248 | 1492 | /* PIO related setup |
31961943 BR |
1493 | */ |
1494 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); | |
8b260248 | 1495 | port->error_addr = |
31961943 BR |
1496 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
1497 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); | |
1498 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); | |
1499 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); | |
1500 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); | |
1501 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); | |
8b260248 | 1502 | port->status_addr = |
31961943 BR |
1503 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
1504 | /* special case: control/altstatus doesn't have ATA_REG_ address */ | |
1505 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; | |
1506 | ||
1507 | /* unused: */ | |
20f733e7 BR |
1508 | port->cmd_addr = port->bmdma_addr = port->scr_addr = 0; |
1509 | ||
31961943 BR |
1510 | /* Clear any currently outstanding port interrupt conditions */ |
1511 | serr_ofs = mv_scr_offset(SCR_ERROR); | |
1512 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); | |
1513 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1514 | ||
20f733e7 | 1515 | /* unmask all EDMA error interrupts */ |
31961943 | 1516 | writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); |
20f733e7 | 1517 | |
8b260248 | 1518 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
31961943 BR |
1519 | readl(port_mmio + EDMA_CFG_OFS), |
1520 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), | |
1521 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); | |
20f733e7 BR |
1522 | } |
1523 | ||
bca1c4eb JG |
1524 | static void mv_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
1525 | { | |
1526 | if (IS_50XX(hpriv)) | |
1527 | mv_enable_leds5(hpriv, mmio); | |
1528 | else | |
1529 | mv_enable_leds6(hpriv, mmio); | |
1530 | } | |
1531 | ||
bca1c4eb JG |
1532 | static int mv_cfg_errata(struct pci_dev *pdev, struct mv_host_priv *hpriv, |
1533 | unsigned int board_idx) | |
1534 | { | |
1535 | u8 rev_id; | |
1536 | u32 hp_flags = hpriv->hp_flags; | |
1537 | ||
1538 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
1539 | ||
1540 | switch(board_idx) { | |
1541 | case chip_504x: | |
1542 | case chip_508x: | |
1543 | hp_flags |= MV_HP_50XX; | |
1544 | ||
1545 | if (pdev->device == 0x5080) { | |
1546 | switch (rev_id) { | |
1547 | case 0x0: | |
1548 | dev_printk(KERN_WARNING, &pdev->dev, | |
1549 | "Applying B0 workarounds to unknown rev 0\n"); | |
1550 | /* fall through */ | |
1551 | case 0x1: | |
1552 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
1553 | break; | |
1554 | case 0x2: | |
1555 | hp_flags |= MV_HP_ERRATA_50XXB1; | |
1556 | break; | |
1557 | case 0x3: | |
1558 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
1559 | break; | |
1560 | default: | |
1561 | dev_printk(KERN_WARNING, &pdev->dev, | |
1562 | "Applying B2 workarounds to future rev\n"); | |
1563 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
1564 | break; | |
1565 | } | |
1566 | } else { | |
1567 | switch (rev_id) { | |
1568 | case 0x0: | |
1569 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
1570 | break; | |
1571 | case 0x1: | |
1572 | dev_printk(KERN_WARNING, &pdev->dev, | |
1573 | "Applying B1 workarounds to unknown rev 1\n"); | |
1574 | /* fall through */ | |
1575 | case 0x2: | |
1576 | hp_flags |= MV_HP_ERRATA_50XXB1; | |
1577 | break; | |
1578 | default: | |
1579 | dev_printk(KERN_WARNING, &pdev->dev, | |
1580 | "Applying B2 workarounds to future rev\n"); | |
1581 | /* fall through */ | |
1582 | case 0x3: | |
1583 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
1584 | break; | |
1585 | } | |
1586 | } | |
1587 | break; | |
1588 | ||
1589 | case chip_604x: | |
1590 | case chip_608x: | |
1591 | switch (rev_id) { | |
1592 | case 0x0: | |
1593 | dev_printk(KERN_WARNING, &pdev->dev, | |
1594 | "Applying A1 workarounds to unknown rev 0\n"); | |
1595 | /* fall through */ | |
1596 | case 0x1: | |
1597 | hp_flags |= MV_HP_ERRATA_60X1A1; | |
1598 | break; | |
1599 | default: | |
1600 | dev_printk(KERN_WARNING, &pdev->dev, | |
1601 | "Applying B0 workarounds to future rev\n"); | |
1602 | /* fall through */ | |
1603 | case 0x2: | |
1604 | hp_flags |= MV_HP_ERRATA_60X1B0; | |
1605 | break; | |
1606 | } | |
1607 | break; | |
1608 | ||
1609 | default: | |
1610 | printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx); | |
1611 | return 1; | |
1612 | } | |
1613 | ||
1614 | hpriv->hp_flags = hp_flags; | |
1615 | ||
1616 | return 0; | |
1617 | } | |
1618 | ||
05b308e1 BR |
1619 | /** |
1620 | * mv_host_init - Perform some early initialization of the host. | |
bca1c4eb | 1621 | * @pdev: host PCI device |
05b308e1 BR |
1622 | * @probe_ent: early data struct representing the host |
1623 | * | |
1624 | * If possible, do an early global reset of the host. Then do | |
1625 | * our port init and clear/unmask all/relevant host interrupts. | |
1626 | * | |
1627 | * LOCKING: | |
1628 | * Inherited from caller. | |
1629 | */ | |
bca1c4eb JG |
1630 | static int mv_host_init(struct pci_dev *pdev, struct ata_probe_ent *probe_ent, |
1631 | unsigned int board_idx) | |
20f733e7 BR |
1632 | { |
1633 | int rc = 0, n_hc, port, hc; | |
1634 | void __iomem *mmio = probe_ent->mmio_base; | |
1635 | void __iomem *port_mmio; | |
bca1c4eb JG |
1636 | struct mv_host_priv *hpriv = probe_ent->private_data; |
1637 | ||
1638 | rc = mv_cfg_errata(pdev, hpriv, board_idx); | |
1639 | if (rc) | |
1640 | goto done; | |
1641 | ||
1642 | n_hc = mv_get_hc_count(probe_ent->host_flags); | |
1643 | probe_ent->n_ports = MV_PORTS_PER_HC * n_hc; | |
1644 | ||
1645 | if (IS_50XX(hpriv)) { | |
1646 | for (port = 0; port < probe_ent->n_ports; port++) | |
1647 | mv_cfg_signal5(hpriv, port, mmio); | |
1648 | } else { | |
1649 | for (port = 0; port < probe_ent->n_ports; port++) | |
1650 | mv_cfg_signal6(hpriv, port, mmio); | |
1651 | } | |
20f733e7 | 1652 | |
8b260248 | 1653 | if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) && |
31961943 | 1654 | mv_global_soft_reset(probe_ent->mmio_base)) { |
20f733e7 BR |
1655 | rc = 1; |
1656 | goto done; | |
1657 | } | |
1658 | ||
bca1c4eb | 1659 | mv_enable_leds(hpriv, mmio); |
20f733e7 BR |
1660 | |
1661 | for (port = 0; port < probe_ent->n_ports; port++) { | |
1662 | port_mmio = mv_port_base(mmio, port); | |
31961943 | 1663 | mv_port_init(&probe_ent->port[port], port_mmio); |
20f733e7 BR |
1664 | } |
1665 | ||
1666 | for (hc = 0; hc < n_hc; hc++) { | |
31961943 BR |
1667 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
1668 | ||
1669 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " | |
1670 | "(before clear)=0x%08x\n", hc, | |
1671 | readl(hc_mmio + HC_CFG_OFS), | |
1672 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); | |
1673 | ||
1674 | /* Clear any currently outstanding hc interrupt conditions */ | |
1675 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); | |
20f733e7 BR |
1676 | } |
1677 | ||
31961943 BR |
1678 | /* Clear any currently outstanding host interrupt conditions */ |
1679 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); | |
1680 | ||
1681 | /* and unmask interrupt generation for host regs */ | |
1682 | writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS); | |
1683 | writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); | |
20f733e7 BR |
1684 | |
1685 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " | |
8b260248 | 1686 | "PCI int cause/mask=0x%08x/0x%08x\n", |
20f733e7 BR |
1687 | readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), |
1688 | readl(mmio + HC_MAIN_IRQ_MASK_OFS), | |
1689 | readl(mmio + PCI_IRQ_CAUSE_OFS), | |
1690 | readl(mmio + PCI_IRQ_MASK_OFS)); | |
bca1c4eb | 1691 | |
31961943 | 1692 | done: |
20f733e7 BR |
1693 | return rc; |
1694 | } | |
1695 | ||
05b308e1 BR |
1696 | /** |
1697 | * mv_print_info - Dump key info to kernel log for perusal. | |
1698 | * @probe_ent: early data struct representing the host | |
1699 | * | |
1700 | * FIXME: complete this. | |
1701 | * | |
1702 | * LOCKING: | |
1703 | * Inherited from caller. | |
1704 | */ | |
31961943 BR |
1705 | static void mv_print_info(struct ata_probe_ent *probe_ent) |
1706 | { | |
1707 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
1708 | struct mv_host_priv *hpriv = probe_ent->private_data; | |
1709 | u8 rev_id, scc; | |
1710 | const char *scc_s; | |
1711 | ||
1712 | /* Use this to determine the HW stepping of the chip so we know | |
1713 | * what errata to workaround | |
1714 | */ | |
1715 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
1716 | ||
1717 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); | |
1718 | if (scc == 0) | |
1719 | scc_s = "SCSI"; | |
1720 | else if (scc == 0x01) | |
1721 | scc_s = "RAID"; | |
1722 | else | |
1723 | scc_s = "unknown"; | |
1724 | ||
a9524a76 JG |
1725 | dev_printk(KERN_INFO, &pdev->dev, |
1726 | "%u slots %u ports %s mode IRQ via %s\n", | |
8b260248 | 1727 | (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, |
31961943 BR |
1728 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
1729 | } | |
1730 | ||
05b308e1 BR |
1731 | /** |
1732 | * mv_init_one - handle a positive probe of a Marvell host | |
1733 | * @pdev: PCI device found | |
1734 | * @ent: PCI device ID entry for the matched host | |
1735 | * | |
1736 | * LOCKING: | |
1737 | * Inherited from caller. | |
1738 | */ | |
20f733e7 BR |
1739 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1740 | { | |
1741 | static int printed_version = 0; | |
1742 | struct ata_probe_ent *probe_ent = NULL; | |
1743 | struct mv_host_priv *hpriv; | |
1744 | unsigned int board_idx = (unsigned int)ent->driver_data; | |
1745 | void __iomem *mmio_base; | |
31961943 | 1746 | int pci_dev_busy = 0, rc; |
20f733e7 | 1747 | |
a9524a76 JG |
1748 | if (!printed_version++) |
1749 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
20f733e7 | 1750 | |
20f733e7 BR |
1751 | rc = pci_enable_device(pdev); |
1752 | if (rc) { | |
1753 | return rc; | |
1754 | } | |
1755 | ||
1756 | rc = pci_request_regions(pdev, DRV_NAME); | |
1757 | if (rc) { | |
1758 | pci_dev_busy = 1; | |
1759 | goto err_out; | |
1760 | } | |
1761 | ||
20f733e7 BR |
1762 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); |
1763 | if (probe_ent == NULL) { | |
1764 | rc = -ENOMEM; | |
1765 | goto err_out_regions; | |
1766 | } | |
1767 | ||
1768 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
1769 | probe_ent->dev = pci_dev_to_dev(pdev); | |
1770 | INIT_LIST_HEAD(&probe_ent->node); | |
1771 | ||
31961943 | 1772 | mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0); |
20f733e7 BR |
1773 | if (mmio_base == NULL) { |
1774 | rc = -ENOMEM; | |
1775 | goto err_out_free_ent; | |
1776 | } | |
1777 | ||
1778 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
1779 | if (!hpriv) { | |
1780 | rc = -ENOMEM; | |
1781 | goto err_out_iounmap; | |
1782 | } | |
1783 | memset(hpriv, 0, sizeof(*hpriv)); | |
1784 | ||
1785 | probe_ent->sht = mv_port_info[board_idx].sht; | |
1786 | probe_ent->host_flags = mv_port_info[board_idx].host_flags; | |
1787 | probe_ent->pio_mask = mv_port_info[board_idx].pio_mask; | |
1788 | probe_ent->udma_mask = mv_port_info[board_idx].udma_mask; | |
1789 | probe_ent->port_ops = mv_port_info[board_idx].port_ops; | |
1790 | ||
1791 | probe_ent->irq = pdev->irq; | |
1792 | probe_ent->irq_flags = SA_SHIRQ; | |
1793 | probe_ent->mmio_base = mmio_base; | |
1794 | probe_ent->private_data = hpriv; | |
1795 | ||
1796 | /* initialize adapter */ | |
bca1c4eb | 1797 | rc = mv_host_init(pdev, probe_ent, board_idx); |
20f733e7 BR |
1798 | if (rc) { |
1799 | goto err_out_hpriv; | |
1800 | } | |
20f733e7 | 1801 | |
31961943 BR |
1802 | /* Enable interrupts */ |
1803 | if (pci_enable_msi(pdev) == 0) { | |
1804 | hpriv->hp_flags |= MV_HP_FLAG_MSI; | |
1805 | } else { | |
1806 | pci_intx(pdev, 1); | |
20f733e7 BR |
1807 | } |
1808 | ||
31961943 BR |
1809 | mv_dump_pci_cfg(pdev, 0x68); |
1810 | mv_print_info(probe_ent); | |
1811 | ||
1812 | if (ata_device_add(probe_ent) == 0) { | |
1813 | rc = -ENODEV; /* No devices discovered */ | |
1814 | goto err_out_dev_add; | |
1815 | } | |
20f733e7 | 1816 | |
31961943 | 1817 | kfree(probe_ent); |
20f733e7 BR |
1818 | return 0; |
1819 | ||
31961943 BR |
1820 | err_out_dev_add: |
1821 | if (MV_HP_FLAG_MSI & hpriv->hp_flags) { | |
1822 | pci_disable_msi(pdev); | |
1823 | } else { | |
1824 | pci_intx(pdev, 0); | |
1825 | } | |
1826 | err_out_hpriv: | |
20f733e7 | 1827 | kfree(hpriv); |
31961943 BR |
1828 | err_out_iounmap: |
1829 | pci_iounmap(pdev, mmio_base); | |
1830 | err_out_free_ent: | |
20f733e7 | 1831 | kfree(probe_ent); |
31961943 | 1832 | err_out_regions: |
20f733e7 | 1833 | pci_release_regions(pdev); |
31961943 | 1834 | err_out: |
20f733e7 BR |
1835 | if (!pci_dev_busy) { |
1836 | pci_disable_device(pdev); | |
1837 | } | |
1838 | ||
1839 | return rc; | |
1840 | } | |
1841 | ||
1842 | static int __init mv_init(void) | |
1843 | { | |
1844 | return pci_module_init(&mv_pci_driver); | |
1845 | } | |
1846 | ||
1847 | static void __exit mv_exit(void) | |
1848 | { | |
1849 | pci_unregister_driver(&mv_pci_driver); | |
1850 | } | |
1851 | ||
1852 | MODULE_AUTHOR("Brett Russ"); | |
1853 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); | |
1854 | MODULE_LICENSE("GPL"); | |
1855 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); | |
1856 | MODULE_VERSION(DRV_VERSION); | |
1857 | ||
1858 | module_init(mv_init); | |
1859 | module_exit(mv_exit); |