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1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/config.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 LT |
42 | #include <scsi/scsi_host.h> |
43 | #include <linux/libata.h> | |
44 | ||
45 | #define DRV_NAME "sata_sis" | |
af64371a | 46 | #define DRV_VERSION "0.6" |
1da177e4 LT |
47 | |
48 | enum { | |
49 | sis_180 = 0, | |
50 | SIS_SCR_PCI_BAR = 5, | |
51 | ||
52 | /* PCI configuration registers */ | |
53 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
54 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
f2c853bc AP |
55 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
56 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | |
57 | SIS_PMR = 0x90, /* port mapping register */ | |
8add7885 | 58 | SIS_PMR_COMBINED = 0x30, |
1da177e4 LT |
59 | |
60 | /* random bits */ | |
61 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
62 | ||
63 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
64 | }; | |
65 | ||
66 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
67 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
68 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
69 | ||
3b7d697d | 70 | static const struct pci_device_id sis_pci_tbl[] = { |
1da177e4 LT |
71 | { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 }, |
72 | { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 }, | |
f2c853bc | 73 | { PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 }, |
1da177e4 LT |
74 | { } /* terminate list */ |
75 | }; | |
76 | ||
77 | ||
78 | static struct pci_driver sis_pci_driver = { | |
79 | .name = DRV_NAME, | |
80 | .id_table = sis_pci_tbl, | |
81 | .probe = sis_init_one, | |
82 | .remove = ata_pci_remove_one, | |
83 | }; | |
84 | ||
193515d5 | 85 | static struct scsi_host_template sis_sht = { |
1da177e4 LT |
86 | .module = THIS_MODULE, |
87 | .name = DRV_NAME, | |
88 | .ioctl = ata_scsi_ioctl, | |
89 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
90 | .can_queue = ATA_DEF_QUEUE, |
91 | .this_id = ATA_SHT_THIS_ID, | |
92 | .sg_tablesize = ATA_MAX_PRD, | |
1da177e4 LT |
93 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
94 | .emulated = ATA_SHT_EMULATED, | |
95 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
96 | .proc_name = DRV_NAME, | |
97 | .dma_boundary = ATA_DMA_BOUNDARY, | |
98 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 99 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 100 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
101 | }; |
102 | ||
057ace5e | 103 | static const struct ata_port_operations sis_ops = { |
1da177e4 LT |
104 | .port_disable = ata_port_disable, |
105 | .tf_load = ata_tf_load, | |
106 | .tf_read = ata_tf_read, | |
107 | .check_status = ata_check_status, | |
108 | .exec_command = ata_exec_command, | |
109 | .dev_select = ata_std_dev_select, | |
110 | .phy_reset = sata_phy_reset, | |
111 | .bmdma_setup = ata_bmdma_setup, | |
112 | .bmdma_start = ata_bmdma_start, | |
113 | .bmdma_stop = ata_bmdma_stop, | |
114 | .bmdma_status = ata_bmdma_status, | |
115 | .qc_prep = ata_qc_prep, | |
116 | .qc_issue = ata_qc_issue_prot, | |
a6b2c5d4 | 117 | .data_xfer = ata_pio_data_xfer, |
1da177e4 LT |
118 | .eng_timeout = ata_eng_timeout, |
119 | .irq_handler = ata_interrupt, | |
120 | .irq_clear = ata_bmdma_irq_clear, | |
121 | .scr_read = sis_scr_read, | |
122 | .scr_write = sis_scr_write, | |
123 | .port_start = ata_port_start, | |
124 | .port_stop = ata_port_stop, | |
aa8f0dc6 | 125 | .host_stop = ata_host_stop, |
1da177e4 LT |
126 | }; |
127 | ||
128 | static struct ata_port_info sis_port_info = { | |
129 | .sht = &sis_sht, | |
130 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET | | |
131 | ATA_FLAG_NO_LEGACY, | |
132 | .pio_mask = 0x1f, | |
133 | .mwdma_mask = 0x7, | |
134 | .udma_mask = 0x7f, | |
135 | .port_ops = &sis_ops, | |
136 | }; | |
137 | ||
138 | ||
139 | MODULE_AUTHOR("Uwe Koziolek"); | |
140 | MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller"); | |
141 | MODULE_LICENSE("GPL"); | |
142 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
143 | MODULE_VERSION(DRV_VERSION); | |
144 | ||
f2c853bc | 145 | static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device) |
1da177e4 LT |
146 | { |
147 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); | |
148 | ||
8add7885 | 149 | if (port_no) { |
f2c853bc AP |
150 | if (device == 0x182) |
151 | addr += SIS182_SATA1_OFS; | |
152 | else | |
153 | addr += SIS180_SATA1_OFS; | |
8add7885 JG |
154 | } |
155 | ||
1da177e4 LT |
156 | return addr; |
157 | } | |
158 | ||
159 | static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg) | |
160 | { | |
161 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
f2c853bc | 162 | unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device); |
668e4bc7 | 163 | u32 val, val2 = 0; |
f2c853bc | 164 | u8 pmr; |
1da177e4 LT |
165 | |
166 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
167 | return 0xffffffff; | |
f2c853bc AP |
168 | |
169 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 170 | |
1da177e4 | 171 | pci_read_config_dword(pdev, cfg_addr, &val); |
f2c853bc | 172 | |
8add7885 | 173 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) |
f2c853bc AP |
174 | pci_read_config_dword(pdev, cfg_addr+0x10, &val2); |
175 | ||
176 | return val|val2; | |
1da177e4 LT |
177 | } |
178 | ||
179 | static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val) | |
180 | { | |
181 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
f2c853bc AP |
182 | unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device); |
183 | u8 pmr; | |
1da177e4 LT |
184 | |
185 | if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
186 | return; | |
f2c853bc AP |
187 | |
188 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 189 | |
1da177e4 | 190 | pci_write_config_dword(pdev, cfg_addr, val); |
f2c853bc AP |
191 | |
192 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) | |
193 | pci_write_config_dword(pdev, cfg_addr+0x10, val); | |
1da177e4 LT |
194 | } |
195 | ||
196 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
197 | { | |
f2c853bc | 198 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
8add7885 | 199 | u32 val, val2 = 0; |
f2c853bc AP |
200 | u8 pmr; |
201 | ||
1da177e4 LT |
202 | if (sc_reg > SCR_CONTROL) |
203 | return 0xffffffffU; | |
204 | ||
205 | if (ap->flags & SIS_FLAG_CFGSCR) | |
206 | return sis_scr_cfg_read(ap, sc_reg); | |
f2c853bc AP |
207 | |
208 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
209 | ||
210 | val = inl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
211 | ||
212 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) | |
8add7885 | 213 | val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); |
f2c853bc | 214 | |
8add7885 | 215 | return val | val2; |
1da177e4 LT |
216 | } |
217 | ||
218 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
219 | { | |
f2c853bc AP |
220 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
221 | u8 pmr; | |
222 | ||
1da177e4 LT |
223 | if (sc_reg > SCR_CONTROL) |
224 | return; | |
225 | ||
f2c853bc | 226 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
8add7885 | 227 | |
1da177e4 LT |
228 | if (ap->flags & SIS_FLAG_CFGSCR) |
229 | sis_scr_cfg_write(ap, sc_reg, val); | |
f2c853bc | 230 | else { |
1da177e4 | 231 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
f2c853bc AP |
232 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) |
233 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); | |
234 | } | |
1da177e4 LT |
235 | } |
236 | ||
1da177e4 LT |
237 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
238 | { | |
a9524a76 | 239 | static int printed_version; |
1da177e4 LT |
240 | struct ata_probe_ent *probe_ent = NULL; |
241 | int rc; | |
242 | u32 genctl; | |
243 | struct ata_port_info *ppi; | |
244 | int pci_dev_busy = 0; | |
f2c853bc AP |
245 | u8 pmr; |
246 | u8 port2_start; | |
1da177e4 | 247 | |
a9524a76 JG |
248 | if (!printed_version++) |
249 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
250 | ||
1da177e4 LT |
251 | rc = pci_enable_device(pdev); |
252 | if (rc) | |
253 | return rc; | |
254 | ||
255 | rc = pci_request_regions(pdev, DRV_NAME); | |
256 | if (rc) { | |
257 | pci_dev_busy = 1; | |
258 | goto err_out; | |
259 | } | |
260 | ||
261 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
262 | if (rc) | |
263 | goto err_out_regions; | |
264 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
265 | if (rc) | |
266 | goto err_out_regions; | |
267 | ||
268 | ppi = &sis_port_info; | |
47a86593 | 269 | probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); |
1da177e4 LT |
270 | if (!probe_ent) { |
271 | rc = -ENOMEM; | |
272 | goto err_out_regions; | |
273 | } | |
274 | ||
275 | /* check and see if the SCRs are in IO space or PCI cfg space */ | |
276 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
277 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
278 | probe_ent->host_flags |= SIS_FLAG_CFGSCR; | |
8a60a071 | 279 | |
1da177e4 LT |
280 | /* if hardware thinks SCRs are in IO space, but there are |
281 | * no IO resources assigned, change to PCI cfg space. | |
282 | */ | |
283 | if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) && | |
284 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || | |
285 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
286 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
287 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
288 | probe_ent->host_flags |= SIS_FLAG_CFGSCR; | |
289 | } | |
290 | ||
f2c853bc AP |
291 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
292 | if (ent->device != 0x182) { | |
293 | if ((pmr & SIS_PMR_COMBINED) == 0) { | |
a9524a76 JG |
294 | dev_printk(KERN_INFO, &pdev->dev, |
295 | "Detected SiS 180/181 chipset in SATA mode\n"); | |
39eb936c | 296 | port2_start = 64; |
f2c853bc AP |
297 | } |
298 | else { | |
a9524a76 JG |
299 | dev_printk(KERN_INFO, &pdev->dev, |
300 | "Detected SiS 180/181 chipset in combined mode\n"); | |
f2c853bc AP |
301 | port2_start=0; |
302 | } | |
303 | } | |
304 | else { | |
a9524a76 | 305 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182 chipset\n"); |
f2c853bc AP |
306 | port2_start = 0x20; |
307 | } | |
308 | ||
1da177e4 LT |
309 | if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) { |
310 | probe_ent->port[0].scr_addr = | |
311 | pci_resource_start(pdev, SIS_SCR_PCI_BAR); | |
312 | probe_ent->port[1].scr_addr = | |
f2c853bc | 313 | pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start; |
1da177e4 LT |
314 | } |
315 | ||
316 | pci_set_master(pdev); | |
a04ce0ff | 317 | pci_intx(pdev, 1); |
1da177e4 LT |
318 | |
319 | /* FIXME: check ata_device_add return value */ | |
320 | ata_device_add(probe_ent); | |
321 | kfree(probe_ent); | |
322 | ||
323 | return 0; | |
324 | ||
325 | err_out_regions: | |
326 | pci_release_regions(pdev); | |
327 | ||
328 | err_out: | |
329 | if (!pci_dev_busy) | |
330 | pci_disable_device(pdev); | |
331 | return rc; | |
332 | ||
333 | } | |
334 | ||
335 | static int __init sis_init(void) | |
336 | { | |
337 | return pci_module_init(&sis_pci_driver); | |
338 | } | |
339 | ||
340 | static void __exit sis_exit(void) | |
341 | { | |
342 | pci_unregister_driver(&sis_pci_driver); | |
343 | } | |
344 | ||
345 | module_init(sis_init); | |
346 | module_exit(sis_exit); | |
347 |