]>
Commit | Line | Data |
---|---|---|
2d0cfb52 PG |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2005 Silicon Graphics, Inc. All Rights Reserved. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * This file contains a module version of the ioc3 serial driver. This | |
11 | * includes all the support functions needed (support functions, etc.) | |
12 | * and the serial driver itself. | |
13 | */ | |
14 | #include <linux/errno.h> | |
15 | #include <linux/tty.h> | |
16 | #include <linux/serial.h> | |
17 | #include <linux/circ_buf.h> | |
18 | #include <linux/serial_reg.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/serial_core.h> | |
22 | #include <linux/ioc3.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
2d0cfb52 PG |
24 | |
25 | /* | |
26 | * Interesting things about the ioc3 | |
27 | */ | |
28 | ||
29 | #define LOGICAL_PORTS 2 /* rs232(0) and rs422(1) */ | |
30 | #define PORTS_PER_CARD 2 | |
31 | #define LOGICAL_PORTS_PER_CARD (PORTS_PER_CARD * LOGICAL_PORTS) | |
32 | #define MAX_CARDS 8 | |
33 | #define MAX_LOGICAL_PORTS (LOGICAL_PORTS_PER_CARD * MAX_CARDS) | |
34 | ||
35 | /* determine given the sio_ir what port it applies to */ | |
36 | #define GET_PORT_FROM_SIO_IR(_x) (_x & SIO_IR_SA) ? 0 : 1 | |
37 | ||
38 | ||
39 | /* | |
40 | * we have 2 logical ports (rs232, rs422) for each physical port | |
41 | * evens are rs232, odds are rs422 | |
42 | */ | |
43 | #define GET_PHYSICAL_PORT(_x) ((_x) >> 1) | |
44 | #define GET_LOGICAL_PORT(_x) ((_x) & 1) | |
45 | #define IS_PHYSICAL_PORT(_x) !((_x) & 1) | |
46 | #define IS_RS232(_x) !((_x) & 1) | |
47 | ||
48 | static unsigned int Num_of_ioc3_cards; | |
49 | static unsigned int Submodule_slot; | |
50 | ||
51 | /* defining this will get you LOTS of great debug info */ | |
52 | //#define DEBUG_INTERRUPTS | |
53 | #define DPRINT_CONFIG(_x...) ; | |
54 | //#define DPRINT_CONFIG(_x...) printk _x | |
55 | #define NOT_PROGRESS() ; | |
71cc2c21 | 56 | //#define NOT_PROGRESS() printk("%s : fails %d\n", __func__, __LINE__) |
2d0cfb52 PG |
57 | |
58 | /* number of characters we want to transmit to the lower level at a time */ | |
59 | #define MAX_CHARS 256 | |
60 | #define FIFO_SIZE (MAX_CHARS-1) /* it's a uchar */ | |
61 | ||
62 | /* Device name we're using */ | |
63 | #define DEVICE_NAME "ttySIOC" | |
64 | #define DEVICE_MAJOR 204 | |
65 | #define DEVICE_MINOR 116 | |
66 | ||
67 | /* flags for next_char_state */ | |
68 | #define NCS_BREAK 0x1 | |
69 | #define NCS_PARITY 0x2 | |
70 | #define NCS_FRAMING 0x4 | |
71 | #define NCS_OVERRUN 0x8 | |
72 | ||
73 | /* cause we need SOME parameters ... */ | |
74 | #define MIN_BAUD_SUPPORTED 1200 | |
75 | #define MAX_BAUD_SUPPORTED 115200 | |
76 | ||
77 | /* protocol types supported */ | |
78 | #define PROTO_RS232 0 | |
79 | #define PROTO_RS422 1 | |
80 | ||
81 | /* Notification types */ | |
82 | #define N_DATA_READY 0x01 | |
83 | #define N_OUTPUT_LOWAT 0x02 | |
84 | #define N_BREAK 0x04 | |
85 | #define N_PARITY_ERROR 0x08 | |
86 | #define N_FRAMING_ERROR 0x10 | |
87 | #define N_OVERRUN_ERROR 0x20 | |
88 | #define N_DDCD 0x40 | |
89 | #define N_DCTS 0x80 | |
90 | ||
91 | #define N_ALL_INPUT (N_DATA_READY | N_BREAK \ | |
92 | | N_PARITY_ERROR | N_FRAMING_ERROR \ | |
93 | | N_OVERRUN_ERROR | N_DDCD | N_DCTS) | |
94 | ||
95 | #define N_ALL_OUTPUT N_OUTPUT_LOWAT | |
96 | ||
97 | #define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR \ | |
98 | | N_OVERRUN_ERROR) | |
99 | ||
100 | #define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK \ | |
101 | | N_PARITY_ERROR | N_FRAMING_ERROR \ | |
102 | | N_OVERRUN_ERROR | N_DDCD | N_DCTS) | |
103 | ||
104 | #define SER_CLK_SPEED(prediv) ((22000000 << 1) / prediv) | |
105 | #define SER_DIVISOR(x, clk) (((clk) + (x) * 8) / ((x) * 16)) | |
106 | #define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div)) | |
107 | ||
108 | /* Some masks */ | |
109 | #define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \ | |
110 | | UART_LCR_WLEN7 | UART_LCR_WLEN8) | |
111 | #define LCR_MASK_STOP_BITS (UART_LCR_STOP) | |
112 | ||
113 | #define PENDING(_a, _p) (readl(&(_p)->vma->sio_ir) & (_a)->ic_enable) | |
114 | ||
115 | #define RING_BUF_SIZE 4096 | |
116 | #define BUF_SIZE_BIT SBBR_L_SIZE | |
117 | #define PROD_CONS_MASK PROD_CONS_PTR_4K | |
118 | ||
119 | #define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4) | |
120 | ||
121 | /* driver specific - one per card */ | |
122 | struct ioc3_card { | |
123 | struct { | |
124 | /* uart ports are allocated here */ | |
125 | struct uart_port icp_uart_port[LOGICAL_PORTS]; | |
126 | /* the ioc3_port used for this port */ | |
127 | struct ioc3_port *icp_port; | |
128 | } ic_port[PORTS_PER_CARD]; | |
129 | /* currently enabled interrupts */ | |
130 | uint32_t ic_enable; | |
131 | }; | |
132 | ||
133 | /* Local port info for each IOC3 serial port */ | |
134 | struct ioc3_port { | |
135 | /* handy reference material */ | |
136 | struct uart_port *ip_port; | |
137 | struct ioc3_card *ip_card; | |
138 | struct ioc3_driver_data *ip_idd; | |
139 | struct ioc3_submodule *ip_is; | |
140 | ||
141 | /* pci mem addresses for this port */ | |
142 | struct ioc3_serialregs __iomem *ip_serial_regs; | |
143 | struct ioc3_uartregs __iomem *ip_uart_regs; | |
144 | ||
145 | /* Ring buffer page for this port */ | |
146 | dma_addr_t ip_dma_ringbuf; | |
147 | /* vaddr of ring buffer */ | |
148 | struct ring_buffer *ip_cpu_ringbuf; | |
149 | ||
150 | /* Rings for this port */ | |
151 | struct ring *ip_inring; | |
152 | struct ring *ip_outring; | |
153 | ||
154 | /* Hook to port specific values */ | |
155 | struct port_hooks *ip_hooks; | |
156 | ||
157 | spinlock_t ip_lock; | |
158 | ||
159 | /* Various rx/tx parameters */ | |
160 | int ip_baud; | |
161 | int ip_tx_lowat; | |
162 | int ip_rx_timeout; | |
163 | ||
164 | /* Copy of notification bits */ | |
165 | int ip_notify; | |
166 | ||
167 | /* Shadow copies of various registers so we don't need to PIO | |
168 | * read them constantly | |
169 | */ | |
170 | uint32_t ip_sscr; | |
171 | uint32_t ip_tx_prod; | |
172 | uint32_t ip_rx_cons; | |
173 | unsigned char ip_flags; | |
174 | }; | |
175 | ||
176 | /* tx low water mark. We need to notify the driver whenever tx is getting | |
177 | * close to empty so it can refill the tx buffer and keep things going. | |
178 | * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll | |
179 | * have no trouble getting in more chars in time (I certainly hope so). | |
180 | */ | |
181 | #define TX_LOWAT_LATENCY 1000 | |
182 | #define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY) | |
183 | #define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ) | |
184 | ||
185 | /* Flags per port */ | |
186 | #define INPUT_HIGH 0x01 | |
187 | /* used to signify that we have turned off the rx_high | |
188 | * temporarily - we need to drain the fifo and don't | |
189 | * want to get blasted with interrupts. | |
190 | */ | |
191 | #define DCD_ON 0x02 | |
192 | /* DCD state is on */ | |
193 | #define LOWAT_WRITTEN 0x04 | |
194 | #define READ_ABORTED 0x08 | |
195 | /* the read was aborted - used to avaoid infinate looping | |
196 | * in the interrupt handler | |
197 | */ | |
198 | #define INPUT_ENABLE 0x10 | |
199 | ||
200 | /* Since each port has different register offsets and bitmasks | |
201 | * for everything, we'll store those that we need in tables so we | |
202 | * don't have to be constantly checking the port we are dealing with. | |
203 | */ | |
204 | struct port_hooks { | |
205 | uint32_t intr_delta_dcd; | |
206 | uint32_t intr_delta_cts; | |
207 | uint32_t intr_tx_mt; | |
208 | uint32_t intr_rx_timer; | |
209 | uint32_t intr_rx_high; | |
210 | uint32_t intr_tx_explicit; | |
211 | uint32_t intr_clear; | |
212 | uint32_t intr_all; | |
213 | char rs422_select_pin; | |
214 | }; | |
215 | ||
216 | static struct port_hooks hooks_array[PORTS_PER_CARD] = { | |
217 | /* values for port A */ | |
218 | { | |
219 | .intr_delta_dcd = SIO_IR_SA_DELTA_DCD, | |
220 | .intr_delta_cts = SIO_IR_SA_DELTA_CTS, | |
221 | .intr_tx_mt = SIO_IR_SA_TX_MT, | |
222 | .intr_rx_timer = SIO_IR_SA_RX_TIMER, | |
223 | .intr_rx_high = SIO_IR_SA_RX_HIGH, | |
224 | .intr_tx_explicit = SIO_IR_SA_TX_EXPLICIT, | |
225 | .intr_clear = (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | |
226 | | SIO_IR_SA_RX_HIGH | |
227 | | SIO_IR_SA_RX_TIMER | |
228 | | SIO_IR_SA_DELTA_DCD | |
229 | | SIO_IR_SA_DELTA_CTS | |
230 | | SIO_IR_SA_INT | |
231 | | SIO_IR_SA_TX_EXPLICIT | |
232 | | SIO_IR_SA_MEMERR), | |
233 | .intr_all = SIO_IR_SA, | |
234 | .rs422_select_pin = GPPR_UARTA_MODESEL_PIN, | |
235 | }, | |
236 | ||
237 | /* values for port B */ | |
238 | { | |
239 | .intr_delta_dcd = SIO_IR_SB_DELTA_DCD, | |
240 | .intr_delta_cts = SIO_IR_SB_DELTA_CTS, | |
241 | .intr_tx_mt = SIO_IR_SB_TX_MT, | |
242 | .intr_rx_timer = SIO_IR_SB_RX_TIMER, | |
243 | .intr_rx_high = SIO_IR_SB_RX_HIGH, | |
244 | .intr_tx_explicit = SIO_IR_SB_TX_EXPLICIT, | |
245 | .intr_clear = (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | |
246 | | SIO_IR_SB_RX_HIGH | |
247 | | SIO_IR_SB_RX_TIMER | |
248 | | SIO_IR_SB_DELTA_DCD | |
249 | | SIO_IR_SB_DELTA_CTS | |
250 | | SIO_IR_SB_INT | |
251 | | SIO_IR_SB_TX_EXPLICIT | |
252 | | SIO_IR_SB_MEMERR), | |
253 | .intr_all = SIO_IR_SB, | |
254 | .rs422_select_pin = GPPR_UARTB_MODESEL_PIN, | |
255 | } | |
256 | }; | |
257 | ||
258 | struct ring_entry { | |
259 | union { | |
260 | struct { | |
261 | uint32_t alldata; | |
262 | uint32_t allsc; | |
263 | } all; | |
264 | struct { | |
265 | char data[4]; /* data bytes */ | |
266 | char sc[4]; /* status/control */ | |
267 | } s; | |
268 | } u; | |
269 | }; | |
270 | ||
271 | /* Test the valid bits in any of the 4 sc chars using "allsc" member */ | |
272 | #define RING_ANY_VALID \ | |
273 | ((uint32_t)(RXSB_MODEM_VALID | RXSB_DATA_VALID) * 0x01010101) | |
274 | ||
275 | #define ring_sc u.s.sc | |
276 | #define ring_data u.s.data | |
277 | #define ring_allsc u.all.allsc | |
278 | ||
279 | /* Number of entries per ring buffer. */ | |
280 | #define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry)) | |
281 | ||
282 | /* An individual ring */ | |
283 | struct ring { | |
284 | struct ring_entry entries[ENTRIES_PER_RING]; | |
285 | }; | |
286 | ||
287 | /* The whole enchilada */ | |
288 | struct ring_buffer { | |
289 | struct ring TX_A; | |
290 | struct ring RX_A; | |
291 | struct ring TX_B; | |
292 | struct ring RX_B; | |
293 | }; | |
294 | ||
295 | /* Get a ring from a port struct */ | |
296 | #define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh) | |
297 | ||
298 | /* for Infinite loop detection */ | |
299 | #define MAXITER 10000000 | |
300 | ||
301 | ||
302 | /** | |
303 | * set_baud - Baud rate setting code | |
304 | * @port: port to set | |
305 | * @baud: baud rate to use | |
306 | */ | |
307 | static int set_baud(struct ioc3_port *port, int baud) | |
308 | { | |
309 | int divisor; | |
310 | int actual_baud; | |
311 | int diff; | |
312 | int lcr, prediv; | |
313 | struct ioc3_uartregs __iomem *uart; | |
314 | ||
315 | for (prediv = 6; prediv < 64; prediv++) { | |
316 | divisor = SER_DIVISOR(baud, SER_CLK_SPEED(prediv)); | |
317 | if (!divisor) | |
318 | continue; /* invalid divisor */ | |
319 | actual_baud = DIVISOR_TO_BAUD(divisor, SER_CLK_SPEED(prediv)); | |
320 | ||
321 | diff = actual_baud - baud; | |
322 | if (diff < 0) | |
323 | diff = -diff; | |
324 | ||
325 | /* if we're within 1% we've found a match */ | |
326 | if (diff * 100 <= actual_baud) | |
327 | break; | |
328 | } | |
329 | ||
330 | /* if the above loop completed, we didn't match | |
331 | * the baud rate. give up. | |
332 | */ | |
333 | if (prediv == 64) { | |
334 | NOT_PROGRESS(); | |
335 | return 1; | |
336 | } | |
337 | ||
338 | uart = port->ip_uart_regs; | |
339 | lcr = readb(&uart->iu_lcr); | |
340 | ||
341 | writeb(lcr | UART_LCR_DLAB, &uart->iu_lcr); | |
342 | writeb((unsigned char)divisor, &uart->iu_dll); | |
343 | writeb((unsigned char)(divisor >> 8), &uart->iu_dlm); | |
344 | writeb((unsigned char)prediv, &uart->iu_scr); | |
345 | writeb((unsigned char)lcr, &uart->iu_lcr); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | /** | |
351 | * get_ioc3_port - given a uart port, return the control structure | |
352 | * @the_port: uart port to find | |
353 | */ | |
354 | static struct ioc3_port *get_ioc3_port(struct uart_port *the_port) | |
355 | { | |
356 | struct ioc3_driver_data *idd = dev_get_drvdata(the_port->dev); | |
357 | struct ioc3_card *card_ptr = idd->data[Submodule_slot]; | |
358 | int ii, jj; | |
359 | ||
360 | if (!card_ptr) { | |
361 | NOT_PROGRESS(); | |
362 | return NULL; | |
363 | } | |
364 | for (ii = 0; ii < PORTS_PER_CARD; ii++) { | |
365 | for (jj = 0; jj < LOGICAL_PORTS; jj++) { | |
366 | if (the_port == &card_ptr->ic_port[ii].icp_uart_port[jj]) | |
367 | return card_ptr->ic_port[ii].icp_port; | |
368 | } | |
369 | } | |
370 | NOT_PROGRESS(); | |
371 | return NULL; | |
372 | } | |
373 | ||
374 | /** | |
375 | * port_init - Initialize the sio and ioc3 hardware for a given port | |
376 | * called per port from attach... | |
377 | * @port: port to initialize | |
378 | */ | |
379 | static int inline port_init(struct ioc3_port *port) | |
380 | { | |
381 | uint32_t sio_cr; | |
382 | struct port_hooks *hooks = port->ip_hooks; | |
383 | struct ioc3_uartregs __iomem *uart; | |
384 | int reset_loop_counter = 0xfffff; | |
385 | struct ioc3_driver_data *idd = port->ip_idd; | |
386 | ||
387 | /* Idle the IOC3 serial interface */ | |
388 | writel(SSCR_RESET, &port->ip_serial_regs->sscr); | |
389 | ||
390 | /* Wait until any pending bus activity for this port has ceased */ | |
391 | do { | |
392 | sio_cr = readl(&idd->vma->sio_cr); | |
393 | if (reset_loop_counter-- <= 0) { | |
394 | printk(KERN_WARNING | |
395 | "IOC3 unable to come out of reset" | |
396 | " scr 0x%x\n", sio_cr); | |
397 | return -1; | |
398 | } | |
399 | } while (!(sio_cr & SIO_CR_ARB_DIAG_IDLE) && | |
400 | (((sio_cr &= SIO_CR_ARB_DIAG) == SIO_CR_ARB_DIAG_TXA) | |
401 | || sio_cr == SIO_CR_ARB_DIAG_TXB | |
402 | || sio_cr == SIO_CR_ARB_DIAG_RXA | |
403 | || sio_cr == SIO_CR_ARB_DIAG_RXB)); | |
404 | ||
405 | /* Finish reset sequence */ | |
406 | writel(0, &port->ip_serial_regs->sscr); | |
407 | ||
408 | /* Once RESET is done, reload cached tx_prod and rx_cons values | |
409 | * and set rings to empty by making prod == cons | |
410 | */ | |
411 | port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK; | |
412 | writel(port->ip_tx_prod, &port->ip_serial_regs->stpir); | |
413 | port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK; | |
414 | writel(port->ip_rx_cons | SRCIR_ARM, &port->ip_serial_regs->srcir); | |
415 | ||
416 | /* Disable interrupts for this 16550 */ | |
417 | uart = port->ip_uart_regs; | |
418 | writeb(0, &uart->iu_lcr); | |
419 | writeb(0, &uart->iu_ier); | |
420 | ||
421 | /* Set the default baud */ | |
422 | set_baud(port, port->ip_baud); | |
423 | ||
424 | /* Set line control to 8 bits no parity */ | |
425 | writeb(UART_LCR_WLEN8 | 0, &uart->iu_lcr); | |
426 | /* UART_LCR_STOP == 1 stop */ | |
427 | ||
428 | /* Enable the FIFOs */ | |
429 | writeb(UART_FCR_ENABLE_FIFO, &uart->iu_fcr); | |
430 | /* then reset 16550 FIFOs */ | |
431 | writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, | |
432 | &uart->iu_fcr); | |
433 | ||
434 | /* Clear modem control register */ | |
435 | writeb(0, &uart->iu_mcr); | |
436 | ||
437 | /* Clear deltas in modem status register */ | |
438 | writel(0, &port->ip_serial_regs->shadow); | |
439 | ||
440 | /* Only do this once per port pair */ | |
441 | if (port->ip_hooks == &hooks_array[0]) { | |
442 | unsigned long ring_pci_addr; | |
443 | uint32_t __iomem *sbbr_l, *sbbr_h; | |
444 | ||
445 | sbbr_l = &idd->vma->sbbr_l; | |
446 | sbbr_h = &idd->vma->sbbr_h; | |
447 | ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf; | |
448 | DPRINT_CONFIG(("%s: ring_pci_addr 0x%p\n", | |
71cc2c21 | 449 | __func__, (void *)ring_pci_addr)); |
2d0cfb52 PG |
450 | |
451 | writel((unsigned int)((uint64_t) ring_pci_addr >> 32), sbbr_h); | |
452 | writel((unsigned int)ring_pci_addr | BUF_SIZE_BIT, sbbr_l); | |
453 | } | |
454 | ||
455 | /* Set the receive timeout value to 10 msec */ | |
456 | writel(SRTR_HZ / 100, &port->ip_serial_regs->srtr); | |
457 | ||
458 | /* Set rx threshold, enable DMA */ | |
459 | /* Set high water mark at 3/4 of full ring */ | |
460 | port->ip_sscr = (ENTRIES_PER_RING * 3 / 4); | |
461 | ||
462 | /* uart experiences pauses at high baud rate reducing actual | |
463 | * throughput by 10% or so unless we enable high speed polling | |
464 | * XXX when this hardware bug is resolved we should revert to | |
465 | * normal polling speed | |
466 | */ | |
467 | port->ip_sscr |= SSCR_HIGH_SPD; | |
468 | ||
469 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
470 | ||
471 | /* Disable and clear all serial related interrupt bits */ | |
472 | port->ip_card->ic_enable &= ~hooks->intr_clear; | |
473 | ioc3_disable(port->ip_is, idd, hooks->intr_clear); | |
474 | ioc3_ack(port->ip_is, idd, hooks->intr_clear); | |
475 | return 0; | |
476 | } | |
477 | ||
478 | /** | |
479 | * enable_intrs - enable interrupts | |
480 | * @port: port to enable | |
481 | * @mask: mask to use | |
482 | */ | |
483 | static void enable_intrs(struct ioc3_port *port, uint32_t mask) | |
484 | { | |
485 | if ((port->ip_card->ic_enable & mask) != mask) { | |
486 | port->ip_card->ic_enable |= mask; | |
487 | ioc3_enable(port->ip_is, port->ip_idd, mask); | |
488 | } | |
489 | } | |
490 | ||
491 | /** | |
492 | * local_open - local open a port | |
493 | * @port: port to open | |
494 | */ | |
495 | static inline int local_open(struct ioc3_port *port) | |
496 | { | |
497 | int spiniter = 0; | |
498 | ||
499 | port->ip_flags = INPUT_ENABLE; | |
500 | ||
501 | /* Pause the DMA interface if necessary */ | |
502 | if (port->ip_sscr & SSCR_DMA_EN) { | |
503 | writel(port->ip_sscr | SSCR_DMA_PAUSE, | |
504 | &port->ip_serial_regs->sscr); | |
505 | while ((readl(&port->ip_serial_regs->sscr) | |
506 | & SSCR_PAUSE_STATE) == 0) { | |
507 | spiniter++; | |
508 | if (spiniter > MAXITER) { | |
509 | NOT_PROGRESS(); | |
510 | return -1; | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
515 | /* Reset the input fifo. If the uart received chars while the port | |
516 | * was closed and DMA is not enabled, the uart may have a bunch of | |
517 | * chars hanging around in its rx fifo which will not be discarded | |
518 | * by rclr in the upper layer. We must get rid of them here. | |
519 | */ | |
520 | writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR, | |
521 | &port->ip_uart_regs->iu_fcr); | |
522 | ||
523 | writeb(UART_LCR_WLEN8, &port->ip_uart_regs->iu_lcr); | |
524 | /* UART_LCR_STOP == 1 stop */ | |
525 | ||
526 | /* Re-enable DMA, set default threshold to intr whenever there is | |
527 | * data available. | |
528 | */ | |
529 | port->ip_sscr &= ~SSCR_RX_THRESHOLD; | |
530 | port->ip_sscr |= 1; /* default threshold */ | |
531 | ||
532 | /* Plug in the new sscr. This implicitly clears the DMA_PAUSE | |
533 | * flag if it was set above | |
534 | */ | |
535 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
536 | port->ip_tx_lowat = 1; | |
537 | return 0; | |
538 | } | |
539 | ||
540 | /** | |
541 | * set_rx_timeout - Set rx timeout and threshold values. | |
542 | * @port: port to use | |
543 | * @timeout: timeout value in ticks | |
544 | */ | |
545 | static inline int set_rx_timeout(struct ioc3_port *port, int timeout) | |
546 | { | |
547 | int threshold; | |
548 | ||
549 | port->ip_rx_timeout = timeout; | |
550 | ||
551 | /* Timeout is in ticks. Let's figure out how many chars we | |
552 | * can receive at the current baud rate in that interval | |
553 | * and set the rx threshold to that amount. There are 4 chars | |
554 | * per ring entry, so we'll divide the number of chars that will | |
555 | * arrive in timeout by 4. | |
556 | * So .... timeout * baud / 10 / HZ / 4, with HZ = 100. | |
557 | */ | |
558 | threshold = timeout * port->ip_baud / 4000; | |
559 | if (threshold == 0) | |
560 | threshold = 1; /* otherwise we'll intr all the time! */ | |
561 | ||
562 | if ((unsigned)threshold > (unsigned)SSCR_RX_THRESHOLD) | |
563 | return 1; | |
564 | ||
565 | port->ip_sscr &= ~SSCR_RX_THRESHOLD; | |
566 | port->ip_sscr |= threshold; | |
567 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
568 | ||
569 | /* Now set the rx timeout to the given value | |
570 | * again timeout * SRTR_HZ / HZ | |
571 | */ | |
572 | timeout = timeout * SRTR_HZ / 100; | |
573 | if (timeout > SRTR_CNT) | |
574 | timeout = SRTR_CNT; | |
575 | writel(timeout, &port->ip_serial_regs->srtr); | |
576 | return 0; | |
577 | } | |
578 | ||
579 | /** | |
580 | * config_port - config the hardware | |
581 | * @port: port to config | |
582 | * @baud: baud rate for the port | |
583 | * @byte_size: data size | |
584 | * @stop_bits: number of stop bits | |
585 | * @parenb: parity enable ? | |
586 | * @parodd: odd parity ? | |
587 | */ | |
588 | static inline int | |
589 | config_port(struct ioc3_port *port, | |
590 | int baud, int byte_size, int stop_bits, int parenb, int parodd) | |
591 | { | |
592 | char lcr, sizebits; | |
593 | int spiniter = 0; | |
594 | ||
595 | DPRINT_CONFIG(("%s: line %d baud %d byte_size %d stop %d parenb %d " | |
596 | "parodd %d\n", | |
71cc2c21 | 597 | __func__, ((struct uart_port *)port->ip_port)->line, |
2d0cfb52 PG |
598 | baud, byte_size, stop_bits, parenb, parodd)); |
599 | ||
600 | if (set_baud(port, baud)) | |
601 | return 1; | |
602 | ||
603 | switch (byte_size) { | |
604 | case 5: | |
605 | sizebits = UART_LCR_WLEN5; | |
606 | break; | |
607 | case 6: | |
608 | sizebits = UART_LCR_WLEN6; | |
609 | break; | |
610 | case 7: | |
611 | sizebits = UART_LCR_WLEN7; | |
612 | break; | |
613 | case 8: | |
614 | sizebits = UART_LCR_WLEN8; | |
615 | break; | |
616 | default: | |
617 | return 1; | |
618 | } | |
619 | ||
620 | /* Pause the DMA interface if necessary */ | |
621 | if (port->ip_sscr & SSCR_DMA_EN) { | |
622 | writel(port->ip_sscr | SSCR_DMA_PAUSE, | |
623 | &port->ip_serial_regs->sscr); | |
624 | while ((readl(&port->ip_serial_regs->sscr) | |
625 | & SSCR_PAUSE_STATE) == 0) { | |
626 | spiniter++; | |
627 | if (spiniter > MAXITER) | |
628 | return -1; | |
629 | } | |
630 | } | |
631 | ||
632 | /* Clear relevant fields in lcr */ | |
633 | lcr = readb(&port->ip_uart_regs->iu_lcr); | |
634 | lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR | | |
635 | UART_LCR_PARITY | LCR_MASK_STOP_BITS); | |
636 | ||
637 | /* Set byte size in lcr */ | |
638 | lcr |= sizebits; | |
639 | ||
640 | /* Set parity */ | |
641 | if (parenb) { | |
642 | lcr |= UART_LCR_PARITY; | |
643 | if (!parodd) | |
644 | lcr |= UART_LCR_EPAR; | |
645 | } | |
646 | ||
647 | /* Set stop bits */ | |
648 | if (stop_bits) | |
649 | lcr |= UART_LCR_STOP /* 2 stop bits */ ; | |
650 | ||
651 | writeb(lcr, &port->ip_uart_regs->iu_lcr); | |
652 | ||
653 | /* Re-enable the DMA interface if necessary */ | |
654 | if (port->ip_sscr & SSCR_DMA_EN) { | |
655 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
656 | } | |
657 | port->ip_baud = baud; | |
658 | ||
659 | /* When we get within this number of ring entries of filling the | |
660 | * entire ring on tx, place an EXPLICIT intr to generate a lowat | |
661 | * notification when output has drained. | |
662 | */ | |
663 | port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4; | |
664 | if (port->ip_tx_lowat == 0) | |
665 | port->ip_tx_lowat = 1; | |
666 | ||
667 | set_rx_timeout(port, 2); | |
668 | return 0; | |
669 | } | |
670 | ||
671 | /** | |
672 | * do_write - Write bytes to the port. Returns the number of bytes | |
673 | * actually written. Called from transmit_chars | |
674 | * @port: port to use | |
675 | * @buf: the stuff to write | |
676 | * @len: how many bytes in 'buf' | |
677 | */ | |
678 | static inline int do_write(struct ioc3_port *port, char *buf, int len) | |
679 | { | |
680 | int prod_ptr, cons_ptr, total = 0; | |
681 | struct ring *outring; | |
682 | struct ring_entry *entry; | |
683 | struct port_hooks *hooks = port->ip_hooks; | |
684 | ||
685 | BUG_ON(!(len >= 0)); | |
686 | ||
687 | prod_ptr = port->ip_tx_prod; | |
688 | cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK; | |
689 | outring = port->ip_outring; | |
690 | ||
691 | /* Maintain a 1-entry red-zone. The ring buffer is full when | |
692 | * (cons - prod) % ring_size is 1. Rather than do this subtraction | |
693 | * in the body of the loop, I'll do it now. | |
694 | */ | |
695 | cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK; | |
696 | ||
697 | /* Stuff the bytes into the output */ | |
698 | while ((prod_ptr != cons_ptr) && (len > 0)) { | |
699 | int xx; | |
700 | ||
701 | /* Get 4 bytes (one ring entry) at a time */ | |
702 | entry = (struct ring_entry *)((caddr_t) outring + prod_ptr); | |
703 | ||
704 | /* Invalidate all entries */ | |
705 | entry->ring_allsc = 0; | |
706 | ||
707 | /* Copy in some bytes */ | |
708 | for (xx = 0; (xx < 4) && (len > 0); xx++) { | |
709 | entry->ring_data[xx] = *buf++; | |
710 | entry->ring_sc[xx] = TXCB_VALID; | |
711 | len--; | |
712 | total++; | |
713 | } | |
714 | ||
715 | /* If we are within some small threshold of filling up the | |
716 | * entire ring buffer, we must place an EXPLICIT intr here | |
717 | * to generate a lowat interrupt in case we subsequently | |
718 | * really do fill up the ring and the caller goes to sleep. | |
719 | * No need to place more than one though. | |
720 | */ | |
721 | if (!(port->ip_flags & LOWAT_WRITTEN) && | |
722 | ((cons_ptr - prod_ptr) & PROD_CONS_MASK) | |
723 | <= port->ip_tx_lowat * (int)sizeof(struct ring_entry)) { | |
724 | port->ip_flags |= LOWAT_WRITTEN; | |
725 | entry->ring_sc[0] |= TXCB_INT_WHEN_DONE; | |
726 | } | |
727 | ||
728 | /* Go on to next entry */ | |
729 | prod_ptr += sizeof(struct ring_entry); | |
730 | prod_ptr &= PROD_CONS_MASK; | |
731 | } | |
732 | ||
733 | /* If we sent something, start DMA if necessary */ | |
734 | if (total > 0 && !(port->ip_sscr & SSCR_DMA_EN)) { | |
735 | port->ip_sscr |= SSCR_DMA_EN; | |
736 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
737 | } | |
738 | ||
739 | /* Store the new producer pointer. If tx is disabled, we stuff the | |
740 | * data into the ring buffer, but we don't actually start tx. | |
741 | */ | |
742 | if (!uart_tx_stopped(port->ip_port)) { | |
743 | writel(prod_ptr, &port->ip_serial_regs->stpir); | |
744 | ||
745 | /* If we are now transmitting, enable tx_mt interrupt so we | |
746 | * can disable DMA if necessary when the tx finishes. | |
747 | */ | |
748 | if (total > 0) | |
749 | enable_intrs(port, hooks->intr_tx_mt); | |
750 | } | |
751 | port->ip_tx_prod = prod_ptr; | |
752 | ||
753 | return total; | |
754 | } | |
755 | ||
756 | /** | |
757 | * disable_intrs - disable interrupts | |
758 | * @port: port to enable | |
759 | * @mask: mask to use | |
760 | */ | |
761 | static inline void disable_intrs(struct ioc3_port *port, uint32_t mask) | |
762 | { | |
763 | if (port->ip_card->ic_enable & mask) { | |
764 | ioc3_disable(port->ip_is, port->ip_idd, mask); | |
765 | port->ip_card->ic_enable &= ~mask; | |
766 | } | |
767 | } | |
768 | ||
769 | /** | |
770 | * set_notification - Modify event notification | |
771 | * @port: port to use | |
772 | * @mask: events mask | |
773 | * @set_on: set ? | |
774 | */ | |
775 | static int set_notification(struct ioc3_port *port, int mask, int set_on) | |
776 | { | |
777 | struct port_hooks *hooks = port->ip_hooks; | |
778 | uint32_t intrbits, sscrbits; | |
779 | ||
780 | BUG_ON(!mask); | |
781 | ||
782 | intrbits = sscrbits = 0; | |
783 | ||
784 | if (mask & N_DATA_READY) | |
785 | intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high); | |
786 | if (mask & N_OUTPUT_LOWAT) | |
787 | intrbits |= hooks->intr_tx_explicit; | |
788 | if (mask & N_DDCD) { | |
789 | intrbits |= hooks->intr_delta_dcd; | |
790 | sscrbits |= SSCR_RX_RING_DCD; | |
791 | } | |
792 | if (mask & N_DCTS) | |
793 | intrbits |= hooks->intr_delta_cts; | |
794 | ||
795 | if (set_on) { | |
796 | enable_intrs(port, intrbits); | |
797 | port->ip_notify |= mask; | |
798 | port->ip_sscr |= sscrbits; | |
799 | } else { | |
800 | disable_intrs(port, intrbits); | |
801 | port->ip_notify &= ~mask; | |
802 | port->ip_sscr &= ~sscrbits; | |
803 | } | |
804 | ||
805 | /* We require DMA if either DATA_READY or DDCD notification is | |
806 | * currently requested. If neither of these is requested and | |
807 | * there is currently no tx in progress, DMA may be disabled. | |
808 | */ | |
809 | if (port->ip_notify & (N_DATA_READY | N_DDCD)) | |
810 | port->ip_sscr |= SSCR_DMA_EN; | |
811 | else if (!(port->ip_card->ic_enable & hooks->intr_tx_mt)) | |
812 | port->ip_sscr &= ~SSCR_DMA_EN; | |
813 | ||
814 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
815 | return 0; | |
816 | } | |
817 | ||
818 | /** | |
819 | * set_mcr - set the master control reg | |
820 | * @the_port: port to use | |
821 | * @mask1: mcr mask | |
822 | * @mask2: shadow mask | |
823 | */ | |
824 | static inline int set_mcr(struct uart_port *the_port, | |
825 | int mask1, int mask2) | |
826 | { | |
827 | struct ioc3_port *port = get_ioc3_port(the_port); | |
828 | uint32_t shadow; | |
829 | int spiniter = 0; | |
830 | char mcr; | |
831 | ||
832 | if (!port) | |
833 | return -1; | |
834 | ||
835 | /* Pause the DMA interface if necessary */ | |
836 | if (port->ip_sscr & SSCR_DMA_EN) { | |
837 | writel(port->ip_sscr | SSCR_DMA_PAUSE, | |
838 | &port->ip_serial_regs->sscr); | |
839 | while ((readl(&port->ip_serial_regs->sscr) | |
840 | & SSCR_PAUSE_STATE) == 0) { | |
841 | spiniter++; | |
842 | if (spiniter > MAXITER) | |
843 | return -1; | |
844 | } | |
845 | } | |
846 | shadow = readl(&port->ip_serial_regs->shadow); | |
847 | mcr = (shadow & 0xff000000) >> 24; | |
848 | ||
849 | /* Set new value */ | |
850 | mcr |= mask1; | |
851 | shadow |= mask2; | |
852 | writeb(mcr, &port->ip_uart_regs->iu_mcr); | |
853 | writel(shadow, &port->ip_serial_regs->shadow); | |
854 | ||
855 | /* Re-enable the DMA interface if necessary */ | |
856 | if (port->ip_sscr & SSCR_DMA_EN) { | |
857 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
858 | } | |
859 | return 0; | |
860 | } | |
861 | ||
862 | /** | |
863 | * ioc3_set_proto - set the protocol for the port | |
864 | * @port: port to use | |
865 | * @proto: protocol to use | |
866 | */ | |
867 | static int ioc3_set_proto(struct ioc3_port *port, int proto) | |
868 | { | |
869 | struct port_hooks *hooks = port->ip_hooks; | |
870 | ||
871 | switch (proto) { | |
872 | default: | |
873 | case PROTO_RS232: | |
874 | /* Clear the appropriate GIO pin */ | |
71cc2c21 | 875 | DPRINT_CONFIG(("%s: rs232\n", __func__)); |
2d0cfb52 PG |
876 | writel(0, (&port->ip_idd->vma->gppr[0] |
877 | + hooks->rs422_select_pin)); | |
878 | break; | |
879 | ||
880 | case PROTO_RS422: | |
881 | /* Set the appropriate GIO pin */ | |
71cc2c21 | 882 | DPRINT_CONFIG(("%s: rs422\n", __func__)); |
2d0cfb52 PG |
883 | writel(1, (&port->ip_idd->vma->gppr[0] |
884 | + hooks->rs422_select_pin)); | |
885 | break; | |
886 | } | |
887 | return 0; | |
888 | } | |
889 | ||
890 | /** | |
891 | * transmit_chars - upper level write, called with the_port->lock | |
892 | * @the_port: port to write | |
893 | */ | |
894 | static void transmit_chars(struct uart_port *the_port) | |
895 | { | |
896 | int xmit_count, tail, head; | |
897 | int result; | |
898 | char *start; | |
899 | struct tty_struct *tty; | |
900 | struct ioc3_port *port = get_ioc3_port(the_port); | |
ebd2c8f6 | 901 | struct uart_state *state; |
2d0cfb52 PG |
902 | |
903 | if (!the_port) | |
904 | return; | |
905 | if (!port) | |
906 | return; | |
907 | ||
ebd2c8f6 AC |
908 | state = the_port->state; |
909 | tty = state->port.tty; | |
2d0cfb52 | 910 | |
ebd2c8f6 | 911 | if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) { |
2d0cfb52 PG |
912 | /* Nothing to do or hw stopped */ |
913 | set_notification(port, N_ALL_OUTPUT, 0); | |
914 | return; | |
915 | } | |
916 | ||
ebd2c8f6 AC |
917 | head = state->xmit.head; |
918 | tail = state->xmit.tail; | |
919 | start = (char *)&state->xmit.buf[tail]; | |
2d0cfb52 PG |
920 | |
921 | /* write out all the data or until the end of the buffer */ | |
922 | xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail); | |
923 | if (xmit_count > 0) { | |
924 | result = do_write(port, start, xmit_count); | |
925 | if (result > 0) { | |
926 | /* booking */ | |
927 | xmit_count -= result; | |
928 | the_port->icount.tx += result; | |
929 | /* advance the pointers */ | |
930 | tail += result; | |
931 | tail &= UART_XMIT_SIZE - 1; | |
ebd2c8f6 AC |
932 | state->xmit.tail = tail; |
933 | start = (char *)&state->xmit.buf[tail]; | |
2d0cfb52 PG |
934 | } |
935 | } | |
ebd2c8f6 | 936 | if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS) |
2d0cfb52 PG |
937 | uart_write_wakeup(the_port); |
938 | ||
ebd2c8f6 | 939 | if (uart_circ_empty(&state->xmit)) { |
2d0cfb52 PG |
940 | set_notification(port, N_OUTPUT_LOWAT, 0); |
941 | } else { | |
942 | set_notification(port, N_OUTPUT_LOWAT, 1); | |
943 | } | |
944 | } | |
945 | ||
946 | /** | |
947 | * ioc3_change_speed - change the speed of the port | |
948 | * @the_port: port to change | |
949 | * @new_termios: new termios settings | |
950 | * @old_termios: old termios settings | |
951 | */ | |
952 | static void | |
953 | ioc3_change_speed(struct uart_port *the_port, | |
606d099c | 954 | struct ktermios *new_termios, struct ktermios *old_termios) |
2d0cfb52 PG |
955 | { |
956 | struct ioc3_port *port = get_ioc3_port(the_port); | |
957 | unsigned int cflag; | |
958 | int baud; | |
959 | int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8; | |
ebd2c8f6 | 960 | struct uart_state *state = the_port->state; |
2d0cfb52 PG |
961 | |
962 | cflag = new_termios->c_cflag; | |
963 | ||
964 | switch (cflag & CSIZE) { | |
965 | case CS5: | |
966 | new_data = 5; | |
967 | break; | |
968 | case CS6: | |
969 | new_data = 6; | |
970 | break; | |
971 | case CS7: | |
972 | new_data = 7; | |
973 | break; | |
974 | case CS8: | |
975 | new_data = 8; | |
976 | break; | |
977 | default: | |
978 | /* cuz we always need a default ... */ | |
979 | new_data = 5; | |
980 | break; | |
981 | } | |
982 | if (cflag & CSTOPB) { | |
983 | new_stop = 1; | |
984 | } | |
985 | if (cflag & PARENB) { | |
986 | new_parity_enable = 1; | |
987 | if (cflag & PARODD) | |
988 | new_parity = 1; | |
989 | } | |
990 | baud = uart_get_baud_rate(the_port, new_termios, old_termios, | |
991 | MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED); | |
71cc2c21 | 992 | DPRINT_CONFIG(("%s: returned baud %d for line %d\n", __func__, baud, |
2d0cfb52 PG |
993 | the_port->line)); |
994 | ||
995 | if (!the_port->fifosize) | |
996 | the_port->fifosize = FIFO_SIZE; | |
997 | uart_update_timeout(the_port, cflag, baud); | |
998 | ||
999 | the_port->ignore_status_mask = N_ALL_INPUT; | |
1000 | ||
ebd2c8f6 | 1001 | state->port.tty->low_latency = 1; |
2d0cfb52 | 1002 | |
ebd2c8f6 | 1003 | if (I_IGNPAR(state->port.tty)) |
2d0cfb52 PG |
1004 | the_port->ignore_status_mask &= ~(N_PARITY_ERROR |
1005 | | N_FRAMING_ERROR); | |
ebd2c8f6 | 1006 | if (I_IGNBRK(state->port.tty)) { |
2d0cfb52 | 1007 | the_port->ignore_status_mask &= ~N_BREAK; |
ebd2c8f6 | 1008 | if (I_IGNPAR(state->port.tty)) |
2d0cfb52 PG |
1009 | the_port->ignore_status_mask &= ~N_OVERRUN_ERROR; |
1010 | } | |
1011 | if (!(cflag & CREAD)) { | |
1012 | /* ignore everything */ | |
1013 | the_port->ignore_status_mask &= ~N_DATA_READY; | |
1014 | } | |
1015 | ||
1016 | if (cflag & CRTSCTS) { | |
1017 | /* enable hardware flow control */ | |
1018 | port->ip_sscr |= SSCR_HFC_EN; | |
1019 | } | |
1020 | else { | |
1021 | /* disable hardware flow control */ | |
1022 | port->ip_sscr &= ~SSCR_HFC_EN; | |
1023 | } | |
1024 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
1025 | ||
1026 | /* Set the configuration and proper notification call */ | |
1027 | DPRINT_CONFIG(("%s : port 0x%p line %d cflag 0%o " | |
1028 | "config_port(baud %d data %d stop %d penable %d " | |
1029 | " parity %d), notification 0x%x\n", | |
71cc2c21 | 1030 | __func__, (void *)port, the_port->line, cflag, baud, |
2d0cfb52 PG |
1031 | new_data, new_stop, new_parity_enable, new_parity, |
1032 | the_port->ignore_status_mask)); | |
1033 | ||
1034 | if ((config_port(port, baud, /* baud */ | |
1035 | new_data, /* byte size */ | |
1036 | new_stop, /* stop bits */ | |
1037 | new_parity_enable, /* set parity */ | |
1038 | new_parity)) >= 0) { /* parity 1==odd */ | |
1039 | set_notification(port, the_port->ignore_status_mask, 1); | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /** | |
1044 | * ic3_startup_local - Start up the serial port - returns >= 0 if no errors | |
1045 | * @the_port: Port to operate on | |
1046 | */ | |
1047 | static inline int ic3_startup_local(struct uart_port *the_port) | |
1048 | { | |
1049 | struct ioc3_port *port; | |
1050 | ||
1051 | if (!the_port) { | |
1052 | NOT_PROGRESS(); | |
1053 | return -1; | |
1054 | } | |
1055 | ||
1056 | port = get_ioc3_port(the_port); | |
1057 | if (!port) { | |
1058 | NOT_PROGRESS(); | |
1059 | return -1; | |
1060 | } | |
1061 | ||
1062 | local_open(port); | |
1063 | ||
1064 | /* set the protocol */ | |
1065 | ioc3_set_proto(port, IS_RS232(the_port->line) ? PROTO_RS232 : | |
1066 | PROTO_RS422); | |
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * ioc3_cb_output_lowat - called when the output low water mark is hit | |
1072 | * @port: port to output | |
1073 | */ | |
1074 | static void ioc3_cb_output_lowat(struct ioc3_port *port) | |
1075 | { | |
1076 | unsigned long pflags; | |
1077 | ||
1078 | /* the_port->lock is set on the call here */ | |
1079 | if (port->ip_port) { | |
1080 | spin_lock_irqsave(&port->ip_port->lock, pflags); | |
1081 | transmit_chars(port->ip_port); | |
1082 | spin_unlock_irqrestore(&port->ip_port->lock, pflags); | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | /* | |
1087 | * ioc3_cb_post_ncs - called for some basic errors | |
1088 | * @port: port to use | |
1089 | * @ncs: event | |
1090 | */ | |
1091 | static void ioc3_cb_post_ncs(struct uart_port *the_port, int ncs) | |
1092 | { | |
1093 | struct uart_icount *icount; | |
1094 | ||
1095 | icount = &the_port->icount; | |
1096 | ||
1097 | if (ncs & NCS_BREAK) | |
1098 | icount->brk++; | |
1099 | if (ncs & NCS_FRAMING) | |
1100 | icount->frame++; | |
1101 | if (ncs & NCS_OVERRUN) | |
1102 | icount->overrun++; | |
1103 | if (ncs & NCS_PARITY) | |
1104 | icount->parity++; | |
1105 | } | |
1106 | ||
1107 | /** | |
1108 | * do_read - Read in bytes from the port. Return the number of bytes | |
1109 | * actually read. | |
1110 | * @the_port: port to use | |
1111 | * @buf: place to put the stuff we read | |
1112 | * @len: how big 'buf' is | |
1113 | */ | |
1114 | ||
1115 | static inline int do_read(struct uart_port *the_port, char *buf, int len) | |
1116 | { | |
1117 | int prod_ptr, cons_ptr, total; | |
1118 | struct ioc3_port *port = get_ioc3_port(the_port); | |
1119 | struct ring *inring; | |
1120 | struct ring_entry *entry; | |
1121 | struct port_hooks *hooks = port->ip_hooks; | |
1122 | int byte_num; | |
1123 | char *sc; | |
1124 | int loop_counter; | |
1125 | ||
1126 | BUG_ON(!(len >= 0)); | |
1127 | BUG_ON(!port); | |
1128 | ||
1129 | /* There is a nasty timing issue in the IOC3. When the rx_timer | |
1130 | * expires or the rx_high condition arises, we take an interrupt. | |
1131 | * At some point while servicing the interrupt, we read bytes from | |
1132 | * the ring buffer and re-arm the rx_timer. However the rx_timer is | |
1133 | * not started until the first byte is received *after* it is armed, | |
1134 | * and any bytes pending in the rx construction buffers are not drained | |
1135 | * to memory until either there are 4 bytes available or the rx_timer | |
1136 | * expires. This leads to a potential situation where data is left | |
1137 | * in the construction buffers forever - 1 to 3 bytes were received | |
1138 | * after the interrupt was generated but before the rx_timer was | |
1139 | * re-armed. At that point as long as no subsequent bytes are received | |
1140 | * the timer will never be started and the bytes will remain in the | |
1141 | * construction buffer forever. The solution is to execute a DRAIN | |
1142 | * command after rearming the timer. This way any bytes received before | |
1143 | * the DRAIN will be drained to memory, and any bytes received after | |
1144 | * the DRAIN will start the TIMER and be drained when it expires. | |
1145 | * Luckily, this only needs to be done when the DMA buffer is empty | |
1146 | * since there is no requirement that this function return all | |
1147 | * available data as long as it returns some. | |
1148 | */ | |
1149 | /* Re-arm the timer */ | |
1150 | ||
1151 | writel(port->ip_rx_cons | SRCIR_ARM, &port->ip_serial_regs->srcir); | |
1152 | ||
1153 | prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK; | |
1154 | cons_ptr = port->ip_rx_cons; | |
1155 | ||
1156 | if (prod_ptr == cons_ptr) { | |
1157 | int reset_dma = 0; | |
1158 | ||
1159 | /* Input buffer appears empty, do a flush. */ | |
1160 | ||
1161 | /* DMA must be enabled for this to work. */ | |
1162 | if (!(port->ip_sscr & SSCR_DMA_EN)) { | |
1163 | port->ip_sscr |= SSCR_DMA_EN; | |
1164 | reset_dma = 1; | |
1165 | } | |
1166 | ||
1167 | /* Potential race condition: we must reload the srpir after | |
1168 | * issuing the drain command, otherwise we could think the rx | |
1169 | * buffer is empty, then take a very long interrupt, and when | |
1170 | * we come back it's full and we wait forever for the drain to | |
1171 | * complete. | |
1172 | */ | |
1173 | writel(port->ip_sscr | SSCR_RX_DRAIN, | |
1174 | &port->ip_serial_regs->sscr); | |
1175 | prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK; | |
1176 | ||
1177 | /* We must not wait for the DRAIN to complete unless there are | |
1178 | * at least 8 bytes (2 ring entries) available to receive the | |
1179 | * data otherwise the DRAIN will never complete and we'll | |
1180 | * deadlock here. | |
1181 | * In fact, to make things easier, I'll just ignore the flush if | |
1182 | * there is any data at all now available. | |
1183 | */ | |
1184 | if (prod_ptr == cons_ptr) { | |
1185 | loop_counter = 0; | |
1186 | while (readl(&port->ip_serial_regs->sscr) & | |
1187 | SSCR_RX_DRAIN) { | |
1188 | loop_counter++; | |
1189 | if (loop_counter > MAXITER) | |
1190 | return -1; | |
1191 | } | |
1192 | ||
1193 | /* SIGH. We have to reload the prod_ptr *again* since | |
1194 | * the drain may have caused it to change | |
1195 | */ | |
1196 | prod_ptr = readl(&port->ip_serial_regs->srpir) | |
1197 | & PROD_CONS_MASK; | |
1198 | } | |
1199 | if (reset_dma) { | |
1200 | port->ip_sscr &= ~SSCR_DMA_EN; | |
1201 | writel(port->ip_sscr, &port->ip_serial_regs->sscr); | |
1202 | } | |
1203 | } | |
1204 | inring = port->ip_inring; | |
1205 | port->ip_flags &= ~READ_ABORTED; | |
1206 | ||
1207 | total = 0; | |
1208 | loop_counter = 0xfffff; /* to avoid hangs */ | |
1209 | ||
1210 | /* Grab bytes from the hardware */ | |
1211 | while ((prod_ptr != cons_ptr) && (len > 0)) { | |
1212 | entry = (struct ring_entry *)((caddr_t) inring + cons_ptr); | |
1213 | ||
1214 | if (loop_counter-- <= 0) { | |
1215 | printk(KERN_WARNING "IOC3 serial: " | |
1216 | "possible hang condition/" | |
1217 | "port stuck on read (line %d).\n", | |
1218 | the_port->line); | |
1219 | break; | |
1220 | } | |
1221 | ||
1222 | /* According to the producer pointer, this ring entry | |
1223 | * must contain some data. But if the PIO happened faster | |
1224 | * than the DMA, the data may not be available yet, so let's | |
1225 | * wait until it arrives. | |
1226 | */ | |
1227 | if ((entry->ring_allsc & RING_ANY_VALID) == 0) { | |
1228 | /* Indicate the read is aborted so we don't disable | |
1229 | * the interrupt thinking that the consumer is | |
1230 | * congested. | |
1231 | */ | |
1232 | port->ip_flags |= READ_ABORTED; | |
1233 | len = 0; | |
1234 | break; | |
1235 | } | |
1236 | ||
1237 | /* Load the bytes/status out of the ring entry */ | |
1238 | for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) { | |
1239 | sc = &(entry->ring_sc[byte_num]); | |
1240 | ||
1241 | /* Check for change in modem state or overrun */ | |
1242 | if ((*sc & RXSB_MODEM_VALID) | |
1243 | && (port->ip_notify & N_DDCD)) { | |
1244 | /* Notify upper layer if DCD dropped */ | |
1245 | if ((port->ip_flags & DCD_ON) | |
1246 | && !(*sc & RXSB_DCD)) { | |
1247 | /* If we have already copied some data, | |
1248 | * return it. We'll pick up the carrier | |
1249 | * drop on the next pass. That way we | |
1250 | * don't throw away the data that has | |
1251 | * already been copied back to | |
1252 | * the caller's buffer. | |
1253 | */ | |
1254 | if (total > 0) { | |
1255 | len = 0; | |
1256 | break; | |
1257 | } | |
1258 | port->ip_flags &= ~DCD_ON; | |
1259 | ||
1260 | /* Turn off this notification so the | |
1261 | * carrier drop protocol won't see it | |
1262 | * again when it does a read. | |
1263 | */ | |
1264 | *sc &= ~RXSB_MODEM_VALID; | |
1265 | ||
1266 | /* To keep things consistent, we need | |
1267 | * to update the consumer pointer so | |
1268 | * the next reader won't come in and | |
1269 | * try to read the same ring entries | |
1270 | * again. This must be done here before | |
1271 | * the dcd change. | |
1272 | */ | |
1273 | ||
1274 | if ((entry->ring_allsc & RING_ANY_VALID) | |
1275 | == 0) { | |
1276 | cons_ptr += (int)sizeof | |
1277 | (struct ring_entry); | |
1278 | cons_ptr &= PROD_CONS_MASK; | |
1279 | } | |
1280 | writel(cons_ptr, | |
1281 | &port->ip_serial_regs->srcir); | |
1282 | port->ip_rx_cons = cons_ptr; | |
1283 | ||
1284 | /* Notify upper layer of carrier drop */ | |
1285 | if ((port->ip_notify & N_DDCD) | |
1286 | && port->ip_port) { | |
1287 | uart_handle_dcd_change | |
1288 | (port->ip_port, 0); | |
1289 | wake_up_interruptible | |
ebd2c8f6 | 1290 | (&the_port->state-> |
bdc04e31 | 1291 | port.delta_msr_wait); |
2d0cfb52 PG |
1292 | } |
1293 | ||
1294 | /* If we had any data to return, we | |
1295 | * would have returned it above. | |
1296 | */ | |
1297 | return 0; | |
1298 | } | |
1299 | } | |
1300 | if (*sc & RXSB_MODEM_VALID) { | |
1301 | /* Notify that an input overrun occurred */ | |
1302 | if ((*sc & RXSB_OVERRUN) | |
1303 | && (port->ip_notify & N_OVERRUN_ERROR)) { | |
1304 | ioc3_cb_post_ncs(the_port, NCS_OVERRUN); | |
1305 | } | |
1306 | /* Don't look at this byte again */ | |
1307 | *sc &= ~RXSB_MODEM_VALID; | |
1308 | } | |
1309 | ||
1310 | /* Check for valid data or RX errors */ | |
1311 | if ((*sc & RXSB_DATA_VALID) && | |
1312 | ((*sc & (RXSB_PAR_ERR | |
1313 | | RXSB_FRAME_ERR | RXSB_BREAK)) | |
1314 | && (port->ip_notify & (N_PARITY_ERROR | |
1315 | | N_FRAMING_ERROR | |
1316 | | N_BREAK)))) { | |
1317 | /* There is an error condition on the next byte. | |
1318 | * If we have already transferred some bytes, | |
1319 | * we'll stop here. Otherwise if this is the | |
1320 | * first byte to be read, we'll just transfer | |
1321 | * it alone after notifying the | |
1322 | * upper layer of its status. | |
1323 | */ | |
1324 | if (total > 0) { | |
1325 | len = 0; | |
1326 | break; | |
1327 | } else { | |
1328 | if ((*sc & RXSB_PAR_ERR) && | |
1329 | (port-> | |
1330 | ip_notify & N_PARITY_ERROR)) { | |
1331 | ioc3_cb_post_ncs(the_port, | |
1332 | NCS_PARITY); | |
1333 | } | |
1334 | if ((*sc & RXSB_FRAME_ERR) && | |
1335 | (port-> | |
1336 | ip_notify & N_FRAMING_ERROR)) { | |
1337 | ioc3_cb_post_ncs(the_port, | |
1338 | NCS_FRAMING); | |
1339 | } | |
1340 | if ((*sc & RXSB_BREAK) | |
1341 | && (port->ip_notify & N_BREAK)) { | |
1342 | ioc3_cb_post_ncs | |
1343 | (the_port, NCS_BREAK); | |
1344 | } | |
1345 | len = 1; | |
1346 | } | |
1347 | } | |
1348 | if (*sc & RXSB_DATA_VALID) { | |
1349 | *sc &= ~RXSB_DATA_VALID; | |
1350 | *buf = entry->ring_data[byte_num]; | |
1351 | buf++; | |
1352 | len--; | |
1353 | total++; | |
1354 | } | |
1355 | } | |
1356 | ||
1357 | /* If we used up this entry entirely, go on to the next one, | |
1358 | * otherwise we must have run out of buffer space, so | |
1359 | * leave the consumer pointer here for the next read in case | |
1360 | * there are still unread bytes in this entry. | |
1361 | */ | |
1362 | if ((entry->ring_allsc & RING_ANY_VALID) == 0) { | |
1363 | cons_ptr += (int)sizeof(struct ring_entry); | |
1364 | cons_ptr &= PROD_CONS_MASK; | |
1365 | } | |
1366 | } | |
1367 | ||
1368 | /* Update consumer pointer and re-arm rx timer interrupt */ | |
1369 | writel(cons_ptr, &port->ip_serial_regs->srcir); | |
1370 | port->ip_rx_cons = cons_ptr; | |
1371 | ||
1372 | /* If we have now dipped below the rx high water mark and we have | |
1373 | * rx_high interrupt turned off, we can now turn it back on again. | |
1374 | */ | |
1375 | if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr) | |
1376 | & PROD_CONS_MASK) < | |
1377 | ((port-> | |
1378 | ip_sscr & | |
1379 | SSCR_RX_THRESHOLD) | |
1380 | << PROD_CONS_PTR_OFF))) { | |
1381 | port->ip_flags &= ~INPUT_HIGH; | |
1382 | enable_intrs(port, hooks->intr_rx_high); | |
1383 | } | |
1384 | return total; | |
1385 | } | |
1386 | ||
1387 | /** | |
1388 | * receive_chars - upper level read. | |
1389 | * @the_port: port to read from | |
1390 | */ | |
1391 | static int receive_chars(struct uart_port *the_port) | |
1392 | { | |
1393 | struct tty_struct *tty; | |
1394 | unsigned char ch[MAX_CHARS]; | |
1395 | int read_count = 0, read_room, flip = 0; | |
ebd2c8f6 | 1396 | struct uart_state *state = the_port->state; |
2d0cfb52 PG |
1397 | struct ioc3_port *port = get_ioc3_port(the_port); |
1398 | unsigned long pflags; | |
1399 | ||
1400 | /* Make sure all the pointers are "good" ones */ | |
ebd2c8f6 | 1401 | if (!state) |
2d0cfb52 | 1402 | return 0; |
ebd2c8f6 | 1403 | if (!state->port.tty) |
2d0cfb52 PG |
1404 | return 0; |
1405 | ||
1406 | if (!(port->ip_flags & INPUT_ENABLE)) | |
1407 | return 0; | |
1408 | ||
1409 | spin_lock_irqsave(&the_port->lock, pflags); | |
ebd2c8f6 | 1410 | tty = state->port.tty; |
2d0cfb52 PG |
1411 | |
1412 | read_count = do_read(the_port, ch, MAX_CHARS); | |
1413 | if (read_count > 0) { | |
1414 | flip = 1; | |
4165fe4e | 1415 | read_room = tty_insert_flip_string(tty, ch, read_count); |
2d0cfb52 PG |
1416 | the_port->icount.rx += read_count; |
1417 | } | |
1418 | spin_unlock_irqrestore(&the_port->lock, pflags); | |
1419 | ||
1420 | if (flip) | |
1421 | tty_flip_buffer_push(tty); | |
1422 | ||
1423 | return read_count; | |
1424 | } | |
1425 | ||
1426 | /** | |
1427 | * ioc3uart_intr_one - lowest level (per port) interrupt handler. | |
1428 | * @is : submodule | |
1429 | * @idd: driver data | |
1430 | * @pending: interrupts to handle | |
2d0cfb52 PG |
1431 | */ |
1432 | ||
1433 | static int inline | |
1434 | ioc3uart_intr_one(struct ioc3_submodule *is, | |
1435 | struct ioc3_driver_data *idd, | |
7d12e780 | 1436 | unsigned int pending) |
2d0cfb52 PG |
1437 | { |
1438 | int port_num = GET_PORT_FROM_SIO_IR(pending); | |
1439 | struct port_hooks *hooks; | |
1440 | unsigned int rx_high_rd_aborted = 0; | |
1441 | unsigned long flags; | |
1442 | struct uart_port *the_port; | |
1443 | struct ioc3_port *port; | |
1444 | int loop_counter; | |
1445 | struct ioc3_card *card_ptr; | |
1446 | unsigned int sio_ir; | |
1447 | ||
1448 | card_ptr = idd->data[is->id]; | |
1449 | port = card_ptr->ic_port[port_num].icp_port; | |
1450 | hooks = port->ip_hooks; | |
1451 | ||
1452 | /* Possible race condition here: The tx_mt interrupt bit may be | |
1453 | * cleared without the intervention of the interrupt handler, | |
1454 | * e.g. by a write. If the top level interrupt handler reads a | |
1455 | * tx_mt, then some other processor does a write, starting up | |
1456 | * output, then we come in here, see the tx_mt and stop DMA, the | |
1457 | * output started by the other processor will hang. Thus we can | |
1458 | * only rely on tx_mt being legitimate if it is read while the | |
1459 | * port lock is held. Therefore this bit must be ignored in the | |
1460 | * passed in interrupt mask which was read by the top level | |
1461 | * interrupt handler since the port lock was not held at the time | |
1462 | * it was read. We can only rely on this bit being accurate if it | |
1463 | * is read while the port lock is held. So we'll clear it for now, | |
1464 | * and reload it later once we have the port lock. | |
1465 | */ | |
1466 | ||
1467 | sio_ir = pending & ~(hooks->intr_tx_mt); | |
1468 | spin_lock_irqsave(&port->ip_lock, flags); | |
1469 | ||
1470 | loop_counter = MAXITER; /* to avoid hangs */ | |
1471 | ||
1472 | do { | |
1473 | uint32_t shadow; | |
1474 | ||
1475 | if (loop_counter-- <= 0) { | |
1476 | printk(KERN_WARNING "IOC3 serial: " | |
1477 | "possible hang condition/" | |
1478 | "port stuck on interrupt (line %d).\n", | |
1479 | ((struct uart_port *)port->ip_port)->line); | |
1480 | break; | |
1481 | } | |
1482 | /* Handle a DCD change */ | |
1483 | if (sio_ir & hooks->intr_delta_dcd) { | |
1484 | ioc3_ack(is, idd, hooks->intr_delta_dcd); | |
1485 | shadow = readl(&port->ip_serial_regs->shadow); | |
1486 | ||
1487 | if ((port->ip_notify & N_DDCD) | |
1488 | && (shadow & SHADOW_DCD) | |
1489 | && (port->ip_port)) { | |
1490 | the_port = port->ip_port; | |
1491 | uart_handle_dcd_change(the_port, | |
1492 | shadow & SHADOW_DCD); | |
1493 | wake_up_interruptible | |
bdc04e31 | 1494 | (&the_port->state->port.delta_msr_wait); |
2d0cfb52 PG |
1495 | } else if ((port->ip_notify & N_DDCD) |
1496 | && !(shadow & SHADOW_DCD)) { | |
1497 | /* Flag delta DCD/no DCD */ | |
1498 | uart_handle_dcd_change(port->ip_port, | |
1499 | shadow & SHADOW_DCD); | |
1500 | port->ip_flags |= DCD_ON; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | /* Handle a CTS change */ | |
1505 | if (sio_ir & hooks->intr_delta_cts) { | |
1506 | ioc3_ack(is, idd, hooks->intr_delta_cts); | |
1507 | shadow = readl(&port->ip_serial_regs->shadow); | |
1508 | ||
1509 | if ((port->ip_notify & N_DCTS) && (port->ip_port)) { | |
1510 | the_port = port->ip_port; | |
1511 | uart_handle_cts_change(the_port, shadow | |
1512 | & SHADOW_CTS); | |
1513 | wake_up_interruptible | |
bdc04e31 | 1514 | (&the_port->state->port.delta_msr_wait); |
2d0cfb52 PG |
1515 | } |
1516 | } | |
1517 | ||
1518 | /* rx timeout interrupt. Must be some data available. Put this | |
1519 | * before the check for rx_high since servicing this condition | |
1520 | * may cause that condition to clear. | |
1521 | */ | |
1522 | if (sio_ir & hooks->intr_rx_timer) { | |
1523 | ioc3_ack(is, idd, hooks->intr_rx_timer); | |
1524 | if ((port->ip_notify & N_DATA_READY) | |
1525 | && (port->ip_port)) { | |
1526 | receive_chars(port->ip_port); | |
1527 | } | |
1528 | } | |
1529 | ||
1530 | /* rx high interrupt. Must be after rx_timer. */ | |
1531 | else if (sio_ir & hooks->intr_rx_high) { | |
1532 | /* Data available, notify upper layer */ | |
1533 | if ((port->ip_notify & N_DATA_READY) && port->ip_port) { | |
1534 | receive_chars(port->ip_port); | |
1535 | } | |
1536 | ||
1537 | /* We can't ACK this interrupt. If receive_chars didn't | |
1538 | * cause the condition to clear, we'll have to disable | |
1539 | * the interrupt until the data is drained. | |
1540 | * If the read was aborted, don't disable the interrupt | |
1541 | * as this may cause us to hang indefinitely. An | |
1542 | * aborted read generally means that this interrupt | |
1543 | * hasn't been delivered to the cpu yet anyway, even | |
1544 | * though we see it as asserted when we read the sio_ir. | |
1545 | */ | |
1546 | if ((sio_ir = PENDING(card_ptr, idd)) | |
1547 | & hooks->intr_rx_high) { | |
1548 | if (port->ip_flags & READ_ABORTED) { | |
1549 | rx_high_rd_aborted++; | |
1550 | } | |
1551 | else { | |
1552 | card_ptr->ic_enable &= ~hooks->intr_rx_high; | |
1553 | port->ip_flags |= INPUT_HIGH; | |
1554 | } | |
1555 | } | |
1556 | } | |
1557 | ||
1558 | /* We got a low water interrupt: notify upper layer to | |
1559 | * send more data. Must come before tx_mt since servicing | |
1560 | * this condition may cause that condition to clear. | |
1561 | */ | |
1562 | if (sio_ir & hooks->intr_tx_explicit) { | |
1563 | port->ip_flags &= ~LOWAT_WRITTEN; | |
1564 | ioc3_ack(is, idd, hooks->intr_tx_explicit); | |
1565 | if (port->ip_notify & N_OUTPUT_LOWAT) | |
1566 | ioc3_cb_output_lowat(port); | |
1567 | } | |
1568 | ||
1569 | /* Handle tx_mt. Must come after tx_explicit. */ | |
1570 | else if (sio_ir & hooks->intr_tx_mt) { | |
1571 | /* If we are expecting a lowat notification | |
1572 | * and we get to this point it probably means that for | |
1573 | * some reason the tx_explicit didn't work as expected | |
1574 | * (that can legitimately happen if the output buffer is | |
1575 | * filled up in just the right way). | |
1576 | * So send the notification now. | |
1577 | */ | |
1578 | if (port->ip_notify & N_OUTPUT_LOWAT) { | |
1579 | ioc3_cb_output_lowat(port); | |
1580 | ||
1581 | /* We need to reload the sio_ir since the lowat | |
1582 | * call may have caused another write to occur, | |
1583 | * clearing the tx_mt condition. | |
1584 | */ | |
1585 | sio_ir = PENDING(card_ptr, idd); | |
1586 | } | |
1587 | ||
1588 | /* If the tx_mt condition still persists even after the | |
1589 | * lowat call, we've got some work to do. | |
1590 | */ | |
1591 | if (sio_ir & hooks->intr_tx_mt) { | |
1592 | /* If we are not currently expecting DMA input, | |
1593 | * and the transmitter has just gone idle, | |
1594 | * there is no longer any reason for DMA, so | |
1595 | * disable it. | |
1596 | */ | |
1597 | if (!(port->ip_notify | |
1598 | & (N_DATA_READY | N_DDCD))) { | |
1599 | BUG_ON(!(port->ip_sscr | |
1600 | & SSCR_DMA_EN)); | |
1601 | port->ip_sscr &= ~SSCR_DMA_EN; | |
1602 | writel(port->ip_sscr, | |
1603 | &port->ip_serial_regs->sscr); | |
1604 | } | |
1605 | /* Prevent infinite tx_mt interrupt */ | |
1606 | card_ptr->ic_enable &= ~hooks->intr_tx_mt; | |
1607 | } | |
1608 | } | |
1609 | sio_ir = PENDING(card_ptr, idd); | |
1610 | ||
1611 | /* if the read was aborted and only hooks->intr_rx_high, | |
1612 | * clear hooks->intr_rx_high, so we do not loop forever. | |
1613 | */ | |
1614 | ||
1615 | if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) { | |
1616 | sio_ir &= ~hooks->intr_rx_high; | |
1617 | } | |
1618 | } while (sio_ir & hooks->intr_all); | |
1619 | ||
1620 | spin_unlock_irqrestore(&port->ip_lock, flags); | |
1621 | ioc3_enable(is, idd, card_ptr->ic_enable); | |
1622 | return 0; | |
1623 | } | |
1624 | ||
1625 | /** | |
1626 | * ioc3uart_intr - field all serial interrupts | |
1627 | * @is : submodule | |
1628 | * @idd: driver data | |
1629 | * @pending: interrupts to handle | |
2d0cfb52 PG |
1630 | * |
1631 | */ | |
1632 | ||
1633 | static int ioc3uart_intr(struct ioc3_submodule *is, | |
1634 | struct ioc3_driver_data *idd, | |
7d12e780 | 1635 | unsigned int pending) |
2d0cfb52 PG |
1636 | { |
1637 | int ret = 0; | |
1638 | ||
1639 | /* | |
1640 | * The upper level interrupt handler sends interrupts for both ports | |
1641 | * here. So we need to call for each port with its interrupts. | |
1642 | */ | |
1643 | ||
1644 | if (pending & SIO_IR_SA) | |
7d12e780 | 1645 | ret |= ioc3uart_intr_one(is, idd, pending & SIO_IR_SA); |
2d0cfb52 | 1646 | if (pending & SIO_IR_SB) |
7d12e780 | 1647 | ret |= ioc3uart_intr_one(is, idd, pending & SIO_IR_SB); |
2d0cfb52 PG |
1648 | |
1649 | return ret; | |
1650 | } | |
1651 | ||
1652 | /** | |
1653 | * ic3_type | |
1654 | * @port: Port to operate with (we ignore since we only have one port) | |
1655 | * | |
1656 | */ | |
1657 | static const char *ic3_type(struct uart_port *the_port) | |
1658 | { | |
1659 | if (IS_RS232(the_port->line)) | |
1660 | return "SGI IOC3 Serial [rs232]"; | |
1661 | else | |
1662 | return "SGI IOC3 Serial [rs422]"; | |
1663 | } | |
1664 | ||
1665 | /** | |
1666 | * ic3_tx_empty - Is the transmitter empty? | |
1667 | * @port: Port to operate on | |
1668 | * | |
1669 | */ | |
1670 | static unsigned int ic3_tx_empty(struct uart_port *the_port) | |
1671 | { | |
1672 | unsigned int ret = 0; | |
1673 | struct ioc3_port *port = get_ioc3_port(the_port); | |
1674 | ||
1675 | if (readl(&port->ip_serial_regs->shadow) & SHADOW_TEMT) | |
1676 | ret = TIOCSER_TEMT; | |
1677 | return ret; | |
1678 | } | |
1679 | ||
1680 | /** | |
1681 | * ic3_stop_tx - stop the transmitter | |
1682 | * @port: Port to operate on | |
1683 | * | |
1684 | */ | |
1685 | static void ic3_stop_tx(struct uart_port *the_port) | |
1686 | { | |
1687 | struct ioc3_port *port = get_ioc3_port(the_port); | |
1688 | ||
1689 | if (port) | |
1690 | set_notification(port, N_OUTPUT_LOWAT, 0); | |
1691 | } | |
1692 | ||
1693 | /** | |
1694 | * ic3_stop_rx - stop the receiver | |
1695 | * @port: Port to operate on | |
1696 | * | |
1697 | */ | |
1698 | static void ic3_stop_rx(struct uart_port *the_port) | |
1699 | { | |
1700 | struct ioc3_port *port = get_ioc3_port(the_port); | |
1701 | ||
1702 | if (port) | |
1703 | port->ip_flags &= ~INPUT_ENABLE; | |
1704 | } | |
1705 | ||
1706 | /** | |
1707 | * null_void_function | |
1708 | * @port: Port to operate on | |
1709 | * | |
1710 | */ | |
1711 | static void null_void_function(struct uart_port *the_port) | |
1712 | { | |
1713 | } | |
1714 | ||
1715 | /** | |
1716 | * ic3_shutdown - shut down the port - free irq and disable | |
1717 | * @port: port to shut down | |
1718 | * | |
1719 | */ | |
1720 | static void ic3_shutdown(struct uart_port *the_port) | |
1721 | { | |
1722 | unsigned long port_flags; | |
1723 | struct ioc3_port *port; | |
ebd2c8f6 | 1724 | struct uart_state *state; |
2d0cfb52 PG |
1725 | |
1726 | port = get_ioc3_port(the_port); | |
1727 | if (!port) | |
1728 | return; | |
1729 | ||
ebd2c8f6 | 1730 | state = the_port->state; |
bdc04e31 | 1731 | wake_up_interruptible(&state->port.delta_msr_wait); |
2d0cfb52 PG |
1732 | |
1733 | spin_lock_irqsave(&the_port->lock, port_flags); | |
1734 | set_notification(port, N_ALL, 0); | |
1735 | spin_unlock_irqrestore(&the_port->lock, port_flags); | |
1736 | } | |
1737 | ||
1738 | /** | |
1739 | * ic3_set_mctrl - set control lines (dtr, rts, etc) | |
1740 | * @port: Port to operate on | |
1741 | * @mctrl: Lines to set/unset | |
1742 | * | |
1743 | */ | |
1744 | static void ic3_set_mctrl(struct uart_port *the_port, unsigned int mctrl) | |
1745 | { | |
1746 | unsigned char mcr = 0; | |
1747 | ||
1748 | if (mctrl & TIOCM_RTS) | |
1749 | mcr |= UART_MCR_RTS; | |
1750 | if (mctrl & TIOCM_DTR) | |
1751 | mcr |= UART_MCR_DTR; | |
1752 | if (mctrl & TIOCM_OUT1) | |
1753 | mcr |= UART_MCR_OUT1; | |
1754 | if (mctrl & TIOCM_OUT2) | |
1755 | mcr |= UART_MCR_OUT2; | |
1756 | if (mctrl & TIOCM_LOOP) | |
1757 | mcr |= UART_MCR_LOOP; | |
1758 | ||
1759 | set_mcr(the_port, mcr, SHADOW_DTR); | |
1760 | } | |
1761 | ||
1762 | /** | |
1763 | * ic3_get_mctrl - get control line info | |
1764 | * @port: port to operate on | |
1765 | * | |
1766 | */ | |
1767 | static unsigned int ic3_get_mctrl(struct uart_port *the_port) | |
1768 | { | |
1769 | struct ioc3_port *port = get_ioc3_port(the_port); | |
1770 | uint32_t shadow; | |
1771 | unsigned int ret = 0; | |
1772 | ||
1773 | if (!port) | |
1774 | return 0; | |
1775 | ||
1776 | shadow = readl(&port->ip_serial_regs->shadow); | |
1777 | if (shadow & SHADOW_DCD) | |
1778 | ret |= TIOCM_CD; | |
1779 | if (shadow & SHADOW_DR) | |
1780 | ret |= TIOCM_DSR; | |
1781 | if (shadow & SHADOW_CTS) | |
1782 | ret |= TIOCM_CTS; | |
1783 | return ret; | |
1784 | } | |
1785 | ||
1786 | /** | |
1787 | * ic3_start_tx - Start transmitter. Called with the_port->lock | |
1788 | * @port: Port to operate on | |
1789 | * | |
1790 | */ | |
1791 | static void ic3_start_tx(struct uart_port *the_port) | |
1792 | { | |
1793 | struct ioc3_port *port = get_ioc3_port(the_port); | |
1794 | ||
1795 | if (port) { | |
1796 | set_notification(port, N_OUTPUT_LOWAT, 1); | |
1797 | enable_intrs(port, port->ip_hooks->intr_tx_mt); | |
1798 | } | |
1799 | } | |
1800 | ||
1801 | /** | |
1802 | * ic3_break_ctl - handle breaks | |
1803 | * @port: Port to operate on | |
1804 | * @break_state: Break state | |
1805 | * | |
1806 | */ | |
1807 | static void ic3_break_ctl(struct uart_port *the_port, int break_state) | |
1808 | { | |
1809 | } | |
1810 | ||
1811 | /** | |
1812 | * ic3_startup - Start up the serial port - always return 0 (We're always on) | |
1813 | * @port: Port to operate on | |
1814 | * | |
1815 | */ | |
1816 | static int ic3_startup(struct uart_port *the_port) | |
1817 | { | |
1818 | int retval; | |
1819 | struct ioc3_port *port; | |
1820 | struct ioc3_card *card_ptr; | |
1821 | unsigned long port_flags; | |
1822 | ||
1823 | if (!the_port) { | |
1824 | NOT_PROGRESS(); | |
1825 | return -ENODEV; | |
1826 | } | |
1827 | port = get_ioc3_port(the_port); | |
1828 | if (!port) { | |
1829 | NOT_PROGRESS(); | |
1830 | return -ENODEV; | |
1831 | } | |
1832 | card_ptr = port->ip_card; | |
1833 | port->ip_port = the_port; | |
1834 | ||
1835 | if (!card_ptr) { | |
1836 | NOT_PROGRESS(); | |
1837 | return -ENODEV; | |
1838 | } | |
1839 | ||
1840 | /* Start up the serial port */ | |
1841 | spin_lock_irqsave(&the_port->lock, port_flags); | |
1842 | retval = ic3_startup_local(the_port); | |
1843 | spin_unlock_irqrestore(&the_port->lock, port_flags); | |
1844 | return retval; | |
1845 | } | |
1846 | ||
1847 | /** | |
1848 | * ic3_set_termios - set termios stuff | |
1849 | * @port: port to operate on | |
1850 | * @termios: New settings | |
1851 | * @termios: Old | |
1852 | * | |
1853 | */ | |
1854 | static void | |
1855 | ic3_set_termios(struct uart_port *the_port, | |
606d099c | 1856 | struct ktermios *termios, struct ktermios *old_termios) |
2d0cfb52 PG |
1857 | { |
1858 | unsigned long port_flags; | |
1859 | ||
1860 | spin_lock_irqsave(&the_port->lock, port_flags); | |
1861 | ioc3_change_speed(the_port, termios, old_termios); | |
1862 | spin_unlock_irqrestore(&the_port->lock, port_flags); | |
1863 | } | |
1864 | ||
1865 | /** | |
1866 | * ic3_request_port - allocate resources for port - no op.... | |
1867 | * @port: port to operate on | |
1868 | * | |
1869 | */ | |
1870 | static int ic3_request_port(struct uart_port *port) | |
1871 | { | |
1872 | return 0; | |
1873 | } | |
1874 | ||
1875 | /* Associate the uart functions above - given to serial core */ | |
1876 | static struct uart_ops ioc3_ops = { | |
1877 | .tx_empty = ic3_tx_empty, | |
1878 | .set_mctrl = ic3_set_mctrl, | |
1879 | .get_mctrl = ic3_get_mctrl, | |
1880 | .stop_tx = ic3_stop_tx, | |
1881 | .start_tx = ic3_start_tx, | |
1882 | .stop_rx = ic3_stop_rx, | |
1883 | .enable_ms = null_void_function, | |
1884 | .break_ctl = ic3_break_ctl, | |
1885 | .startup = ic3_startup, | |
1886 | .shutdown = ic3_shutdown, | |
1887 | .set_termios = ic3_set_termios, | |
1888 | .type = ic3_type, | |
1889 | .release_port = null_void_function, | |
1890 | .request_port = ic3_request_port, | |
1891 | }; | |
1892 | ||
1893 | /* | |
1894 | * Boot-time initialization code | |
1895 | */ | |
1896 | ||
1897 | static struct uart_driver ioc3_uart = { | |
1898 | .owner = THIS_MODULE, | |
1899 | .driver_name = "ioc3_serial", | |
1900 | .dev_name = DEVICE_NAME, | |
1901 | .major = DEVICE_MAJOR, | |
1902 | .minor = DEVICE_MINOR, | |
1903 | .nr = MAX_LOGICAL_PORTS | |
1904 | }; | |
1905 | ||
1906 | /** | |
1907 | * ioc3_serial_core_attach - register with serial core | |
1908 | * This is done during pci probing | |
1909 | * @is: submodule struct for this | |
1910 | * @idd: handle for this card | |
1911 | */ | |
1912 | static inline int ioc3_serial_core_attach( struct ioc3_submodule *is, | |
1913 | struct ioc3_driver_data *idd) | |
1914 | { | |
1915 | struct ioc3_port *port; | |
1916 | struct uart_port *the_port; | |
1917 | struct ioc3_card *card_ptr = idd->data[is->id]; | |
1918 | int ii, phys_port; | |
1919 | struct pci_dev *pdev = idd->pdev; | |
1920 | ||
1921 | DPRINT_CONFIG(("%s: attach pdev 0x%p - card_ptr 0x%p\n", | |
71cc2c21 | 1922 | __func__, pdev, (void *)card_ptr)); |
2d0cfb52 PG |
1923 | |
1924 | if (!card_ptr) | |
1925 | return -ENODEV; | |
1926 | ||
1927 | /* once around for each logical port on this card */ | |
1928 | for (ii = 0; ii < LOGICAL_PORTS_PER_CARD; ii++) { | |
1929 | phys_port = GET_PHYSICAL_PORT(ii); | |
1930 | the_port = &card_ptr->ic_port[phys_port]. | |
1931 | icp_uart_port[GET_LOGICAL_PORT(ii)]; | |
1932 | port = card_ptr->ic_port[phys_port].icp_port; | |
1933 | port->ip_port = the_port; | |
1934 | ||
1935 | DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p [%d/%d]\n", | |
71cc2c21 | 1936 | __func__, (void *)the_port, (void *)port, |
2d0cfb52 PG |
1937 | phys_port, ii)); |
1938 | ||
1939 | /* membase, iobase and mapbase just need to be non-0 */ | |
1940 | the_port->membase = (unsigned char __iomem *)1; | |
1941 | the_port->iobase = (pdev->bus->number << 16) | ii; | |
1942 | the_port->line = (Num_of_ioc3_cards << 2) | ii; | |
1943 | the_port->mapbase = 1; | |
1944 | the_port->type = PORT_16550A; | |
1945 | the_port->fifosize = FIFO_SIZE; | |
1946 | the_port->ops = &ioc3_ops; | |
1947 | the_port->irq = idd->irq_io; | |
1948 | the_port->dev = &pdev->dev; | |
1949 | ||
1950 | if (uart_add_one_port(&ioc3_uart, the_port) < 0) { | |
1951 | printk(KERN_WARNING | |
1952 | "%s: unable to add port %d bus %d\n", | |
71cc2c21 | 1953 | __func__, the_port->line, pdev->bus->number); |
2d0cfb52 PG |
1954 | } else { |
1955 | DPRINT_CONFIG(("IOC3 serial port %d irq %d bus %d\n", | |
1956 | the_port->line, the_port->irq, pdev->bus->number)); | |
1957 | } | |
1958 | ||
1959 | /* all ports are rs232 for now */ | |
1960 | if (IS_PHYSICAL_PORT(ii)) | |
1961 | ioc3_set_proto(port, PROTO_RS232); | |
1962 | } | |
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | /** | |
1967 | * ioc3uart_remove - register detach function | |
1968 | * @is: submodule struct for this submodule | |
1969 | * @idd: ioc3 driver data for this submodule | |
1970 | */ | |
1971 | ||
1972 | static int ioc3uart_remove(struct ioc3_submodule *is, | |
1973 | struct ioc3_driver_data *idd) | |
1974 | { | |
1975 | struct ioc3_card *card_ptr = idd->data[is->id]; | |
1976 | struct uart_port *the_port; | |
1977 | struct ioc3_port *port; | |
1978 | int ii; | |
1979 | ||
1980 | if (card_ptr) { | |
1981 | for (ii = 0; ii < LOGICAL_PORTS_PER_CARD; ii++) { | |
1982 | the_port = &card_ptr->ic_port[GET_PHYSICAL_PORT(ii)]. | |
1983 | icp_uart_port[GET_LOGICAL_PORT(ii)]; | |
1984 | if (the_port) | |
1985 | uart_remove_one_port(&ioc3_uart, the_port); | |
1986 | port = card_ptr->ic_port[GET_PHYSICAL_PORT(ii)].icp_port; | |
1987 | if (port && IS_PHYSICAL_PORT(ii) | |
1988 | && (GET_PHYSICAL_PORT(ii) == 0)) { | |
1989 | pci_free_consistent(port->ip_idd->pdev, | |
1990 | TOTAL_RING_BUF_SIZE, | |
1991 | (void *)port->ip_cpu_ringbuf, | |
1992 | port->ip_dma_ringbuf); | |
1993 | kfree(port); | |
1994 | card_ptr->ic_port[GET_PHYSICAL_PORT(ii)]. | |
1995 | icp_port = NULL; | |
1996 | } | |
1997 | } | |
1998 | kfree(card_ptr); | |
1999 | idd->data[is->id] = NULL; | |
2000 | } | |
2001 | return 0; | |
2002 | } | |
2003 | ||
2004 | /** | |
2005 | * ioc3uart_probe - card probe function called from shim driver | |
2006 | * @is: submodule struct for this submodule | |
2007 | * @idd: ioc3 driver data for this card | |
2008 | */ | |
2009 | ||
2010 | static int __devinit | |
2011 | ioc3uart_probe(struct ioc3_submodule *is, struct ioc3_driver_data *idd) | |
2012 | { | |
2013 | struct pci_dev *pdev = idd->pdev; | |
2014 | struct ioc3_card *card_ptr; | |
2015 | int ret = 0; | |
2016 | struct ioc3_port *port; | |
2017 | struct ioc3_port *ports[PORTS_PER_CARD]; | |
2018 | int phys_port; | |
2019 | ||
71cc2c21 | 2020 | DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, is, idd)); |
2d0cfb52 | 2021 | |
8f31bb39 | 2022 | card_ptr = kzalloc(sizeof(struct ioc3_card), GFP_KERNEL); |
2d0cfb52 PG |
2023 | if (!card_ptr) { |
2024 | printk(KERN_WARNING "ioc3_attach_one" | |
2025 | ": unable to get memory for the IOC3\n"); | |
2026 | return -ENOMEM; | |
2027 | } | |
2d0cfb52 PG |
2028 | idd->data[is->id] = card_ptr; |
2029 | Submodule_slot = is->id; | |
2030 | ||
2031 | writel(((UARTA_BASE >> 3) << SIO_CR_SER_A_BASE_SHIFT) | | |
2032 | ((UARTB_BASE >> 3) << SIO_CR_SER_B_BASE_SHIFT) | | |
2033 | (0xf << SIO_CR_CMD_PULSE_SHIFT), &idd->vma->sio_cr); | |
2034 | ||
2035 | pci_write_config_dword(pdev, PCI_LAT, 0xff00); | |
2036 | ||
2037 | /* Enable serial port mode select generic PIO pins as outputs */ | |
2038 | ioc3_gpcr_set(idd, GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL); | |
2039 | ||
2040 | /* Create port structures for each port */ | |
2041 | for (phys_port = 0; phys_port < PORTS_PER_CARD; phys_port++) { | |
8f31bb39 | 2042 | port = kzalloc(sizeof(struct ioc3_port), GFP_KERNEL); |
2d0cfb52 PG |
2043 | if (!port) { |
2044 | printk(KERN_WARNING | |
2045 | "IOC3 serial memory not available for port\n"); | |
2046 | goto out4; | |
2047 | } | |
2d0cfb52 PG |
2048 | spin_lock_init(&port->ip_lock); |
2049 | ||
2050 | /* we need to remember the previous ones, to point back to | |
2051 | * them farther down - setting up the ring buffers. | |
2052 | */ | |
2053 | ports[phys_port] = port; | |
2054 | ||
2055 | /* init to something useful */ | |
2056 | card_ptr->ic_port[phys_port].icp_port = port; | |
2057 | port->ip_is = is; | |
2058 | port->ip_idd = idd; | |
2059 | port->ip_baud = 9600; | |
2060 | port->ip_card = card_ptr; | |
2061 | port->ip_hooks = &hooks_array[phys_port]; | |
2062 | ||
2063 | /* Setup each port */ | |
2064 | if (phys_port == 0) { | |
2065 | port->ip_serial_regs = &idd->vma->port_a; | |
2066 | port->ip_uart_regs = &idd->vma->sregs.uarta; | |
2067 | ||
2068 | DPRINT_CONFIG(("%s : Port A ip_serial_regs 0x%p " | |
2069 | "ip_uart_regs 0x%p\n", | |
71cc2c21 | 2070 | __func__, |
2d0cfb52 PG |
2071 | (void *)port->ip_serial_regs, |
2072 | (void *)port->ip_uart_regs)); | |
2073 | ||
2074 | /* setup ring buffers */ | |
2075 | port->ip_cpu_ringbuf = pci_alloc_consistent(pdev, | |
2076 | TOTAL_RING_BUF_SIZE, &port->ip_dma_ringbuf); | |
2077 | ||
2078 | BUG_ON(!((((int64_t) port->ip_dma_ringbuf) & | |
2079 | (TOTAL_RING_BUF_SIZE - 1)) == 0)); | |
2080 | port->ip_inring = RING(port, RX_A); | |
2081 | port->ip_outring = RING(port, TX_A); | |
2082 | DPRINT_CONFIG(("%s : Port A ip_cpu_ringbuf 0x%p " | |
2083 | "ip_dma_ringbuf 0x%p, ip_inring 0x%p " | |
2084 | "ip_outring 0x%p\n", | |
71cc2c21 | 2085 | __func__, |
2d0cfb52 PG |
2086 | (void *)port->ip_cpu_ringbuf, |
2087 | (void *)port->ip_dma_ringbuf, | |
2088 | (void *)port->ip_inring, | |
2089 | (void *)port->ip_outring)); | |
2090 | } | |
2091 | else { | |
2092 | port->ip_serial_regs = &idd->vma->port_b; | |
2093 | port->ip_uart_regs = &idd->vma->sregs.uartb; | |
2094 | ||
2095 | DPRINT_CONFIG(("%s : Port B ip_serial_regs 0x%p " | |
2096 | "ip_uart_regs 0x%p\n", | |
71cc2c21 | 2097 | __func__, |
2d0cfb52 PG |
2098 | (void *)port->ip_serial_regs, |
2099 | (void *)port->ip_uart_regs)); | |
2100 | ||
2101 | /* share the ring buffers */ | |
2102 | port->ip_dma_ringbuf = | |
2103 | ports[phys_port - 1]->ip_dma_ringbuf; | |
2104 | port->ip_cpu_ringbuf = | |
2105 | ports[phys_port - 1]->ip_cpu_ringbuf; | |
2106 | port->ip_inring = RING(port, RX_B); | |
2107 | port->ip_outring = RING(port, TX_B); | |
2108 | DPRINT_CONFIG(("%s : Port B ip_cpu_ringbuf 0x%p " | |
2109 | "ip_dma_ringbuf 0x%p, ip_inring 0x%p " | |
2110 | "ip_outring 0x%p\n", | |
71cc2c21 | 2111 | __func__, |
2d0cfb52 PG |
2112 | (void *)port->ip_cpu_ringbuf, |
2113 | (void *)port->ip_dma_ringbuf, | |
2114 | (void *)port->ip_inring, | |
2115 | (void *)port->ip_outring)); | |
2116 | } | |
2117 | ||
2118 | DPRINT_CONFIG(("%s : port %d [addr 0x%p] card_ptr 0x%p", | |
71cc2c21 | 2119 | __func__, |
2d0cfb52 PG |
2120 | phys_port, (void *)port, (void *)card_ptr)); |
2121 | DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n", | |
2122 | (void *)port->ip_serial_regs, | |
2123 | (void *)port->ip_uart_regs)); | |
2124 | ||
2125 | /* Initialize the hardware for IOC3 */ | |
2126 | port_init(port); | |
2127 | ||
2128 | DPRINT_CONFIG(("%s: phys_port %d port 0x%p inring 0x%p " | |
2129 | "outring 0x%p\n", | |
71cc2c21 | 2130 | __func__, |
2d0cfb52 PG |
2131 | phys_port, (void *)port, |
2132 | (void *)port->ip_inring, | |
2133 | (void *)port->ip_outring)); | |
2134 | ||
2135 | } | |
2136 | ||
2137 | /* register port with the serial core */ | |
2138 | ||
2139 | if ((ret = ioc3_serial_core_attach(is, idd))) | |
2140 | goto out4; | |
2141 | ||
2142 | Num_of_ioc3_cards++; | |
2143 | ||
2144 | return ret; | |
2145 | ||
2146 | /* error exits that give back resources */ | |
2147 | out4: | |
2148 | kfree(card_ptr); | |
2149 | return ret; | |
2150 | } | |
2151 | ||
3c0db899 | 2152 | static struct ioc3_submodule ioc3uart_ops = { |
2d0cfb52 PG |
2153 | .name = "IOC3uart", |
2154 | .probe = ioc3uart_probe, | |
2155 | .remove = ioc3uart_remove, | |
2156 | /* call .intr for both ports initially */ | |
2157 | .irq_mask = SIO_IR_SA | SIO_IR_SB, | |
2158 | .intr = ioc3uart_intr, | |
2159 | .owner = THIS_MODULE, | |
2160 | }; | |
2161 | ||
2162 | /** | |
2163 | * ioc3_detect - module init called, | |
2164 | */ | |
2ea5d35a | 2165 | static int __init ioc3uart_init(void) |
2d0cfb52 PG |
2166 | { |
2167 | int ret; | |
2168 | ||
2169 | /* register with serial core */ | |
2170 | if ((ret = uart_register_driver(&ioc3_uart)) < 0) { | |
2171 | printk(KERN_WARNING | |
2172 | "%s: Couldn't register IOC3 uart serial driver\n", | |
71cc2c21 | 2173 | __func__); |
2d0cfb52 PG |
2174 | return ret; |
2175 | } | |
3c0db899 | 2176 | ret = ioc3_register_submodule(&ioc3uart_ops); |
2d0cfb52 PG |
2177 | if (ret) |
2178 | uart_unregister_driver(&ioc3_uart); | |
2179 | return ret; | |
2180 | } | |
2181 | ||
2ea5d35a | 2182 | static void __exit ioc3uart_exit(void) |
2d0cfb52 | 2183 | { |
3c0db899 | 2184 | ioc3_unregister_submodule(&ioc3uart_ops); |
2d0cfb52 PG |
2185 | uart_unregister_driver(&ioc3_uart); |
2186 | } | |
2187 | ||
2188 | module_init(ioc3uart_init); | |
2189 | module_exit(ioc3uart_exit); | |
2190 | ||
2191 | MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>"); | |
2192 | MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC3 card"); | |
2193 | MODULE_LICENSE("GPL"); |