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5762ab71 RP |
1 | /* |
2 | * Marvell Armada-3700 SPI controller driver | |
3 | * | |
4 | * Copyright (C) 2016 Marvell Ltd. | |
5 | * | |
6 | * Author: Wilson Ding <dingwei@marvell.com> | |
7 | * Author: Romain Perier <romain.perier@free-electrons.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/completion.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_irq.h> | |
24 | #include <linux/of_device.h> | |
25 | #include <linux/pinctrl/consumer.h> | |
26 | #include <linux/spi/spi.h> | |
27 | ||
28 | #define DRIVER_NAME "armada_3700_spi" | |
29 | ||
30 | #define A3700_SPI_TIMEOUT 10 | |
31 | ||
32 | /* SPI Register Offest */ | |
33 | #define A3700_SPI_IF_CTRL_REG 0x00 | |
34 | #define A3700_SPI_IF_CFG_REG 0x04 | |
35 | #define A3700_SPI_DATA_OUT_REG 0x08 | |
36 | #define A3700_SPI_DATA_IN_REG 0x0C | |
37 | #define A3700_SPI_IF_INST_REG 0x10 | |
38 | #define A3700_SPI_IF_ADDR_REG 0x14 | |
39 | #define A3700_SPI_IF_RMODE_REG 0x18 | |
40 | #define A3700_SPI_IF_HDR_CNT_REG 0x1C | |
41 | #define A3700_SPI_IF_DIN_CNT_REG 0x20 | |
42 | #define A3700_SPI_IF_TIME_REG 0x24 | |
43 | #define A3700_SPI_INT_STAT_REG 0x28 | |
44 | #define A3700_SPI_INT_MASK_REG 0x2C | |
45 | ||
46 | /* A3700_SPI_IF_CTRL_REG */ | |
47 | #define A3700_SPI_EN BIT(16) | |
48 | #define A3700_SPI_ADDR_NOT_CONFIG BIT(12) | |
49 | #define A3700_SPI_WFIFO_OVERFLOW BIT(11) | |
50 | #define A3700_SPI_WFIFO_UNDERFLOW BIT(10) | |
51 | #define A3700_SPI_RFIFO_OVERFLOW BIT(9) | |
52 | #define A3700_SPI_RFIFO_UNDERFLOW BIT(8) | |
53 | #define A3700_SPI_WFIFO_FULL BIT(7) | |
54 | #define A3700_SPI_WFIFO_EMPTY BIT(6) | |
55 | #define A3700_SPI_RFIFO_FULL BIT(5) | |
56 | #define A3700_SPI_RFIFO_EMPTY BIT(4) | |
57 | #define A3700_SPI_WFIFO_RDY BIT(3) | |
58 | #define A3700_SPI_RFIFO_RDY BIT(2) | |
59 | #define A3700_SPI_XFER_RDY BIT(1) | |
60 | #define A3700_SPI_XFER_DONE BIT(0) | |
61 | ||
62 | /* A3700_SPI_IF_CFG_REG */ | |
63 | #define A3700_SPI_WFIFO_THRS BIT(28) | |
64 | #define A3700_SPI_RFIFO_THRS BIT(24) | |
65 | #define A3700_SPI_AUTO_CS BIT(20) | |
66 | #define A3700_SPI_DMA_RD_EN BIT(18) | |
67 | #define A3700_SPI_FIFO_MODE BIT(17) | |
68 | #define A3700_SPI_SRST BIT(16) | |
69 | #define A3700_SPI_XFER_START BIT(15) | |
70 | #define A3700_SPI_XFER_STOP BIT(14) | |
71 | #define A3700_SPI_INST_PIN BIT(13) | |
72 | #define A3700_SPI_ADDR_PIN BIT(12) | |
73 | #define A3700_SPI_DATA_PIN1 BIT(11) | |
74 | #define A3700_SPI_DATA_PIN0 BIT(10) | |
75 | #define A3700_SPI_FIFO_FLUSH BIT(9) | |
76 | #define A3700_SPI_RW_EN BIT(8) | |
77 | #define A3700_SPI_CLK_POL BIT(7) | |
78 | #define A3700_SPI_CLK_PHA BIT(6) | |
79 | #define A3700_SPI_BYTE_LEN BIT(5) | |
80 | #define A3700_SPI_CLK_PRESCALE BIT(0) | |
81 | #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) | |
82 | ||
83 | #define A3700_SPI_WFIFO_THRS_BIT 28 | |
84 | #define A3700_SPI_RFIFO_THRS_BIT 24 | |
85 | #define A3700_SPI_FIFO_THRS_MASK 0x7 | |
86 | ||
87 | #define A3700_SPI_DATA_PIN_MASK 0x3 | |
88 | ||
89 | /* A3700_SPI_IF_HDR_CNT_REG */ | |
90 | #define A3700_SPI_DUMMY_CNT_BIT 12 | |
91 | #define A3700_SPI_DUMMY_CNT_MASK 0x7 | |
92 | #define A3700_SPI_RMODE_CNT_BIT 8 | |
93 | #define A3700_SPI_RMODE_CNT_MASK 0x3 | |
94 | #define A3700_SPI_ADDR_CNT_BIT 4 | |
95 | #define A3700_SPI_ADDR_CNT_MASK 0x7 | |
96 | #define A3700_SPI_INSTR_CNT_BIT 0 | |
97 | #define A3700_SPI_INSTR_CNT_MASK 0x3 | |
98 | ||
99 | /* A3700_SPI_IF_TIME_REG */ | |
100 | #define A3700_SPI_CLK_CAPT_EDGE BIT(7) | |
101 | ||
102 | /* Flags and macros for struct a3700_spi */ | |
103 | #define A3700_INSTR_CNT 1 | |
104 | #define A3700_ADDR_CNT 3 | |
105 | #define A3700_DUMMY_CNT 1 | |
106 | ||
107 | struct a3700_spi { | |
108 | struct spi_master *master; | |
109 | void __iomem *base; | |
110 | struct clk *clk; | |
111 | unsigned int irq; | |
112 | unsigned int flags; | |
113 | bool xmit_data; | |
114 | const u8 *tx_buf; | |
115 | u8 *rx_buf; | |
116 | size_t buf_len; | |
117 | u8 byte_len; | |
118 | u32 wait_mask; | |
119 | struct completion done; | |
120 | u32 addr_cnt; | |
121 | u32 instr_cnt; | |
122 | size_t hdr_cnt; | |
123 | }; | |
124 | ||
125 | static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) | |
126 | { | |
127 | return readl(a3700_spi->base + offset); | |
128 | } | |
129 | ||
130 | static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) | |
131 | { | |
132 | writel(data, a3700_spi->base + offset); | |
133 | } | |
134 | ||
135 | static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) | |
136 | { | |
137 | u32 val; | |
138 | ||
139 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
140 | val &= ~A3700_SPI_AUTO_CS; | |
141 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
142 | } | |
143 | ||
144 | static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) | |
145 | { | |
146 | u32 val; | |
147 | ||
148 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
149 | val |= (A3700_SPI_EN << cs); | |
150 | spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); | |
151 | } | |
152 | ||
153 | static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, | |
154 | unsigned int cs) | |
155 | { | |
156 | u32 val; | |
157 | ||
158 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
159 | val &= ~(A3700_SPI_EN << cs); | |
160 | spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); | |
161 | } | |
162 | ||
163 | static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, | |
d227be3f | 164 | unsigned int pin_mode, bool receiving) |
5762ab71 RP |
165 | { |
166 | u32 val; | |
167 | ||
168 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
169 | val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); | |
170 | val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); | |
171 | ||
172 | switch (pin_mode) { | |
cfd6693c | 173 | case SPI_NBITS_SINGLE: |
5762ab71 | 174 | break; |
cfd6693c | 175 | case SPI_NBITS_DUAL: |
5762ab71 RP |
176 | val |= A3700_SPI_DATA_PIN0; |
177 | break; | |
cfd6693c | 178 | case SPI_NBITS_QUAD: |
5762ab71 | 179 | val |= A3700_SPI_DATA_PIN1; |
d227be3f MR |
180 | /* RX during address reception uses 4-pin */ |
181 | if (receiving) | |
182 | val |= A3700_SPI_ADDR_PIN; | |
5762ab71 RP |
183 | break; |
184 | default: | |
185 | dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); | |
186 | return -EINVAL; | |
187 | } | |
188 | ||
189 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi) | |
195 | { | |
196 | u32 val; | |
197 | ||
198 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
199 | val |= A3700_SPI_FIFO_MODE; | |
200 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
201 | } | |
202 | ||
203 | static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, | |
204 | unsigned int mode_bits) | |
205 | { | |
206 | u32 val; | |
207 | ||
208 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
209 | ||
210 | if (mode_bits & SPI_CPOL) | |
211 | val |= A3700_SPI_CLK_POL; | |
212 | else | |
213 | val &= ~A3700_SPI_CLK_POL; | |
214 | ||
215 | if (mode_bits & SPI_CPHA) | |
216 | val |= A3700_SPI_CLK_PHA; | |
217 | else | |
218 | val &= ~A3700_SPI_CLK_PHA; | |
219 | ||
220 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
221 | } | |
222 | ||
223 | static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, | |
224 | unsigned int speed_hz, u16 mode) | |
225 | { | |
226 | u32 val; | |
227 | u32 prescale; | |
228 | ||
229 | prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); | |
230 | ||
231 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
232 | val = val & ~A3700_SPI_CLK_PRESCALE_MASK; | |
233 | ||
234 | val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); | |
235 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
236 | ||
237 | if (prescale <= 2) { | |
238 | val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); | |
239 | val |= A3700_SPI_CLK_CAPT_EDGE; | |
240 | spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); | |
241 | } | |
242 | ||
243 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
244 | val &= ~(A3700_SPI_CLK_POL | A3700_SPI_CLK_PHA); | |
245 | ||
246 | if (mode & SPI_CPOL) | |
247 | val |= A3700_SPI_CLK_POL; | |
248 | ||
249 | if (mode & SPI_CPHA) | |
250 | val |= A3700_SPI_CLK_PHA; | |
251 | ||
252 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
253 | } | |
254 | ||
255 | static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) | |
256 | { | |
257 | u32 val; | |
258 | ||
259 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
260 | if (len == 4) | |
261 | val |= A3700_SPI_BYTE_LEN; | |
262 | else | |
263 | val &= ~A3700_SPI_BYTE_LEN; | |
264 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
265 | ||
266 | a3700_spi->byte_len = len; | |
267 | } | |
268 | ||
269 | static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) | |
270 | { | |
271 | int timeout = A3700_SPI_TIMEOUT; | |
272 | u32 val; | |
273 | ||
274 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
275 | val |= A3700_SPI_FIFO_FLUSH; | |
276 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
277 | ||
278 | while (--timeout) { | |
279 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
280 | if (!(val & A3700_SPI_FIFO_FLUSH)) | |
281 | return 0; | |
282 | udelay(1); | |
283 | } | |
284 | ||
285 | return -ETIMEDOUT; | |
286 | } | |
287 | ||
288 | static int a3700_spi_init(struct a3700_spi *a3700_spi) | |
289 | { | |
290 | struct spi_master *master = a3700_spi->master; | |
291 | u32 val; | |
292 | int i, ret = 0; | |
293 | ||
294 | /* Reset SPI unit */ | |
295 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
296 | val |= A3700_SPI_SRST; | |
297 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
298 | ||
299 | udelay(A3700_SPI_TIMEOUT); | |
300 | ||
301 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
302 | val &= ~A3700_SPI_SRST; | |
303 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
304 | ||
305 | /* Disable AUTO_CS and deactivate all chip-selects */ | |
306 | a3700_spi_auto_cs_unset(a3700_spi); | |
307 | for (i = 0; i < master->num_chipselect; i++) | |
308 | a3700_spi_deactivate_cs(a3700_spi, i); | |
309 | ||
310 | /* Enable FIFO mode */ | |
311 | a3700_spi_fifo_mode_set(a3700_spi); | |
312 | ||
313 | /* Set SPI mode */ | |
314 | a3700_spi_mode_set(a3700_spi, master->mode_bits); | |
315 | ||
316 | /* Reset counters */ | |
317 | spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); | |
318 | spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); | |
319 | ||
320 | /* Mask the interrupts and clear cause bits */ | |
321 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
322 | spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); | |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
327 | static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) | |
328 | { | |
329 | struct spi_master *master = dev_id; | |
330 | struct a3700_spi *a3700_spi; | |
331 | u32 cause; | |
332 | ||
333 | a3700_spi = spi_master_get_devdata(master); | |
334 | ||
335 | /* Get interrupt causes */ | |
336 | cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); | |
337 | ||
338 | if (!cause || !(a3700_spi->wait_mask & cause)) | |
339 | return IRQ_NONE; | |
340 | ||
341 | /* mask and acknowledge the SPI interrupts */ | |
342 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
343 | spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); | |
344 | ||
345 | /* Wake up the transfer */ | |
0cc059ab | 346 | complete(&a3700_spi->done); |
5762ab71 RP |
347 | |
348 | return IRQ_HANDLED; | |
349 | } | |
350 | ||
351 | static bool a3700_spi_wait_completion(struct spi_device *spi) | |
352 | { | |
353 | struct a3700_spi *a3700_spi; | |
354 | unsigned int timeout; | |
355 | unsigned int ctrl_reg; | |
356 | unsigned long timeout_jiffies; | |
357 | ||
358 | a3700_spi = spi_master_get_devdata(spi->master); | |
359 | ||
360 | /* SPI interrupt is edge-triggered, which means an interrupt will | |
361 | * be generated only when detecting a specific status bit changed | |
362 | * from '0' to '1'. So when we start waiting for a interrupt, we | |
363 | * need to check status bit in control reg first, if it is already 1, | |
364 | * then we do not need to wait for interrupt | |
365 | */ | |
366 | ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
367 | if (a3700_spi->wait_mask & ctrl_reg) | |
368 | return true; | |
369 | ||
370 | reinit_completion(&a3700_spi->done); | |
371 | ||
372 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, | |
373 | a3700_spi->wait_mask); | |
374 | ||
375 | timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); | |
376 | timeout = wait_for_completion_timeout(&a3700_spi->done, | |
377 | timeout_jiffies); | |
378 | ||
379 | a3700_spi->wait_mask = 0; | |
380 | ||
381 | if (timeout) | |
382 | return true; | |
383 | ||
384 | /* there might be the case that right after we checked the | |
385 | * status bits in this routine and before start to wait for | |
386 | * interrupt by wait_for_completion_timeout, the interrupt | |
387 | * happens, to avoid missing it we need to double check | |
388 | * status bits in control reg, if it is already 1, then | |
389 | * consider that we have the interrupt successfully and | |
390 | * return true. | |
391 | */ | |
392 | ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
393 | if (a3700_spi->wait_mask & ctrl_reg) | |
394 | return true; | |
395 | ||
396 | spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); | |
397 | ||
b6534e3f MC |
398 | /* Timeout was reached */ |
399 | return false; | |
5762ab71 RP |
400 | } |
401 | ||
402 | static bool a3700_spi_transfer_wait(struct spi_device *spi, | |
403 | unsigned int bit_mask) | |
404 | { | |
405 | struct a3700_spi *a3700_spi; | |
406 | ||
407 | a3700_spi = spi_master_get_devdata(spi->master); | |
408 | a3700_spi->wait_mask = bit_mask; | |
409 | ||
410 | return a3700_spi_wait_completion(spi); | |
411 | } | |
412 | ||
413 | static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, | |
414 | unsigned int bytes) | |
415 | { | |
416 | u32 val; | |
417 | ||
418 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
419 | val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); | |
420 | val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; | |
421 | val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); | |
422 | val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; | |
423 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
424 | } | |
425 | ||
426 | static void a3700_spi_transfer_setup(struct spi_device *spi, | |
85798e15 | 427 | struct spi_transfer *xfer) |
5762ab71 RP |
428 | { |
429 | struct a3700_spi *a3700_spi; | |
430 | unsigned int byte_len; | |
431 | ||
432 | a3700_spi = spi_master_get_devdata(spi->master); | |
433 | ||
434 | a3700_spi_clock_set(a3700_spi, xfer->speed_hz, spi->mode); | |
435 | ||
436 | byte_len = xfer->bits_per_word >> 3; | |
437 | ||
438 | a3700_spi_fifo_thres_set(a3700_spi, byte_len); | |
439 | } | |
440 | ||
441 | static void a3700_spi_set_cs(struct spi_device *spi, bool enable) | |
442 | { | |
443 | struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); | |
444 | ||
445 | if (!enable) | |
446 | a3700_spi_activate_cs(a3700_spi, spi->chip_select); | |
447 | else | |
448 | a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); | |
449 | } | |
450 | ||
451 | static void a3700_spi_header_set(struct a3700_spi *a3700_spi) | |
452 | { | |
453 | u32 instr_cnt = 0, addr_cnt = 0, dummy_cnt = 0; | |
454 | u32 val = 0; | |
455 | ||
456 | /* Clear the header registers */ | |
457 | spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); | |
458 | spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); | |
459 | spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); | |
460 | ||
461 | /* Set header counters */ | |
462 | if (a3700_spi->tx_buf) { | |
463 | if (a3700_spi->buf_len <= a3700_spi->instr_cnt) { | |
464 | instr_cnt = a3700_spi->buf_len; | |
465 | } else if (a3700_spi->buf_len <= (a3700_spi->instr_cnt + | |
466 | a3700_spi->addr_cnt)) { | |
467 | instr_cnt = a3700_spi->instr_cnt; | |
468 | addr_cnt = a3700_spi->buf_len - instr_cnt; | |
469 | } else if (a3700_spi->buf_len <= a3700_spi->hdr_cnt) { | |
470 | instr_cnt = a3700_spi->instr_cnt; | |
471 | addr_cnt = a3700_spi->addr_cnt; | |
472 | /* Need to handle the normal write case with 1 byte | |
473 | * data | |
474 | */ | |
475 | if (!a3700_spi->tx_buf[instr_cnt + addr_cnt]) | |
476 | dummy_cnt = a3700_spi->buf_len - instr_cnt - | |
477 | addr_cnt; | |
478 | } | |
479 | val |= ((instr_cnt & A3700_SPI_INSTR_CNT_MASK) | |
480 | << A3700_SPI_INSTR_CNT_BIT); | |
481 | val |= ((addr_cnt & A3700_SPI_ADDR_CNT_MASK) | |
482 | << A3700_SPI_ADDR_CNT_BIT); | |
483 | val |= ((dummy_cnt & A3700_SPI_DUMMY_CNT_MASK) | |
484 | << A3700_SPI_DUMMY_CNT_BIT); | |
485 | } | |
486 | spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); | |
487 | ||
488 | /* Update the buffer length to be transferred */ | |
489 | a3700_spi->buf_len -= (instr_cnt + addr_cnt + dummy_cnt); | |
490 | ||
491 | /* Set Instruction */ | |
492 | val = 0; | |
493 | while (instr_cnt--) { | |
494 | val = (val << 8) | a3700_spi->tx_buf[0]; | |
495 | a3700_spi->tx_buf++; | |
496 | } | |
497 | spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, val); | |
498 | ||
499 | /* Set Address */ | |
500 | val = 0; | |
501 | while (addr_cnt--) { | |
502 | val = (val << 8) | a3700_spi->tx_buf[0]; | |
503 | a3700_spi->tx_buf++; | |
504 | } | |
505 | spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); | |
506 | } | |
507 | ||
508 | static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) | |
509 | { | |
510 | u32 val; | |
511 | ||
512 | val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
513 | return (val & A3700_SPI_WFIFO_FULL); | |
514 | } | |
515 | ||
516 | static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) | |
517 | { | |
518 | u32 val; | |
519 | int i = 0; | |
520 | ||
521 | while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { | |
522 | val = 0; | |
523 | if (a3700_spi->buf_len >= 4) { | |
524 | val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf); | |
525 | spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); | |
526 | ||
527 | a3700_spi->buf_len -= 4; | |
528 | a3700_spi->tx_buf += 4; | |
529 | } else { | |
530 | /* | |
531 | * If the remained buffer length is less than 4-bytes, | |
532 | * we should pad the write buffer with all ones. So that | |
533 | * it avoids overwrite the unexpected bytes following | |
534 | * the last one. | |
535 | */ | |
536 | val = GENMASK(31, 0); | |
537 | while (a3700_spi->buf_len) { | |
538 | val &= ~(0xff << (8 * i)); | |
539 | val |= *a3700_spi->tx_buf++ << (8 * i); | |
540 | i++; | |
541 | a3700_spi->buf_len--; | |
542 | ||
543 | spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, | |
544 | val); | |
545 | } | |
546 | break; | |
547 | } | |
548 | } | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
553 | static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) | |
554 | { | |
555 | u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); | |
556 | ||
557 | return (val & A3700_SPI_RFIFO_EMPTY); | |
558 | } | |
559 | ||
560 | static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) | |
561 | { | |
562 | u32 val; | |
563 | ||
564 | while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { | |
565 | val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); | |
566 | if (a3700_spi->buf_len >= 4) { | |
567 | u32 data = le32_to_cpu(val); | |
85798e15 | 568 | |
5762ab71 RP |
569 | memcpy(a3700_spi->rx_buf, &data, 4); |
570 | ||
571 | a3700_spi->buf_len -= 4; | |
572 | a3700_spi->rx_buf += 4; | |
573 | } else { | |
574 | /* | |
575 | * When remain bytes is not larger than 4, we should | |
576 | * avoid memory overwriting and just write the left rx | |
577 | * buffer bytes. | |
578 | */ | |
579 | while (a3700_spi->buf_len) { | |
580 | *a3700_spi->rx_buf = val & 0xff; | |
581 | val >>= 8; | |
582 | ||
583 | a3700_spi->buf_len--; | |
584 | a3700_spi->rx_buf++; | |
585 | } | |
586 | } | |
587 | } | |
588 | ||
589 | return 0; | |
590 | } | |
591 | ||
592 | static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) | |
593 | { | |
594 | int timeout = A3700_SPI_TIMEOUT; | |
595 | u32 val; | |
596 | ||
597 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
598 | val |= A3700_SPI_XFER_STOP; | |
599 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
600 | ||
601 | while (--timeout) { | |
602 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
603 | if (!(val & A3700_SPI_XFER_START)) | |
604 | break; | |
605 | udelay(1); | |
606 | } | |
607 | ||
608 | a3700_spi_fifo_flush(a3700_spi); | |
609 | ||
610 | val &= ~A3700_SPI_XFER_STOP; | |
611 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
612 | } | |
613 | ||
614 | static int a3700_spi_prepare_message(struct spi_master *master, | |
615 | struct spi_message *message) | |
616 | { | |
617 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
618 | struct spi_device *spi = message->spi; | |
619 | int ret; | |
620 | ||
621 | ret = clk_enable(a3700_spi->clk); | |
622 | if (ret) { | |
623 | dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); | |
624 | return ret; | |
625 | } | |
626 | ||
627 | /* Flush the FIFOs */ | |
628 | ret = a3700_spi_fifo_flush(a3700_spi); | |
629 | if (ret) | |
630 | return ret; | |
631 | ||
632 | a3700_spi_bytelen_set(a3700_spi, 4); | |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
637 | static int a3700_spi_transfer_one(struct spi_master *master, | |
638 | struct spi_device *spi, | |
639 | struct spi_transfer *xfer) | |
640 | { | |
641 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
642 | int ret = 0, timeout = A3700_SPI_TIMEOUT; | |
643 | unsigned int nbits = 0; | |
644 | u32 val; | |
645 | ||
646 | a3700_spi_transfer_setup(spi, xfer); | |
647 | ||
648 | a3700_spi->tx_buf = xfer->tx_buf; | |
649 | a3700_spi->rx_buf = xfer->rx_buf; | |
650 | a3700_spi->buf_len = xfer->len; | |
651 | ||
652 | /* SPI transfer headers */ | |
653 | a3700_spi_header_set(a3700_spi); | |
654 | ||
655 | if (xfer->tx_buf) | |
656 | nbits = xfer->tx_nbits; | |
657 | else if (xfer->rx_buf) | |
658 | nbits = xfer->rx_nbits; | |
659 | ||
d227be3f | 660 | a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); |
5762ab71 RP |
661 | |
662 | if (xfer->rx_buf) { | |
663 | /* Set read data length */ | |
664 | spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, | |
665 | a3700_spi->buf_len); | |
666 | /* Start READ transfer */ | |
667 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
668 | val &= ~A3700_SPI_RW_EN; | |
669 | val |= A3700_SPI_XFER_START; | |
670 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
671 | } else if (xfer->tx_buf) { | |
672 | /* Start Write transfer */ | |
673 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
674 | val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); | |
675 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
676 | ||
677 | /* | |
678 | * If there are data to be written to the SPI device, xmit_data | |
679 | * flag is set true; otherwise the instruction in SPI_INSTR does | |
680 | * not require data to be written to the SPI device, then | |
681 | * xmit_data flag is set false. | |
682 | */ | |
683 | a3700_spi->xmit_data = (a3700_spi->buf_len != 0); | |
684 | } | |
685 | ||
686 | while (a3700_spi->buf_len) { | |
687 | if (a3700_spi->tx_buf) { | |
688 | /* Wait wfifo ready */ | |
689 | if (!a3700_spi_transfer_wait(spi, | |
690 | A3700_SPI_WFIFO_RDY)) { | |
691 | dev_err(&spi->dev, | |
692 | "wait wfifo ready timed out\n"); | |
693 | ret = -ETIMEDOUT; | |
694 | goto error; | |
695 | } | |
696 | /* Fill up the wfifo */ | |
697 | ret = a3700_spi_fifo_write(a3700_spi); | |
698 | if (ret) | |
699 | goto error; | |
700 | } else if (a3700_spi->rx_buf) { | |
701 | /* Wait rfifo ready */ | |
702 | if (!a3700_spi_transfer_wait(spi, | |
703 | A3700_SPI_RFIFO_RDY)) { | |
704 | dev_err(&spi->dev, | |
705 | "wait rfifo ready timed out\n"); | |
706 | ret = -ETIMEDOUT; | |
707 | goto error; | |
708 | } | |
709 | /* Drain out the rfifo */ | |
710 | ret = a3700_spi_fifo_read(a3700_spi); | |
711 | if (ret) | |
712 | goto error; | |
713 | } | |
714 | } | |
715 | ||
716 | /* | |
717 | * Stop a write transfer in fifo mode: | |
718 | * - wait all the bytes in wfifo to be shifted out | |
719 | * - set XFER_STOP bit | |
720 | * - wait XFER_START bit clear | |
721 | * - clear XFER_STOP bit | |
722 | * Stop a read transfer in fifo mode: | |
723 | * - the hardware is to reset the XFER_START bit | |
724 | * after the number of bytes indicated in DIN_CNT | |
725 | * register | |
726 | * - just wait XFER_START bit clear | |
727 | */ | |
728 | if (a3700_spi->tx_buf) { | |
729 | if (a3700_spi->xmit_data) { | |
730 | /* | |
731 | * If there are data written to the SPI device, wait | |
732 | * until SPI_WFIFO_EMPTY is 1 to wait for all data to | |
733 | * transfer out of write FIFO. | |
734 | */ | |
735 | if (!a3700_spi_transfer_wait(spi, | |
736 | A3700_SPI_WFIFO_EMPTY)) { | |
737 | dev_err(&spi->dev, "wait wfifo empty timed out\n"); | |
738 | return -ETIMEDOUT; | |
739 | } | |
740 | } else { | |
741 | /* | |
742 | * If the instruction in SPI_INSTR does not require data | |
743 | * to be written to the SPI device, wait until SPI_RDY | |
744 | * is 1 for the SPI interface to be in idle. | |
745 | */ | |
746 | if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { | |
747 | dev_err(&spi->dev, "wait xfer ready timed out\n"); | |
748 | return -ETIMEDOUT; | |
749 | } | |
750 | } | |
751 | ||
752 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
753 | val |= A3700_SPI_XFER_STOP; | |
754 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
755 | } | |
756 | ||
757 | while (--timeout) { | |
758 | val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); | |
759 | if (!(val & A3700_SPI_XFER_START)) | |
760 | break; | |
761 | udelay(1); | |
762 | } | |
763 | ||
764 | if (timeout == 0) { | |
765 | dev_err(&spi->dev, "wait transfer start clear timed out\n"); | |
766 | ret = -ETIMEDOUT; | |
767 | goto error; | |
768 | } | |
769 | ||
770 | val &= ~A3700_SPI_XFER_STOP; | |
771 | spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); | |
772 | goto out; | |
773 | ||
774 | error: | |
775 | a3700_spi_transfer_abort_fifo(a3700_spi); | |
776 | out: | |
777 | spi_finalize_current_transfer(master); | |
778 | ||
779 | return ret; | |
780 | } | |
781 | ||
782 | static int a3700_spi_unprepare_message(struct spi_master *master, | |
783 | struct spi_message *message) | |
784 | { | |
785 | struct a3700_spi *a3700_spi = spi_master_get_devdata(master); | |
786 | ||
787 | clk_disable(a3700_spi->clk); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | static const struct of_device_id a3700_spi_dt_ids[] = { | |
793 | { .compatible = "marvell,armada-3700-spi", .data = NULL }, | |
794 | {}, | |
795 | }; | |
796 | ||
797 | MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); | |
798 | ||
799 | static int a3700_spi_probe(struct platform_device *pdev) | |
800 | { | |
801 | struct device *dev = &pdev->dev; | |
802 | struct device_node *of_node = dev->of_node; | |
803 | struct resource *res; | |
804 | struct spi_master *master; | |
805 | struct a3700_spi *spi; | |
806 | u32 num_cs = 0; | |
f6f0083c | 807 | int irq, ret = 0; |
5762ab71 RP |
808 | |
809 | master = spi_alloc_master(dev, sizeof(*spi)); | |
810 | if (!master) { | |
811 | dev_err(dev, "master allocation failed\n"); | |
812 | ret = -ENOMEM; | |
813 | goto out; | |
814 | } | |
815 | ||
816 | if (of_property_read_u32(of_node, "num-cs", &num_cs)) { | |
817 | dev_err(dev, "could not find num-cs\n"); | |
818 | ret = -ENXIO; | |
819 | goto error; | |
820 | } | |
821 | ||
822 | master->bus_num = pdev->id; | |
823 | master->dev.of_node = of_node; | |
824 | master->mode_bits = SPI_MODE_3; | |
825 | master->num_chipselect = num_cs; | |
826 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); | |
827 | master->prepare_message = a3700_spi_prepare_message; | |
828 | master->transfer_one = a3700_spi_transfer_one; | |
829 | master->unprepare_message = a3700_spi_unprepare_message; | |
830 | master->set_cs = a3700_spi_set_cs; | |
831 | master->flags = SPI_MASTER_HALF_DUPLEX; | |
42cd4ed8 | 832 | master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL | |
5762ab71 RP |
833 | SPI_RX_QUAD | SPI_TX_QUAD); |
834 | ||
835 | platform_set_drvdata(pdev, master); | |
836 | ||
837 | spi = spi_master_get_devdata(master); | |
838 | memset(spi, 0, sizeof(struct a3700_spi)); | |
839 | ||
840 | spi->master = master; | |
841 | spi->instr_cnt = A3700_INSTR_CNT; | |
842 | spi->addr_cnt = A3700_ADDR_CNT; | |
843 | spi->hdr_cnt = A3700_INSTR_CNT + A3700_ADDR_CNT + | |
844 | A3700_DUMMY_CNT; | |
845 | ||
846 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
847 | spi->base = devm_ioremap_resource(dev, res); | |
848 | if (IS_ERR(spi->base)) { | |
849 | ret = PTR_ERR(spi->base); | |
850 | goto error; | |
851 | } | |
852 | ||
f6f0083c CIK |
853 | irq = platform_get_irq(pdev, 0); |
854 | if (irq < 0) { | |
855 | dev_err(dev, "could not get irq: %d\n", irq); | |
5762ab71 RP |
856 | ret = -ENXIO; |
857 | goto error; | |
858 | } | |
f6f0083c | 859 | spi->irq = irq; |
5762ab71 RP |
860 | |
861 | init_completion(&spi->done); | |
862 | ||
863 | spi->clk = devm_clk_get(dev, NULL); | |
864 | if (IS_ERR(spi->clk)) { | |
865 | dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); | |
866 | goto error; | |
867 | } | |
868 | ||
869 | ret = clk_prepare(spi->clk); | |
870 | if (ret) { | |
871 | dev_err(dev, "could not prepare clk: %d\n", ret); | |
872 | goto error; | |
873 | } | |
874 | ||
875 | ret = a3700_spi_init(spi); | |
876 | if (ret) | |
877 | goto error_clk; | |
878 | ||
879 | ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, | |
880 | dev_name(dev), master); | |
881 | if (ret) { | |
882 | dev_err(dev, "could not request IRQ: %d\n", ret); | |
883 | goto error_clk; | |
884 | } | |
885 | ||
886 | ret = devm_spi_register_master(dev, master); | |
887 | if (ret) { | |
888 | dev_err(dev, "Failed to register master\n"); | |
889 | goto error_clk; | |
890 | } | |
891 | ||
892 | return 0; | |
893 | ||
894 | error_clk: | |
895 | clk_disable_unprepare(spi->clk); | |
896 | error: | |
897 | spi_master_put(master); | |
898 | out: | |
899 | return ret; | |
900 | } | |
901 | ||
902 | static int a3700_spi_remove(struct platform_device *pdev) | |
903 | { | |
904 | struct spi_master *master = platform_get_drvdata(pdev); | |
905 | struct a3700_spi *spi = spi_master_get_devdata(master); | |
906 | ||
907 | clk_unprepare(spi->clk); | |
5762ab71 RP |
908 | |
909 | return 0; | |
910 | } | |
911 | ||
912 | static struct platform_driver a3700_spi_driver = { | |
913 | .driver = { | |
914 | .name = DRIVER_NAME, | |
5762ab71 RP |
915 | .of_match_table = of_match_ptr(a3700_spi_dt_ids), |
916 | }, | |
917 | .probe = a3700_spi_probe, | |
918 | .remove = a3700_spi_remove, | |
919 | }; | |
920 | ||
921 | module_platform_driver(a3700_spi_driver); | |
922 | ||
923 | MODULE_DESCRIPTION("Armada-3700 SPI driver"); | |
924 | MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); | |
925 | MODULE_LICENSE("GPL"); | |
926 | MODULE_ALIAS("platform:" DRIVER_NAME); |