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754ce4f2 HS |
1 | /* |
2 | * Driver for Atmel AT32 and AT91 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/spi/spi.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
bcd2360c | 22 | #include <linux/platform_data/atmel.h> |
850a5b67 | 23 | #include <linux/of.h> |
754ce4f2 | 24 | |
d4820b74 WY |
25 | #include <linux/io.h> |
26 | #include <linux/gpio.h> | |
bb2d1c36 | 27 | |
ca632f55 GL |
28 | /* SPI register offsets */ |
29 | #define SPI_CR 0x0000 | |
30 | #define SPI_MR 0x0004 | |
31 | #define SPI_RDR 0x0008 | |
32 | #define SPI_TDR 0x000c | |
33 | #define SPI_SR 0x0010 | |
34 | #define SPI_IER 0x0014 | |
35 | #define SPI_IDR 0x0018 | |
36 | #define SPI_IMR 0x001c | |
37 | #define SPI_CSR0 0x0030 | |
38 | #define SPI_CSR1 0x0034 | |
39 | #define SPI_CSR2 0x0038 | |
40 | #define SPI_CSR3 0x003c | |
d4820b74 | 41 | #define SPI_VERSION 0x00fc |
ca632f55 GL |
42 | #define SPI_RPR 0x0100 |
43 | #define SPI_RCR 0x0104 | |
44 | #define SPI_TPR 0x0108 | |
45 | #define SPI_TCR 0x010c | |
46 | #define SPI_RNPR 0x0110 | |
47 | #define SPI_RNCR 0x0114 | |
48 | #define SPI_TNPR 0x0118 | |
49 | #define SPI_TNCR 0x011c | |
50 | #define SPI_PTCR 0x0120 | |
51 | #define SPI_PTSR 0x0124 | |
52 | ||
53 | /* Bitfields in CR */ | |
54 | #define SPI_SPIEN_OFFSET 0 | |
55 | #define SPI_SPIEN_SIZE 1 | |
56 | #define SPI_SPIDIS_OFFSET 1 | |
57 | #define SPI_SPIDIS_SIZE 1 | |
58 | #define SPI_SWRST_OFFSET 7 | |
59 | #define SPI_SWRST_SIZE 1 | |
60 | #define SPI_LASTXFER_OFFSET 24 | |
61 | #define SPI_LASTXFER_SIZE 1 | |
62 | ||
63 | /* Bitfields in MR */ | |
64 | #define SPI_MSTR_OFFSET 0 | |
65 | #define SPI_MSTR_SIZE 1 | |
66 | #define SPI_PS_OFFSET 1 | |
67 | #define SPI_PS_SIZE 1 | |
68 | #define SPI_PCSDEC_OFFSET 2 | |
69 | #define SPI_PCSDEC_SIZE 1 | |
70 | #define SPI_FDIV_OFFSET 3 | |
71 | #define SPI_FDIV_SIZE 1 | |
72 | #define SPI_MODFDIS_OFFSET 4 | |
73 | #define SPI_MODFDIS_SIZE 1 | |
d4820b74 WY |
74 | #define SPI_WDRBT_OFFSET 5 |
75 | #define SPI_WDRBT_SIZE 1 | |
ca632f55 GL |
76 | #define SPI_LLB_OFFSET 7 |
77 | #define SPI_LLB_SIZE 1 | |
78 | #define SPI_PCS_OFFSET 16 | |
79 | #define SPI_PCS_SIZE 4 | |
80 | #define SPI_DLYBCS_OFFSET 24 | |
81 | #define SPI_DLYBCS_SIZE 8 | |
82 | ||
83 | /* Bitfields in RDR */ | |
84 | #define SPI_RD_OFFSET 0 | |
85 | #define SPI_RD_SIZE 16 | |
86 | ||
87 | /* Bitfields in TDR */ | |
88 | #define SPI_TD_OFFSET 0 | |
89 | #define SPI_TD_SIZE 16 | |
90 | ||
91 | /* Bitfields in SR */ | |
92 | #define SPI_RDRF_OFFSET 0 | |
93 | #define SPI_RDRF_SIZE 1 | |
94 | #define SPI_TDRE_OFFSET 1 | |
95 | #define SPI_TDRE_SIZE 1 | |
96 | #define SPI_MODF_OFFSET 2 | |
97 | #define SPI_MODF_SIZE 1 | |
98 | #define SPI_OVRES_OFFSET 3 | |
99 | #define SPI_OVRES_SIZE 1 | |
100 | #define SPI_ENDRX_OFFSET 4 | |
101 | #define SPI_ENDRX_SIZE 1 | |
102 | #define SPI_ENDTX_OFFSET 5 | |
103 | #define SPI_ENDTX_SIZE 1 | |
104 | #define SPI_RXBUFF_OFFSET 6 | |
105 | #define SPI_RXBUFF_SIZE 1 | |
106 | #define SPI_TXBUFE_OFFSET 7 | |
107 | #define SPI_TXBUFE_SIZE 1 | |
108 | #define SPI_NSSR_OFFSET 8 | |
109 | #define SPI_NSSR_SIZE 1 | |
110 | #define SPI_TXEMPTY_OFFSET 9 | |
111 | #define SPI_TXEMPTY_SIZE 1 | |
112 | #define SPI_SPIENS_OFFSET 16 | |
113 | #define SPI_SPIENS_SIZE 1 | |
114 | ||
115 | /* Bitfields in CSR0 */ | |
116 | #define SPI_CPOL_OFFSET 0 | |
117 | #define SPI_CPOL_SIZE 1 | |
118 | #define SPI_NCPHA_OFFSET 1 | |
119 | #define SPI_NCPHA_SIZE 1 | |
120 | #define SPI_CSAAT_OFFSET 3 | |
121 | #define SPI_CSAAT_SIZE 1 | |
122 | #define SPI_BITS_OFFSET 4 | |
123 | #define SPI_BITS_SIZE 4 | |
124 | #define SPI_SCBR_OFFSET 8 | |
125 | #define SPI_SCBR_SIZE 8 | |
126 | #define SPI_DLYBS_OFFSET 16 | |
127 | #define SPI_DLYBS_SIZE 8 | |
128 | #define SPI_DLYBCT_OFFSET 24 | |
129 | #define SPI_DLYBCT_SIZE 8 | |
130 | ||
131 | /* Bitfields in RCR */ | |
132 | #define SPI_RXCTR_OFFSET 0 | |
133 | #define SPI_RXCTR_SIZE 16 | |
134 | ||
135 | /* Bitfields in TCR */ | |
136 | #define SPI_TXCTR_OFFSET 0 | |
137 | #define SPI_TXCTR_SIZE 16 | |
138 | ||
139 | /* Bitfields in RNCR */ | |
140 | #define SPI_RXNCR_OFFSET 0 | |
141 | #define SPI_RXNCR_SIZE 16 | |
142 | ||
143 | /* Bitfields in TNCR */ | |
144 | #define SPI_TXNCR_OFFSET 0 | |
145 | #define SPI_TXNCR_SIZE 16 | |
146 | ||
147 | /* Bitfields in PTCR */ | |
148 | #define SPI_RXTEN_OFFSET 0 | |
149 | #define SPI_RXTEN_SIZE 1 | |
150 | #define SPI_RXTDIS_OFFSET 1 | |
151 | #define SPI_RXTDIS_SIZE 1 | |
152 | #define SPI_TXTEN_OFFSET 8 | |
153 | #define SPI_TXTEN_SIZE 1 | |
154 | #define SPI_TXTDIS_OFFSET 9 | |
155 | #define SPI_TXTDIS_SIZE 1 | |
156 | ||
157 | /* Constants for BITS */ | |
158 | #define SPI_BITS_8_BPT 0 | |
159 | #define SPI_BITS_9_BPT 1 | |
160 | #define SPI_BITS_10_BPT 2 | |
161 | #define SPI_BITS_11_BPT 3 | |
162 | #define SPI_BITS_12_BPT 4 | |
163 | #define SPI_BITS_13_BPT 5 | |
164 | #define SPI_BITS_14_BPT 6 | |
165 | #define SPI_BITS_15_BPT 7 | |
166 | #define SPI_BITS_16_BPT 8 | |
167 | ||
168 | /* Bit manipulation macros */ | |
169 | #define SPI_BIT(name) \ | |
170 | (1 << SPI_##name##_OFFSET) | |
171 | #define SPI_BF(name,value) \ | |
172 | (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) | |
173 | #define SPI_BFEXT(name,value) \ | |
174 | (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) | |
175 | #define SPI_BFINS(name,value,old) \ | |
176 | ( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ | |
177 | | SPI_BF(name,value)) | |
178 | ||
179 | /* Register access macros */ | |
180 | #define spi_readl(port,reg) \ | |
181 | __raw_readl((port)->regs + SPI_##reg) | |
182 | #define spi_writel(port,reg,value) \ | |
183 | __raw_writel((value), (port)->regs + SPI_##reg) | |
184 | ||
d4820b74 WY |
185 | struct atmel_spi_caps { |
186 | bool is_spi2; | |
187 | bool has_wdrbt; | |
188 | bool has_dma_support; | |
189 | }; | |
754ce4f2 HS |
190 | |
191 | /* | |
192 | * The core SPI transfer engine just talks to a register bank to set up | |
193 | * DMA transfers; transfer queue progress is driven by IRQs. The clock | |
194 | * framework provides the base clock, subdivided for each spi_device. | |
754ce4f2 HS |
195 | */ |
196 | struct atmel_spi { | |
197 | spinlock_t lock; | |
8aad7924 | 198 | unsigned long flags; |
754ce4f2 | 199 | |
dfab30ee | 200 | phys_addr_t phybase; |
754ce4f2 HS |
201 | void __iomem *regs; |
202 | int irq; | |
203 | struct clk *clk; | |
204 | struct platform_device *pdev; | |
defbd3b4 | 205 | struct spi_device *stay; |
754ce4f2 HS |
206 | |
207 | u8 stopping; | |
208 | struct list_head queue; | |
209 | struct spi_transfer *current_transfer; | |
154443c7 SE |
210 | unsigned long current_remaining_bytes; |
211 | struct spi_transfer *next_transfer; | |
212 | unsigned long next_remaining_bytes; | |
823cd045 | 213 | int done_status; |
754ce4f2 HS |
214 | |
215 | void *buffer; | |
216 | dma_addr_t buffer_dma; | |
d4820b74 WY |
217 | |
218 | struct atmel_spi_caps caps; | |
754ce4f2 HS |
219 | }; |
220 | ||
5ee36c98 HS |
221 | /* Controller-specific per-slave state */ |
222 | struct atmel_spi_device { | |
223 | unsigned int npcs_pin; | |
224 | u32 csr; | |
225 | }; | |
226 | ||
754ce4f2 HS |
227 | #define BUFFER_SIZE PAGE_SIZE |
228 | #define INVALID_DMA_ADDRESS 0xffffffff | |
229 | ||
5bfa26ca HS |
230 | /* |
231 | * Version 2 of the SPI controller has | |
232 | * - CR.LASTXFER | |
233 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) | |
234 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) | |
235 | * - SPI_CSRx.CSAAT | |
236 | * - SPI_CSRx.SBCR allows faster clocking | |
5bfa26ca | 237 | */ |
d4820b74 | 238 | static bool atmel_spi_is_v2(struct atmel_spi *as) |
5bfa26ca | 239 | { |
d4820b74 | 240 | return as->caps.is_spi2; |
5bfa26ca HS |
241 | } |
242 | ||
754ce4f2 HS |
243 | /* |
244 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby | |
245 | * they assume that spi slave device state will not change on deselect, so | |
defbd3b4 DB |
246 | * that automagic deselection is OK. ("NPCSx rises if no data is to be |
247 | * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer | |
248 | * controllers have CSAAT and friends. | |
754ce4f2 | 249 | * |
defbd3b4 DB |
250 | * Since the CSAAT functionality is a bit weird on newer controllers as |
251 | * well, we use GPIO to control nCSx pins on all controllers, updating | |
252 | * MR.PCS to avoid confusing the controller. Using GPIOs also lets us | |
253 | * support active-high chipselects despite the controller's belief that | |
254 | * only active-low devices/systems exists. | |
255 | * | |
256 | * However, at91rm9200 has a second erratum whereby nCS0 doesn't work | |
257 | * right when driven with GPIO. ("Mode Fault does not allow more than one | |
258 | * Master on Chip Select 0.") No workaround exists for that ... so for | |
259 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, | |
260 | * and (c) will trigger that first erratum in some cases. | |
754ce4f2 HS |
261 | */ |
262 | ||
defbd3b4 | 263 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 264 | { |
5ee36c98 | 265 | struct atmel_spi_device *asd = spi->controller_state; |
754ce4f2 | 266 | unsigned active = spi->mode & SPI_CS_HIGH; |
defbd3b4 DB |
267 | u32 mr; |
268 | ||
d4820b74 | 269 | if (atmel_spi_is_v2(as)) { |
97ed465b WY |
270 | spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr); |
271 | /* For the low SPI version, there is a issue that PDC transfer | |
272 | * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS | |
5ee36c98 HS |
273 | */ |
274 | spi_writel(as, CSR0, asd->csr); | |
d4820b74 | 275 | if (as->caps.has_wdrbt) { |
97ed465b WY |
276 | spi_writel(as, MR, |
277 | SPI_BF(PCS, ~(0x01 << spi->chip_select)) | |
278 | | SPI_BIT(WDRBT) | |
279 | | SPI_BIT(MODFDIS) | |
280 | | SPI_BIT(MSTR)); | |
d4820b74 | 281 | } else { |
97ed465b WY |
282 | spi_writel(as, MR, |
283 | SPI_BF(PCS, ~(0x01 << spi->chip_select)) | |
284 | | SPI_BIT(MODFDIS) | |
285 | | SPI_BIT(MSTR)); | |
d4820b74 | 286 | } |
5ee36c98 HS |
287 | mr = spi_readl(as, MR); |
288 | gpio_set_value(asd->npcs_pin, active); | |
289 | } else { | |
290 | u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; | |
291 | int i; | |
292 | u32 csr; | |
293 | ||
294 | /* Make sure clock polarity is correct */ | |
295 | for (i = 0; i < spi->master->num_chipselect; i++) { | |
296 | csr = spi_readl(as, CSR0 + 4 * i); | |
297 | if ((csr ^ cpol) & SPI_BIT(CPOL)) | |
298 | spi_writel(as, CSR0 + 4 * i, | |
299 | csr ^ SPI_BIT(CPOL)); | |
300 | } | |
301 | ||
302 | mr = spi_readl(as, MR); | |
303 | mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr); | |
304 | if (spi->chip_select != 0) | |
305 | gpio_set_value(asd->npcs_pin, active); | |
306 | spi_writel(as, MR, mr); | |
307 | } | |
defbd3b4 DB |
308 | |
309 | dev_dbg(&spi->dev, "activate %u%s, mr %08x\n", | |
5ee36c98 | 310 | asd->npcs_pin, active ? " (high)" : "", |
defbd3b4 | 311 | mr); |
754ce4f2 HS |
312 | } |
313 | ||
defbd3b4 | 314 | static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 | 315 | { |
5ee36c98 | 316 | struct atmel_spi_device *asd = spi->controller_state; |
754ce4f2 | 317 | unsigned active = spi->mode & SPI_CS_HIGH; |
defbd3b4 DB |
318 | u32 mr; |
319 | ||
320 | /* only deactivate *this* device; sometimes transfers to | |
321 | * another device may be active when this routine is called. | |
322 | */ | |
323 | mr = spi_readl(as, MR); | |
324 | if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) { | |
325 | mr = SPI_BFINS(PCS, 0xf, mr); | |
326 | spi_writel(as, MR, mr); | |
327 | } | |
754ce4f2 | 328 | |
defbd3b4 | 329 | dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n", |
5ee36c98 | 330 | asd->npcs_pin, active ? " (low)" : "", |
defbd3b4 DB |
331 | mr); |
332 | ||
d4820b74 | 333 | if (atmel_spi_is_v2(as) || spi->chip_select != 0) |
5ee36c98 | 334 | gpio_set_value(asd->npcs_pin, !active); |
754ce4f2 HS |
335 | } |
336 | ||
8aad7924 NF |
337 | static void atmel_spi_lock(struct atmel_spi *as) |
338 | { | |
339 | spin_lock_irqsave(&as->lock, as->flags); | |
340 | } | |
341 | ||
342 | static void atmel_spi_unlock(struct atmel_spi *as) | |
343 | { | |
344 | spin_unlock_irqrestore(&as->lock, as->flags); | |
345 | } | |
346 | ||
154443c7 SE |
347 | static inline int atmel_spi_xfer_is_last(struct spi_message *msg, |
348 | struct spi_transfer *xfer) | |
349 | { | |
350 | return msg->transfers.prev == &xfer->transfer_list; | |
351 | } | |
352 | ||
353 | static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer) | |
354 | { | |
355 | return xfer->delay_usecs == 0 && !xfer->cs_change; | |
356 | } | |
357 | ||
358 | static void atmel_spi_next_xfer_data(struct spi_master *master, | |
359 | struct spi_transfer *xfer, | |
360 | dma_addr_t *tx_dma, | |
361 | dma_addr_t *rx_dma, | |
362 | u32 *plen) | |
363 | { | |
364 | struct atmel_spi *as = spi_master_get_devdata(master); | |
365 | u32 len = *plen; | |
366 | ||
367 | /* use scratch buffer only when rx or tx data is unspecified */ | |
368 | if (xfer->rx_buf) | |
6aed4ee9 | 369 | *rx_dma = xfer->rx_dma + xfer->len - *plen; |
154443c7 SE |
370 | else { |
371 | *rx_dma = as->buffer_dma; | |
372 | if (len > BUFFER_SIZE) | |
373 | len = BUFFER_SIZE; | |
374 | } | |
375 | if (xfer->tx_buf) | |
6aed4ee9 | 376 | *tx_dma = xfer->tx_dma + xfer->len - *plen; |
154443c7 SE |
377 | else { |
378 | *tx_dma = as->buffer_dma; | |
379 | if (len > BUFFER_SIZE) | |
380 | len = BUFFER_SIZE; | |
381 | memset(as->buffer, 0, len); | |
382 | dma_sync_single_for_device(&as->pdev->dev, | |
383 | as->buffer_dma, len, DMA_TO_DEVICE); | |
384 | } | |
385 | ||
386 | *plen = len; | |
387 | } | |
388 | ||
754ce4f2 HS |
389 | /* |
390 | * Submit next transfer for DMA. | |
391 | * lock is held, spi irq is blocked | |
392 | */ | |
393 | static void atmel_spi_next_xfer(struct spi_master *master, | |
394 | struct spi_message *msg) | |
395 | { | |
396 | struct atmel_spi *as = spi_master_get_devdata(master); | |
397 | struct spi_transfer *xfer; | |
dc329442 GK |
398 | u32 len, remaining; |
399 | u32 ieval; | |
754ce4f2 HS |
400 | dma_addr_t tx_dma, rx_dma; |
401 | ||
154443c7 SE |
402 | if (!as->current_transfer) |
403 | xfer = list_entry(msg->transfers.next, | |
404 | struct spi_transfer, transfer_list); | |
405 | else if (!as->next_transfer) | |
406 | xfer = list_entry(as->current_transfer->transfer_list.next, | |
407 | struct spi_transfer, transfer_list); | |
408 | else | |
409 | xfer = NULL; | |
410 | ||
411 | if (xfer) { | |
dc329442 GK |
412 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
413 | ||
154443c7 SE |
414 | len = xfer->len; |
415 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); | |
416 | remaining = xfer->len - len; | |
417 | ||
418 | spi_writel(as, RPR, rx_dma); | |
419 | spi_writel(as, TPR, tx_dma); | |
420 | ||
421 | if (msg->spi->bits_per_word > 8) | |
422 | len >>= 1; | |
423 | spi_writel(as, RCR, len); | |
424 | spi_writel(as, TCR, len); | |
8bacb219 HS |
425 | |
426 | dev_dbg(&msg->spi->dev, | |
427 | " start xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
428 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
429 | xfer->rx_buf, xfer->rx_dma); | |
154443c7 SE |
430 | } else { |
431 | xfer = as->next_transfer; | |
432 | remaining = as->next_remaining_bytes; | |
754ce4f2 HS |
433 | } |
434 | ||
154443c7 SE |
435 | as->current_transfer = xfer; |
436 | as->current_remaining_bytes = remaining; | |
754ce4f2 | 437 | |
154443c7 SE |
438 | if (remaining > 0) |
439 | len = remaining; | |
8bacb219 HS |
440 | else if (!atmel_spi_xfer_is_last(msg, xfer) |
441 | && atmel_spi_xfer_can_be_chained(xfer)) { | |
154443c7 SE |
442 | xfer = list_entry(xfer->transfer_list.next, |
443 | struct spi_transfer, transfer_list); | |
444 | len = xfer->len; | |
445 | } else | |
446 | xfer = NULL; | |
754ce4f2 | 447 | |
154443c7 | 448 | as->next_transfer = xfer; |
754ce4f2 | 449 | |
154443c7 | 450 | if (xfer) { |
dc329442 GK |
451 | u32 total; |
452 | ||
154443c7 SE |
453 | total = len; |
454 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); | |
455 | as->next_remaining_bytes = total - len; | |
754ce4f2 | 456 | |
154443c7 SE |
457 | spi_writel(as, RNPR, rx_dma); |
458 | spi_writel(as, TNPR, tx_dma); | |
754ce4f2 | 459 | |
154443c7 SE |
460 | if (msg->spi->bits_per_word > 8) |
461 | len >>= 1; | |
462 | spi_writel(as, RNCR, len); | |
463 | spi_writel(as, TNCR, len); | |
8bacb219 HS |
464 | |
465 | dev_dbg(&msg->spi->dev, | |
466 | " next xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
467 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
468 | xfer->rx_buf, xfer->rx_dma); | |
dc329442 | 469 | ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES); |
154443c7 SE |
470 | } else { |
471 | spi_writel(as, RNCR, 0); | |
472 | spi_writel(as, TNCR, 0); | |
dc329442 | 473 | ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES); |
154443c7 SE |
474 | } |
475 | ||
476 | /* REVISIT: We're waiting for ENDRX before we start the next | |
754ce4f2 HS |
477 | * transfer because we need to handle some difficult timing |
478 | * issues otherwise. If we wait for ENDTX in one transfer and | |
479 | * then starts waiting for ENDRX in the next, it's difficult | |
480 | * to tell the difference between the ENDRX interrupt we're | |
481 | * actually waiting for and the ENDRX interrupt of the | |
482 | * previous transfer. | |
483 | * | |
484 | * It should be doable, though. Just not now... | |
485 | */ | |
dc329442 | 486 | spi_writel(as, IER, ieval); |
754ce4f2 HS |
487 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); |
488 | } | |
489 | ||
490 | static void atmel_spi_next_message(struct spi_master *master) | |
491 | { | |
492 | struct atmel_spi *as = spi_master_get_devdata(master); | |
493 | struct spi_message *msg; | |
defbd3b4 | 494 | struct spi_device *spi; |
754ce4f2 HS |
495 | |
496 | BUG_ON(as->current_transfer); | |
497 | ||
498 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
defbd3b4 | 499 | spi = msg->spi; |
754ce4f2 | 500 | |
49dce689 | 501 | dev_dbg(master->dev.parent, "start message %p for %s\n", |
6c7377ab | 502 | msg, dev_name(&spi->dev)); |
defbd3b4 DB |
503 | |
504 | /* select chip if it's not still active */ | |
505 | if (as->stay) { | |
506 | if (as->stay != spi) { | |
507 | cs_deactivate(as, as->stay); | |
508 | cs_activate(as, spi); | |
509 | } | |
510 | as->stay = NULL; | |
511 | } else | |
512 | cs_activate(as, spi); | |
754ce4f2 HS |
513 | |
514 | atmel_spi_next_xfer(master, msg); | |
515 | } | |
516 | ||
8da0859a DB |
517 | /* |
518 | * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: | |
519 | * - The buffer is either valid for CPU access, else NULL | |
b595076a | 520 | * - If the buffer is valid, so is its DMA address |
8da0859a | 521 | * |
b595076a | 522 | * This driver manages the dma address unless message->is_dma_mapped. |
8da0859a DB |
523 | */ |
524 | static int | |
754ce4f2 HS |
525 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) |
526 | { | |
8da0859a DB |
527 | struct device *dev = &as->pdev->dev; |
528 | ||
754ce4f2 | 529 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; |
8da0859a | 530 | if (xfer->tx_buf) { |
214b574a JCPV |
531 | /* tx_buf is a const void* where we need a void * for the dma |
532 | * mapping */ | |
533 | void *nonconst_tx = (void *)xfer->tx_buf; | |
534 | ||
8da0859a | 535 | xfer->tx_dma = dma_map_single(dev, |
214b574a | 536 | nonconst_tx, xfer->len, |
754ce4f2 | 537 | DMA_TO_DEVICE); |
8d8bb39b | 538 | if (dma_mapping_error(dev, xfer->tx_dma)) |
8da0859a DB |
539 | return -ENOMEM; |
540 | } | |
541 | if (xfer->rx_buf) { | |
542 | xfer->rx_dma = dma_map_single(dev, | |
754ce4f2 HS |
543 | xfer->rx_buf, xfer->len, |
544 | DMA_FROM_DEVICE); | |
8d8bb39b | 545 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
8da0859a DB |
546 | if (xfer->tx_buf) |
547 | dma_unmap_single(dev, | |
548 | xfer->tx_dma, xfer->len, | |
549 | DMA_TO_DEVICE); | |
550 | return -ENOMEM; | |
551 | } | |
552 | } | |
553 | return 0; | |
754ce4f2 HS |
554 | } |
555 | ||
556 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, | |
557 | struct spi_transfer *xfer) | |
558 | { | |
559 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 560 | dma_unmap_single(master->dev.parent, xfer->tx_dma, |
754ce4f2 HS |
561 | xfer->len, DMA_TO_DEVICE); |
562 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 563 | dma_unmap_single(master->dev.parent, xfer->rx_dma, |
754ce4f2 HS |
564 | xfer->len, DMA_FROM_DEVICE); |
565 | } | |
566 | ||
567 | static void | |
568 | atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as, | |
823cd045 | 569 | struct spi_message *msg, int stay) |
754ce4f2 | 570 | { |
823cd045 | 571 | if (!stay || as->done_status < 0) |
defbd3b4 DB |
572 | cs_deactivate(as, msg->spi); |
573 | else | |
574 | as->stay = msg->spi; | |
575 | ||
754ce4f2 | 576 | list_del(&msg->queue); |
823cd045 | 577 | msg->status = as->done_status; |
754ce4f2 | 578 | |
49dce689 | 579 | dev_dbg(master->dev.parent, |
754ce4f2 HS |
580 | "xfer complete: %u bytes transferred\n", |
581 | msg->actual_length); | |
582 | ||
8aad7924 | 583 | atmel_spi_unlock(as); |
754ce4f2 | 584 | msg->complete(msg->context); |
8aad7924 | 585 | atmel_spi_lock(as); |
754ce4f2 HS |
586 | |
587 | as->current_transfer = NULL; | |
154443c7 | 588 | as->next_transfer = NULL; |
823cd045 | 589 | as->done_status = 0; |
754ce4f2 HS |
590 | |
591 | /* continue if needed */ | |
592 | if (list_empty(&as->queue) || as->stopping) | |
593 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
594 | else | |
595 | atmel_spi_next_message(master); | |
596 | } | |
597 | ||
598 | static irqreturn_t | |
599 | atmel_spi_interrupt(int irq, void *dev_id) | |
600 | { | |
601 | struct spi_master *master = dev_id; | |
602 | struct atmel_spi *as = spi_master_get_devdata(master); | |
603 | struct spi_message *msg; | |
604 | struct spi_transfer *xfer; | |
605 | u32 status, pending, imr; | |
606 | int ret = IRQ_NONE; | |
607 | ||
8aad7924 | 608 | atmel_spi_lock(as); |
754ce4f2 HS |
609 | |
610 | xfer = as->current_transfer; | |
611 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
612 | ||
613 | imr = spi_readl(as, IMR); | |
614 | status = spi_readl(as, SR); | |
615 | pending = status & imr; | |
616 | ||
617 | if (pending & SPI_BIT(OVRES)) { | |
618 | int timeout; | |
619 | ||
620 | ret = IRQ_HANDLED; | |
621 | ||
dc329442 | 622 | spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) |
754ce4f2 HS |
623 | | SPI_BIT(OVRES))); |
624 | ||
625 | /* | |
626 | * When we get an overrun, we disregard the current | |
627 | * transfer. Data will not be copied back from any | |
628 | * bounce buffer and msg->actual_len will not be | |
629 | * updated with the last xfer. | |
630 | * | |
631 | * We will also not process any remaning transfers in | |
632 | * the message. | |
633 | * | |
634 | * First, stop the transfer and unmap the DMA buffers. | |
635 | */ | |
636 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
637 | if (!msg->is_dma_mapped) | |
638 | atmel_spi_dma_unmap_xfer(master, xfer); | |
639 | ||
640 | /* REVISIT: udelay in irq is unfriendly */ | |
641 | if (xfer->delay_usecs) | |
642 | udelay(xfer->delay_usecs); | |
643 | ||
dc329442 | 644 | dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n", |
754ce4f2 HS |
645 | spi_readl(as, TCR), spi_readl(as, RCR)); |
646 | ||
647 | /* | |
648 | * Clean up DMA registers and make sure the data | |
649 | * registers are empty. | |
650 | */ | |
651 | spi_writel(as, RNCR, 0); | |
652 | spi_writel(as, TNCR, 0); | |
653 | spi_writel(as, RCR, 0); | |
654 | spi_writel(as, TCR, 0); | |
655 | for (timeout = 1000; timeout; timeout--) | |
656 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) | |
657 | break; | |
658 | if (!timeout) | |
49dce689 | 659 | dev_warn(master->dev.parent, |
754ce4f2 HS |
660 | "timeout waiting for TXEMPTY"); |
661 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) | |
662 | spi_readl(as, RDR); | |
663 | ||
664 | /* Clear any overrun happening while cleaning up */ | |
665 | spi_readl(as, SR); | |
666 | ||
823cd045 NF |
667 | as->done_status = -EIO; |
668 | atmel_spi_msg_done(master, as, msg, 0); | |
dc329442 | 669 | } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { |
754ce4f2 HS |
670 | ret = IRQ_HANDLED; |
671 | ||
672 | spi_writel(as, IDR, pending); | |
673 | ||
154443c7 | 674 | if (as->current_remaining_bytes == 0) { |
754ce4f2 HS |
675 | msg->actual_length += xfer->len; |
676 | ||
677 | if (!msg->is_dma_mapped) | |
678 | atmel_spi_dma_unmap_xfer(master, xfer); | |
679 | ||
680 | /* REVISIT: udelay in irq is unfriendly */ | |
681 | if (xfer->delay_usecs) | |
682 | udelay(xfer->delay_usecs); | |
683 | ||
154443c7 | 684 | if (atmel_spi_xfer_is_last(msg, xfer)) { |
754ce4f2 | 685 | /* report completed message */ |
823cd045 | 686 | atmel_spi_msg_done(master, as, msg, |
defbd3b4 | 687 | xfer->cs_change); |
754ce4f2 HS |
688 | } else { |
689 | if (xfer->cs_change) { | |
defbd3b4 | 690 | cs_deactivate(as, msg->spi); |
754ce4f2 | 691 | udelay(1); |
defbd3b4 | 692 | cs_activate(as, msg->spi); |
754ce4f2 HS |
693 | } |
694 | ||
695 | /* | |
696 | * Not done yet. Submit the next transfer. | |
697 | * | |
698 | * FIXME handle protocol options for xfer | |
699 | */ | |
700 | atmel_spi_next_xfer(master, msg); | |
701 | } | |
702 | } else { | |
703 | /* | |
704 | * Keep going, we still have data to send in | |
705 | * the current transfer. | |
706 | */ | |
707 | atmel_spi_next_xfer(master, msg); | |
708 | } | |
709 | } | |
710 | ||
8aad7924 | 711 | atmel_spi_unlock(as); |
754ce4f2 HS |
712 | |
713 | return ret; | |
714 | } | |
715 | ||
754ce4f2 HS |
716 | static int atmel_spi_setup(struct spi_device *spi) |
717 | { | |
718 | struct atmel_spi *as; | |
5ee36c98 | 719 | struct atmel_spi_device *asd; |
754ce4f2 HS |
720 | u32 scbr, csr; |
721 | unsigned int bits = spi->bits_per_word; | |
592e7bf8 | 722 | unsigned long bus_hz; |
754ce4f2 HS |
723 | unsigned int npcs_pin; |
724 | int ret; | |
725 | ||
726 | as = spi_master_get_devdata(spi->master); | |
727 | ||
728 | if (as->stopping) | |
729 | return -ESHUTDOWN; | |
730 | ||
731 | if (spi->chip_select > spi->master->num_chipselect) { | |
732 | dev_dbg(&spi->dev, | |
733 | "setup: invalid chipselect %u (%u defined)\n", | |
734 | spi->chip_select, spi->master->num_chipselect); | |
735 | return -EINVAL; | |
736 | } | |
737 | ||
754ce4f2 HS |
738 | if (bits < 8 || bits > 16) { |
739 | dev_dbg(&spi->dev, | |
740 | "setup: invalid bits_per_word %u (8 to 16)\n", | |
741 | bits); | |
742 | return -EINVAL; | |
743 | } | |
744 | ||
defbd3b4 | 745 | /* see notes above re chipselect */ |
d4820b74 | 746 | if (!atmel_spi_is_v2(as) |
defbd3b4 DB |
747 | && spi->chip_select == 0 |
748 | && (spi->mode & SPI_CS_HIGH)) { | |
749 | dev_dbg(&spi->dev, "setup: can't be active-high\n"); | |
750 | return -EINVAL; | |
751 | } | |
752 | ||
5bfa26ca | 753 | /* v1 chips start out at half the peripheral bus speed. */ |
754ce4f2 | 754 | bus_hz = clk_get_rate(as->clk); |
d4820b74 | 755 | if (!atmel_spi_is_v2(as)) |
592e7bf8 HS |
756 | bus_hz /= 2; |
757 | ||
754ce4f2 | 758 | if (spi->max_speed_hz) { |
592e7bf8 HS |
759 | /* |
760 | * Calculate the lowest divider that satisfies the | |
761 | * constraint, assuming div32/fdiv/mbz == 0. | |
762 | */ | |
763 | scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz); | |
764 | ||
765 | /* | |
766 | * If the resulting divider doesn't fit into the | |
767 | * register bitfield, we can't satisfy the constraint. | |
768 | */ | |
754ce4f2 | 769 | if (scbr >= (1 << SPI_SCBR_SIZE)) { |
8da0859a DB |
770 | dev_dbg(&spi->dev, |
771 | "setup: %d Hz too slow, scbr %u; min %ld Hz\n", | |
772 | spi->max_speed_hz, scbr, bus_hz/255); | |
754ce4f2 HS |
773 | return -EINVAL; |
774 | } | |
775 | } else | |
592e7bf8 | 776 | /* speed zero means "as slow as possible" */ |
754ce4f2 | 777 | scbr = 0xff; |
754ce4f2 HS |
778 | |
779 | csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8); | |
780 | if (spi->mode & SPI_CPOL) | |
781 | csr |= SPI_BIT(CPOL); | |
782 | if (!(spi->mode & SPI_CPHA)) | |
783 | csr |= SPI_BIT(NCPHA); | |
784 | ||
1eed29df HS |
785 | /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. |
786 | * | |
787 | * DLYBCT would add delays between words, slowing down transfers. | |
788 | * It could potentially be useful to cope with DMA bottlenecks, but | |
789 | * in those cases it's probably best to just use a lower bitrate. | |
790 | */ | |
791 | csr |= SPI_BF(DLYBS, 0); | |
792 | csr |= SPI_BF(DLYBCT, 0); | |
754ce4f2 HS |
793 | |
794 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ | |
795 | npcs_pin = (unsigned int)spi->controller_data; | |
850a5b67 JCPV |
796 | |
797 | if (gpio_is_valid(spi->cs_gpio)) | |
798 | npcs_pin = spi->cs_gpio; | |
799 | ||
5ee36c98 HS |
800 | asd = spi->controller_state; |
801 | if (!asd) { | |
802 | asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); | |
803 | if (!asd) | |
804 | return -ENOMEM; | |
805 | ||
6c7377ab | 806 | ret = gpio_request(npcs_pin, dev_name(&spi->dev)); |
5ee36c98 HS |
807 | if (ret) { |
808 | kfree(asd); | |
754ce4f2 | 809 | return ret; |
5ee36c98 HS |
810 | } |
811 | ||
812 | asd->npcs_pin = npcs_pin; | |
813 | spi->controller_state = asd; | |
28735a72 | 814 | gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); |
defbd3b4 | 815 | } else { |
8aad7924 | 816 | atmel_spi_lock(as); |
defbd3b4 DB |
817 | if (as->stay == spi) |
818 | as->stay = NULL; | |
819 | cs_deactivate(as, spi); | |
8aad7924 | 820 | atmel_spi_unlock(as); |
754ce4f2 HS |
821 | } |
822 | ||
5ee36c98 HS |
823 | asd->csr = csr; |
824 | ||
754ce4f2 HS |
825 | dev_dbg(&spi->dev, |
826 | "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n", | |
592e7bf8 | 827 | bus_hz / scbr, bits, spi->mode, spi->chip_select, csr); |
754ce4f2 | 828 | |
d4820b74 | 829 | if (!atmel_spi_is_v2(as)) |
5ee36c98 | 830 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); |
754ce4f2 HS |
831 | |
832 | return 0; | |
833 | } | |
834 | ||
835 | static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
836 | { | |
837 | struct atmel_spi *as; | |
838 | struct spi_transfer *xfer; | |
49dce689 | 839 | struct device *controller = spi->master->dev.parent; |
b9d228f9 MB |
840 | u8 bits; |
841 | struct atmel_spi_device *asd; | |
754ce4f2 HS |
842 | |
843 | as = spi_master_get_devdata(spi->master); | |
844 | ||
845 | dev_dbg(controller, "new message %p submitted for %s\n", | |
6c7377ab | 846 | msg, dev_name(&spi->dev)); |
754ce4f2 | 847 | |
5b96f172 | 848 | if (unlikely(list_empty(&msg->transfers))) |
754ce4f2 HS |
849 | return -EINVAL; |
850 | ||
851 | if (as->stopping) | |
852 | return -ESHUTDOWN; | |
853 | ||
854 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
06719814 | 855 | if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { |
754ce4f2 HS |
856 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); |
857 | return -EINVAL; | |
858 | } | |
859 | ||
b9d228f9 MB |
860 | if (xfer->bits_per_word) { |
861 | asd = spi->controller_state; | |
862 | bits = (asd->csr >> 4) & 0xf; | |
863 | if (bits != xfer->bits_per_word - 8) { | |
864 | dev_dbg(&spi->dev, "you can't yet change " | |
ee2007d2 | 865 | "bits_per_word in transfers\n"); |
b9d228f9 MB |
866 | return -ENOPROTOOPT; |
867 | } | |
868 | } | |
869 | ||
754ce4f2 | 870 | /* FIXME implement these protocol options!! */ |
b9d228f9 | 871 | if (xfer->speed_hz) { |
754ce4f2 HS |
872 | dev_dbg(&spi->dev, "no protocol options yet\n"); |
873 | return -ENOPROTOOPT; | |
874 | } | |
754ce4f2 | 875 | |
8da0859a DB |
876 | /* |
877 | * DMA map early, for performance (empties dcache ASAP) and | |
878 | * better fault reporting. This is a DMA-only driver. | |
879 | * | |
880 | * NOTE that if dma_unmap_single() ever starts to do work on | |
881 | * platforms supported by this driver, we would need to clean | |
882 | * up mappings for previously-mapped transfers. | |
883 | */ | |
884 | if (!msg->is_dma_mapped) { | |
885 | if (atmel_spi_dma_map_xfer(as, xfer) < 0) | |
886 | return -ENOMEM; | |
887 | } | |
754ce4f2 HS |
888 | } |
889 | ||
defbd3b4 | 890 | #ifdef VERBOSE |
754ce4f2 HS |
891 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
892 | dev_dbg(controller, | |
893 | " xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
894 | xfer, xfer->len, | |
895 | xfer->tx_buf, xfer->tx_dma, | |
896 | xfer->rx_buf, xfer->rx_dma); | |
897 | } | |
defbd3b4 | 898 | #endif |
754ce4f2 HS |
899 | |
900 | msg->status = -EINPROGRESS; | |
901 | msg->actual_length = 0; | |
902 | ||
8aad7924 | 903 | atmel_spi_lock(as); |
754ce4f2 HS |
904 | list_add_tail(&msg->queue, &as->queue); |
905 | if (!as->current_transfer) | |
906 | atmel_spi_next_message(spi->master); | |
8aad7924 | 907 | atmel_spi_unlock(as); |
754ce4f2 HS |
908 | |
909 | return 0; | |
910 | } | |
911 | ||
bb2d1c36 | 912 | static void atmel_spi_cleanup(struct spi_device *spi) |
754ce4f2 | 913 | { |
defbd3b4 | 914 | struct atmel_spi *as = spi_master_get_devdata(spi->master); |
5ee36c98 | 915 | struct atmel_spi_device *asd = spi->controller_state; |
defbd3b4 | 916 | unsigned gpio = (unsigned) spi->controller_data; |
defbd3b4 | 917 | |
5ee36c98 | 918 | if (!asd) |
defbd3b4 DB |
919 | return; |
920 | ||
8aad7924 | 921 | atmel_spi_lock(as); |
defbd3b4 DB |
922 | if (as->stay == spi) { |
923 | as->stay = NULL; | |
924 | cs_deactivate(as, spi); | |
925 | } | |
8aad7924 | 926 | atmel_spi_unlock(as); |
defbd3b4 | 927 | |
5ee36c98 | 928 | spi->controller_state = NULL; |
defbd3b4 | 929 | gpio_free(gpio); |
5ee36c98 | 930 | kfree(asd); |
754ce4f2 HS |
931 | } |
932 | ||
d4820b74 WY |
933 | static inline unsigned int atmel_get_version(struct atmel_spi *as) |
934 | { | |
935 | return spi_readl(as, VERSION) & 0x00000fff; | |
936 | } | |
937 | ||
938 | static void atmel_get_caps(struct atmel_spi *as) | |
939 | { | |
940 | unsigned int version; | |
941 | ||
942 | version = atmel_get_version(as); | |
943 | dev_info(&as->pdev->dev, "version: 0x%x\n", version); | |
944 | ||
945 | as->caps.is_spi2 = version > 0x121; | |
946 | as->caps.has_wdrbt = version >= 0x210; | |
947 | as->caps.has_dma_support = version >= 0x212; | |
948 | } | |
949 | ||
754ce4f2 HS |
950 | /*-------------------------------------------------------------------------*/ |
951 | ||
fd4a319b | 952 | static int atmel_spi_probe(struct platform_device *pdev) |
754ce4f2 HS |
953 | { |
954 | struct resource *regs; | |
955 | int irq; | |
956 | struct clk *clk; | |
957 | int ret; | |
958 | struct spi_master *master; | |
959 | struct atmel_spi *as; | |
960 | ||
961 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
962 | if (!regs) | |
963 | return -ENXIO; | |
964 | ||
965 | irq = platform_get_irq(pdev, 0); | |
966 | if (irq < 0) | |
967 | return irq; | |
968 | ||
969 | clk = clk_get(&pdev->dev, "spi_clk"); | |
970 | if (IS_ERR(clk)) | |
971 | return PTR_ERR(clk); | |
972 | ||
973 | /* setup spi core then atmel-specific driver state */ | |
974 | ret = -ENOMEM; | |
975 | master = spi_alloc_master(&pdev->dev, sizeof *as); | |
976 | if (!master) | |
977 | goto out_free; | |
978 | ||
e7db06b5 DB |
979 | /* the spi->mode bits understood by this driver: */ |
980 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
981 | ||
850a5b67 | 982 | master->dev.of_node = pdev->dev.of_node; |
754ce4f2 | 983 | master->bus_num = pdev->id; |
850a5b67 | 984 | master->num_chipselect = master->dev.of_node ? 0 : 4; |
754ce4f2 HS |
985 | master->setup = atmel_spi_setup; |
986 | master->transfer = atmel_spi_transfer; | |
987 | master->cleanup = atmel_spi_cleanup; | |
988 | platform_set_drvdata(pdev, master); | |
989 | ||
990 | as = spi_master_get_devdata(master); | |
991 | ||
8da0859a DB |
992 | /* |
993 | * Scratch buffer is used for throwaway rx and tx data. | |
994 | * It's coherent to minimize dcache pollution. | |
995 | */ | |
754ce4f2 HS |
996 | as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, |
997 | &as->buffer_dma, GFP_KERNEL); | |
998 | if (!as->buffer) | |
999 | goto out_free; | |
1000 | ||
1001 | spin_lock_init(&as->lock); | |
1002 | INIT_LIST_HEAD(&as->queue); | |
1003 | as->pdev = pdev; | |
905aa0ae | 1004 | as->regs = ioremap(regs->start, resource_size(regs)); |
754ce4f2 HS |
1005 | if (!as->regs) |
1006 | goto out_free_buffer; | |
dfab30ee | 1007 | as->phybase = regs->start; |
754ce4f2 HS |
1008 | as->irq = irq; |
1009 | as->clk = clk; | |
754ce4f2 | 1010 | |
d4820b74 WY |
1011 | atmel_get_caps(as); |
1012 | ||
754ce4f2 | 1013 | ret = request_irq(irq, atmel_spi_interrupt, 0, |
6c7377ab | 1014 | dev_name(&pdev->dev), master); |
754ce4f2 HS |
1015 | if (ret) |
1016 | goto out_unmap_regs; | |
1017 | ||
1018 | /* Initialize the hardware */ | |
1019 | clk_enable(clk); | |
1020 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 1021 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
d4820b74 WY |
1022 | if (as->caps.has_wdrbt) { |
1023 | spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) | |
1024 | | SPI_BIT(MSTR)); | |
1025 | } else { | |
1026 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); | |
1027 | } | |
754ce4f2 HS |
1028 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
1029 | spi_writel(as, CR, SPI_BIT(SPIEN)); | |
1030 | ||
1031 | /* go! */ | |
1032 | dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", | |
1033 | (unsigned long)regs->start, irq); | |
1034 | ||
1035 | ret = spi_register_master(master); | |
1036 | if (ret) | |
1037 | goto out_reset_hw; | |
1038 | ||
1039 | return 0; | |
1040 | ||
1041 | out_reset_hw: | |
1042 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 1043 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
1044 | clk_disable(clk); |
1045 | free_irq(irq, master); | |
1046 | out_unmap_regs: | |
1047 | iounmap(as->regs); | |
1048 | out_free_buffer: | |
1049 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
1050 | as->buffer_dma); | |
1051 | out_free: | |
1052 | clk_put(clk); | |
1053 | spi_master_put(master); | |
1054 | return ret; | |
1055 | } | |
1056 | ||
fd4a319b | 1057 | static int atmel_spi_remove(struct platform_device *pdev) |
754ce4f2 HS |
1058 | { |
1059 | struct spi_master *master = platform_get_drvdata(pdev); | |
1060 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1061 | struct spi_message *msg; | |
1888e8f2 | 1062 | struct spi_transfer *xfer; |
754ce4f2 HS |
1063 | |
1064 | /* reset the hardware and block queue progress */ | |
1065 | spin_lock_irq(&as->lock); | |
1066 | as->stopping = 1; | |
1067 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
50d7d5bf | 1068 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
754ce4f2 HS |
1069 | spi_readl(as, SR); |
1070 | spin_unlock_irq(&as->lock); | |
1071 | ||
1072 | /* Terminate remaining queued transfers */ | |
1073 | list_for_each_entry(msg, &as->queue, queue) { | |
1888e8f2 NF |
1074 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
1075 | if (!msg->is_dma_mapped) | |
1076 | atmel_spi_dma_unmap_xfer(master, xfer); | |
1077 | } | |
754ce4f2 HS |
1078 | msg->status = -ESHUTDOWN; |
1079 | msg->complete(msg->context); | |
1080 | } | |
1081 | ||
1082 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
1083 | as->buffer_dma); | |
1084 | ||
1085 | clk_disable(as->clk); | |
1086 | clk_put(as->clk); | |
1087 | free_irq(as->irq, master); | |
1088 | iounmap(as->regs); | |
1089 | ||
1090 | spi_unregister_master(master); | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | #ifdef CONFIG_PM | |
1096 | ||
1097 | static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg) | |
1098 | { | |
1099 | struct spi_master *master = platform_get_drvdata(pdev); | |
1100 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1101 | ||
1102 | clk_disable(as->clk); | |
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | static int atmel_spi_resume(struct platform_device *pdev) | |
1107 | { | |
1108 | struct spi_master *master = platform_get_drvdata(pdev); | |
1109 | struct atmel_spi *as = spi_master_get_devdata(master); | |
1110 | ||
1111 | clk_enable(as->clk); | |
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | #else | |
1116 | #define atmel_spi_suspend NULL | |
1117 | #define atmel_spi_resume NULL | |
1118 | #endif | |
1119 | ||
850a5b67 JCPV |
1120 | #if defined(CONFIG_OF) |
1121 | static const struct of_device_id atmel_spi_dt_ids[] = { | |
1122 | { .compatible = "atmel,at91rm9200-spi" }, | |
1123 | { /* sentinel */ } | |
1124 | }; | |
1125 | ||
1126 | MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); | |
1127 | #endif | |
754ce4f2 HS |
1128 | |
1129 | static struct platform_driver atmel_spi_driver = { | |
1130 | .driver = { | |
1131 | .name = "atmel_spi", | |
1132 | .owner = THIS_MODULE, | |
850a5b67 | 1133 | .of_match_table = of_match_ptr(atmel_spi_dt_ids), |
754ce4f2 HS |
1134 | }, |
1135 | .suspend = atmel_spi_suspend, | |
1136 | .resume = atmel_spi_resume, | |
1cb201af | 1137 | .probe = atmel_spi_probe, |
2deff8d6 | 1138 | .remove = atmel_spi_remove, |
754ce4f2 | 1139 | }; |
940ab889 | 1140 | module_platform_driver(atmel_spi_driver); |
754ce4f2 HS |
1141 | |
1142 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | |
e05503ef | 1143 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
754ce4f2 | 1144 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 1145 | MODULE_ALIAS("platform:atmel_spi"); |