[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-npcm-pspi.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology corporation.

#include <linux/kernel.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>

#include <asm/unaligned.h>

#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

struct npcm_pspi {
	struct completion xfer_done;
	struct regmap *rst_regmap;
	struct spi_master *master;
	unsigned int tx_bytes;
	unsigned int rx_bytes;
	void __iomem *base;
	bool is_save_param;
	u8 bits_per_word;
	const u8 *tx_buf;
	struct clk *clk;
	u32 speed_hz;
	u8 *rx_buf;
	u16 mode;
	u32 id;
};

#define DRIVER_NAME "npcm-pspi"

#define NPCM_PSPI_DATA		0x00
#define NPCM_PSPI_CTL1		0x02
#define NPCM_PSPI_STAT		0x04

/* definitions for control and status register */
#define NPCM_PSPI_CTL1_SPIEN	BIT(0)
#define NPCM_PSPI_CTL1_MOD	BIT(2)
#define NPCM_PSPI_CTL1_EIR	BIT(5)
#define NPCM_PSPI_CTL1_EIW	BIT(6)
#define NPCM_PSPI_CTL1_SCM	BIT(7)
#define NPCM_PSPI_CTL1_SCIDL	BIT(8)
#define NPCM_PSPI_CTL1_SCDV6_0	GENMASK(15, 9)

#define NPCM_PSPI_STAT_BSY	BIT(0)
#define NPCM_PSPI_STAT_RBF	BIT(1)

/* general definitions */
#define NPCM_PSPI_TIMEOUT_MS		2000
#define NPCM_PSPI_MAX_CLK_DIVIDER	256
#define NPCM_PSPI_MIN_CLK_DIVIDER	4
#define NPCM_PSPI_DEFAULT_CLK		25000000

/* reset register */
#define NPCM7XX_IPSRST2_OFFSET	0x24

#define NPCM7XX_PSPI1_RESET	BIT(22)
#define NPCM7XX_PSPI2_RESET	BIT(23)

static inline unsigned int bytes_per_word(unsigned int bits)
{
	return bits <= 8 ? 1 : 2;
}

static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
{
	u16 val;

	val = ioread16(priv->base + NPCM_PSPI_CTL1);
	val |= mask;
	iowrite16(val, priv->base + NPCM_PSPI_CTL1);
}

static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
{
	u16 val;

	val = ioread16(priv->base + NPCM_PSPI_CTL1);
	val &= ~mask;
	iowrite16(val, priv->base + NPCM_PSPI_CTL1);
}

static inline void npcm_pspi_enable(struct npcm_pspi *priv)
{
	u16 val;

	val = ioread16(priv->base + NPCM_PSPI_CTL1);
	val |= NPCM_PSPI_CTL1_SPIEN;
	iowrite16(val, priv->base + NPCM_PSPI_CTL1);
}

static inline void npcm_pspi_disable(struct npcm_pspi *priv)
{
	u16 val;

	val = ioread16(priv->base + NPCM_PSPI_CTL1);
	val &= ~NPCM_PSPI_CTL1_SPIEN;
	iowrite16(val, priv->base + NPCM_PSPI_CTL1);
}

static void npcm_pspi_set_mode(struct spi_device *spi)
{
	struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
	u16 regtemp;
	u16 mode_val;

	switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
	case SPI_MODE_0:
		mode_val = 0;
		break;
	case SPI_MODE_1:
		mode_val = NPCM_PSPI_CTL1_SCIDL;
		break;
	case SPI_MODE_2:
		mode_val = NPCM_PSPI_CTL1_SCM;
		break;
	case SPI_MODE_3:
		mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM;
		break;
	}

	regtemp = ioread16(priv->base + NPCM_PSPI_CTL1);
	regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL);
	iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1);
}

static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size)
{
	u16 regtemp;

	regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);

	switch (size) {
	case 8:
		regtemp &= ~NPCM_PSPI_CTL1_MOD;
		break;
	case 16:
		regtemp |= NPCM_PSPI_CTL1_MOD;
		break;
	}

	iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base);
}

static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed)
{
	u32 ckdiv;
	u16 regtemp;

	/* the supported rates are numbers from 4 to 256. */
	ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1;

	regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
	regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0;
	iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base);
}

static void npcm_pspi_setup_transfer(struct spi_device *spi,
				     struct spi_transfer *t)
{
	struct npcm_pspi *priv = spi_master_get_devdata(spi->master);

	priv->tx_buf = t->tx_buf;
	priv->rx_buf = t->rx_buf;
	priv->tx_bytes = t->len;
	priv->rx_bytes = t->len;

	if (!priv->is_save_param || priv->mode != spi->mode) {
		npcm_pspi_set_mode(spi);
		priv->mode = spi->mode;
	}

	if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
		npcm_pspi_set_transfer_size(priv, t->bits_per_word);
		priv->bits_per_word = t->bits_per_word;
	}

	if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
		npcm_pspi_set_baudrate(priv, t->speed_hz);
		priv->speed_hz = t->speed_hz;
	}

	if (!priv->is_save_param)
		priv->is_save_param = true;
}

static void npcm_pspi_send(struct npcm_pspi *priv)
{
	int wsize;

	wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
	priv->tx_bytes -= wsize;

	if (priv->tx_buf) {
		if (wsize == 1)
			iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
		if (wsize == 2)
			iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);

		priv->tx_buf += wsize;
	}
}

static void npcm_pspi_recv(struct npcm_pspi *priv)
{
	int rsize;
	u16 val;

	rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
	priv->rx_bytes -= rsize;

	if (!priv->rx_buf)
		return;

	switch (rsize) {
	case 1:
		val = ioread8(priv->base + NPCM_PSPI_DATA);
		break;
	case 2:
		val = ioread16(priv->base + NPCM_PSPI_DATA);
		break;
	default:
		WARN_ON_ONCE(1);
		return;
	}

	*priv->rx_buf = val;
	priv->rx_buf += rsize;
}

static int npcm_pspi_transfer_one(struct spi_master *master,
				  struct spi_device *spi,
				  struct spi_transfer *t)
{
	struct npcm_pspi *priv = spi_master_get_devdata(master);
	int status;

	npcm_pspi_setup_transfer(spi, t);
	reinit_completion(&priv->xfer_done);
	npcm_pspi_enable(priv);
	status = wait_for_completion_timeout(&priv->xfer_done,
					     msecs_to_jiffies
					     (NPCM_PSPI_TIMEOUT_MS));
	if (status == 0) {
		npcm_pspi_disable(priv);
		return -ETIMEDOUT;
	}

	return 0;
}

static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master)
{
	struct npcm_pspi *priv = spi_master_get_devdata(master);

	npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);

	return 0;
}

static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master)
{
	struct npcm_pspi *priv = spi_master_get_devdata(master);

	npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);

	return 0;
}

static void npcm_pspi_reset_hw(struct npcm_pspi *priv)
{
	regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET,
		     NPCM7XX_PSPI1_RESET << priv->id);
	regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET, 0x0);
}

static irqreturn_t npcm_pspi_handler(int irq, void *dev_id)
{
	struct npcm_pspi *priv = dev_id;
	u16 val;
	u8 stat;

	stat = ioread8(priv->base + NPCM_PSPI_STAT);

	if (!priv->tx_buf && !priv->rx_buf)
		return IRQ_NONE;

	if (priv->tx_buf) {
		if (stat & NPCM_PSPI_STAT_RBF) {
			val = ioread8(NPCM_PSPI_DATA + priv->base);
			if (priv->tx_bytes == 0) {
				npcm_pspi_disable(priv);
				complete(&priv->xfer_done);
				return IRQ_HANDLED;
			}
		}

		if ((stat & NPCM_PSPI_STAT_BSY) == 0)
			if (priv->tx_bytes)
				npcm_pspi_send(priv);
	}

	if (priv->rx_buf) {
		if (stat & NPCM_PSPI_STAT_RBF) {
			if (!priv->rx_bytes)
				return IRQ_NONE;

			npcm_pspi_recv(priv);

			if (!priv->rx_bytes) {
				npcm_pspi_disable(priv);
				complete(&priv->xfer_done);
				return IRQ_HANDLED;
			}
		}

		if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf)
			iowrite8(0x0, NPCM_PSPI_DATA + priv->base);
	}

	return IRQ_HANDLED;
}

static int npcm_pspi_probe(struct platform_device *pdev)
{
	struct npcm_pspi *priv;
	struct spi_master *master;
	struct resource *res;
	unsigned long clk_hz;
	struct device_node *np = pdev->dev.of_node;
	int num_cs, i;
	int csgpio;
	int irq;
	int ret;

	num_cs = of_gpio_named_count(np, "cs-gpios");
	if (num_cs < 0)
		return num_cs;

	pdev->id = of_alias_get_id(np, "spi");
	if (pdev->id < 0)
		pdev->id = 0;

	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
	if (!master)
		return -ENOMEM;

	platform_set_drvdata(pdev, master);

	priv = spi_master_get_devdata(master);
	priv->master = master;
	priv->is_save_param = false;
	priv->id = pdev->id;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(priv->base)) {
		ret = PTR_ERR(priv->base);
		goto out_master_put;
	}

	priv->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		ret = PTR_ERR(priv->clk);
		goto out_master_put;
	}

	ret = clk_prepare_enable(priv->clk);
	if (ret)
		goto out_master_put;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "failed to get IRQ\n");
		ret = irq;
		goto out_disable_clk;
	}

	priv->rst_regmap =
		syscon_regmap_lookup_by_compatible("nuvoton,npcm750-rst");
	if (IS_ERR(priv->rst_regmap)) {
		dev_err(&pdev->dev, "failed to find nuvoton,npcm750-rst\n");
		return PTR_ERR(priv->rst_regmap);
	}

	/* reset SPI-HW block */
	npcm_pspi_reset_hw(priv);

	ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0,
			       "npcm-pspi", priv);
	if (ret) {
		dev_err(&pdev->dev, "failed to request IRQ\n");
		goto out_disable_clk;
	}

	init_completion(&priv->xfer_done);

	clk_hz = clk_get_rate(priv->clk);

	master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER);
	master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER);
	master->mode_bits = SPI_CPHA | SPI_CPOL;
	master->dev.of_node = pdev->dev.of_node;
	master->bus_num = pdev->id;
	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
	master->transfer_one = npcm_pspi_transfer_one;
	master->prepare_transfer_hardware =
		npcm_pspi_prepare_transfer_hardware;
	master->unprepare_transfer_hardware =
		npcm_pspi_unprepare_transfer_hardware;
	master->num_chipselect = num_cs;

	for (i = 0; i < num_cs; i++) {
		csgpio = of_get_named_gpio(np, "cs-gpios", i);
		if (csgpio < 0) {
			dev_err(&pdev->dev, "failed to get csgpio#%u\n", i);
			goto out_disable_clk;
		}
		dev_dbg(&pdev->dev, "csgpio#%u = %d\n", i, csgpio);
		ret = devm_gpio_request_one(&pdev->dev, csgpio,
					    GPIOF_OUT_INIT_HIGH, DRIVER_NAME);
		if (ret < 0) {
			dev_err(&pdev->dev,
				"failed to configure csgpio#%u %d\n"
				, i, csgpio);
			goto out_disable_clk;
		}
	}

	/* set to default clock rate */
	npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK);

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret)
		goto out_disable_clk;

	pr_info("NPCM Peripheral SPI %d probed\n", pdev->id);

	return 0;

out_disable_clk:
	clk_disable_unprepare(priv->clk);

out_master_put:
	spi_master_put(master);
	return ret;
}

static int npcm_pspi_remove(struct platform_device *pdev)
{
	struct npcm_pspi *priv = platform_get_drvdata(pdev);

	npcm_pspi_reset_hw(priv);
	clk_disable_unprepare(priv->clk);

	return 0;
}

static const struct of_device_id npcm_pspi_match[] = {
	{ .compatible = "nuvoton,npcm750-pspi", .data = NULL },
	{}
};
MODULE_DEVICE_TABLE(of, npcm_pspi_match);

static struct platform_driver npcm_pspi_driver = {
	.driver		= {
		.name		= DRIVER_NAME,
		.of_match_table	= npcm_pspi_match,
	},
	.probe		= npcm_pspi_probe,
	.remove		= npcm_pspi_remove,
};
module_platform_driver(npcm_pspi_driver);

MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver");
MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2a22f1b3 TM	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (c) 2018 Nuvoton Technology corporation.
	3
	4	#include <linux/kernel.h>
	5	#include <linux/bitfield.h>
	6	#include <linux/bitops.h>
	7	#include <linux/clk.h>
	8	#include <linux/interrupt.h>
	9	#include <linux/io.h>
	10	#include <linux/module.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/spi/spi.h>
	13	#include <linux/gpio.h>
	14	#include <linux/of_gpio.h>
	15
	16	#include <asm/unaligned.h>
	17
	18	#include <linux/regmap.h>
	19	#include <linux/mfd/syscon.h>
	20
	21	struct npcm_pspi {
	22	struct completion xfer_done;
	23	struct regmap *rst_regmap;
	24	struct spi_master *master;
	25	unsigned int tx_bytes;
	26	unsigned int rx_bytes;
	27	void __iomem *base;
	28	bool is_save_param;
	29	u8 bits_per_word;
	30	const u8 *tx_buf;
	31	struct clk *clk;
	32	u32 speed_hz;
	33	u8 *rx_buf;
	34	u16 mode;
	35	u32 id;
	36	};
	37
	38	#define DRIVER_NAME "npcm-pspi"
	39
	40	#define NPCM_PSPI_DATA 0x00
	41	#define NPCM_PSPI_CTL1 0x02
	42	#define NPCM_PSPI_STAT 0x04
	43
	44	/* definitions for control and status register */
	45	#define NPCM_PSPI_CTL1_SPIEN BIT(0)
	46	#define NPCM_PSPI_CTL1_MOD BIT(2)
	47	#define NPCM_PSPI_CTL1_EIR BIT(5)
	48	#define NPCM_PSPI_CTL1_EIW BIT(6)
	49	#define NPCM_PSPI_CTL1_SCM BIT(7)
	50	#define NPCM_PSPI_CTL1_SCIDL BIT(8)
	51	#define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9)
	52
	53	#define NPCM_PSPI_STAT_BSY BIT(0)
	54	#define NPCM_PSPI_STAT_RBF BIT(1)
	55
	56	/* general definitions */
	57	#define NPCM_PSPI_TIMEOUT_MS 2000
	58	#define NPCM_PSPI_MAX_CLK_DIVIDER 256
	59	#define NPCM_PSPI_MIN_CLK_DIVIDER 4
	60	#define NPCM_PSPI_DEFAULT_CLK 25000000
	61
	62	/* reset register */
	63	#define NPCM7XX_IPSRST2_OFFSET 0x24
	64
65	#define NPCM7XX_PSPI1_RESET BIT(22)
66	#define NPCM7XX_PSPI2_RESET BIT(23)
67
68	static inline unsigned int bytes_per_word(unsigned int bits)
69	{
70	return bits <= 8 ? 1 : 2;
71	}
72
73	static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
74	{
75	u16 val;
76
77	val = ioread16(priv->base + NPCM_PSPI_CTL1);
78	val \|= mask;
79	iowrite16(val, priv->base + NPCM_PSPI_CTL1);
80	}
81
82	static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
83	{
84	u16 val;
85
86	val = ioread16(priv->base + NPCM_PSPI_CTL1);
87	val &= ~mask;
88	iowrite16(val, priv->base + NPCM_PSPI_CTL1);
89	}
90
91	static inline void npcm_pspi_enable(struct npcm_pspi *priv)
92	{
93	u16 val;
94
95	val = ioread16(priv->base + NPCM_PSPI_CTL1);
96	val \|= NPCM_PSPI_CTL1_SPIEN;
97	iowrite16(val, priv->base + NPCM_PSPI_CTL1);
98	}
99
100	static inline void npcm_pspi_disable(struct npcm_pspi *priv)
101	{
102	u16 val;
103
104	val = ioread16(priv->base + NPCM_PSPI_CTL1);
105	val &= ~NPCM_PSPI_CTL1_SPIEN;
106	iowrite16(val, priv->base + NPCM_PSPI_CTL1);
107	}
108
109	static void npcm_pspi_set_mode(struct spi_device *spi)
110	{
111	struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
112	u16 regtemp;
113	u16 mode_val;
114
115	switch (spi->mode & (SPI_CPOL \| SPI_CPHA)) {
116	case SPI_MODE_0:
117	mode_val = 0;
118	break;
119	case SPI_MODE_1:
120	mode_val = NPCM_PSPI_CTL1_SCIDL;
121	break;
122	case SPI_MODE_2:
123	mode_val = NPCM_PSPI_CTL1_SCM;
124	break;
125	case SPI_MODE_3:
126	mode_val = NPCM_PSPI_CTL1_SCIDL \| NPCM_PSPI_CTL1_SCM;
127	break;
128	}
129
130	regtemp = ioread16(priv->base + NPCM_PSPI_CTL1);
131	regtemp &= ~(NPCM_PSPI_CTL1_SCM \| NPCM_PSPI_CTL1_SCIDL);
132	iowrite16(regtemp \| mode_val, priv->base + NPCM_PSPI_CTL1);
133	}
134
135	static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size)
136	{
137	u16 regtemp;
138
139	regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
140
141	switch (size) {
142	case 8:
143	regtemp &= ~NPCM_PSPI_CTL1_MOD;
144	break;
145	case 16:
146	regtemp \|= NPCM_PSPI_CTL1_MOD;
147	break;
148	}
149
150	iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base);
151	}
152
153	static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed)
154	{
155	u32 ckdiv;
156	u16 regtemp;
157
158	/* the supported rates are numbers from 4 to 256. */
159	ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1;
160
161	regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
162	regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0;
163	iowrite16(regtemp \| (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base);
164	}
165
166	static void npcm_pspi_setup_transfer(struct spi_device *spi,
167	struct spi_transfer *t)
168	{
169	struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
170
171	priv->tx_buf = t->tx_buf;
172	priv->rx_buf = t->rx_buf;
173	priv->tx_bytes = t->len;
174	priv->rx_bytes = t->len;
175
176	if (!priv->is_save_param \|\| priv->mode != spi->mode) {
177	npcm_pspi_set_mode(spi);
178	priv->mode = spi->mode;
179	}
180
181	if (!priv->is_save_param \|\| priv->bits_per_word != t->bits_per_word) {
182	npcm_pspi_set_transfer_size(priv, t->bits_per_word);
183	priv->bits_per_word = t->bits_per_word;
184	}
185
186	if (!priv->is_save_param \|\| priv->speed_hz != t->speed_hz) {
187	npcm_pspi_set_baudrate(priv, t->speed_hz);
188	priv->speed_hz = t->speed_hz;
189	}
190
191	if (!priv->is_save_param)
192	priv->is_save_param = true;
193	}
194
195	static void npcm_pspi_send(struct npcm_pspi *priv)
196	{
197	int wsize;
198
199	wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
200	priv->tx_bytes -= wsize;
201
202	if (priv->tx_buf) {
203	if (wsize == 1)
204	iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
205	if (wsize == 2)
206	iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
207
208	priv->tx_buf += wsize;
209	}
210	}
211
212	static void npcm_pspi_recv(struct npcm_pspi *priv)
213	{
214	int rsize;
215	u16 val;
216
217	rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
218	priv->rx_bytes -= rsize;
219
1d2319ef OJ	220	if (!priv->rx_buf)
	221	return;
	222
	223	switch (rsize) {
	224	case 1:
	225	val = ioread8(priv->base + NPCM_PSPI_DATA);
	226	break;
	227	case 2:
	228	val = ioread16(priv->base + NPCM_PSPI_DATA);
	229	break;
	230	default:
	231	WARN_ON_ONCE(1);
	232	return;
2a22f1b3	233	}
1d2319ef OJ	234
	235	*priv->rx_buf = val;
	236	priv->rx_buf += rsize;
2a22f1b3 TM	237	}
	238
	239	static int npcm_pspi_transfer_one(struct spi_master *master,
	240	struct spi_device *spi,
	241	struct spi_transfer *t)
	242	{
	243	struct npcm_pspi *priv = spi_master_get_devdata(master);
	244	int status;
	245
	246	npcm_pspi_setup_transfer(spi, t);
	247	reinit_completion(&priv->xfer_done);
	248	npcm_pspi_enable(priv);
	249	status = wait_for_completion_timeout(&priv->xfer_done,
	250	msecs_to_jiffies
	251	(NPCM_PSPI_TIMEOUT_MS));
	252	if (status == 0) {
	253	npcm_pspi_disable(priv);
	254	return -ETIMEDOUT;
	255	}
	256
	257	return 0;
	258	}
	259
	260	static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master)
	261	{
	262	struct npcm_pspi *priv = spi_master_get_devdata(master);
	263
	264	npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR \| NPCM_PSPI_CTL1_EIW);
	265
	266	return 0;
	267	}
	268
	269	static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master)
	270	{
	271	struct npcm_pspi *priv = spi_master_get_devdata(master);
	272
	273	npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR \| NPCM_PSPI_CTL1_EIW);
	274
	275	return 0;
	276	}
	277
	278	static void npcm_pspi_reset_hw(struct npcm_pspi *priv)
	279	{
	280	regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET,
	281	NPCM7XX_PSPI1_RESET << priv->id);
	282	regmap_write(priv->rst_regmap, NPCM7XX_IPSRST2_OFFSET, 0x0);
	283	}
	284
	285	static irqreturn_t npcm_pspi_handler(int irq, void *dev_id)
	286	{
	287	struct npcm_pspi *priv = dev_id;
	288	u16 val;
	289	u8 stat;
	290
	291	stat = ioread8(priv->base + NPCM_PSPI_STAT);
	292
	293	if (!priv->tx_buf && !priv->rx_buf)
	294	return IRQ_NONE;
	295
	296	if (priv->tx_buf) {
	297	if (stat & NPCM_PSPI_STAT_RBF) {
	298	val = ioread8(NPCM_PSPI_DATA + priv->base);
	299	if (priv->tx_bytes == 0) {
	300	npcm_pspi_disable(priv);
301	complete(&priv->xfer_done);
302	return IRQ_HANDLED;
303	}
304	}
305
306	if ((stat & NPCM_PSPI_STAT_BSY) == 0)
307	if (priv->tx_bytes)
308	npcm_pspi_send(priv);
309	}
310
311	if (priv->rx_buf) {
312	if (stat & NPCM_PSPI_STAT_RBF) {
313	if (!priv->rx_bytes)
314	return IRQ_NONE;
315
316	npcm_pspi_recv(priv);
317
318	if (!priv->rx_bytes) {
319	npcm_pspi_disable(priv);
320	complete(&priv->xfer_done);
321	return IRQ_HANDLED;
322	}
323	}
324
325	if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf)
326	iowrite8(0x0, NPCM_PSPI_DATA + priv->base);
327	}
328
329	return IRQ_HANDLED;
330	}
331
332	static int npcm_pspi_probe(struct platform_device *pdev)
333	{
334	struct npcm_pspi *priv;
335	struct spi_master *master;
336	struct resource *res;
337	unsigned long clk_hz;
338	struct device_node *np = pdev->dev.of_node;
339	int num_cs, i;
757ec116	340	int csgpio;
2a22f1b3 TM	341	int irq;
	342	int ret;
	343
	344	num_cs = of_gpio_named_count(np, "cs-gpios");
	345	if (num_cs < 0)
	346	return num_cs;
	347
	348	pdev->id = of_alias_get_id(np, "spi");
	349	if (pdev->id < 0)
	350	pdev->id = 0;
	351
	352	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
	353	if (!master)
	354	return -ENOMEM;
	355
	356	platform_set_drvdata(pdev, master);
	357
	358	priv = spi_master_get_devdata(master);
	359	priv->master = master;
	360	priv->is_save_param = false;
	361	priv->id = pdev->id;
	362
	363	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	364	priv->base = devm_ioremap_resource(&pdev->dev, res);
	365	if (IS_ERR(priv->base)) {
	366	ret = PTR_ERR(priv->base);
	367	goto out_master_put;
	368	}
	369
	370	priv->clk = devm_clk_get(&pdev->dev, NULL);
	371	if (IS_ERR(priv->clk)) {
	372	dev_err(&pdev->dev, "failed to get clock\n");
	373	ret = PTR_ERR(priv->clk);
	374	goto out_master_put;
	375	}
	376
	377	ret = clk_prepare_enable(priv->clk);
	378	if (ret)
	379	goto out_master_put;
	380
	381	irq = platform_get_irq(pdev, 0);
	382	if (irq < 0) {
	383	dev_err(&pdev->dev, "failed to get IRQ\n");
	384	ret = irq;
	385	goto out_disable_clk;
	386	}
	387
	388	priv->rst_regmap =
	389	syscon_regmap_lookup_by_compatible("nuvoton,npcm750-rst");
	390	if (IS_ERR(priv->rst_regmap)) {
	391	dev_err(&pdev->dev, "failed to find nuvoton,npcm750-rst\n");
428f977a	392	return PTR_ERR(priv->rst_regmap);
2a22f1b3 TM	393	}
	394
	395	/* reset SPI-HW block */
	396	npcm_pspi_reset_hw(priv);
	397
	398	ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0,
	399	"npcm-pspi", priv);
	400	if (ret) {
	401	dev_err(&pdev->dev, "failed to request IRQ\n");
	402	goto out_disable_clk;
	403	}
	404
	405	init_completion(&priv->xfer_done);
	406
	407	clk_hz = clk_get_rate(priv->clk);
	408
	409	master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER);
	410	master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER);
	411	master->mode_bits = SPI_CPHA \| SPI_CPOL;
	412	master->dev.of_node = pdev->dev.of_node;
	413	master->bus_num = pdev->id;
	414	master->bits_per_word_mask = SPI_BPW_MASK(8) \| SPI_BPW_MASK(16);
	415	master->transfer_one = npcm_pspi_transfer_one;
	416	master->prepare_transfer_hardware =
	417	npcm_pspi_prepare_transfer_hardware;
	418	master->unprepare_transfer_hardware =
	419	npcm_pspi_unprepare_transfer_hardware;
	420	master->num_chipselect = num_cs;
	421
	422	for (i = 0; i < num_cs; i++) {
	423	csgpio = of_get_named_gpio(np, "cs-gpios", i);
	424	if (csgpio < 0) {
	425	dev_err(&pdev->dev, "failed to get csgpio#%u\n", i);
	426	goto out_disable_clk;
	427	}
757ec116	428	dev_dbg(&pdev->dev, "csgpio#%u = %d\n", i, csgpio);
2a22f1b3 TM	429	ret = devm_gpio_request_one(&pdev->dev, csgpio,
	430	GPIOF_OUT_INIT_HIGH, DRIVER_NAME);
	431	if (ret < 0) {
	432	dev_err(&pdev->dev,
757ec116	433	"failed to configure csgpio#%u %d\n"
2a22f1b3 TM	434	, i, csgpio);
	435	goto out_disable_clk;
	436	}
	437	}
	438
	439	/* set to default clock rate */
	440	npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK);
	441
	442	ret = devm_spi_register_master(&pdev->dev, master);
	443	if (ret)
	444	goto out_disable_clk;
	445
	446	pr_info("NPCM Peripheral SPI %d probed\n", pdev->id);
	447
	448	return 0;
	449
	450	out_disable_clk:
	451	clk_disable_unprepare(priv->clk);
	452
	453	out_master_put:
	454	spi_master_put(master);
	455	return ret;
	456	}
	457
	458	static int npcm_pspi_remove(struct platform_device *pdev)
	459	{
	460	struct npcm_pspi *priv = platform_get_drvdata(pdev);
	461
	462	npcm_pspi_reset_hw(priv);
	463	clk_disable_unprepare(priv->clk);
	464
	465	return 0;
	466	}
	467
	468	static const struct of_device_id npcm_pspi_match[] = {
	469	{ .compatible = "nuvoton,npcm750-pspi", .data = NULL },
	470	{}
	471	};
	472	MODULE_DEVICE_TABLE(of, npcm_pspi_match);
	473
	474	static struct platform_driver npcm_pspi_driver = {
	475	.driver = {
	476	.name = DRIVER_NAME,
	477	.of_match_table = npcm_pspi_match,
2a22f1b3 TM	478	},
	479	.probe = npcm_pspi_probe,
	480	.remove = npcm_pspi_remove,
	481	};
	482	module_platform_driver(npcm_pspi_driver);
	483
	484	MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver");
	485	MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
	486	MODULE_LICENSE("GPL v2");
	487