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Commit | Line | Data |
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5928808e MW |
1 | /* |
2 | * PXA2xx SPI DMA engine support. | |
3 | * | |
4 | * Copyright (C) 2013, Intel Corporation | |
5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
5928808e MW |
12 | #include <linux/device.h> |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/dmaengine.h> | |
15 | #include <linux/pxa2xx_ssp.h> | |
16 | #include <linux/scatterlist.h> | |
17 | #include <linux/sizes.h> | |
18 | #include <linux/spi/spi.h> | |
19 | #include <linux/spi/pxa2xx_spi.h> | |
20 | ||
21 | #include "spi-pxa2xx.h" | |
22 | ||
5928808e MW |
23 | static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data, |
24 | bool error) | |
25 | { | |
4fc0caac | 26 | struct spi_message *msg = drv_data->master->cur_msg; |
5928808e MW |
27 | |
28 | /* | |
29 | * It is possible that one CPU is handling ROR interrupt and other | |
30 | * just gets DMA completion. Calling pump_transfers() twice for the | |
31 | * same transfer leads to problems thus we prevent concurrent calls | |
32 | * by using ->dma_running. | |
33 | */ | |
34 | if (atomic_dec_and_test(&drv_data->dma_running)) { | |
5928808e MW |
35 | /* |
36 | * If the other CPU is still handling the ROR interrupt we | |
37 | * might not know about the error yet. So we re-check the | |
38 | * ROR bit here before we clear the status register. | |
39 | */ | |
40 | if (!error) { | |
c039dd27 JN |
41 | u32 status = pxa2xx_spi_read(drv_data, SSSR) |
42 | & drv_data->mask_sr; | |
5928808e MW |
43 | error = status & SSSR_ROR; |
44 | } | |
45 | ||
46 | /* Clear status & disable interrupts */ | |
c039dd27 JN |
47 | pxa2xx_spi_write(drv_data, SSCR1, |
48 | pxa2xx_spi_read(drv_data, SSCR1) | |
49 | & ~drv_data->dma_cr1); | |
5928808e MW |
50 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
51 | if (!pxa25x_ssp_comp(drv_data)) | |
c039dd27 | 52 | pxa2xx_spi_write(drv_data, SSTO, 0); |
5928808e MW |
53 | |
54 | if (!error) { | |
5928808e MW |
55 | msg->actual_length += drv_data->len; |
56 | msg->state = pxa2xx_spi_next_transfer(drv_data); | |
57 | } else { | |
58 | /* In case we got an error we disable the SSP now */ | |
c039dd27 JN |
59 | pxa2xx_spi_write(drv_data, SSCR0, |
60 | pxa2xx_spi_read(drv_data, SSCR0) | |
61 | & ~SSCR0_SSE); | |
5928808e MW |
62 | |
63 | msg->state = ERROR_STATE; | |
64 | } | |
65 | ||
66 | tasklet_schedule(&drv_data->pump_transfers); | |
67 | } | |
68 | } | |
69 | ||
70 | static void pxa2xx_spi_dma_callback(void *data) | |
71 | { | |
72 | pxa2xx_spi_dma_transfer_complete(data, false); | |
73 | } | |
74 | ||
75 | static struct dma_async_tx_descriptor * | |
76 | pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data, | |
77 | enum dma_transfer_direction dir) | |
78 | { | |
96579a4e JN |
79 | struct chip_data *chip = |
80 | spi_get_ctldata(drv_data->master->cur_msg->spi); | |
b6ced294 | 81 | struct spi_transfer *xfer = drv_data->cur_transfer; |
5928808e MW |
82 | enum dma_slave_buswidth width; |
83 | struct dma_slave_config cfg; | |
84 | struct dma_chan *chan; | |
85 | struct sg_table *sgt; | |
b6ced294 | 86 | int ret; |
5928808e MW |
87 | |
88 | switch (drv_data->n_bytes) { | |
89 | case 1: | |
90 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
91 | break; | |
92 | case 2: | |
93 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
94 | break; | |
95 | default: | |
96 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
97 | break; | |
98 | } | |
99 | ||
100 | memset(&cfg, 0, sizeof(cfg)); | |
101 | cfg.direction = dir; | |
102 | ||
103 | if (dir == DMA_MEM_TO_DEV) { | |
104 | cfg.dst_addr = drv_data->ssdr_physical; | |
105 | cfg.dst_addr_width = width; | |
106 | cfg.dst_maxburst = chip->dma_burst_size; | |
5928808e | 107 | |
b6ced294 JN |
108 | sgt = &xfer->tx_sg; |
109 | chan = drv_data->master->dma_tx; | |
5928808e MW |
110 | } else { |
111 | cfg.src_addr = drv_data->ssdr_physical; | |
112 | cfg.src_addr_width = width; | |
113 | cfg.src_maxburst = chip->dma_burst_size; | |
5928808e | 114 | |
b6ced294 JN |
115 | sgt = &xfer->rx_sg; |
116 | chan = drv_data->master->dma_rx; | |
5928808e MW |
117 | } |
118 | ||
119 | ret = dmaengine_slave_config(chan, &cfg); | |
120 | if (ret) { | |
121 | dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n"); | |
122 | return NULL; | |
123 | } | |
124 | ||
b6ced294 | 125 | return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, |
5928808e MW |
126 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
127 | } | |
128 | ||
5928808e MW |
129 | irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data) |
130 | { | |
131 | u32 status; | |
132 | ||
c039dd27 | 133 | status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr; |
5928808e MW |
134 | if (status & SSSR_ROR) { |
135 | dev_err(&drv_data->pdev->dev, "FIFO overrun\n"); | |
136 | ||
b6ced294 JN |
137 | dmaengine_terminate_async(drv_data->master->dma_rx); |
138 | dmaengine_terminate_async(drv_data->master->dma_tx); | |
5928808e MW |
139 | |
140 | pxa2xx_spi_dma_transfer_complete(drv_data, true); | |
141 | return IRQ_HANDLED; | |
142 | } | |
143 | ||
144 | return IRQ_NONE; | |
145 | } | |
146 | ||
147 | int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst) | |
148 | { | |
149 | struct dma_async_tx_descriptor *tx_desc, *rx_desc; | |
bffc967e | 150 | int err; |
5928808e MW |
151 | |
152 | tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV); | |
153 | if (!tx_desc) { | |
154 | dev_err(&drv_data->pdev->dev, | |
155 | "failed to get DMA TX descriptor\n"); | |
7d1f1bf6 AS |
156 | err = -EBUSY; |
157 | goto err_tx; | |
5928808e MW |
158 | } |
159 | ||
160 | rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM); | |
161 | if (!rx_desc) { | |
162 | dev_err(&drv_data->pdev->dev, | |
163 | "failed to get DMA RX descriptor\n"); | |
7d1f1bf6 AS |
164 | err = -EBUSY; |
165 | goto err_rx; | |
5928808e MW |
166 | } |
167 | ||
168 | /* We are ready when RX completes */ | |
169 | rx_desc->callback = pxa2xx_spi_dma_callback; | |
170 | rx_desc->callback_param = drv_data; | |
171 | ||
172 | dmaengine_submit(rx_desc); | |
173 | dmaengine_submit(tx_desc); | |
174 | return 0; | |
7d1f1bf6 AS |
175 | |
176 | err_rx: | |
b6ced294 | 177 | dmaengine_terminate_async(drv_data->master->dma_tx); |
7d1f1bf6 | 178 | err_tx: |
7d1f1bf6 | 179 | return err; |
5928808e MW |
180 | } |
181 | ||
182 | void pxa2xx_spi_dma_start(struct driver_data *drv_data) | |
183 | { | |
b6ced294 JN |
184 | dma_async_issue_pending(drv_data->master->dma_rx); |
185 | dma_async_issue_pending(drv_data->master->dma_tx); | |
5928808e MW |
186 | |
187 | atomic_set(&drv_data->dma_running, 1); | |
188 | } | |
189 | ||
190 | int pxa2xx_spi_dma_setup(struct driver_data *drv_data) | |
191 | { | |
192 | struct pxa2xx_spi_master *pdata = drv_data->master_info; | |
cddb339b | 193 | struct device *dev = &drv_data->pdev->dev; |
b6ced294 | 194 | struct spi_master *master = drv_data->master; |
5928808e MW |
195 | dma_cap_mask_t mask; |
196 | ||
197 | dma_cap_zero(mask); | |
198 | dma_cap_set(DMA_SLAVE, mask); | |
199 | ||
b6ced294 | 200 | master->dma_tx = dma_request_slave_channel_compat(mask, |
b729bf34 | 201 | pdata->dma_filter, pdata->tx_param, dev, "tx"); |
b6ced294 | 202 | if (!master->dma_tx) |
5928808e MW |
203 | return -ENODEV; |
204 | ||
b6ced294 | 205 | master->dma_rx = dma_request_slave_channel_compat(mask, |
b729bf34 | 206 | pdata->dma_filter, pdata->rx_param, dev, "rx"); |
b6ced294 JN |
207 | if (!master->dma_rx) { |
208 | dma_release_channel(master->dma_tx); | |
209 | master->dma_tx = NULL; | |
5928808e MW |
210 | return -ENODEV; |
211 | } | |
212 | ||
213 | return 0; | |
214 | } | |
215 | ||
216 | void pxa2xx_spi_dma_release(struct driver_data *drv_data) | |
217 | { | |
b6ced294 JN |
218 | struct spi_master *master = drv_data->master; |
219 | ||
220 | if (master->dma_rx) { | |
221 | dmaengine_terminate_sync(master->dma_rx); | |
222 | dma_release_channel(master->dma_rx); | |
223 | master->dma_rx = NULL; | |
5928808e | 224 | } |
b6ced294 JN |
225 | if (master->dma_tx) { |
226 | dmaengine_terminate_sync(master->dma_tx); | |
227 | dma_release_channel(master->dma_tx); | |
228 | master->dma_tx = NULL; | |
5928808e MW |
229 | } |
230 | } | |
231 | ||
5928808e MW |
232 | int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, |
233 | struct spi_device *spi, | |
234 | u8 bits_per_word, u32 *burst_code, | |
235 | u32 *threshold) | |
236 | { | |
237 | struct pxa2xx_spi_chip *chip_info = spi->controller_data; | |
238 | ||
239 | /* | |
240 | * If the DMA burst size is given in chip_info we use that, | |
241 | * otherwise we use the default. Also we use the default FIFO | |
242 | * thresholds for now. | |
243 | */ | |
01d7aafb | 244 | *burst_code = chip_info ? chip_info->dma_burst_size : 1; |
5928808e MW |
245 | *threshold = SSCR1_RxTresh(RX_THRESH_DFLT) |
246 | | SSCR1_TxTresh(TX_THRESH_DFLT); | |
247 | ||
248 | return 0; | |
249 | } |