]>
Commit | Line | Data |
---|---|---|
64ff247a II |
1 | /* |
2 | * Copyright (c) 2008-2014, The Linux foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License rev 2 and | |
6 | * only rev 2 as published by the free Software foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/spi/spi.h> | |
612762e8 AG |
25 | #include <linux/dmaengine.h> |
26 | #include <linux/dma-mapping.h> | |
64ff247a II |
27 | |
28 | #define QUP_CONFIG 0x0000 | |
29 | #define QUP_STATE 0x0004 | |
30 | #define QUP_IO_M_MODES 0x0008 | |
31 | #define QUP_SW_RESET 0x000c | |
32 | #define QUP_OPERATIONAL 0x0018 | |
33 | #define QUP_ERROR_FLAGS 0x001c | |
34 | #define QUP_ERROR_FLAGS_EN 0x0020 | |
35 | #define QUP_OPERATIONAL_MASK 0x0028 | |
36 | #define QUP_HW_VERSION 0x0030 | |
37 | #define QUP_MX_OUTPUT_CNT 0x0100 | |
38 | #define QUP_OUTPUT_FIFO 0x0110 | |
39 | #define QUP_MX_WRITE_CNT 0x0150 | |
40 | #define QUP_MX_INPUT_CNT 0x0200 | |
41 | #define QUP_MX_READ_CNT 0x0208 | |
42 | #define QUP_INPUT_FIFO 0x0218 | |
43 | ||
44 | #define SPI_CONFIG 0x0300 | |
45 | #define SPI_IO_CONTROL 0x0304 | |
46 | #define SPI_ERROR_FLAGS 0x0308 | |
47 | #define SPI_ERROR_FLAGS_EN 0x030c | |
48 | ||
49 | /* QUP_CONFIG fields */ | |
50 | #define QUP_CONFIG_SPI_MODE (1 << 8) | |
51 | #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13) | |
52 | #define QUP_CONFIG_NO_INPUT BIT(7) | |
53 | #define QUP_CONFIG_NO_OUTPUT BIT(6) | |
54 | #define QUP_CONFIG_N 0x001f | |
55 | ||
56 | /* QUP_STATE fields */ | |
57 | #define QUP_STATE_VALID BIT(2) | |
58 | #define QUP_STATE_RESET 0 | |
59 | #define QUP_STATE_RUN 1 | |
60 | #define QUP_STATE_PAUSE 3 | |
61 | #define QUP_STATE_MASK 3 | |
62 | #define QUP_STATE_CLEAR 2 | |
63 | ||
64 | #define QUP_HW_VERSION_2_1_1 0x20010001 | |
65 | ||
66 | /* QUP_IO_M_MODES fields */ | |
67 | #define QUP_IO_M_PACK_EN BIT(15) | |
68 | #define QUP_IO_M_UNPACK_EN BIT(14) | |
69 | #define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12 | |
70 | #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10 | |
71 | #define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT) | |
72 | #define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT) | |
73 | ||
74 | #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0) | |
75 | #define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2) | |
76 | #define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5) | |
77 | #define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7) | |
78 | ||
79 | #define QUP_IO_M_MODE_FIFO 0 | |
80 | #define QUP_IO_M_MODE_BLOCK 1 | |
81 | #define QUP_IO_M_MODE_DMOV 2 | |
82 | #define QUP_IO_M_MODE_BAM 3 | |
83 | ||
84 | /* QUP_OPERATIONAL fields */ | |
7538726f VN |
85 | #define QUP_OP_IN_BLOCK_READ_REQ BIT(13) |
86 | #define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12) | |
64ff247a II |
87 | #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11) |
88 | #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10) | |
89 | #define QUP_OP_IN_SERVICE_FLAG BIT(9) | |
90 | #define QUP_OP_OUT_SERVICE_FLAG BIT(8) | |
91 | #define QUP_OP_IN_FIFO_FULL BIT(7) | |
92 | #define QUP_OP_OUT_FIFO_FULL BIT(6) | |
93 | #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5) | |
94 | #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4) | |
95 | ||
96 | /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */ | |
97 | #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5) | |
98 | #define QUP_ERROR_INPUT_UNDER_RUN BIT(4) | |
99 | #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3) | |
100 | #define QUP_ERROR_INPUT_OVER_RUN BIT(2) | |
101 | ||
102 | /* SPI_CONFIG fields */ | |
103 | #define SPI_CONFIG_HS_MODE BIT(10) | |
104 | #define SPI_CONFIG_INPUT_FIRST BIT(9) | |
105 | #define SPI_CONFIG_LOOPBACK BIT(8) | |
106 | ||
107 | /* SPI_IO_CONTROL fields */ | |
108 | #define SPI_IO_C_FORCE_CS BIT(11) | |
109 | #define SPI_IO_C_CLK_IDLE_HIGH BIT(10) | |
110 | #define SPI_IO_C_MX_CS_MODE BIT(8) | |
111 | #define SPI_IO_C_CS_N_POLARITY_0 BIT(4) | |
112 | #define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2) | |
113 | #define SPI_IO_C_CS_SELECT_MASK 0x000c | |
114 | #define SPI_IO_C_TRISTATE_CS BIT(1) | |
115 | #define SPI_IO_C_NO_TRI_STATE BIT(0) | |
116 | ||
117 | /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */ | |
118 | #define SPI_ERROR_CLK_OVER_RUN BIT(1) | |
119 | #define SPI_ERROR_CLK_UNDER_RUN BIT(0) | |
120 | ||
121 | #define SPI_NUM_CHIPSELECTS 4 | |
122 | ||
612762e8 AG |
123 | #define SPI_MAX_DMA_XFER (SZ_64K - 64) |
124 | ||
64ff247a II |
125 | /* high speed mode is when bus rate is greater then 26MHz */ |
126 | #define SPI_HS_MIN_RATE 26000000 | |
127 | #define SPI_MAX_RATE 50000000 | |
128 | ||
129 | #define SPI_DELAY_THRESHOLD 1 | |
130 | #define SPI_DELAY_RETRY 10 | |
131 | ||
64ff247a II |
132 | struct spi_qup { |
133 | void __iomem *base; | |
134 | struct device *dev; | |
135 | struct clk *cclk; /* core clock */ | |
136 | struct clk *iclk; /* interface clock */ | |
137 | int irq; | |
64ff247a II |
138 | spinlock_t lock; |
139 | ||
140 | int in_fifo_sz; | |
141 | int out_fifo_sz; | |
142 | int in_blk_sz; | |
143 | int out_blk_sz; | |
144 | ||
145 | struct spi_transfer *xfer; | |
146 | struct completion done; | |
147 | int error; | |
148 | int w_size; /* bytes per SPI word */ | |
612762e8 | 149 | int n_words; |
64ff247a II |
150 | int tx_bytes; |
151 | int rx_bytes; | |
70cea0a9 | 152 | int qup_v1; |
612762e8 | 153 | |
32ecab99 | 154 | int mode; |
612762e8 AG |
155 | struct dma_slave_config rx_conf; |
156 | struct dma_slave_config tx_conf; | |
64ff247a II |
157 | }; |
158 | ||
7538726f VN |
159 | static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) |
160 | { | |
161 | u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); | |
162 | ||
163 | return (opflag & flag) != 0; | |
164 | } | |
165 | ||
32ecab99 VN |
166 | static inline bool spi_qup_is_dma_xfer(int mode) |
167 | { | |
168 | if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM) | |
169 | return true; | |
170 | ||
171 | return false; | |
172 | } | |
64ff247a II |
173 | |
174 | static inline bool spi_qup_is_valid_state(struct spi_qup *controller) | |
175 | { | |
176 | u32 opstate = readl_relaxed(controller->base + QUP_STATE); | |
177 | ||
178 | return opstate & QUP_STATE_VALID; | |
179 | } | |
180 | ||
181 | static int spi_qup_set_state(struct spi_qup *controller, u32 state) | |
182 | { | |
183 | unsigned long loop; | |
184 | u32 cur_state; | |
185 | ||
186 | loop = 0; | |
187 | while (!spi_qup_is_valid_state(controller)) { | |
188 | ||
189 | usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); | |
190 | ||
191 | if (++loop > SPI_DELAY_RETRY) | |
192 | return -EIO; | |
193 | } | |
194 | ||
195 | if (loop) | |
196 | dev_dbg(controller->dev, "invalid state for %ld,us %d\n", | |
197 | loop, state); | |
198 | ||
199 | cur_state = readl_relaxed(controller->base + QUP_STATE); | |
200 | /* | |
201 | * Per spec: for PAUSE_STATE to RESET_STATE, two writes | |
202 | * of (b10) are required | |
203 | */ | |
204 | if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) && | |
205 | (state == QUP_STATE_RESET)) { | |
206 | writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); | |
207 | writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); | |
208 | } else { | |
209 | cur_state &= ~QUP_STATE_MASK; | |
210 | cur_state |= state; | |
211 | writel_relaxed(cur_state, controller->base + QUP_STATE); | |
212 | } | |
213 | ||
214 | loop = 0; | |
215 | while (!spi_qup_is_valid_state(controller)) { | |
216 | ||
217 | usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); | |
218 | ||
219 | if (++loop > SPI_DELAY_RETRY) | |
220 | return -EIO; | |
221 | } | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
7538726f VN |
226 | static void spi_qup_read_from_fifo(struct spi_qup *controller, |
227 | struct spi_transfer *xfer, u32 num_words) | |
64ff247a II |
228 | { |
229 | u8 *rx_buf = xfer->rx_buf; | |
7538726f VN |
230 | int i, shift, num_bytes; |
231 | u32 word; | |
64ff247a | 232 | |
7538726f | 233 | for (; num_words; num_words--) { |
64ff247a II |
234 | |
235 | word = readl_relaxed(controller->base + QUP_INPUT_FIFO); | |
236 | ||
7538726f VN |
237 | num_bytes = min_t(int, xfer->len - controller->rx_bytes, |
238 | controller->w_size); | |
239 | ||
64ff247a | 240 | if (!rx_buf) { |
7538726f | 241 | controller->rx_bytes += num_bytes; |
64ff247a II |
242 | continue; |
243 | } | |
244 | ||
7538726f | 245 | for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { |
64ff247a II |
246 | /* |
247 | * The data format depends on bytes per SPI word: | |
248 | * 4 bytes: 0x12345678 | |
249 | * 2 bytes: 0x00001234 | |
250 | * 1 byte : 0x00000012 | |
251 | */ | |
252 | shift = BITS_PER_BYTE; | |
7538726f | 253 | shift *= (controller->w_size - i - 1); |
64ff247a II |
254 | rx_buf[controller->rx_bytes] = word >> shift; |
255 | } | |
256 | } | |
257 | } | |
258 | ||
7538726f | 259 | static void spi_qup_read(struct spi_qup *controller, |
64ff247a II |
260 | struct spi_transfer *xfer) |
261 | { | |
7538726f VN |
262 | u32 remainder, words_per_block, num_words; |
263 | bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; | |
264 | ||
265 | remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes, | |
266 | controller->w_size); | |
267 | words_per_block = controller->in_blk_sz >> 2; | |
268 | ||
269 | do { | |
270 | /* ACK by clearing service flag */ | |
271 | writel_relaxed(QUP_OP_IN_SERVICE_FLAG, | |
272 | controller->base + QUP_OPERATIONAL); | |
273 | ||
274 | if (is_block_mode) { | |
275 | num_words = (remainder > words_per_block) ? | |
276 | words_per_block : remainder; | |
277 | } else { | |
278 | if (!spi_qup_is_flag_set(controller, | |
279 | QUP_OP_IN_FIFO_NOT_EMPTY)) | |
280 | break; | |
64ff247a | 281 | |
7538726f VN |
282 | num_words = 1; |
283 | } | |
64ff247a | 284 | |
7538726f VN |
285 | /* read up to the maximum transfer size available */ |
286 | spi_qup_read_from_fifo(controller, xfer, num_words); | |
64ff247a | 287 | |
7538726f VN |
288 | remainder -= num_words; |
289 | ||
290 | /* if block mode, check to see if next block is available */ | |
291 | if (is_block_mode && !spi_qup_is_flag_set(controller, | |
292 | QUP_OP_IN_BLOCK_READ_REQ)) | |
64ff247a II |
293 | break; |
294 | ||
7538726f VN |
295 | } while (remainder); |
296 | ||
297 | /* | |
298 | * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block | |
299 | * mode reads, it has to be cleared again at the very end | |
300 | */ | |
301 | if (is_block_mode && spi_qup_is_flag_set(controller, | |
302 | QUP_OP_MAX_INPUT_DONE_FLAG)) | |
303 | writel_relaxed(QUP_OP_IN_SERVICE_FLAG, | |
304 | controller->base + QUP_OPERATIONAL); | |
305 | ||
306 | } | |
307 | ||
308 | static void spi_qup_write_to_fifo(struct spi_qup *controller, | |
309 | struct spi_transfer *xfer, u32 num_words) | |
310 | { | |
311 | const u8 *tx_buf = xfer->tx_buf; | |
312 | int i, num_bytes; | |
313 | u32 word, data; | |
314 | ||
315 | for (; num_words; num_words--) { | |
64ff247a | 316 | word = 0; |
64ff247a | 317 | |
7538726f VN |
318 | num_bytes = min_t(int, xfer->len - controller->tx_bytes, |
319 | controller->w_size); | |
320 | if (tx_buf) | |
321 | for (i = 0; i < num_bytes; i++) { | |
322 | data = tx_buf[controller->tx_bytes + i]; | |
323 | word |= data << (BITS_PER_BYTE * (3 - i)); | |
64ff247a II |
324 | } |
325 | ||
7538726f | 326 | controller->tx_bytes += num_bytes; |
64ff247a II |
327 | |
328 | writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); | |
329 | } | |
330 | } | |
331 | ||
612762e8 AG |
332 | static void spi_qup_dma_done(void *data) |
333 | { | |
334 | struct spi_qup *qup = data; | |
335 | ||
336 | complete(&qup->done); | |
337 | } | |
338 | ||
7538726f VN |
339 | static void spi_qup_write(struct spi_qup *controller, |
340 | struct spi_transfer *xfer) | |
341 | { | |
342 | bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; | |
343 | u32 remainder, words_per_block, num_words; | |
344 | ||
345 | remainder = DIV_ROUND_UP(xfer->len - controller->tx_bytes, | |
346 | controller->w_size); | |
347 | words_per_block = controller->out_blk_sz >> 2; | |
348 | ||
349 | do { | |
350 | /* ACK by clearing service flag */ | |
351 | writel_relaxed(QUP_OP_OUT_SERVICE_FLAG, | |
352 | controller->base + QUP_OPERATIONAL); | |
353 | ||
354 | if (is_block_mode) { | |
355 | num_words = (remainder > words_per_block) ? | |
356 | words_per_block : remainder; | |
357 | } else { | |
358 | if (spi_qup_is_flag_set(controller, | |
359 | QUP_OP_OUT_FIFO_FULL)) | |
360 | break; | |
361 | ||
362 | num_words = 1; | |
363 | } | |
364 | ||
365 | spi_qup_write_to_fifo(controller, xfer, num_words); | |
366 | ||
367 | remainder -= num_words; | |
368 | ||
369 | /* if block mode, check to see if next block is available */ | |
370 | if (is_block_mode && !spi_qup_is_flag_set(controller, | |
371 | QUP_OP_OUT_BLOCK_WRITE_REQ)) | |
372 | break; | |
373 | ||
374 | } while (remainder); | |
375 | } | |
376 | ||
612762e8 AG |
377 | static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer, |
378 | enum dma_transfer_direction dir, | |
379 | dma_async_tx_callback callback) | |
380 | { | |
381 | struct spi_qup *qup = spi_master_get_devdata(master); | |
382 | unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE; | |
383 | struct dma_async_tx_descriptor *desc; | |
384 | struct scatterlist *sgl; | |
385 | struct dma_chan *chan; | |
386 | dma_cookie_t cookie; | |
387 | unsigned int nents; | |
388 | ||
389 | if (dir == DMA_MEM_TO_DEV) { | |
390 | chan = master->dma_tx; | |
391 | nents = xfer->tx_sg.nents; | |
392 | sgl = xfer->tx_sg.sgl; | |
393 | } else { | |
394 | chan = master->dma_rx; | |
395 | nents = xfer->rx_sg.nents; | |
396 | sgl = xfer->rx_sg.sgl; | |
397 | } | |
398 | ||
399 | desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); | |
d9a09a6c VN |
400 | if (IS_ERR_OR_NULL(desc)) |
401 | return desc ? PTR_ERR(desc) : -EINVAL; | |
612762e8 AG |
402 | |
403 | desc->callback = callback; | |
404 | desc->callback_param = qup; | |
405 | ||
406 | cookie = dmaengine_submit(desc); | |
407 | ||
408 | return dma_submit_error(cookie); | |
409 | } | |
410 | ||
411 | static void spi_qup_dma_terminate(struct spi_master *master, | |
412 | struct spi_transfer *xfer) | |
413 | { | |
414 | if (xfer->tx_buf) | |
415 | dmaengine_terminate_all(master->dma_tx); | |
416 | if (xfer->rx_buf) | |
417 | dmaengine_terminate_all(master->dma_rx); | |
418 | } | |
419 | ||
5f13fd60 VN |
420 | static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer, |
421 | unsigned long timeout) | |
612762e8 | 422 | { |
5f13fd60 | 423 | struct spi_qup *qup = spi_master_get_devdata(master); |
612762e8 AG |
424 | dma_async_tx_callback rx_done = NULL, tx_done = NULL; |
425 | int ret; | |
426 | ||
427 | if (xfer->rx_buf) | |
428 | rx_done = spi_qup_dma_done; | |
429 | else if (xfer->tx_buf) | |
430 | tx_done = spi_qup_dma_done; | |
431 | ||
ce00bab3 VN |
432 | /* before issuing the descriptors, set the QUP to run */ |
433 | ret = spi_qup_set_state(qup, QUP_STATE_RUN); | |
434 | if (ret) { | |
435 | dev_warn(qup->dev, "%s(%d): cannot set RUN state\n", | |
436 | __func__, __LINE__); | |
437 | return ret; | |
438 | } | |
439 | ||
612762e8 AG |
440 | if (xfer->rx_buf) { |
441 | ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done); | |
442 | if (ret) | |
443 | return ret; | |
444 | ||
445 | dma_async_issue_pending(master->dma_rx); | |
446 | } | |
447 | ||
448 | if (xfer->tx_buf) { | |
449 | ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done); | |
450 | if (ret) | |
451 | return ret; | |
452 | ||
453 | dma_async_issue_pending(master->dma_tx); | |
454 | } | |
455 | ||
5f13fd60 VN |
456 | if (!wait_for_completion_timeout(&qup->done, timeout)) |
457 | return -ETIMEDOUT; | |
458 | ||
612762e8 AG |
459 | return 0; |
460 | } | |
461 | ||
5f13fd60 VN |
462 | static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer, |
463 | unsigned long timeout) | |
612762e8 AG |
464 | { |
465 | struct spi_qup *qup = spi_master_get_devdata(master); | |
466 | int ret; | |
467 | ||
468 | ret = spi_qup_set_state(qup, QUP_STATE_RUN); | |
469 | if (ret) { | |
470 | dev_warn(qup->dev, "cannot set RUN state\n"); | |
471 | return ret; | |
472 | } | |
473 | ||
474 | ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); | |
475 | if (ret) { | |
476 | dev_warn(qup->dev, "cannot set PAUSE state\n"); | |
477 | return ret; | |
478 | } | |
479 | ||
7538726f VN |
480 | if (qup->mode == QUP_IO_M_MODE_FIFO) |
481 | spi_qup_write(qup, xfer); | |
612762e8 | 482 | |
ce00bab3 VN |
483 | ret = spi_qup_set_state(qup, QUP_STATE_RUN); |
484 | if (ret) { | |
485 | dev_warn(qup->dev, "%s(%d): cannot set RUN state\n", | |
486 | __func__, __LINE__); | |
487 | return ret; | |
488 | } | |
489 | ||
5f13fd60 VN |
490 | if (!wait_for_completion_timeout(&qup->done, timeout)) |
491 | return -ETIMEDOUT; | |
492 | ||
612762e8 AG |
493 | return 0; |
494 | } | |
495 | ||
64ff247a II |
496 | static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) |
497 | { | |
498 | struct spi_qup *controller = dev_id; | |
ce7dfc71 | 499 | struct spi_transfer *xfer = controller->xfer; |
64ff247a | 500 | u32 opflags, qup_err, spi_err; |
64ff247a II |
501 | int error = 0; |
502 | ||
64ff247a II |
503 | qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); |
504 | spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); | |
505 | opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); | |
506 | ||
507 | writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); | |
508 | writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); | |
64ff247a II |
509 | |
510 | if (qup_err) { | |
511 | if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN) | |
512 | dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); | |
513 | if (qup_err & QUP_ERROR_INPUT_UNDER_RUN) | |
514 | dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); | |
515 | if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN) | |
516 | dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); | |
517 | if (qup_err & QUP_ERROR_INPUT_OVER_RUN) | |
518 | dev_warn(controller->dev, "INPUT_OVER_RUN\n"); | |
519 | ||
520 | error = -EIO; | |
521 | } | |
522 | ||
523 | if (spi_err) { | |
524 | if (spi_err & SPI_ERROR_CLK_OVER_RUN) | |
525 | dev_warn(controller->dev, "CLK_OVER_RUN\n"); | |
526 | if (spi_err & SPI_ERROR_CLK_UNDER_RUN) | |
527 | dev_warn(controller->dev, "CLK_UNDER_RUN\n"); | |
528 | ||
529 | error = -EIO; | |
530 | } | |
531 | ||
ce7dfc71 VN |
532 | if (spi_qup_is_dma_xfer(controller->mode)) { |
533 | writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); | |
534 | } else { | |
612762e8 | 535 | if (opflags & QUP_OP_IN_SERVICE_FLAG) |
7538726f | 536 | spi_qup_read(controller, xfer); |
64ff247a | 537 | |
612762e8 | 538 | if (opflags & QUP_OP_OUT_SERVICE_FLAG) |
7538726f | 539 | spi_qup_write(controller, xfer); |
612762e8 | 540 | } |
64ff247a | 541 | |
ce7dfc71 | 542 | if ((opflags & QUP_OP_MAX_INPUT_DONE_FLAG) || error) |
64ff247a II |
543 | complete(&controller->done); |
544 | ||
545 | return IRQ_HANDLED; | |
546 | } | |
547 | ||
94b9149f VN |
548 | /* set clock freq ... bits per word, determine mode */ |
549 | static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer) | |
64ff247a | 550 | { |
00cce74d | 551 | struct spi_qup *controller = spi_master_get_devdata(spi->master); |
94b9149f | 552 | int ret; |
64ff247a | 553 | |
00cce74d | 554 | if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { |
64ff247a II |
555 | dev_err(controller->dev, "too big size for loopback %d > %d\n", |
556 | xfer->len, controller->in_fifo_sz); | |
557 | return -EIO; | |
558 | } | |
559 | ||
560 | ret = clk_set_rate(controller->cclk, xfer->speed_hz); | |
561 | if (ret) { | |
562 | dev_err(controller->dev, "fail to set frequency %d", | |
563 | xfer->speed_hz); | |
564 | return -EIO; | |
565 | } | |
566 | ||
32ecab99 VN |
567 | controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); |
568 | controller->n_words = xfer->len / controller->w_size; | |
32ecab99 | 569 | |
94b9149f | 570 | if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) |
32ecab99 | 571 | controller->mode = QUP_IO_M_MODE_FIFO; |
94b9149f VN |
572 | else if (spi->master->can_dma && |
573 | spi->master->can_dma(spi->master, spi, xfer) && | |
574 | spi->master->cur_msg_mapped) | |
575 | controller->mode = QUP_IO_M_MODE_BAM; | |
576 | else | |
577 | controller->mode = QUP_IO_M_MODE_BLOCK; | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
582 | /* prep qup for another spi transaction of specific type */ | |
583 | static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) | |
584 | { | |
585 | struct spi_qup *controller = spi_master_get_devdata(spi->master); | |
586 | u32 config, iomode, control; | |
587 | unsigned long flags; | |
32ecab99 | 588 | |
94b9149f VN |
589 | spin_lock_irqsave(&controller->lock, flags); |
590 | controller->xfer = xfer; | |
591 | controller->error = 0; | |
592 | controller->rx_bytes = 0; | |
593 | controller->tx_bytes = 0; | |
594 | spin_unlock_irqrestore(&controller->lock, flags); | |
595 | ||
596 | ||
597 | if (spi_qup_set_state(controller, QUP_STATE_RESET)) { | |
598 | dev_err(controller->dev, "cannot set RESET state\n"); | |
599 | return -EIO; | |
600 | } | |
601 | ||
602 | switch (controller->mode) { | |
603 | case QUP_IO_M_MODE_FIFO: | |
604 | writel_relaxed(controller->n_words, | |
605 | controller->base + QUP_MX_READ_CNT); | |
606 | writel_relaxed(controller->n_words, | |
607 | controller->base + QUP_MX_WRITE_CNT); | |
64ff247a II |
608 | /* must be zero for FIFO */ |
609 | writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); | |
610 | writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); | |
94b9149f VN |
611 | break; |
612 | case QUP_IO_M_MODE_BAM: | |
613 | writel_relaxed(controller->n_words, | |
614 | controller->base + QUP_MX_INPUT_CNT); | |
615 | writel_relaxed(controller->n_words, | |
616 | controller->base + QUP_MX_OUTPUT_CNT); | |
64ff247a II |
617 | /* must be zero for BLOCK and BAM */ |
618 | writel_relaxed(0, controller->base + QUP_MX_READ_CNT); | |
619 | writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); | |
612762e8 AG |
620 | |
621 | if (!controller->qup_v1) { | |
622 | void __iomem *input_cnt; | |
623 | ||
624 | input_cnt = controller->base + QUP_MX_INPUT_CNT; | |
625 | /* | |
626 | * for DMA transfers, both QUP_MX_INPUT_CNT and | |
627 | * QUP_MX_OUTPUT_CNT must be zero to all cases but one. | |
628 | * That case is a non-balanced transfer when there is | |
629 | * only a rx_buf. | |
630 | */ | |
631 | if (xfer->tx_buf) | |
632 | writel_relaxed(0, input_cnt); | |
633 | else | |
94b9149f | 634 | writel_relaxed(controller->n_words, input_cnt); |
612762e8 AG |
635 | |
636 | writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); | |
637 | } | |
94b9149f VN |
638 | break; |
639 | case QUP_IO_M_MODE_BLOCK: | |
640 | reinit_completion(&controller->done); | |
641 | writel_relaxed(controller->n_words, | |
642 | controller->base + QUP_MX_INPUT_CNT); | |
643 | writel_relaxed(controller->n_words, | |
644 | controller->base + QUP_MX_OUTPUT_CNT); | |
32ecab99 VN |
645 | /* must be zero for BLOCK and BAM */ |
646 | writel_relaxed(0, controller->base + QUP_MX_READ_CNT); | |
647 | writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); | |
94b9149f VN |
648 | break; |
649 | default: | |
650 | dev_err(controller->dev, "unknown mode = %d\n", | |
651 | controller->mode); | |
652 | return -EIO; | |
64ff247a II |
653 | } |
654 | ||
655 | iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); | |
656 | /* Set input and output transfer mode */ | |
657 | iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK); | |
612762e8 | 658 | |
32ecab99 | 659 | if (!spi_qup_is_dma_xfer(controller->mode)) |
612762e8 AG |
660 | iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); |
661 | else | |
662 | iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN; | |
663 | ||
32ecab99 VN |
664 | iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); |
665 | iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); | |
64ff247a II |
666 | |
667 | writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); | |
668 | ||
0667dd5f II |
669 | control = readl_relaxed(controller->base + SPI_IO_CONTROL); |
670 | ||
671 | if (spi->mode & SPI_CPOL) | |
672 | control |= SPI_IO_C_CLK_IDLE_HIGH; | |
673 | else | |
674 | control &= ~SPI_IO_C_CLK_IDLE_HIGH; | |
675 | ||
676 | writel_relaxed(control, controller->base + SPI_IO_CONTROL); | |
677 | ||
64ff247a II |
678 | config = readl_relaxed(controller->base + SPI_CONFIG); |
679 | ||
00cce74d | 680 | if (spi->mode & SPI_LOOP) |
64ff247a II |
681 | config |= SPI_CONFIG_LOOPBACK; |
682 | else | |
683 | config &= ~SPI_CONFIG_LOOPBACK; | |
684 | ||
00cce74d | 685 | if (spi->mode & SPI_CPHA) |
64ff247a II |
686 | config &= ~SPI_CONFIG_INPUT_FIRST; |
687 | else | |
688 | config |= SPI_CONFIG_INPUT_FIRST; | |
689 | ||
690 | /* | |
691 | * HS_MODE improves signal stability for spi-clk high rates, | |
692 | * but is invalid in loop back mode. | |
693 | */ | |
00cce74d | 694 | if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP)) |
64ff247a II |
695 | config |= SPI_CONFIG_HS_MODE; |
696 | else | |
697 | config &= ~SPI_CONFIG_HS_MODE; | |
698 | ||
699 | writel_relaxed(config, controller->base + SPI_CONFIG); | |
700 | ||
701 | config = readl_relaxed(controller->base + QUP_CONFIG); | |
702 | config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); | |
703 | config |= xfer->bits_per_word - 1; | |
704 | config |= QUP_CONFIG_SPI_MODE; | |
612762e8 | 705 | |
32ecab99 | 706 | if (spi_qup_is_dma_xfer(controller->mode)) { |
612762e8 AG |
707 | if (!xfer->tx_buf) |
708 | config |= QUP_CONFIG_NO_OUTPUT; | |
709 | if (!xfer->rx_buf) | |
710 | config |= QUP_CONFIG_NO_INPUT; | |
711 | } | |
712 | ||
64ff247a II |
713 | writel_relaxed(config, controller->base + QUP_CONFIG); |
714 | ||
70cea0a9 | 715 | /* only write to OPERATIONAL_MASK when register is present */ |
612762e8 AG |
716 | if (!controller->qup_v1) { |
717 | u32 mask = 0; | |
718 | ||
719 | /* | |
720 | * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO | |
721 | * status change in BAM mode | |
722 | */ | |
723 | ||
32ecab99 | 724 | if (spi_qup_is_dma_xfer(controller->mode)) |
612762e8 AG |
725 | mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG; |
726 | ||
727 | writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); | |
728 | } | |
729 | ||
64ff247a II |
730 | return 0; |
731 | } | |
732 | ||
64ff247a II |
733 | static int spi_qup_transfer_one(struct spi_master *master, |
734 | struct spi_device *spi, | |
735 | struct spi_transfer *xfer) | |
736 | { | |
737 | struct spi_qup *controller = spi_master_get_devdata(master); | |
64ff247a II |
738 | unsigned long timeout, flags; |
739 | int ret = -EIO; | |
740 | ||
94b9149f VN |
741 | ret = spi_qup_io_prep(spi, xfer); |
742 | if (ret) | |
743 | return ret; | |
744 | ||
00cce74d | 745 | ret = spi_qup_io_config(spi, xfer); |
64ff247a II |
746 | if (ret) |
747 | return ret; | |
748 | ||
749 | timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); | |
750 | timeout = DIV_ROUND_UP(xfer->len * 8, timeout); | |
751 | timeout = 100 * msecs_to_jiffies(timeout); | |
752 | ||
753 | reinit_completion(&controller->done); | |
754 | ||
755 | spin_lock_irqsave(&controller->lock, flags); | |
756 | controller->xfer = xfer; | |
757 | controller->error = 0; | |
758 | controller->rx_bytes = 0; | |
759 | controller->tx_bytes = 0; | |
760 | spin_unlock_irqrestore(&controller->lock, flags); | |
761 | ||
32ecab99 | 762 | if (spi_qup_is_dma_xfer(controller->mode)) |
5f13fd60 | 763 | ret = spi_qup_do_dma(master, xfer, timeout); |
612762e8 | 764 | else |
5f13fd60 | 765 | ret = spi_qup_do_pio(master, xfer, timeout); |
64ff247a | 766 | |
612762e8 | 767 | if (ret) |
64ff247a | 768 | goto exit; |
64ff247a | 769 | |
64ff247a II |
770 | exit: |
771 | spi_qup_set_state(controller, QUP_STATE_RESET); | |
772 | spin_lock_irqsave(&controller->lock, flags); | |
64ff247a II |
773 | if (!ret) |
774 | ret = controller->error; | |
775 | spin_unlock_irqrestore(&controller->lock, flags); | |
612762e8 | 776 | |
32ecab99 | 777 | if (ret && spi_qup_is_dma_xfer(controller->mode)) |
612762e8 AG |
778 | spi_qup_dma_terminate(master, xfer); |
779 | ||
780 | return ret; | |
781 | } | |
782 | ||
783 | static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi, | |
784 | struct spi_transfer *xfer) | |
785 | { | |
786 | struct spi_qup *qup = spi_master_get_devdata(master); | |
787 | size_t dma_align = dma_get_cache_alignment(); | |
32ecab99 | 788 | int n_words; |
612762e8 | 789 | |
32ecab99 VN |
790 | if (xfer->rx_buf) { |
791 | if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) || | |
792 | IS_ERR_OR_NULL(master->dma_rx)) | |
793 | return false; | |
794 | if (qup->qup_v1 && (xfer->len % qup->in_blk_sz)) | |
795 | return false; | |
796 | } | |
612762e8 | 797 | |
32ecab99 VN |
798 | if (xfer->tx_buf) { |
799 | if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) || | |
800 | IS_ERR_OR_NULL(master->dma_tx)) | |
801 | return false; | |
802 | if (qup->qup_v1 && (xfer->len % qup->out_blk_sz)) | |
803 | return false; | |
804 | } | |
612762e8 | 805 | |
32ecab99 VN |
806 | n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8); |
807 | if (n_words <= (qup->in_fifo_sz / sizeof(u32))) | |
612762e8 AG |
808 | return false; |
809 | ||
612762e8 AG |
810 | return true; |
811 | } | |
812 | ||
813 | static void spi_qup_release_dma(struct spi_master *master) | |
814 | { | |
815 | if (!IS_ERR_OR_NULL(master->dma_rx)) | |
816 | dma_release_channel(master->dma_rx); | |
817 | if (!IS_ERR_OR_NULL(master->dma_tx)) | |
818 | dma_release_channel(master->dma_tx); | |
819 | } | |
820 | ||
821 | static int spi_qup_init_dma(struct spi_master *master, resource_size_t base) | |
822 | { | |
823 | struct spi_qup *spi = spi_master_get_devdata(master); | |
824 | struct dma_slave_config *rx_conf = &spi->rx_conf, | |
825 | *tx_conf = &spi->tx_conf; | |
826 | struct device *dev = spi->dev; | |
827 | int ret; | |
828 | ||
829 | /* allocate dma resources, if available */ | |
830 | master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); | |
831 | if (IS_ERR(master->dma_rx)) | |
832 | return PTR_ERR(master->dma_rx); | |
833 | ||
834 | master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); | |
835 | if (IS_ERR(master->dma_tx)) { | |
836 | ret = PTR_ERR(master->dma_tx); | |
837 | goto err_tx; | |
838 | } | |
839 | ||
840 | /* set DMA parameters */ | |
841 | rx_conf->direction = DMA_DEV_TO_MEM; | |
842 | rx_conf->device_fc = 1; | |
843 | rx_conf->src_addr = base + QUP_INPUT_FIFO; | |
844 | rx_conf->src_maxburst = spi->in_blk_sz; | |
845 | ||
846 | tx_conf->direction = DMA_MEM_TO_DEV; | |
847 | tx_conf->device_fc = 1; | |
848 | tx_conf->dst_addr = base + QUP_OUTPUT_FIFO; | |
849 | tx_conf->dst_maxburst = spi->out_blk_sz; | |
850 | ||
851 | ret = dmaengine_slave_config(master->dma_rx, rx_conf); | |
852 | if (ret) { | |
853 | dev_err(dev, "failed to configure RX channel\n"); | |
854 | goto err; | |
855 | } | |
856 | ||
857 | ret = dmaengine_slave_config(master->dma_tx, tx_conf); | |
858 | if (ret) { | |
859 | dev_err(dev, "failed to configure TX channel\n"); | |
860 | goto err; | |
861 | } | |
862 | ||
863 | return 0; | |
864 | ||
865 | err: | |
866 | dma_release_channel(master->dma_tx); | |
867 | err_tx: | |
868 | dma_release_channel(master->dma_rx); | |
64ff247a II |
869 | return ret; |
870 | } | |
871 | ||
b702b9fb VN |
872 | static void spi_qup_set_cs(struct spi_device *spi, bool val) |
873 | { | |
874 | struct spi_qup *controller; | |
875 | u32 spi_ioc; | |
876 | u32 spi_ioc_orig; | |
877 | ||
878 | controller = spi_master_get_devdata(spi->master); | |
879 | spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); | |
880 | spi_ioc_orig = spi_ioc; | |
881 | if (!val) | |
882 | spi_ioc |= SPI_IO_C_FORCE_CS; | |
883 | else | |
884 | spi_ioc &= ~SPI_IO_C_FORCE_CS; | |
885 | ||
886 | if (spi_ioc != spi_ioc_orig) | |
887 | writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); | |
888 | } | |
889 | ||
64ff247a II |
890 | static int spi_qup_probe(struct platform_device *pdev) |
891 | { | |
892 | struct spi_master *master; | |
893 | struct clk *iclk, *cclk; | |
894 | struct spi_qup *controller; | |
895 | struct resource *res; | |
896 | struct device *dev; | |
897 | void __iomem *base; | |
12cb89e3 | 898 | u32 max_freq, iomode, num_cs; |
64ff247a II |
899 | int ret, irq, size; |
900 | ||
901 | dev = &pdev->dev; | |
902 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
903 | base = devm_ioremap_resource(dev, res); | |
904 | if (IS_ERR(base)) | |
905 | return PTR_ERR(base); | |
906 | ||
907 | irq = platform_get_irq(pdev, 0); | |
64ff247a II |
908 | if (irq < 0) |
909 | return irq; | |
910 | ||
911 | cclk = devm_clk_get(dev, "core"); | |
912 | if (IS_ERR(cclk)) | |
913 | return PTR_ERR(cclk); | |
914 | ||
915 | iclk = devm_clk_get(dev, "iface"); | |
916 | if (IS_ERR(iclk)) | |
917 | return PTR_ERR(iclk); | |
918 | ||
919 | /* This is optional parameter */ | |
920 | if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) | |
921 | max_freq = SPI_MAX_RATE; | |
922 | ||
923 | if (!max_freq || max_freq > SPI_MAX_RATE) { | |
924 | dev_err(dev, "invalid clock frequency %d\n", max_freq); | |
925 | return -ENXIO; | |
926 | } | |
927 | ||
928 | ret = clk_prepare_enable(cclk); | |
929 | if (ret) { | |
930 | dev_err(dev, "cannot enable core clock\n"); | |
931 | return ret; | |
932 | } | |
933 | ||
934 | ret = clk_prepare_enable(iclk); | |
935 | if (ret) { | |
936 | clk_disable_unprepare(cclk); | |
937 | dev_err(dev, "cannot enable iface clock\n"); | |
938 | return ret; | |
939 | } | |
940 | ||
64ff247a II |
941 | master = spi_alloc_master(dev, sizeof(struct spi_qup)); |
942 | if (!master) { | |
943 | clk_disable_unprepare(cclk); | |
944 | clk_disable_unprepare(iclk); | |
945 | dev_err(dev, "cannot allocate master\n"); | |
946 | return -ENOMEM; | |
947 | } | |
948 | ||
4a8573ab | 949 | /* use num-cs unless not present or out of range */ |
12cb89e3 II |
950 | if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) || |
951 | num_cs > SPI_NUM_CHIPSELECTS) | |
4a8573ab | 952 | master->num_chipselect = SPI_NUM_CHIPSELECTS; |
12cb89e3 II |
953 | else |
954 | master->num_chipselect = num_cs; | |
4a8573ab | 955 | |
64ff247a II |
956 | master->bus_num = pdev->id; |
957 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
64ff247a | 958 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
cb64ca54 | 959 | master->max_speed_hz = max_freq; |
64ff247a II |
960 | master->transfer_one = spi_qup_transfer_one; |
961 | master->dev.of_node = pdev->dev.of_node; | |
962 | master->auto_runtime_pm = true; | |
612762e8 AG |
963 | master->dma_alignment = dma_get_cache_alignment(); |
964 | master->max_dma_len = SPI_MAX_DMA_XFER; | |
64ff247a II |
965 | |
966 | platform_set_drvdata(pdev, master); | |
967 | ||
968 | controller = spi_master_get_devdata(master); | |
969 | ||
970 | controller->dev = dev; | |
971 | controller->base = base; | |
972 | controller->iclk = iclk; | |
973 | controller->cclk = cclk; | |
974 | controller->irq = irq; | |
64ff247a | 975 | |
612762e8 AG |
976 | ret = spi_qup_init_dma(master, res->start); |
977 | if (ret == -EPROBE_DEFER) | |
978 | goto error; | |
979 | else if (!ret) | |
980 | master->can_dma = spi_qup_can_dma; | |
981 | ||
70cea0a9 AG |
982 | /* set v1 flag if device is version 1 */ |
983 | if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1")) | |
984 | controller->qup_v1 = 1; | |
985 | ||
b702b9fb VN |
986 | if (!controller->qup_v1) |
987 | master->set_cs = spi_qup_set_cs; | |
988 | ||
64ff247a II |
989 | spin_lock_init(&controller->lock); |
990 | init_completion(&controller->done); | |
991 | ||
992 | iomode = readl_relaxed(base + QUP_IO_M_MODES); | |
993 | ||
994 | size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode); | |
995 | if (size) | |
996 | controller->out_blk_sz = size * 16; | |
997 | else | |
998 | controller->out_blk_sz = 4; | |
999 | ||
1000 | size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode); | |
1001 | if (size) | |
1002 | controller->in_blk_sz = size * 16; | |
1003 | else | |
1004 | controller->in_blk_sz = 4; | |
1005 | ||
1006 | size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode); | |
1007 | controller->out_fifo_sz = controller->out_blk_sz * (2 << size); | |
1008 | ||
1009 | size = QUP_IO_M_INPUT_FIFO_SIZE(iomode); | |
1010 | controller->in_fifo_sz = controller->in_blk_sz * (2 << size); | |
1011 | ||
70cea0a9 AG |
1012 | dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", |
1013 | controller->in_blk_sz, controller->in_fifo_sz, | |
64ff247a II |
1014 | controller->out_blk_sz, controller->out_fifo_sz); |
1015 | ||
1016 | writel_relaxed(1, base + QUP_SW_RESET); | |
1017 | ||
1018 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
1019 | if (ret) { | |
1020 | dev_err(dev, "cannot set RESET state\n"); | |
612762e8 | 1021 | goto error_dma; |
64ff247a II |
1022 | } |
1023 | ||
1024 | writel_relaxed(0, base + QUP_OPERATIONAL); | |
1025 | writel_relaxed(0, base + QUP_IO_M_MODES); | |
70cea0a9 AG |
1026 | |
1027 | if (!controller->qup_v1) | |
1028 | writel_relaxed(0, base + QUP_OPERATIONAL_MASK); | |
1029 | ||
64ff247a II |
1030 | writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN, |
1031 | base + SPI_ERROR_FLAGS_EN); | |
1032 | ||
70cea0a9 AG |
1033 | /* if earlier version of the QUP, disable INPUT_OVERRUN */ |
1034 | if (controller->qup_v1) | |
1035 | writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN | | |
1036 | QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN, | |
1037 | base + QUP_ERROR_FLAGS_EN); | |
1038 | ||
64ff247a II |
1039 | writel_relaxed(0, base + SPI_CONFIG); |
1040 | writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); | |
1041 | ||
1042 | ret = devm_request_irq(dev, irq, spi_qup_qup_irq, | |
1043 | IRQF_TRIGGER_HIGH, pdev->name, controller); | |
1044 | if (ret) | |
612762e8 | 1045 | goto error_dma; |
64ff247a | 1046 | |
64ff247a II |
1047 | pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); |
1048 | pm_runtime_use_autosuspend(dev); | |
1049 | pm_runtime_set_active(dev); | |
1050 | pm_runtime_enable(dev); | |
045c243a AG |
1051 | |
1052 | ret = devm_spi_register_master(dev, master); | |
1053 | if (ret) | |
1054 | goto disable_pm; | |
1055 | ||
64ff247a II |
1056 | return 0; |
1057 | ||
045c243a AG |
1058 | disable_pm: |
1059 | pm_runtime_disable(&pdev->dev); | |
612762e8 AG |
1060 | error_dma: |
1061 | spi_qup_release_dma(master); | |
64ff247a II |
1062 | error: |
1063 | clk_disable_unprepare(cclk); | |
1064 | clk_disable_unprepare(iclk); | |
1065 | spi_master_put(master); | |
1066 | return ret; | |
1067 | } | |
1068 | ||
ec833050 | 1069 | #ifdef CONFIG_PM |
64ff247a II |
1070 | static int spi_qup_pm_suspend_runtime(struct device *device) |
1071 | { | |
1072 | struct spi_master *master = dev_get_drvdata(device); | |
1073 | struct spi_qup *controller = spi_master_get_devdata(master); | |
1074 | u32 config; | |
1075 | ||
1076 | /* Enable clocks auto gaiting */ | |
1077 | config = readl(controller->base + QUP_CONFIG); | |
f0ceb114 | 1078 | config |= QUP_CONFIG_CLOCK_AUTO_GATE; |
64ff247a | 1079 | writel_relaxed(config, controller->base + QUP_CONFIG); |
dae1a770 PG |
1080 | |
1081 | clk_disable_unprepare(controller->cclk); | |
1082 | clk_disable_unprepare(controller->iclk); | |
1083 | ||
64ff247a II |
1084 | return 0; |
1085 | } | |
1086 | ||
1087 | static int spi_qup_pm_resume_runtime(struct device *device) | |
1088 | { | |
1089 | struct spi_master *master = dev_get_drvdata(device); | |
1090 | struct spi_qup *controller = spi_master_get_devdata(master); | |
1091 | u32 config; | |
dae1a770 PG |
1092 | int ret; |
1093 | ||
1094 | ret = clk_prepare_enable(controller->iclk); | |
1095 | if (ret) | |
1096 | return ret; | |
1097 | ||
1098 | ret = clk_prepare_enable(controller->cclk); | |
1099 | if (ret) | |
1100 | return ret; | |
64ff247a II |
1101 | |
1102 | /* Disable clocks auto gaiting */ | |
1103 | config = readl_relaxed(controller->base + QUP_CONFIG); | |
f0ceb114 | 1104 | config &= ~QUP_CONFIG_CLOCK_AUTO_GATE; |
64ff247a II |
1105 | writel_relaxed(config, controller->base + QUP_CONFIG); |
1106 | return 0; | |
1107 | } | |
ec833050 | 1108 | #endif /* CONFIG_PM */ |
64ff247a II |
1109 | |
1110 | #ifdef CONFIG_PM_SLEEP | |
1111 | static int spi_qup_suspend(struct device *device) | |
1112 | { | |
1113 | struct spi_master *master = dev_get_drvdata(device); | |
1114 | struct spi_qup *controller = spi_master_get_devdata(master); | |
1115 | int ret; | |
1116 | ||
1117 | ret = spi_master_suspend(master); | |
1118 | if (ret) | |
1119 | return ret; | |
1120 | ||
1121 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
1122 | if (ret) | |
1123 | return ret; | |
1124 | ||
9d04d8bc SH |
1125 | if (!pm_runtime_suspended(device)) { |
1126 | clk_disable_unprepare(controller->cclk); | |
1127 | clk_disable_unprepare(controller->iclk); | |
1128 | } | |
64ff247a II |
1129 | return 0; |
1130 | } | |
1131 | ||
1132 | static int spi_qup_resume(struct device *device) | |
1133 | { | |
1134 | struct spi_master *master = dev_get_drvdata(device); | |
1135 | struct spi_qup *controller = spi_master_get_devdata(master); | |
1136 | int ret; | |
1137 | ||
1138 | ret = clk_prepare_enable(controller->iclk); | |
1139 | if (ret) | |
1140 | return ret; | |
1141 | ||
1142 | ret = clk_prepare_enable(controller->cclk); | |
1143 | if (ret) | |
1144 | return ret; | |
1145 | ||
1146 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
1147 | if (ret) | |
1148 | return ret; | |
1149 | ||
1150 | return spi_master_resume(master); | |
1151 | } | |
1152 | #endif /* CONFIG_PM_SLEEP */ | |
1153 | ||
1154 | static int spi_qup_remove(struct platform_device *pdev) | |
1155 | { | |
1156 | struct spi_master *master = dev_get_drvdata(&pdev->dev); | |
1157 | struct spi_qup *controller = spi_master_get_devdata(master); | |
1158 | int ret; | |
1159 | ||
1160 | ret = pm_runtime_get_sync(&pdev->dev); | |
3d89e141 | 1161 | if (ret < 0) |
64ff247a II |
1162 | return ret; |
1163 | ||
1164 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
1165 | if (ret) | |
1166 | return ret; | |
1167 | ||
612762e8 AG |
1168 | spi_qup_release_dma(master); |
1169 | ||
64ff247a II |
1170 | clk_disable_unprepare(controller->cclk); |
1171 | clk_disable_unprepare(controller->iclk); | |
1172 | ||
1173 | pm_runtime_put_noidle(&pdev->dev); | |
1174 | pm_runtime_disable(&pdev->dev); | |
d2442287 | 1175 | |
64ff247a II |
1176 | return 0; |
1177 | } | |
1178 | ||
113b1a07 | 1179 | static const struct of_device_id spi_qup_dt_match[] = { |
70cea0a9 | 1180 | { .compatible = "qcom,spi-qup-v1.1.1", }, |
64ff247a II |
1181 | { .compatible = "qcom,spi-qup-v2.1.1", }, |
1182 | { .compatible = "qcom,spi-qup-v2.2.1", }, | |
1183 | { } | |
1184 | }; | |
1185 | MODULE_DEVICE_TABLE(of, spi_qup_dt_match); | |
1186 | ||
1187 | static const struct dev_pm_ops spi_qup_dev_pm_ops = { | |
1188 | SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume) | |
1189 | SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime, | |
1190 | spi_qup_pm_resume_runtime, | |
1191 | NULL) | |
1192 | }; | |
1193 | ||
1194 | static struct platform_driver spi_qup_driver = { | |
1195 | .driver = { | |
1196 | .name = "spi_qup", | |
64ff247a II |
1197 | .pm = &spi_qup_dev_pm_ops, |
1198 | .of_match_table = spi_qup_dt_match, | |
1199 | }, | |
1200 | .probe = spi_qup_probe, | |
1201 | .remove = spi_qup_remove, | |
1202 | }; | |
1203 | module_platform_driver(spi_qup_driver); | |
1204 | ||
1205 | MODULE_LICENSE("GPL v2"); | |
64ff247a | 1206 | MODULE_ALIAS("platform:spi_qup"); |