]>
Commit | Line | Data |
---|---|---|
64e36824 | 1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
5dcc44ed | 3 | * Author: Addy Ke <addy.ke@rock-chips.com> |
64e36824 | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | */ | |
15 | ||
64e36824 | 16 | #include <linux/clk.h> |
ec5c5d8a SL |
17 | #include <linux/dmaengine.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
23e291c2 | 20 | #include <linux/pinctrl/consumer.h> |
64e36824 | 21 | #include <linux/platform_device.h> |
64e36824 | 22 | #include <linux/spi/spi.h> |
64e36824 | 23 | #include <linux/pm_runtime.h> |
ec5c5d8a | 24 | #include <linux/scatterlist.h> |
64e36824 | 25 | |
26 | #define DRIVER_NAME "rockchip-spi" | |
27 | ||
aa099382 JC |
28 | #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ |
29 | writel_relaxed(readl_relaxed(reg) & ~(bits), reg) | |
30 | #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ | |
31 | writel_relaxed(readl_relaxed(reg) | (bits), reg) | |
32 | ||
64e36824 | 33 | /* SPI register offsets */ |
34 | #define ROCKCHIP_SPI_CTRLR0 0x0000 | |
35 | #define ROCKCHIP_SPI_CTRLR1 0x0004 | |
36 | #define ROCKCHIP_SPI_SSIENR 0x0008 | |
37 | #define ROCKCHIP_SPI_SER 0x000c | |
38 | #define ROCKCHIP_SPI_BAUDR 0x0010 | |
39 | #define ROCKCHIP_SPI_TXFTLR 0x0014 | |
40 | #define ROCKCHIP_SPI_RXFTLR 0x0018 | |
41 | #define ROCKCHIP_SPI_TXFLR 0x001c | |
42 | #define ROCKCHIP_SPI_RXFLR 0x0020 | |
43 | #define ROCKCHIP_SPI_SR 0x0024 | |
44 | #define ROCKCHIP_SPI_IPR 0x0028 | |
45 | #define ROCKCHIP_SPI_IMR 0x002c | |
46 | #define ROCKCHIP_SPI_ISR 0x0030 | |
47 | #define ROCKCHIP_SPI_RISR 0x0034 | |
48 | #define ROCKCHIP_SPI_ICR 0x0038 | |
49 | #define ROCKCHIP_SPI_DMACR 0x003c | |
50 | #define ROCKCHIP_SPI_DMATDLR 0x0040 | |
51 | #define ROCKCHIP_SPI_DMARDLR 0x0044 | |
52 | #define ROCKCHIP_SPI_TXDR 0x0400 | |
53 | #define ROCKCHIP_SPI_RXDR 0x0800 | |
54 | ||
55 | /* Bit fields in CTRLR0 */ | |
56 | #define CR0_DFS_OFFSET 0 | |
57 | ||
58 | #define CR0_CFS_OFFSET 2 | |
59 | ||
60 | #define CR0_SCPH_OFFSET 6 | |
61 | ||
62 | #define CR0_SCPOL_OFFSET 7 | |
63 | ||
64 | #define CR0_CSM_OFFSET 8 | |
65 | #define CR0_CSM_KEEP 0x0 | |
66 | /* ss_n be high for half sclk_out cycles */ | |
67 | #define CR0_CSM_HALF 0X1 | |
68 | /* ss_n be high for one sclk_out cycle */ | |
69 | #define CR0_CSM_ONE 0x2 | |
70 | ||
71 | /* ss_n to sclk_out delay */ | |
72 | #define CR0_SSD_OFFSET 10 | |
73 | /* | |
74 | * The period between ss_n active and | |
75 | * sclk_out active is half sclk_out cycles | |
76 | */ | |
77 | #define CR0_SSD_HALF 0x0 | |
78 | /* | |
79 | * The period between ss_n active and | |
80 | * sclk_out active is one sclk_out cycle | |
81 | */ | |
82 | #define CR0_SSD_ONE 0x1 | |
83 | ||
84 | #define CR0_EM_OFFSET 11 | |
85 | #define CR0_EM_LITTLE 0x0 | |
86 | #define CR0_EM_BIG 0x1 | |
87 | ||
88 | #define CR0_FBM_OFFSET 12 | |
89 | #define CR0_FBM_MSB 0x0 | |
90 | #define CR0_FBM_LSB 0x1 | |
91 | ||
92 | #define CR0_BHT_OFFSET 13 | |
93 | #define CR0_BHT_16BIT 0x0 | |
94 | #define CR0_BHT_8BIT 0x1 | |
95 | ||
96 | #define CR0_RSD_OFFSET 14 | |
97 | ||
98 | #define CR0_FRF_OFFSET 16 | |
99 | #define CR0_FRF_SPI 0x0 | |
100 | #define CR0_FRF_SSP 0x1 | |
101 | #define CR0_FRF_MICROWIRE 0x2 | |
102 | ||
103 | #define CR0_XFM_OFFSET 18 | |
104 | #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) | |
105 | #define CR0_XFM_TR 0x0 | |
106 | #define CR0_XFM_TO 0x1 | |
107 | #define CR0_XFM_RO 0x2 | |
108 | ||
109 | #define CR0_OPM_OFFSET 20 | |
110 | #define CR0_OPM_MASTER 0x0 | |
111 | #define CR0_OPM_SLAVE 0x1 | |
112 | ||
113 | #define CR0_MTM_OFFSET 0x21 | |
114 | ||
115 | /* Bit fields in SER, 2bit */ | |
116 | #define SER_MASK 0x3 | |
117 | ||
118 | /* Bit fields in SR, 5bit */ | |
119 | #define SR_MASK 0x1f | |
120 | #define SR_BUSY (1 << 0) | |
121 | #define SR_TF_FULL (1 << 1) | |
122 | #define SR_TF_EMPTY (1 << 2) | |
123 | #define SR_RF_EMPTY (1 << 3) | |
124 | #define SR_RF_FULL (1 << 4) | |
125 | ||
126 | /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ | |
127 | #define INT_MASK 0x1f | |
128 | #define INT_TF_EMPTY (1 << 0) | |
129 | #define INT_TF_OVERFLOW (1 << 1) | |
130 | #define INT_RF_UNDERFLOW (1 << 2) | |
131 | #define INT_RF_OVERFLOW (1 << 3) | |
132 | #define INT_RF_FULL (1 << 4) | |
133 | ||
134 | /* Bit fields in ICR, 4bit */ | |
135 | #define ICR_MASK 0x0f | |
136 | #define ICR_ALL (1 << 0) | |
137 | #define ICR_RF_UNDERFLOW (1 << 1) | |
138 | #define ICR_RF_OVERFLOW (1 << 2) | |
139 | #define ICR_TF_OVERFLOW (1 << 3) | |
140 | ||
141 | /* Bit fields in DMACR */ | |
142 | #define RF_DMA_EN (1 << 0) | |
143 | #define TF_DMA_EN (1 << 1) | |
144 | ||
145 | #define RXBUSY (1 << 0) | |
146 | #define TXBUSY (1 << 1) | |
147 | ||
f9cfd522 AK |
148 | /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ |
149 | #define MAX_SCLK_OUT 50000000 | |
150 | ||
5185a81c BN |
151 | /* |
152 | * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, | |
153 | * the controller seems to hang when given 0x10000, so stick with this for now. | |
154 | */ | |
155 | #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff | |
156 | ||
aa099382 JC |
157 | #define ROCKCHIP_SPI_MAX_CS_NUM 2 |
158 | ||
64e36824 | 159 | struct rockchip_spi_dma_data { |
160 | struct dma_chan *ch; | |
64e36824 | 161 | dma_addr_t addr; |
162 | }; | |
163 | ||
164 | struct rockchip_spi { | |
165 | struct device *dev; | |
166 | struct spi_master *master; | |
167 | ||
168 | struct clk *spiclk; | |
169 | struct clk *apb_pclk; | |
170 | ||
171 | void __iomem *regs; | |
172 | /*depth of the FIFO buffer */ | |
173 | u32 fifo_len; | |
174 | /* max bus freq supported */ | |
175 | u32 max_freq; | |
64e36824 | 176 | |
177 | u16 mode; | |
178 | u8 tmode; | |
179 | u8 bpw; | |
180 | u8 n_bytes; | |
108b5c8b | 181 | u32 rsd_nsecs; |
64e36824 | 182 | unsigned len; |
183 | u32 speed; | |
184 | ||
185 | const void *tx; | |
186 | const void *tx_end; | |
187 | void *rx; | |
188 | void *rx_end; | |
189 | ||
190 | u32 state; | |
5dcc44ed | 191 | /* protect state */ |
64e36824 | 192 | spinlock_t lock; |
193 | ||
aa099382 JC |
194 | bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; |
195 | ||
f340b920 | 196 | bool use_dma; |
64e36824 | 197 | struct sg_table tx_sg; |
198 | struct sg_table rx_sg; | |
199 | struct rockchip_spi_dma_data dma_rx; | |
200 | struct rockchip_spi_dma_data dma_tx; | |
201 | }; | |
202 | ||
30688e4e | 203 | static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) |
64e36824 | 204 | { |
30688e4e | 205 | writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); |
64e36824 | 206 | } |
207 | ||
208 | static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) | |
209 | { | |
210 | writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); | |
211 | } | |
212 | ||
213 | static inline void flush_fifo(struct rockchip_spi *rs) | |
214 | { | |
215 | while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) | |
216 | readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
217 | } | |
218 | ||
2df08e78 AK |
219 | static inline void wait_for_idle(struct rockchip_spi *rs) |
220 | { | |
221 | unsigned long timeout = jiffies + msecs_to_jiffies(5); | |
222 | ||
223 | do { | |
224 | if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) | |
225 | return; | |
64bc0110 | 226 | } while (!time_after(jiffies, timeout)); |
2df08e78 AK |
227 | |
228 | dev_warn(rs->dev, "spi controller is in busy state!\n"); | |
229 | } | |
230 | ||
64e36824 | 231 | static u32 get_fifo_len(struct rockchip_spi *rs) |
232 | { | |
233 | u32 fifo; | |
234 | ||
235 | for (fifo = 2; fifo < 32; fifo++) { | |
236 | writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
237 | if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) | |
238 | break; | |
239 | } | |
240 | ||
241 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
242 | ||
243 | return (fifo == 31) ? 0 : fifo; | |
244 | } | |
245 | ||
246 | static inline u32 tx_max(struct rockchip_spi *rs) | |
247 | { | |
248 | u32 tx_left, tx_room; | |
249 | ||
250 | tx_left = (rs->tx_end - rs->tx) / rs->n_bytes; | |
251 | tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); | |
252 | ||
253 | return min(tx_left, tx_room); | |
254 | } | |
255 | ||
256 | static inline u32 rx_max(struct rockchip_spi *rs) | |
257 | { | |
258 | u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes; | |
259 | u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); | |
260 | ||
261 | return min(rx_left, rx_room); | |
262 | } | |
263 | ||
264 | static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) | |
265 | { | |
b920cc31 HH |
266 | struct spi_master *master = spi->master; |
267 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
aa099382 | 268 | bool cs_asserted = !enable; |
b920cc31 | 269 | |
aa099382 JC |
270 | /* Return immediately for no-op */ |
271 | if (cs_asserted == rs->cs_asserted[spi->chip_select]) | |
272 | return; | |
64e36824 | 273 | |
aa099382 JC |
274 | if (cs_asserted) { |
275 | /* Keep things powered as long as CS is asserted */ | |
276 | pm_runtime_get_sync(rs->dev); | |
64e36824 | 277 | |
aa099382 JC |
278 | ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, |
279 | BIT(spi->chip_select)); | |
280 | } else { | |
281 | ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, | |
282 | BIT(spi->chip_select)); | |
64e36824 | 283 | |
aa099382 JC |
284 | /* Drop reference from when we first asserted CS */ |
285 | pm_runtime_put(rs->dev); | |
286 | } | |
b920cc31 | 287 | |
aa099382 | 288 | rs->cs_asserted[spi->chip_select] = cs_asserted; |
64e36824 | 289 | } |
290 | ||
291 | static int rockchip_spi_prepare_message(struct spi_master *master, | |
5dcc44ed | 292 | struct spi_message *msg) |
64e36824 | 293 | { |
294 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
295 | struct spi_device *spi = msg->spi; | |
296 | ||
64e36824 | 297 | rs->mode = spi->mode; |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
2291793c AS |
302 | static void rockchip_spi_handle_err(struct spi_master *master, |
303 | struct spi_message *msg) | |
64e36824 | 304 | { |
305 | unsigned long flags; | |
306 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
307 | ||
308 | spin_lock_irqsave(&rs->lock, flags); | |
309 | ||
5dcc44ed AK |
310 | /* |
311 | * For DMA mode, we need terminate DMA channel and flush | |
312 | * fifo for the next transfer if DMA thansfer timeout. | |
2291793c AS |
313 | * handle_err() was called by core if transfer failed. |
314 | * Maybe it is reasonable for error handling here. | |
5dcc44ed | 315 | */ |
64e36824 | 316 | if (rs->use_dma) { |
317 | if (rs->state & RXBUSY) { | |
557b7ea3 | 318 | dmaengine_terminate_async(rs->dma_rx.ch); |
64e36824 | 319 | flush_fifo(rs); |
320 | } | |
321 | ||
322 | if (rs->state & TXBUSY) | |
557b7ea3 | 323 | dmaengine_terminate_async(rs->dma_tx.ch); |
64e36824 | 324 | } |
325 | ||
326 | spin_unlock_irqrestore(&rs->lock, flags); | |
2291793c AS |
327 | } |
328 | ||
329 | static int rockchip_spi_unprepare_message(struct spi_master *master, | |
330 | struct spi_message *msg) | |
331 | { | |
332 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
64e36824 | 333 | |
30688e4e | 334 | spi_enable_chip(rs, false); |
c28be31b | 335 | |
64e36824 | 336 | return 0; |
337 | } | |
338 | ||
339 | static void rockchip_spi_pio_writer(struct rockchip_spi *rs) | |
340 | { | |
341 | u32 max = tx_max(rs); | |
342 | u32 txw = 0; | |
343 | ||
344 | while (max--) { | |
345 | if (rs->n_bytes == 1) | |
346 | txw = *(u8 *)(rs->tx); | |
347 | else | |
348 | txw = *(u16 *)(rs->tx); | |
349 | ||
350 | writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); | |
351 | rs->tx += rs->n_bytes; | |
352 | } | |
353 | } | |
354 | ||
355 | static void rockchip_spi_pio_reader(struct rockchip_spi *rs) | |
356 | { | |
357 | u32 max = rx_max(rs); | |
358 | u32 rxw; | |
359 | ||
360 | while (max--) { | |
361 | rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
362 | if (rs->n_bytes == 1) | |
363 | *(u8 *)(rs->rx) = (u8)rxw; | |
364 | else | |
365 | *(u16 *)(rs->rx) = (u16)rxw; | |
366 | rs->rx += rs->n_bytes; | |
5dcc44ed | 367 | } |
64e36824 | 368 | } |
369 | ||
370 | static int rockchip_spi_pio_transfer(struct rockchip_spi *rs) | |
371 | { | |
372 | int remain = 0; | |
373 | ||
30688e4e | 374 | spi_enable_chip(rs, true); |
a3c17402 | 375 | |
64e36824 | 376 | do { |
377 | if (rs->tx) { | |
378 | remain = rs->tx_end - rs->tx; | |
379 | rockchip_spi_pio_writer(rs); | |
380 | } | |
381 | ||
382 | if (rs->rx) { | |
383 | remain = rs->rx_end - rs->rx; | |
384 | rockchip_spi_pio_reader(rs); | |
385 | } | |
386 | ||
387 | cpu_relax(); | |
388 | } while (remain); | |
389 | ||
2df08e78 AK |
390 | /* If tx, wait until the FIFO data completely. */ |
391 | if (rs->tx) | |
392 | wait_for_idle(rs); | |
393 | ||
30688e4e | 394 | spi_enable_chip(rs, false); |
c28be31b | 395 | |
64e36824 | 396 | return 0; |
397 | } | |
398 | ||
399 | static void rockchip_spi_dma_rxcb(void *data) | |
400 | { | |
401 | unsigned long flags; | |
402 | struct rockchip_spi *rs = data; | |
403 | ||
404 | spin_lock_irqsave(&rs->lock, flags); | |
405 | ||
406 | rs->state &= ~RXBUSY; | |
c28be31b | 407 | if (!(rs->state & TXBUSY)) { |
30688e4e | 408 | spi_enable_chip(rs, false); |
64e36824 | 409 | spi_finalize_current_transfer(rs->master); |
c28be31b | 410 | } |
64e36824 | 411 | |
412 | spin_unlock_irqrestore(&rs->lock, flags); | |
413 | } | |
414 | ||
415 | static void rockchip_spi_dma_txcb(void *data) | |
416 | { | |
417 | unsigned long flags; | |
418 | struct rockchip_spi *rs = data; | |
419 | ||
2df08e78 AK |
420 | /* Wait until the FIFO data completely. */ |
421 | wait_for_idle(rs); | |
422 | ||
64e36824 | 423 | spin_lock_irqsave(&rs->lock, flags); |
424 | ||
425 | rs->state &= ~TXBUSY; | |
2c2bc748 | 426 | if (!(rs->state & RXBUSY)) { |
30688e4e | 427 | spi_enable_chip(rs, false); |
64e36824 | 428 | spi_finalize_current_transfer(rs->master); |
2c2bc748 | 429 | } |
64e36824 | 430 | |
431 | spin_unlock_irqrestore(&rs->lock, flags); | |
432 | } | |
433 | ||
ea984911 | 434 | static int rockchip_spi_prepare_dma(struct rockchip_spi *rs) |
64e36824 | 435 | { |
436 | unsigned long flags; | |
64e36824 | 437 | struct dma_async_tx_descriptor *rxdesc, *txdesc; |
438 | ||
439 | spin_lock_irqsave(&rs->lock, flags); | |
440 | rs->state &= ~RXBUSY; | |
441 | rs->state &= ~TXBUSY; | |
442 | spin_unlock_irqrestore(&rs->lock, flags); | |
443 | ||
97cf5669 | 444 | rxdesc = NULL; |
64e36824 | 445 | if (rs->rx) { |
31bcb57b ERB |
446 | struct dma_slave_config rxconf = { |
447 | .direction = DMA_DEV_TO_MEM, | |
448 | .src_addr = rs->dma_rx.addr, | |
449 | .src_addr_width = rs->n_bytes, | |
450 | .src_maxburst = 1, | |
451 | }; | |
452 | ||
64e36824 | 453 | dmaengine_slave_config(rs->dma_rx.ch, &rxconf); |
454 | ||
5dcc44ed AK |
455 | rxdesc = dmaengine_prep_slave_sg( |
456 | rs->dma_rx.ch, | |
64e36824 | 457 | rs->rx_sg.sgl, rs->rx_sg.nents, |
d9071b7e | 458 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); |
ea984911 SL |
459 | if (!rxdesc) |
460 | return -EINVAL; | |
64e36824 | 461 | |
462 | rxdesc->callback = rockchip_spi_dma_rxcb; | |
463 | rxdesc->callback_param = rs; | |
464 | } | |
465 | ||
97cf5669 | 466 | txdesc = NULL; |
64e36824 | 467 | if (rs->tx) { |
31bcb57b ERB |
468 | struct dma_slave_config txconf = { |
469 | .direction = DMA_MEM_TO_DEV, | |
470 | .dst_addr = rs->dma_tx.addr, | |
471 | .dst_addr_width = rs->n_bytes, | |
472 | .dst_maxburst = rs->fifo_len / 2, | |
473 | }; | |
474 | ||
64e36824 | 475 | dmaengine_slave_config(rs->dma_tx.ch, &txconf); |
476 | ||
5dcc44ed AK |
477 | txdesc = dmaengine_prep_slave_sg( |
478 | rs->dma_tx.ch, | |
64e36824 | 479 | rs->tx_sg.sgl, rs->tx_sg.nents, |
d9071b7e | 480 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); |
ea984911 SL |
481 | if (!txdesc) { |
482 | if (rxdesc) | |
483 | dmaengine_terminate_sync(rs->dma_rx.ch); | |
484 | return -EINVAL; | |
485 | } | |
64e36824 | 486 | |
487 | txdesc->callback = rockchip_spi_dma_txcb; | |
488 | txdesc->callback_param = rs; | |
489 | } | |
490 | ||
491 | /* rx must be started before tx due to spi instinct */ | |
97cf5669 | 492 | if (rxdesc) { |
64e36824 | 493 | spin_lock_irqsave(&rs->lock, flags); |
494 | rs->state |= RXBUSY; | |
495 | spin_unlock_irqrestore(&rs->lock, flags); | |
496 | dmaengine_submit(rxdesc); | |
497 | dma_async_issue_pending(rs->dma_rx.ch); | |
498 | } | |
499 | ||
30688e4e | 500 | spi_enable_chip(rs, true); |
a3c17402 | 501 | |
97cf5669 | 502 | if (txdesc) { |
64e36824 | 503 | spin_lock_irqsave(&rs->lock, flags); |
504 | rs->state |= TXBUSY; | |
505 | spin_unlock_irqrestore(&rs->lock, flags); | |
506 | dmaengine_submit(txdesc); | |
507 | dma_async_issue_pending(rs->dma_tx.ch); | |
508 | } | |
ea984911 | 509 | |
a3c17402 ERB |
510 | /* 1 means the transfer is in progress */ |
511 | return 1; | |
64e36824 | 512 | } |
513 | ||
514 | static void rockchip_spi_config(struct rockchip_spi *rs) | |
515 | { | |
516 | u32 div = 0; | |
517 | u32 dmacr = 0; | |
76b17e6e | 518 | int rsd = 0; |
64e36824 | 519 | |
2410d6a3 ERB |
520 | u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET |
521 | | CR0_BHT_8BIT << CR0_BHT_OFFSET | |
522 | | CR0_SSD_ONE << CR0_SSD_OFFSET | |
523 | | CR0_EM_BIG << CR0_EM_OFFSET; | |
64e36824 | 524 | |
525 | cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); | |
526 | cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); | |
527 | cr0 |= (rs->tmode << CR0_XFM_OFFSET); | |
64e36824 | 528 | |
529 | if (rs->use_dma) { | |
530 | if (rs->tx) | |
531 | dmacr |= TF_DMA_EN; | |
532 | if (rs->rx) | |
533 | dmacr |= RF_DMA_EN; | |
534 | } | |
535 | ||
f9cfd522 AK |
536 | if (WARN_ON(rs->speed > MAX_SCLK_OUT)) |
537 | rs->speed = MAX_SCLK_OUT; | |
538 | ||
bb51537a | 539 | /* the minimum divisor is 2 */ |
f9cfd522 AK |
540 | if (rs->max_freq < 2 * rs->speed) { |
541 | clk_set_rate(rs->spiclk, 2 * rs->speed); | |
542 | rs->max_freq = clk_get_rate(rs->spiclk); | |
543 | } | |
544 | ||
64e36824 | 545 | /* div doesn't support odd number */ |
754ec43c | 546 | div = DIV_ROUND_UP(rs->max_freq, rs->speed); |
64e36824 | 547 | div = (div + 1) & 0xfffe; |
548 | ||
76b17e6e JW |
549 | /* Rx sample delay is expressed in parent clock cycles (max 3) */ |
550 | rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8), | |
551 | 1000000000 >> 8); | |
552 | if (!rsd && rs->rsd_nsecs) { | |
553 | pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n", | |
554 | rs->max_freq, rs->rsd_nsecs); | |
555 | } else if (rsd > 3) { | |
556 | rsd = 3; | |
557 | pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n", | |
558 | rs->max_freq, rs->rsd_nsecs, | |
559 | rsd * 1000000000U / rs->max_freq); | |
560 | } | |
561 | cr0 |= rsd << CR0_RSD_OFFSET; | |
562 | ||
64e36824 | 563 | writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); |
564 | ||
04b37d2d HH |
565 | if (rs->n_bytes == 1) |
566 | writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); | |
567 | else if (rs->n_bytes == 2) | |
568 | writel_relaxed((rs->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); | |
569 | else | |
570 | writel_relaxed((rs->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); | |
571 | ||
64e36824 | 572 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); |
573 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); | |
574 | ||
dcfc861d | 575 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR); |
64e36824 | 576 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); |
577 | writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); | |
578 | ||
579 | spi_set_clk(rs, div); | |
580 | ||
5dcc44ed | 581 | dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div); |
64e36824 | 582 | } |
583 | ||
5185a81c BN |
584 | static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) |
585 | { | |
586 | return ROCKCHIP_SPI_MAX_TRANLEN; | |
587 | } | |
588 | ||
5dcc44ed AK |
589 | static int rockchip_spi_transfer_one( |
590 | struct spi_master *master, | |
64e36824 | 591 | struct spi_device *spi, |
592 | struct spi_transfer *xfer) | |
593 | { | |
64e36824 | 594 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
595 | ||
62946172 DA |
596 | WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && |
597 | (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); | |
64e36824 | 598 | |
599 | if (!xfer->tx_buf && !xfer->rx_buf) { | |
600 | dev_err(rs->dev, "No buffer for transfer\n"); | |
601 | return -EINVAL; | |
602 | } | |
603 | ||
5185a81c BN |
604 | if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { |
605 | dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); | |
606 | return -EINVAL; | |
607 | } | |
608 | ||
64e36824 | 609 | rs->speed = xfer->speed_hz; |
610 | rs->bpw = xfer->bits_per_word; | |
611 | rs->n_bytes = rs->bpw >> 3; | |
612 | ||
613 | rs->tx = xfer->tx_buf; | |
614 | rs->tx_end = rs->tx + xfer->len; | |
615 | rs->rx = xfer->rx_buf; | |
616 | rs->rx_end = rs->rx + xfer->len; | |
617 | rs->len = xfer->len; | |
618 | ||
619 | rs->tx_sg = xfer->tx_sg; | |
620 | rs->rx_sg = xfer->rx_sg; | |
621 | ||
64e36824 | 622 | if (rs->tx && rs->rx) |
623 | rs->tmode = CR0_XFM_TR; | |
624 | else if (rs->tx) | |
625 | rs->tmode = CR0_XFM_TO; | |
626 | else if (rs->rx) | |
627 | rs->tmode = CR0_XFM_RO; | |
628 | ||
a24e70c0 | 629 | /* we need prepare dma before spi was enabled */ |
c28be31b | 630 | if (master->can_dma && master->can_dma(master, spi, xfer)) |
f340b920 | 631 | rs->use_dma = true; |
c28be31b | 632 | else |
f340b920 | 633 | rs->use_dma = false; |
64e36824 | 634 | |
635 | rockchip_spi_config(rs); | |
636 | ||
a3c17402 ERB |
637 | if (rs->use_dma) |
638 | return rockchip_spi_prepare_dma(rs); | |
64e36824 | 639 | |
a3c17402 | 640 | return rockchip_spi_pio_transfer(rs); |
64e36824 | 641 | } |
642 | ||
643 | static bool rockchip_spi_can_dma(struct spi_master *master, | |
5dcc44ed AK |
644 | struct spi_device *spi, |
645 | struct spi_transfer *xfer) | |
64e36824 | 646 | { |
647 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
648 | ||
649 | return (xfer->len > rs->fifo_len); | |
650 | } | |
651 | ||
652 | static int rockchip_spi_probe(struct platform_device *pdev) | |
653 | { | |
43de979d | 654 | int ret; |
64e36824 | 655 | struct rockchip_spi *rs; |
656 | struct spi_master *master; | |
657 | struct resource *mem; | |
76b17e6e | 658 | u32 rsd_nsecs; |
64e36824 | 659 | |
660 | master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); | |
5dcc44ed | 661 | if (!master) |
64e36824 | 662 | return -ENOMEM; |
5dcc44ed | 663 | |
64e36824 | 664 | platform_set_drvdata(pdev, master); |
665 | ||
666 | rs = spi_master_get_devdata(master); | |
64e36824 | 667 | |
668 | /* Get basic io resource and map it */ | |
669 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
670 | rs->regs = devm_ioremap_resource(&pdev->dev, mem); | |
671 | if (IS_ERR(rs->regs)) { | |
64e36824 | 672 | ret = PTR_ERR(rs->regs); |
c351587e | 673 | goto err_put_master; |
64e36824 | 674 | } |
675 | ||
676 | rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
677 | if (IS_ERR(rs->apb_pclk)) { | |
678 | dev_err(&pdev->dev, "Failed to get apb_pclk\n"); | |
679 | ret = PTR_ERR(rs->apb_pclk); | |
c351587e | 680 | goto err_put_master; |
64e36824 | 681 | } |
682 | ||
683 | rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); | |
684 | if (IS_ERR(rs->spiclk)) { | |
685 | dev_err(&pdev->dev, "Failed to get spi_pclk\n"); | |
686 | ret = PTR_ERR(rs->spiclk); | |
c351587e | 687 | goto err_put_master; |
64e36824 | 688 | } |
689 | ||
690 | ret = clk_prepare_enable(rs->apb_pclk); | |
43de979d | 691 | if (ret < 0) { |
64e36824 | 692 | dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); |
c351587e | 693 | goto err_put_master; |
64e36824 | 694 | } |
695 | ||
696 | ret = clk_prepare_enable(rs->spiclk); | |
43de979d | 697 | if (ret < 0) { |
64e36824 | 698 | dev_err(&pdev->dev, "Failed to enable spi_clk\n"); |
c351587e | 699 | goto err_disable_apbclk; |
64e36824 | 700 | } |
701 | ||
30688e4e | 702 | spi_enable_chip(rs, false); |
64e36824 | 703 | |
64e36824 | 704 | rs->master = master; |
705 | rs->dev = &pdev->dev; | |
706 | rs->max_freq = clk_get_rate(rs->spiclk); | |
707 | ||
76b17e6e JW |
708 | if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", |
709 | &rsd_nsecs)) | |
710 | rs->rsd_nsecs = rsd_nsecs; | |
711 | ||
64e36824 | 712 | rs->fifo_len = get_fifo_len(rs); |
713 | if (!rs->fifo_len) { | |
714 | dev_err(&pdev->dev, "Failed to get fifo length\n"); | |
db7e8d90 | 715 | ret = -EINVAL; |
c351587e | 716 | goto err_disable_spiclk; |
64e36824 | 717 | } |
718 | ||
719 | spin_lock_init(&rs->lock); | |
720 | ||
721 | pm_runtime_set_active(&pdev->dev); | |
722 | pm_runtime_enable(&pdev->dev); | |
723 | ||
724 | master->auto_runtime_pm = true; | |
725 | master->bus_num = pdev->id; | |
ee780997 | 726 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
aa099382 | 727 | master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM; |
64e36824 | 728 | master->dev.of_node = pdev->dev.of_node; |
729 | master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); | |
730 | ||
731 | master->set_cs = rockchip_spi_set_cs; | |
732 | master->prepare_message = rockchip_spi_prepare_message; | |
733 | master->unprepare_message = rockchip_spi_unprepare_message; | |
734 | master->transfer_one = rockchip_spi_transfer_one; | |
5185a81c | 735 | master->max_transfer_size = rockchip_spi_max_transfer_size; |
2291793c | 736 | master->handle_err = rockchip_spi_handle_err; |
c863795c | 737 | master->flags = SPI_MASTER_GPIO_SS; |
64e36824 | 738 | |
e4c0e06f SL |
739 | rs->dma_tx.ch = dma_request_chan(rs->dev, "tx"); |
740 | if (IS_ERR(rs->dma_tx.ch)) { | |
61cadcf4 SL |
741 | /* Check tx to see if we need defer probing driver */ |
742 | if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) { | |
743 | ret = -EPROBE_DEFER; | |
c351587e | 744 | goto err_disable_pm_runtime; |
61cadcf4 | 745 | } |
64e36824 | 746 | dev_warn(rs->dev, "Failed to request TX DMA channel\n"); |
e4c0e06f | 747 | rs->dma_tx.ch = NULL; |
61cadcf4 | 748 | } |
64e36824 | 749 | |
e4c0e06f SL |
750 | rs->dma_rx.ch = dma_request_chan(rs->dev, "rx"); |
751 | if (IS_ERR(rs->dma_rx.ch)) { | |
752 | if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) { | |
e4c0e06f | 753 | ret = -EPROBE_DEFER; |
5de7ed0c | 754 | goto err_free_dma_tx; |
64e36824 | 755 | } |
756 | dev_warn(rs->dev, "Failed to request RX DMA channel\n"); | |
e4c0e06f | 757 | rs->dma_rx.ch = NULL; |
64e36824 | 758 | } |
759 | ||
760 | if (rs->dma_tx.ch && rs->dma_rx.ch) { | |
761 | rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); | |
762 | rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); | |
64e36824 | 763 | |
764 | master->can_dma = rockchip_spi_can_dma; | |
765 | master->dma_tx = rs->dma_tx.ch; | |
766 | master->dma_rx = rs->dma_rx.ch; | |
767 | } | |
768 | ||
769 | ret = devm_spi_register_master(&pdev->dev, master); | |
43de979d | 770 | if (ret < 0) { |
64e36824 | 771 | dev_err(&pdev->dev, "Failed to register master\n"); |
c351587e | 772 | goto err_free_dma_rx; |
64e36824 | 773 | } |
774 | ||
64e36824 | 775 | return 0; |
776 | ||
c351587e | 777 | err_free_dma_rx: |
64e36824 | 778 | if (rs->dma_rx.ch) |
779 | dma_release_channel(rs->dma_rx.ch); | |
5de7ed0c DC |
780 | err_free_dma_tx: |
781 | if (rs->dma_tx.ch) | |
782 | dma_release_channel(rs->dma_tx.ch); | |
c351587e JC |
783 | err_disable_pm_runtime: |
784 | pm_runtime_disable(&pdev->dev); | |
785 | err_disable_spiclk: | |
64e36824 | 786 | clk_disable_unprepare(rs->spiclk); |
c351587e | 787 | err_disable_apbclk: |
64e36824 | 788 | clk_disable_unprepare(rs->apb_pclk); |
c351587e | 789 | err_put_master: |
64e36824 | 790 | spi_master_put(master); |
791 | ||
792 | return ret; | |
793 | } | |
794 | ||
795 | static int rockchip_spi_remove(struct platform_device *pdev) | |
796 | { | |
797 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
798 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
799 | ||
6a06e895 | 800 | pm_runtime_get_sync(&pdev->dev); |
64e36824 | 801 | |
802 | clk_disable_unprepare(rs->spiclk); | |
803 | clk_disable_unprepare(rs->apb_pclk); | |
804 | ||
6a06e895 JC |
805 | pm_runtime_put_noidle(&pdev->dev); |
806 | pm_runtime_disable(&pdev->dev); | |
807 | pm_runtime_set_suspended(&pdev->dev); | |
808 | ||
64e36824 | 809 | if (rs->dma_tx.ch) |
810 | dma_release_channel(rs->dma_tx.ch); | |
811 | if (rs->dma_rx.ch) | |
812 | dma_release_channel(rs->dma_rx.ch); | |
813 | ||
844c9f47 SL |
814 | spi_master_put(master); |
815 | ||
64e36824 | 816 | return 0; |
817 | } | |
818 | ||
819 | #ifdef CONFIG_PM_SLEEP | |
820 | static int rockchip_spi_suspend(struct device *dev) | |
821 | { | |
43de979d | 822 | int ret; |
64e36824 | 823 | struct spi_master *master = dev_get_drvdata(dev); |
824 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
825 | ||
826 | ret = spi_master_suspend(rs->master); | |
43de979d | 827 | if (ret < 0) |
64e36824 | 828 | return ret; |
829 | ||
d38c4ae1 JC |
830 | ret = pm_runtime_force_suspend(dev); |
831 | if (ret < 0) | |
832 | return ret; | |
64e36824 | 833 | |
23e291c2 BN |
834 | pinctrl_pm_select_sleep_state(dev); |
835 | ||
43de979d | 836 | return 0; |
64e36824 | 837 | } |
838 | ||
839 | static int rockchip_spi_resume(struct device *dev) | |
840 | { | |
43de979d | 841 | int ret; |
64e36824 | 842 | struct spi_master *master = dev_get_drvdata(dev); |
843 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
844 | ||
23e291c2 BN |
845 | pinctrl_pm_select_default_state(dev); |
846 | ||
d38c4ae1 JC |
847 | ret = pm_runtime_force_resume(dev); |
848 | if (ret < 0) | |
849 | return ret; | |
64e36824 | 850 | |
851 | ret = spi_master_resume(rs->master); | |
852 | if (ret < 0) { | |
853 | clk_disable_unprepare(rs->spiclk); | |
854 | clk_disable_unprepare(rs->apb_pclk); | |
855 | } | |
856 | ||
43de979d | 857 | return 0; |
64e36824 | 858 | } |
859 | #endif /* CONFIG_PM_SLEEP */ | |
860 | ||
ec833050 | 861 | #ifdef CONFIG_PM |
64e36824 | 862 | static int rockchip_spi_runtime_suspend(struct device *dev) |
863 | { | |
864 | struct spi_master *master = dev_get_drvdata(dev); | |
865 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
866 | ||
867 | clk_disable_unprepare(rs->spiclk); | |
868 | clk_disable_unprepare(rs->apb_pclk); | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | static int rockchip_spi_runtime_resume(struct device *dev) | |
874 | { | |
875 | int ret; | |
876 | struct spi_master *master = dev_get_drvdata(dev); | |
877 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
878 | ||
879 | ret = clk_prepare_enable(rs->apb_pclk); | |
43de979d | 880 | if (ret < 0) |
64e36824 | 881 | return ret; |
882 | ||
883 | ret = clk_prepare_enable(rs->spiclk); | |
43de979d | 884 | if (ret < 0) |
64e36824 | 885 | clk_disable_unprepare(rs->apb_pclk); |
886 | ||
43de979d | 887 | return 0; |
64e36824 | 888 | } |
ec833050 | 889 | #endif /* CONFIG_PM */ |
64e36824 | 890 | |
891 | static const struct dev_pm_ops rockchip_spi_pm = { | |
892 | SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) | |
893 | SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, | |
894 | rockchip_spi_runtime_resume, NULL) | |
895 | }; | |
896 | ||
897 | static const struct of_device_id rockchip_spi_dt_match[] = { | |
6b860e69 | 898 | { .compatible = "rockchip,rv1108-spi", }, |
aa29ea3d | 899 | { .compatible = "rockchip,rk3036-spi", }, |
64e36824 | 900 | { .compatible = "rockchip,rk3066-spi", }, |
b839b785 | 901 | { .compatible = "rockchip,rk3188-spi", }, |
aa29ea3d | 902 | { .compatible = "rockchip,rk3228-spi", }, |
b839b785 | 903 | { .compatible = "rockchip,rk3288-spi", }, |
aa29ea3d | 904 | { .compatible = "rockchip,rk3368-spi", }, |
9b7a5622 | 905 | { .compatible = "rockchip,rk3399-spi", }, |
64e36824 | 906 | { }, |
907 | }; | |
908 | MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); | |
909 | ||
910 | static struct platform_driver rockchip_spi_driver = { | |
911 | .driver = { | |
912 | .name = DRIVER_NAME, | |
64e36824 | 913 | .pm = &rockchip_spi_pm, |
914 | .of_match_table = of_match_ptr(rockchip_spi_dt_match), | |
915 | }, | |
916 | .probe = rockchip_spi_probe, | |
917 | .remove = rockchip_spi_remove, | |
918 | }; | |
919 | ||
920 | module_platform_driver(rockchip_spi_driver); | |
921 | ||
5dcc44ed | 922 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); |
64e36824 | 923 | MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); |
924 | MODULE_LICENSE("GPL v2"); |