]>
Commit | Line | Data |
---|---|---|
64e36824 | 1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
5dcc44ed | 3 | * Author: Addy Ke <addy.ke@rock-chips.com> |
64e36824 | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | */ | |
15 | ||
64e36824 | 16 | #include <linux/clk.h> |
ec5c5d8a SL |
17 | #include <linux/dmaengine.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
23e291c2 | 20 | #include <linux/pinctrl/consumer.h> |
64e36824 | 21 | #include <linux/platform_device.h> |
64e36824 | 22 | #include <linux/spi/spi.h> |
64e36824 | 23 | #include <linux/pm_runtime.h> |
ec5c5d8a | 24 | #include <linux/scatterlist.h> |
64e36824 | 25 | |
26 | #define DRIVER_NAME "rockchip-spi" | |
27 | ||
aa099382 JC |
28 | #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ |
29 | writel_relaxed(readl_relaxed(reg) & ~(bits), reg) | |
30 | #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ | |
31 | writel_relaxed(readl_relaxed(reg) | (bits), reg) | |
32 | ||
64e36824 | 33 | /* SPI register offsets */ |
34 | #define ROCKCHIP_SPI_CTRLR0 0x0000 | |
35 | #define ROCKCHIP_SPI_CTRLR1 0x0004 | |
36 | #define ROCKCHIP_SPI_SSIENR 0x0008 | |
37 | #define ROCKCHIP_SPI_SER 0x000c | |
38 | #define ROCKCHIP_SPI_BAUDR 0x0010 | |
39 | #define ROCKCHIP_SPI_TXFTLR 0x0014 | |
40 | #define ROCKCHIP_SPI_RXFTLR 0x0018 | |
41 | #define ROCKCHIP_SPI_TXFLR 0x001c | |
42 | #define ROCKCHIP_SPI_RXFLR 0x0020 | |
43 | #define ROCKCHIP_SPI_SR 0x0024 | |
44 | #define ROCKCHIP_SPI_IPR 0x0028 | |
45 | #define ROCKCHIP_SPI_IMR 0x002c | |
46 | #define ROCKCHIP_SPI_ISR 0x0030 | |
47 | #define ROCKCHIP_SPI_RISR 0x0034 | |
48 | #define ROCKCHIP_SPI_ICR 0x0038 | |
49 | #define ROCKCHIP_SPI_DMACR 0x003c | |
50 | #define ROCKCHIP_SPI_DMATDLR 0x0040 | |
51 | #define ROCKCHIP_SPI_DMARDLR 0x0044 | |
52 | #define ROCKCHIP_SPI_TXDR 0x0400 | |
53 | #define ROCKCHIP_SPI_RXDR 0x0800 | |
54 | ||
55 | /* Bit fields in CTRLR0 */ | |
56 | #define CR0_DFS_OFFSET 0 | |
65498c6a ERB |
57 | #define CR0_DFS_4BIT 0x0 |
58 | #define CR0_DFS_8BIT 0x1 | |
59 | #define CR0_DFS_16BIT 0x2 | |
64e36824 | 60 | |
61 | #define CR0_CFS_OFFSET 2 | |
62 | ||
63 | #define CR0_SCPH_OFFSET 6 | |
64 | ||
65 | #define CR0_SCPOL_OFFSET 7 | |
66 | ||
67 | #define CR0_CSM_OFFSET 8 | |
68 | #define CR0_CSM_KEEP 0x0 | |
69 | /* ss_n be high for half sclk_out cycles */ | |
70 | #define CR0_CSM_HALF 0X1 | |
71 | /* ss_n be high for one sclk_out cycle */ | |
72 | #define CR0_CSM_ONE 0x2 | |
73 | ||
74 | /* ss_n to sclk_out delay */ | |
75 | #define CR0_SSD_OFFSET 10 | |
76 | /* | |
77 | * The period between ss_n active and | |
78 | * sclk_out active is half sclk_out cycles | |
79 | */ | |
80 | #define CR0_SSD_HALF 0x0 | |
81 | /* | |
82 | * The period between ss_n active and | |
83 | * sclk_out active is one sclk_out cycle | |
84 | */ | |
85 | #define CR0_SSD_ONE 0x1 | |
86 | ||
87 | #define CR0_EM_OFFSET 11 | |
88 | #define CR0_EM_LITTLE 0x0 | |
89 | #define CR0_EM_BIG 0x1 | |
90 | ||
91 | #define CR0_FBM_OFFSET 12 | |
92 | #define CR0_FBM_MSB 0x0 | |
93 | #define CR0_FBM_LSB 0x1 | |
94 | ||
95 | #define CR0_BHT_OFFSET 13 | |
96 | #define CR0_BHT_16BIT 0x0 | |
97 | #define CR0_BHT_8BIT 0x1 | |
98 | ||
99 | #define CR0_RSD_OFFSET 14 | |
74b7efa8 | 100 | #define CR0_RSD_MAX 0x3 |
64e36824 | 101 | |
102 | #define CR0_FRF_OFFSET 16 | |
103 | #define CR0_FRF_SPI 0x0 | |
104 | #define CR0_FRF_SSP 0x1 | |
105 | #define CR0_FRF_MICROWIRE 0x2 | |
106 | ||
107 | #define CR0_XFM_OFFSET 18 | |
108 | #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) | |
109 | #define CR0_XFM_TR 0x0 | |
110 | #define CR0_XFM_TO 0x1 | |
111 | #define CR0_XFM_RO 0x2 | |
112 | ||
113 | #define CR0_OPM_OFFSET 20 | |
114 | #define CR0_OPM_MASTER 0x0 | |
115 | #define CR0_OPM_SLAVE 0x1 | |
116 | ||
117 | #define CR0_MTM_OFFSET 0x21 | |
118 | ||
119 | /* Bit fields in SER, 2bit */ | |
120 | #define SER_MASK 0x3 | |
121 | ||
420b82f8 ERB |
122 | /* Bit fields in BAUDR */ |
123 | #define BAUDR_SCKDV_MIN 2 | |
124 | #define BAUDR_SCKDV_MAX 65534 | |
125 | ||
64e36824 | 126 | /* Bit fields in SR, 5bit */ |
127 | #define SR_MASK 0x1f | |
128 | #define SR_BUSY (1 << 0) | |
129 | #define SR_TF_FULL (1 << 1) | |
130 | #define SR_TF_EMPTY (1 << 2) | |
131 | #define SR_RF_EMPTY (1 << 3) | |
132 | #define SR_RF_FULL (1 << 4) | |
133 | ||
134 | /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ | |
135 | #define INT_MASK 0x1f | |
136 | #define INT_TF_EMPTY (1 << 0) | |
137 | #define INT_TF_OVERFLOW (1 << 1) | |
138 | #define INT_RF_UNDERFLOW (1 << 2) | |
139 | #define INT_RF_OVERFLOW (1 << 3) | |
140 | #define INT_RF_FULL (1 << 4) | |
141 | ||
142 | /* Bit fields in ICR, 4bit */ | |
143 | #define ICR_MASK 0x0f | |
144 | #define ICR_ALL (1 << 0) | |
145 | #define ICR_RF_UNDERFLOW (1 << 1) | |
146 | #define ICR_RF_OVERFLOW (1 << 2) | |
147 | #define ICR_TF_OVERFLOW (1 << 3) | |
148 | ||
149 | /* Bit fields in DMACR */ | |
150 | #define RF_DMA_EN (1 << 0) | |
151 | #define TF_DMA_EN (1 << 1) | |
152 | ||
fab3e487 ERB |
153 | /* Driver state flags */ |
154 | #define RXDMA (1 << 0) | |
155 | #define TXDMA (1 << 1) | |
64e36824 | 156 | |
f9cfd522 | 157 | /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ |
420b82f8 | 158 | #define MAX_SCLK_OUT 50000000U |
f9cfd522 | 159 | |
5185a81c BN |
160 | /* |
161 | * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, | |
162 | * the controller seems to hang when given 0x10000, so stick with this for now. | |
163 | */ | |
164 | #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff | |
165 | ||
aa099382 JC |
166 | #define ROCKCHIP_SPI_MAX_CS_NUM 2 |
167 | ||
64e36824 | 168 | struct rockchip_spi { |
169 | struct device *dev; | |
64e36824 | 170 | |
171 | struct clk *spiclk; | |
172 | struct clk *apb_pclk; | |
173 | ||
174 | void __iomem *regs; | |
eee06a9e ERB |
175 | dma_addr_t dma_addr_rx; |
176 | dma_addr_t dma_addr_tx; | |
fab3e487 | 177 | |
01b59ce5 ERB |
178 | const void *tx; |
179 | void *rx; | |
180 | unsigned int tx_left; | |
181 | unsigned int rx_left; | |
182 | ||
fab3e487 ERB |
183 | atomic_t state; |
184 | ||
64e36824 | 185 | /*depth of the FIFO buffer */ |
186 | u32 fifo_len; | |
420b82f8 ERB |
187 | /* frequency of spiclk */ |
188 | u32 freq; | |
64e36824 | 189 | |
64e36824 | 190 | u8 n_bytes; |
74b7efa8 | 191 | u8 rsd; |
64e36824 | 192 | |
aa099382 | 193 | bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; |
64e36824 | 194 | }; |
195 | ||
30688e4e | 196 | static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) |
64e36824 | 197 | { |
30688e4e | 198 | writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); |
64e36824 | 199 | } |
200 | ||
2df08e78 AK |
201 | static inline void wait_for_idle(struct rockchip_spi *rs) |
202 | { | |
203 | unsigned long timeout = jiffies + msecs_to_jiffies(5); | |
204 | ||
205 | do { | |
206 | if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) | |
207 | return; | |
64bc0110 | 208 | } while (!time_after(jiffies, timeout)); |
2df08e78 AK |
209 | |
210 | dev_warn(rs->dev, "spi controller is in busy state!\n"); | |
211 | } | |
212 | ||
64e36824 | 213 | static u32 get_fifo_len(struct rockchip_spi *rs) |
214 | { | |
215 | u32 fifo; | |
216 | ||
217 | for (fifo = 2; fifo < 32; fifo++) { | |
218 | writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
219 | if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) | |
220 | break; | |
221 | } | |
222 | ||
223 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
224 | ||
225 | return (fifo == 31) ? 0 : fifo; | |
226 | } | |
227 | ||
64e36824 | 228 | static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) |
229 | { | |
b920cc31 HH |
230 | struct spi_master *master = spi->master; |
231 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
aa099382 | 232 | bool cs_asserted = !enable; |
b920cc31 | 233 | |
aa099382 JC |
234 | /* Return immediately for no-op */ |
235 | if (cs_asserted == rs->cs_asserted[spi->chip_select]) | |
236 | return; | |
64e36824 | 237 | |
aa099382 JC |
238 | if (cs_asserted) { |
239 | /* Keep things powered as long as CS is asserted */ | |
240 | pm_runtime_get_sync(rs->dev); | |
64e36824 | 241 | |
aa099382 JC |
242 | ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, |
243 | BIT(spi->chip_select)); | |
244 | } else { | |
245 | ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, | |
246 | BIT(spi->chip_select)); | |
64e36824 | 247 | |
aa099382 JC |
248 | /* Drop reference from when we first asserted CS */ |
249 | pm_runtime_put(rs->dev); | |
250 | } | |
b920cc31 | 251 | |
aa099382 | 252 | rs->cs_asserted[spi->chip_select] = cs_asserted; |
64e36824 | 253 | } |
254 | ||
2291793c AS |
255 | static void rockchip_spi_handle_err(struct spi_master *master, |
256 | struct spi_message *msg) | |
64e36824 | 257 | { |
64e36824 | 258 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
259 | ||
ce386100 ERB |
260 | /* stop running spi transfer |
261 | * this also flushes both rx and tx fifos | |
5dcc44ed | 262 | */ |
ce386100 ERB |
263 | spi_enable_chip(rs, false); |
264 | ||
01b59ce5 ERB |
265 | /* make sure all interrupts are masked */ |
266 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); | |
267 | ||
fab3e487 | 268 | if (atomic_read(&rs->state) & TXDMA) |
eee06a9e | 269 | dmaengine_terminate_async(master->dma_tx); |
64e36824 | 270 | |
ce386100 | 271 | if (atomic_read(&rs->state) & RXDMA) |
eee06a9e | 272 | dmaengine_terminate_async(master->dma_rx); |
64e36824 | 273 | } |
274 | ||
275 | static void rockchip_spi_pio_writer(struct rockchip_spi *rs) | |
276 | { | |
01b59ce5 ERB |
277 | u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); |
278 | u32 words = min(rs->tx_left, tx_free); | |
279 | ||
280 | rs->tx_left -= words; | |
281 | for (; words; words--) { | |
282 | u32 txw; | |
64e36824 | 283 | |
64e36824 | 284 | if (rs->n_bytes == 1) |
01b59ce5 | 285 | txw = *(u8 *)rs->tx; |
64e36824 | 286 | else |
01b59ce5 | 287 | txw = *(u16 *)rs->tx; |
64e36824 | 288 | |
289 | writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); | |
290 | rs->tx += rs->n_bytes; | |
291 | } | |
292 | } | |
293 | ||
294 | static void rockchip_spi_pio_reader(struct rockchip_spi *rs) | |
295 | { | |
01b59ce5 ERB |
296 | u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); |
297 | u32 rx_left = rs->rx_left - words; | |
298 | ||
299 | /* the hardware doesn't allow us to change fifo threshold | |
300 | * level while spi is enabled, so instead make sure to leave | |
301 | * enough words in the rx fifo to get the last interrupt | |
302 | * exactly when all words have been received | |
303 | */ | |
304 | if (rx_left) { | |
305 | u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1; | |
306 | ||
307 | if (rx_left < ftl) { | |
308 | rx_left = ftl; | |
309 | words = rs->rx_left - rx_left; | |
310 | } | |
311 | } | |
312 | ||
313 | rs->rx_left = rx_left; | |
314 | for (; words; words--) { | |
315 | u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
316 | ||
317 | if (!rs->rx) | |
318 | continue; | |
64e36824 | 319 | |
64e36824 | 320 | if (rs->n_bytes == 1) |
01b59ce5 | 321 | *(u8 *)rs->rx = (u8)rxw; |
64e36824 | 322 | else |
01b59ce5 | 323 | *(u16 *)rs->rx = (u16)rxw; |
64e36824 | 324 | rs->rx += rs->n_bytes; |
5dcc44ed | 325 | } |
64e36824 | 326 | } |
327 | ||
01b59ce5 | 328 | static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) |
64e36824 | 329 | { |
01b59ce5 ERB |
330 | struct spi_master *master = dev_id; |
331 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
64e36824 | 332 | |
01b59ce5 ERB |
333 | if (rs->tx_left) |
334 | rockchip_spi_pio_writer(rs); | |
a3c17402 | 335 | |
01b59ce5 ERB |
336 | rockchip_spi_pio_reader(rs); |
337 | if (!rs->rx_left) { | |
338 | spi_enable_chip(rs, false); | |
339 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); | |
340 | spi_finalize_current_transfer(master); | |
341 | } | |
64e36824 | 342 | |
01b59ce5 ERB |
343 | return IRQ_HANDLED; |
344 | } | |
64e36824 | 345 | |
01b59ce5 ERB |
346 | static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, |
347 | struct spi_transfer *xfer) | |
348 | { | |
349 | rs->tx = xfer->tx_buf; | |
350 | rs->rx = xfer->rx_buf; | |
351 | rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0; | |
352 | rs->rx_left = xfer->len / rs->n_bytes; | |
64e36824 | 353 | |
01b59ce5 ERB |
354 | writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR); |
355 | spi_enable_chip(rs, true); | |
2df08e78 | 356 | |
01b59ce5 ERB |
357 | if (rs->tx_left) |
358 | rockchip_spi_pio_writer(rs); | |
c28be31b | 359 | |
01b59ce5 ERB |
360 | /* 1 means the transfer is in progress */ |
361 | return 1; | |
64e36824 | 362 | } |
363 | ||
364 | static void rockchip_spi_dma_rxcb(void *data) | |
365 | { | |
d790c342 ERB |
366 | struct spi_master *master = data; |
367 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
fab3e487 | 368 | int state = atomic_fetch_andnot(RXDMA, &rs->state); |
64e36824 | 369 | |
fab3e487 ERB |
370 | if (state & TXDMA) |
371 | return; | |
64e36824 | 372 | |
fab3e487 | 373 | spi_enable_chip(rs, false); |
d790c342 | 374 | spi_finalize_current_transfer(master); |
64e36824 | 375 | } |
376 | ||
377 | static void rockchip_spi_dma_txcb(void *data) | |
378 | { | |
d790c342 ERB |
379 | struct spi_master *master = data; |
380 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
fab3e487 ERB |
381 | int state = atomic_fetch_andnot(TXDMA, &rs->state); |
382 | ||
383 | if (state & RXDMA) | |
384 | return; | |
64e36824 | 385 | |
2df08e78 AK |
386 | /* Wait until the FIFO data completely. */ |
387 | wait_for_idle(rs); | |
388 | ||
fab3e487 | 389 | spi_enable_chip(rs, false); |
d790c342 | 390 | spi_finalize_current_transfer(master); |
64e36824 | 391 | } |
392 | ||
fc1ad8ee | 393 | static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, |
eee06a9e | 394 | struct spi_master *master, struct spi_transfer *xfer) |
64e36824 | 395 | { |
64e36824 | 396 | struct dma_async_tx_descriptor *rxdesc, *txdesc; |
397 | ||
fab3e487 | 398 | atomic_set(&rs->state, 0); |
64e36824 | 399 | |
97cf5669 | 400 | rxdesc = NULL; |
fc1ad8ee | 401 | if (xfer->rx_buf) { |
31bcb57b ERB |
402 | struct dma_slave_config rxconf = { |
403 | .direction = DMA_DEV_TO_MEM, | |
eee06a9e | 404 | .src_addr = rs->dma_addr_rx, |
31bcb57b ERB |
405 | .src_addr_width = rs->n_bytes, |
406 | .src_maxburst = 1, | |
407 | }; | |
408 | ||
eee06a9e | 409 | dmaengine_slave_config(master->dma_rx, &rxconf); |
64e36824 | 410 | |
5dcc44ed | 411 | rxdesc = dmaengine_prep_slave_sg( |
eee06a9e | 412 | master->dma_rx, |
fc1ad8ee | 413 | xfer->rx_sg.sgl, xfer->rx_sg.nents, |
d9071b7e | 414 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); |
ea984911 SL |
415 | if (!rxdesc) |
416 | return -EINVAL; | |
64e36824 | 417 | |
418 | rxdesc->callback = rockchip_spi_dma_rxcb; | |
d790c342 | 419 | rxdesc->callback_param = master; |
64e36824 | 420 | } |
421 | ||
97cf5669 | 422 | txdesc = NULL; |
fc1ad8ee | 423 | if (xfer->tx_buf) { |
31bcb57b ERB |
424 | struct dma_slave_config txconf = { |
425 | .direction = DMA_MEM_TO_DEV, | |
eee06a9e | 426 | .dst_addr = rs->dma_addr_tx, |
31bcb57b ERB |
427 | .dst_addr_width = rs->n_bytes, |
428 | .dst_maxburst = rs->fifo_len / 2, | |
429 | }; | |
430 | ||
eee06a9e | 431 | dmaengine_slave_config(master->dma_tx, &txconf); |
64e36824 | 432 | |
5dcc44ed | 433 | txdesc = dmaengine_prep_slave_sg( |
eee06a9e | 434 | master->dma_tx, |
fc1ad8ee | 435 | xfer->tx_sg.sgl, xfer->tx_sg.nents, |
d9071b7e | 436 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); |
ea984911 SL |
437 | if (!txdesc) { |
438 | if (rxdesc) | |
eee06a9e | 439 | dmaengine_terminate_sync(master->dma_rx); |
ea984911 SL |
440 | return -EINVAL; |
441 | } | |
64e36824 | 442 | |
443 | txdesc->callback = rockchip_spi_dma_txcb; | |
d790c342 | 444 | txdesc->callback_param = master; |
64e36824 | 445 | } |
446 | ||
447 | /* rx must be started before tx due to spi instinct */ | |
97cf5669 | 448 | if (rxdesc) { |
fab3e487 | 449 | atomic_or(RXDMA, &rs->state); |
64e36824 | 450 | dmaengine_submit(rxdesc); |
eee06a9e | 451 | dma_async_issue_pending(master->dma_rx); |
64e36824 | 452 | } |
453 | ||
30688e4e | 454 | spi_enable_chip(rs, true); |
a3c17402 | 455 | |
97cf5669 | 456 | if (txdesc) { |
fab3e487 | 457 | atomic_or(TXDMA, &rs->state); |
64e36824 | 458 | dmaengine_submit(txdesc); |
eee06a9e | 459 | dma_async_issue_pending(master->dma_tx); |
64e36824 | 460 | } |
ea984911 | 461 | |
a3c17402 ERB |
462 | /* 1 means the transfer is in progress */ |
463 | return 1; | |
64e36824 | 464 | } |
465 | ||
fc1ad8ee | 466 | static void rockchip_spi_config(struct rockchip_spi *rs, |
eff0275e ERB |
467 | struct spi_device *spi, struct spi_transfer *xfer, |
468 | bool use_dma) | |
64e36824 | 469 | { |
2410d6a3 ERB |
470 | u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET |
471 | | CR0_BHT_8BIT << CR0_BHT_OFFSET | |
472 | | CR0_SSD_ONE << CR0_SSD_OFFSET | |
473 | | CR0_EM_BIG << CR0_EM_OFFSET; | |
65498c6a ERB |
474 | u32 cr1; |
475 | u32 dmacr = 0; | |
64e36824 | 476 | |
74b7efa8 | 477 | cr0 |= rs->rsd << CR0_RSD_OFFSET; |
fc1ad8ee | 478 | cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; |
04290192 ERB |
479 | if (spi->mode & SPI_LSB_FIRST) |
480 | cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; | |
fc1ad8ee ERB |
481 | |
482 | if (xfer->rx_buf && xfer->tx_buf) | |
483 | cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; | |
484 | else if (xfer->rx_buf) | |
485 | cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; | |
01b59ce5 | 486 | else if (use_dma) |
fc1ad8ee | 487 | cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; |
64e36824 | 488 | |
65498c6a ERB |
489 | switch (xfer->bits_per_word) { |
490 | case 4: | |
491 | cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; | |
492 | cr1 = xfer->len - 1; | |
493 | break; | |
494 | case 8: | |
495 | cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; | |
496 | cr1 = xfer->len - 1; | |
497 | break; | |
498 | case 16: | |
499 | cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; | |
500 | cr1 = xfer->len / 2 - 1; | |
501 | break; | |
502 | default: | |
503 | /* we only whitelist 4, 8 and 16 bit words in | |
504 | * master->bits_per_word_mask, so this shouldn't | |
505 | * happen | |
506 | */ | |
507 | unreachable(); | |
508 | } | |
509 | ||
eff0275e | 510 | if (use_dma) { |
fc1ad8ee | 511 | if (xfer->tx_buf) |
64e36824 | 512 | dmacr |= TF_DMA_EN; |
fc1ad8ee | 513 | if (xfer->rx_buf) |
64e36824 | 514 | dmacr |= RF_DMA_EN; |
515 | } | |
516 | ||
64e36824 | 517 | writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); |
65498c6a | 518 | writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); |
04b37d2d | 519 | |
01b59ce5 ERB |
520 | /* unfortunately setting the fifo threshold level to generate an |
521 | * interrupt exactly when the fifo is full doesn't seem to work, | |
522 | * so we need the strict inequality here | |
523 | */ | |
524 | if (xfer->len < rs->fifo_len) | |
525 | writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); | |
526 | else | |
527 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); | |
64e36824 | 528 | |
dcfc861d | 529 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR); |
64e36824 | 530 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); |
531 | writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); | |
532 | ||
420b82f8 ERB |
533 | /* the hardware only supports an even clock divisor, so |
534 | * round divisor = spiclk / speed up to nearest even number | |
535 | * so that the resulting speed is <= the requested speed | |
536 | */ | |
537 | writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), | |
538 | rs->regs + ROCKCHIP_SPI_BAUDR); | |
64e36824 | 539 | } |
540 | ||
5185a81c BN |
541 | static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) |
542 | { | |
543 | return ROCKCHIP_SPI_MAX_TRANLEN; | |
544 | } | |
545 | ||
5dcc44ed AK |
546 | static int rockchip_spi_transfer_one( |
547 | struct spi_master *master, | |
64e36824 | 548 | struct spi_device *spi, |
549 | struct spi_transfer *xfer) | |
550 | { | |
64e36824 | 551 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
eff0275e | 552 | bool use_dma; |
64e36824 | 553 | |
62946172 DA |
554 | WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && |
555 | (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); | |
64e36824 | 556 | |
557 | if (!xfer->tx_buf && !xfer->rx_buf) { | |
558 | dev_err(rs->dev, "No buffer for transfer\n"); | |
559 | return -EINVAL; | |
560 | } | |
561 | ||
5185a81c BN |
562 | if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { |
563 | dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); | |
564 | return -EINVAL; | |
565 | } | |
566 | ||
65498c6a | 567 | rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2; |
64e36824 | 568 | |
eff0275e | 569 | use_dma = master->can_dma ? master->can_dma(master, spi, xfer) : false; |
64e36824 | 570 | |
eff0275e | 571 | rockchip_spi_config(rs, spi, xfer, use_dma); |
64e36824 | 572 | |
eff0275e | 573 | if (use_dma) |
eee06a9e | 574 | return rockchip_spi_prepare_dma(rs, master, xfer); |
64e36824 | 575 | |
01b59ce5 | 576 | return rockchip_spi_prepare_irq(rs, xfer); |
64e36824 | 577 | } |
578 | ||
579 | static bool rockchip_spi_can_dma(struct spi_master *master, | |
5dcc44ed AK |
580 | struct spi_device *spi, |
581 | struct spi_transfer *xfer) | |
64e36824 | 582 | { |
583 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
01b59ce5 | 584 | unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2; |
64e36824 | 585 | |
01b59ce5 ERB |
586 | /* if the numbor of spi words to transfer is less than the fifo |
587 | * length we can just fill the fifo and wait for a single irq, | |
588 | * so don't bother setting up dma | |
589 | */ | |
590 | return xfer->len / bytes_per_word >= rs->fifo_len; | |
64e36824 | 591 | } |
592 | ||
593 | static int rockchip_spi_probe(struct platform_device *pdev) | |
594 | { | |
43de979d | 595 | int ret; |
64e36824 | 596 | struct rockchip_spi *rs; |
597 | struct spi_master *master; | |
598 | struct resource *mem; | |
76b17e6e | 599 | u32 rsd_nsecs; |
64e36824 | 600 | |
601 | master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); | |
5dcc44ed | 602 | if (!master) |
64e36824 | 603 | return -ENOMEM; |
5dcc44ed | 604 | |
64e36824 | 605 | platform_set_drvdata(pdev, master); |
606 | ||
607 | rs = spi_master_get_devdata(master); | |
64e36824 | 608 | |
609 | /* Get basic io resource and map it */ | |
610 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
611 | rs->regs = devm_ioremap_resource(&pdev->dev, mem); | |
612 | if (IS_ERR(rs->regs)) { | |
64e36824 | 613 | ret = PTR_ERR(rs->regs); |
c351587e | 614 | goto err_put_master; |
64e36824 | 615 | } |
616 | ||
617 | rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
618 | if (IS_ERR(rs->apb_pclk)) { | |
619 | dev_err(&pdev->dev, "Failed to get apb_pclk\n"); | |
620 | ret = PTR_ERR(rs->apb_pclk); | |
c351587e | 621 | goto err_put_master; |
64e36824 | 622 | } |
623 | ||
624 | rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); | |
625 | if (IS_ERR(rs->spiclk)) { | |
626 | dev_err(&pdev->dev, "Failed to get spi_pclk\n"); | |
627 | ret = PTR_ERR(rs->spiclk); | |
c351587e | 628 | goto err_put_master; |
64e36824 | 629 | } |
630 | ||
631 | ret = clk_prepare_enable(rs->apb_pclk); | |
43de979d | 632 | if (ret < 0) { |
64e36824 | 633 | dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); |
c351587e | 634 | goto err_put_master; |
64e36824 | 635 | } |
636 | ||
637 | ret = clk_prepare_enable(rs->spiclk); | |
43de979d | 638 | if (ret < 0) { |
64e36824 | 639 | dev_err(&pdev->dev, "Failed to enable spi_clk\n"); |
c351587e | 640 | goto err_disable_apbclk; |
64e36824 | 641 | } |
642 | ||
30688e4e | 643 | spi_enable_chip(rs, false); |
64e36824 | 644 | |
01b59ce5 ERB |
645 | ret = platform_get_irq(pdev, 0); |
646 | if (ret < 0) | |
647 | goto err_disable_spiclk; | |
648 | ||
649 | ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, | |
650 | IRQF_ONESHOT, dev_name(&pdev->dev), master); | |
651 | if (ret) | |
652 | goto err_disable_spiclk; | |
653 | ||
64e36824 | 654 | rs->dev = &pdev->dev; |
420b82f8 | 655 | rs->freq = clk_get_rate(rs->spiclk); |
64e36824 | 656 | |
76b17e6e | 657 | if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", |
74b7efa8 ERB |
658 | &rsd_nsecs)) { |
659 | /* rx sample delay is expressed in parent clock cycles (max 3) */ | |
660 | u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), | |
661 | 1000000000 >> 8); | |
662 | if (!rsd) { | |
663 | dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", | |
664 | rs->freq, rsd_nsecs); | |
665 | } else if (rsd > CR0_RSD_MAX) { | |
666 | rsd = CR0_RSD_MAX; | |
667 | dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", | |
668 | rs->freq, rsd_nsecs, | |
669 | CR0_RSD_MAX * 1000000000U / rs->freq); | |
670 | } | |
671 | rs->rsd = rsd; | |
672 | } | |
76b17e6e | 673 | |
64e36824 | 674 | rs->fifo_len = get_fifo_len(rs); |
675 | if (!rs->fifo_len) { | |
676 | dev_err(&pdev->dev, "Failed to get fifo length\n"); | |
db7e8d90 | 677 | ret = -EINVAL; |
c351587e | 678 | goto err_disable_spiclk; |
64e36824 | 679 | } |
680 | ||
64e36824 | 681 | pm_runtime_set_active(&pdev->dev); |
682 | pm_runtime_enable(&pdev->dev); | |
683 | ||
684 | master->auto_runtime_pm = true; | |
685 | master->bus_num = pdev->id; | |
04290192 | 686 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; |
aa099382 | 687 | master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM; |
64e36824 | 688 | master->dev.of_node = pdev->dev.of_node; |
65498c6a | 689 | master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4); |
420b82f8 ERB |
690 | master->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; |
691 | master->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); | |
64e36824 | 692 | |
693 | master->set_cs = rockchip_spi_set_cs; | |
64e36824 | 694 | master->transfer_one = rockchip_spi_transfer_one; |
5185a81c | 695 | master->max_transfer_size = rockchip_spi_max_transfer_size; |
2291793c | 696 | master->handle_err = rockchip_spi_handle_err; |
c863795c | 697 | master->flags = SPI_MASTER_GPIO_SS; |
64e36824 | 698 | |
eee06a9e ERB |
699 | master->dma_tx = dma_request_chan(rs->dev, "tx"); |
700 | if (IS_ERR(master->dma_tx)) { | |
61cadcf4 | 701 | /* Check tx to see if we need defer probing driver */ |
eee06a9e | 702 | if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { |
61cadcf4 | 703 | ret = -EPROBE_DEFER; |
c351587e | 704 | goto err_disable_pm_runtime; |
61cadcf4 | 705 | } |
64e36824 | 706 | dev_warn(rs->dev, "Failed to request TX DMA channel\n"); |
eee06a9e | 707 | master->dma_tx = NULL; |
61cadcf4 | 708 | } |
64e36824 | 709 | |
eee06a9e ERB |
710 | master->dma_rx = dma_request_chan(rs->dev, "rx"); |
711 | if (IS_ERR(master->dma_rx)) { | |
712 | if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { | |
e4c0e06f | 713 | ret = -EPROBE_DEFER; |
5de7ed0c | 714 | goto err_free_dma_tx; |
64e36824 | 715 | } |
716 | dev_warn(rs->dev, "Failed to request RX DMA channel\n"); | |
eee06a9e | 717 | master->dma_rx = NULL; |
64e36824 | 718 | } |
719 | ||
eee06a9e ERB |
720 | if (master->dma_tx && master->dma_rx) { |
721 | rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR; | |
722 | rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR; | |
64e36824 | 723 | master->can_dma = rockchip_spi_can_dma; |
64e36824 | 724 | } |
725 | ||
726 | ret = devm_spi_register_master(&pdev->dev, master); | |
43de979d | 727 | if (ret < 0) { |
64e36824 | 728 | dev_err(&pdev->dev, "Failed to register master\n"); |
c351587e | 729 | goto err_free_dma_rx; |
64e36824 | 730 | } |
731 | ||
64e36824 | 732 | return 0; |
733 | ||
c351587e | 734 | err_free_dma_rx: |
eee06a9e ERB |
735 | if (master->dma_rx) |
736 | dma_release_channel(master->dma_rx); | |
5de7ed0c | 737 | err_free_dma_tx: |
eee06a9e ERB |
738 | if (master->dma_tx) |
739 | dma_release_channel(master->dma_tx); | |
c351587e JC |
740 | err_disable_pm_runtime: |
741 | pm_runtime_disable(&pdev->dev); | |
742 | err_disable_spiclk: | |
64e36824 | 743 | clk_disable_unprepare(rs->spiclk); |
c351587e | 744 | err_disable_apbclk: |
64e36824 | 745 | clk_disable_unprepare(rs->apb_pclk); |
c351587e | 746 | err_put_master: |
64e36824 | 747 | spi_master_put(master); |
748 | ||
749 | return ret; | |
750 | } | |
751 | ||
752 | static int rockchip_spi_remove(struct platform_device *pdev) | |
753 | { | |
754 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
755 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
756 | ||
6a06e895 | 757 | pm_runtime_get_sync(&pdev->dev); |
64e36824 | 758 | |
759 | clk_disable_unprepare(rs->spiclk); | |
760 | clk_disable_unprepare(rs->apb_pclk); | |
761 | ||
6a06e895 JC |
762 | pm_runtime_put_noidle(&pdev->dev); |
763 | pm_runtime_disable(&pdev->dev); | |
764 | pm_runtime_set_suspended(&pdev->dev); | |
765 | ||
eee06a9e ERB |
766 | if (master->dma_tx) |
767 | dma_release_channel(master->dma_tx); | |
768 | if (master->dma_rx) | |
769 | dma_release_channel(master->dma_rx); | |
64e36824 | 770 | |
844c9f47 SL |
771 | spi_master_put(master); |
772 | ||
64e36824 | 773 | return 0; |
774 | } | |
775 | ||
776 | #ifdef CONFIG_PM_SLEEP | |
777 | static int rockchip_spi_suspend(struct device *dev) | |
778 | { | |
43de979d | 779 | int ret; |
64e36824 | 780 | struct spi_master *master = dev_get_drvdata(dev); |
64e36824 | 781 | |
d790c342 | 782 | ret = spi_master_suspend(master); |
43de979d | 783 | if (ret < 0) |
64e36824 | 784 | return ret; |
785 | ||
d38c4ae1 JC |
786 | ret = pm_runtime_force_suspend(dev); |
787 | if (ret < 0) | |
788 | return ret; | |
64e36824 | 789 | |
23e291c2 BN |
790 | pinctrl_pm_select_sleep_state(dev); |
791 | ||
43de979d | 792 | return 0; |
64e36824 | 793 | } |
794 | ||
795 | static int rockchip_spi_resume(struct device *dev) | |
796 | { | |
43de979d | 797 | int ret; |
64e36824 | 798 | struct spi_master *master = dev_get_drvdata(dev); |
799 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
800 | ||
23e291c2 BN |
801 | pinctrl_pm_select_default_state(dev); |
802 | ||
d38c4ae1 JC |
803 | ret = pm_runtime_force_resume(dev); |
804 | if (ret < 0) | |
805 | return ret; | |
64e36824 | 806 | |
d790c342 | 807 | ret = spi_master_resume(master); |
64e36824 | 808 | if (ret < 0) { |
809 | clk_disable_unprepare(rs->spiclk); | |
810 | clk_disable_unprepare(rs->apb_pclk); | |
811 | } | |
812 | ||
43de979d | 813 | return 0; |
64e36824 | 814 | } |
815 | #endif /* CONFIG_PM_SLEEP */ | |
816 | ||
ec833050 | 817 | #ifdef CONFIG_PM |
64e36824 | 818 | static int rockchip_spi_runtime_suspend(struct device *dev) |
819 | { | |
820 | struct spi_master *master = dev_get_drvdata(dev); | |
821 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
822 | ||
823 | clk_disable_unprepare(rs->spiclk); | |
824 | clk_disable_unprepare(rs->apb_pclk); | |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
829 | static int rockchip_spi_runtime_resume(struct device *dev) | |
830 | { | |
831 | int ret; | |
832 | struct spi_master *master = dev_get_drvdata(dev); | |
833 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
834 | ||
835 | ret = clk_prepare_enable(rs->apb_pclk); | |
43de979d | 836 | if (ret < 0) |
64e36824 | 837 | return ret; |
838 | ||
839 | ret = clk_prepare_enable(rs->spiclk); | |
43de979d | 840 | if (ret < 0) |
64e36824 | 841 | clk_disable_unprepare(rs->apb_pclk); |
842 | ||
43de979d | 843 | return 0; |
64e36824 | 844 | } |
ec833050 | 845 | #endif /* CONFIG_PM */ |
64e36824 | 846 | |
847 | static const struct dev_pm_ops rockchip_spi_pm = { | |
848 | SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) | |
849 | SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, | |
850 | rockchip_spi_runtime_resume, NULL) | |
851 | }; | |
852 | ||
853 | static const struct of_device_id rockchip_spi_dt_match[] = { | |
6b860e69 | 854 | { .compatible = "rockchip,rv1108-spi", }, |
aa29ea3d | 855 | { .compatible = "rockchip,rk3036-spi", }, |
64e36824 | 856 | { .compatible = "rockchip,rk3066-spi", }, |
b839b785 | 857 | { .compatible = "rockchip,rk3188-spi", }, |
aa29ea3d | 858 | { .compatible = "rockchip,rk3228-spi", }, |
b839b785 | 859 | { .compatible = "rockchip,rk3288-spi", }, |
aa29ea3d | 860 | { .compatible = "rockchip,rk3368-spi", }, |
9b7a5622 | 861 | { .compatible = "rockchip,rk3399-spi", }, |
64e36824 | 862 | { }, |
863 | }; | |
864 | MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); | |
865 | ||
866 | static struct platform_driver rockchip_spi_driver = { | |
867 | .driver = { | |
868 | .name = DRIVER_NAME, | |
64e36824 | 869 | .pm = &rockchip_spi_pm, |
870 | .of_match_table = of_match_ptr(rockchip_spi_dt_match), | |
871 | }, | |
872 | .probe = rockchip_spi_probe, | |
873 | .remove = rockchip_spi_remove, | |
874 | }; | |
875 | ||
876 | module_platform_driver(rockchip_spi_driver); | |
877 | ||
5dcc44ed | 878 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); |
64e36824 | 879 | MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); |
880 | MODULE_LICENSE("GPL v2"); |