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Commit | Line | Data |
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0b2182dd SY |
1 | /* |
2 | * SH RSPI driver | |
3 | * | |
93722206 | 4 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
0b2182dd SY |
5 | * |
6 | * Based on spi-sh.c: | |
7 | * Copyright (C) 2011 Renesas Solutions Corp. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/errno.h> | |
0b2182dd SY |
28 | #include <linux/interrupt.h> |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/clk.h> | |
a3633fe7 SY |
32 | #include <linux/dmaengine.h> |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/sh_dma.h> | |
0b2182dd | 35 | #include <linux/spi/spi.h> |
a3633fe7 | 36 | #include <linux/spi/rspi.h> |
0b2182dd | 37 | |
6ab4865b GU |
38 | #define RSPI_SPCR 0x00 /* Control Register */ |
39 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
40 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
41 | #define RSPI_SPSR 0x03 /* Status Register */ | |
42 | #define RSPI_SPDR 0x04 /* Data Register */ | |
43 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
44 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
45 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
46 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
47 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
48 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
49 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
862d357f | 50 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
6ab4865b GU |
51 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
52 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
53 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
54 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
55 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
56 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
57 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
58 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
862d357f GU |
59 | |
60 | /* RSPI on RZ only */ | |
6ab4865b GU |
61 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
62 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 63 | |
862d357f | 64 | /* QSPI only */ |
fbe5072b GU |
65 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
66 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
67 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
68 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
69 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
70 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
5ce0ba88 | 71 | |
6ab4865b GU |
72 | /* SPCR - Control Register */ |
73 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
74 | #define SPCR_SPE 0x40 /* Function Enable */ | |
75 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
76 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
77 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
78 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
79 | /* RSPI on SH only */ | |
80 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
81 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
fbe5072b GU |
82 | /* QSPI on R-Car M2 only */ |
83 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ | |
84 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
85 | |
86 | /* SSLP - Slave Select Polarity Register */ | |
87 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ | |
88 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ | |
89 | ||
90 | /* SPPCR - Pin Control Register */ | |
91 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
92 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 93 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
94 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
95 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
96 | ||
fbe5072b GU |
97 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
98 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
99 | ||
6ab4865b GU |
100 | /* SPSR - Status Register */ |
101 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
102 | #define SPSR_TEND 0x40 /* Transmit End */ | |
103 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
104 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
105 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
106 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
862d357f | 107 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
6ab4865b GU |
108 | |
109 | /* SPSCR - Sequence Control Register */ | |
110 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
111 | ||
112 | /* SPSSR - Sequence Status Register */ | |
113 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
114 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
115 | ||
116 | /* SPDCR - Data Control Register */ | |
117 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
118 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
119 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
120 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
121 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
122 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
123 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
862d357f | 124 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
0b2182dd SY |
125 | #define SPDCR_SLSEL1 0x08 |
126 | #define SPDCR_SLSEL0 0x04 | |
862d357f | 127 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
0b2182dd SY |
128 | #define SPDCR_SPFC1 0x02 |
129 | #define SPDCR_SPFC0 0x01 | |
862d357f | 130 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
0b2182dd | 131 | |
6ab4865b GU |
132 | /* SPCKD - Clock Delay Register */ |
133 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 134 | |
6ab4865b GU |
135 | /* SSLND - Slave Select Negation Delay Register */ |
136 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 137 | |
6ab4865b GU |
138 | /* SPND - Next-Access Delay Register */ |
139 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 140 | |
6ab4865b GU |
141 | /* SPCR2 - Control Register 2 */ |
142 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
143 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
144 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
145 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 146 | |
6ab4865b GU |
147 | /* SPCMDn - Command Registers */ |
148 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
149 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
150 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
151 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
152 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 153 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
5ce0ba88 HCM |
154 | #define SPCMD_SPB_8BIT 0x0000 /* qspi only */ |
155 | #define SPCMD_SPB_16BIT 0x0100 | |
0b2182dd SY |
156 | #define SPCMD_SPB_20BIT 0x0000 |
157 | #define SPCMD_SPB_24BIT 0x0100 | |
158 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 159 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
160 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
161 | #define SPCMD_SPIMOD1 0x0040 | |
162 | #define SPCMD_SPIMOD0 0x0020 | |
163 | #define SPCMD_SPIMOD_SINGLE 0 | |
164 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
165 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
166 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
6ab4865b GU |
167 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
168 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ | |
169 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ | |
170 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
171 | ||
172 | /* SPBFCR - Buffer Control Register */ | |
862d357f GU |
173 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
174 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ | |
6ab4865b GU |
175 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
176 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
5ce0ba88 | 177 | |
2aae80b2 GU |
178 | #define DUMMY_DATA 0x00 |
179 | ||
0b2182dd SY |
180 | struct rspi_data { |
181 | void __iomem *addr; | |
182 | u32 max_speed_hz; | |
183 | struct spi_master *master; | |
0b2182dd | 184 | wait_queue_head_t wait; |
0b2182dd | 185 | struct clk *clk; |
348e5153 | 186 | u16 spcmd; |
06a7a3cf GU |
187 | u8 spsr; |
188 | u8 sppcr; | |
93722206 | 189 | int rx_irq, tx_irq; |
5ce0ba88 | 190 | const struct spi_ops *ops; |
a3633fe7 SY |
191 | |
192 | /* for dmaengine */ | |
a3633fe7 SY |
193 | struct dma_chan *chan_tx; |
194 | struct dma_chan *chan_rx; | |
a3633fe7 SY |
195 | |
196 | unsigned dma_width_16bit:1; | |
197 | unsigned dma_callbacked:1; | |
74da7686 | 198 | unsigned byte_access:1; |
0b2182dd SY |
199 | }; |
200 | ||
baf588f4 | 201 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
202 | { |
203 | iowrite8(data, rspi->addr + offset); | |
204 | } | |
205 | ||
baf588f4 | 206 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
207 | { |
208 | iowrite16(data, rspi->addr + offset); | |
209 | } | |
210 | ||
baf588f4 | 211 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
212 | { |
213 | iowrite32(data, rspi->addr + offset); | |
214 | } | |
215 | ||
baf588f4 | 216 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
217 | { |
218 | return ioread8(rspi->addr + offset); | |
219 | } | |
220 | ||
baf588f4 | 221 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
222 | { |
223 | return ioread16(rspi->addr + offset); | |
224 | } | |
225 | ||
74da7686 GU |
226 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
227 | { | |
228 | if (rspi->byte_access) | |
229 | rspi_write8(rspi, data, RSPI_SPDR); | |
230 | else /* 16 bit */ | |
231 | rspi_write16(rspi, data, RSPI_SPDR); | |
232 | } | |
233 | ||
234 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
235 | { | |
236 | if (rspi->byte_access) | |
237 | return rspi_read8(rspi, RSPI_SPDR); | |
238 | else /* 16 bit */ | |
239 | return rspi_read16(rspi, RSPI_SPDR); | |
240 | } | |
241 | ||
5ce0ba88 HCM |
242 | /* optional functions */ |
243 | struct spi_ops { | |
74da7686 | 244 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
eb557f75 GU |
245 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
246 | struct spi_transfer *xfer); | |
5ce0ba88 HCM |
247 | }; |
248 | ||
249 | /* | |
862d357f | 250 | * functions for RSPI on legacy SH |
5ce0ba88 | 251 | */ |
74da7686 | 252 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 253 | { |
5ce0ba88 HCM |
254 | int spbr; |
255 | ||
06a7a3cf GU |
256 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
257 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
0b2182dd | 258 | |
5ce0ba88 HCM |
259 | /* Sets transfer bit rate */ |
260 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
261 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
262 | ||
74da7686 GU |
263 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
264 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
265 | rspi->byte_access = 0; | |
0b2182dd | 266 | |
5ce0ba88 HCM |
267 | /* Sets RSPCK, SSL, next-access delay value */ |
268 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
269 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
270 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
271 | ||
272 | /* Sets parity, interrupt mask */ | |
273 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
274 | ||
275 | /* Sets SPCMD */ | |
348e5153 | 276 | rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, |
5ce0ba88 HCM |
277 | RSPI_SPCMD0); |
278 | ||
279 | /* Sets RSPI mode */ | |
280 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
281 | ||
282 | return 0; | |
0b2182dd SY |
283 | } |
284 | ||
862d357f GU |
285 | /* |
286 | * functions for RSPI on RZ | |
287 | */ | |
288 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) | |
289 | { | |
290 | int spbr; | |
291 | ||
06a7a3cf GU |
292 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
293 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
862d357f GU |
294 | |
295 | /* Sets transfer bit rate */ | |
296 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
297 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
298 | ||
299 | /* Disable dummy transmission, set byte access */ | |
300 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); | |
301 | rspi->byte_access = 1; | |
302 | ||
303 | /* Sets RSPCK, SSL, next-access delay value */ | |
304 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
305 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
306 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
307 | ||
308 | /* Sets SPCMD */ | |
309 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); | |
310 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
311 | ||
312 | /* Sets RSPI mode */ | |
313 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
5ce0ba88 HCM |
318 | /* |
319 | * functions for QSPI | |
320 | */ | |
74da7686 | 321 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 HCM |
322 | { |
323 | u16 spcmd; | |
324 | int spbr; | |
325 | ||
06a7a3cf GU |
326 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
327 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
5ce0ba88 HCM |
328 | |
329 | /* Sets transfer bit rate */ | |
330 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); | |
331 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
332 | ||
74da7686 GU |
333 | /* Disable dummy transmission, set byte access */ |
334 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
335 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
336 | |
337 | /* Sets RSPCK, SSL, next-access delay value */ | |
338 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
339 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
340 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
341 | ||
342 | /* Data Length Setting */ | |
343 | if (access_size == 8) | |
344 | spcmd = SPCMD_SPB_8BIT; | |
345 | else if (access_size == 16) | |
346 | spcmd = SPCMD_SPB_16BIT; | |
8e1c8096 | 347 | else |
5ce0ba88 HCM |
348 | spcmd = SPCMD_SPB_32BIT; |
349 | ||
348e5153 | 350 | spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; |
5ce0ba88 HCM |
351 | |
352 | /* Resets transfer data length */ | |
353 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
354 | ||
355 | /* Resets transmit and receive buffer */ | |
356 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
357 | /* Sets buffer to allow normal operation */ | |
358 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
359 | ||
360 | /* Sets SPCMD */ | |
361 | rspi_write16(rspi, spcmd, RSPI_SPCMD0); | |
362 | ||
363 | /* Enables SPI function in a master mode */ | |
364 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
369 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) | |
370 | ||
baf588f4 | 371 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
372 | { |
373 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
374 | } | |
375 | ||
baf588f4 | 376 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
377 | { |
378 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
379 | } | |
380 | ||
381 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
382 | u8 enable_bit) | |
383 | { | |
384 | int ret; | |
385 | ||
386 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
387 | rspi_enable_irq(rspi, enable_bit); | |
388 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
389 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
390 | return -ETIMEDOUT; | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
35301c99 GU |
395 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
396 | { | |
397 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
398 | dev_err(&rspi->master->dev, "transmit timeout\n"); | |
399 | return -ETIMEDOUT; | |
400 | } | |
401 | rspi_write_data(rspi, data); | |
402 | return 0; | |
403 | } | |
404 | ||
405 | static int rspi_data_in(struct rspi_data *rspi) | |
406 | { | |
407 | u8 data; | |
408 | ||
409 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | |
410 | dev_err(&rspi->master->dev, "receive timeout\n"); | |
411 | return -ETIMEDOUT; | |
412 | } | |
413 | data = rspi_read_data(rspi); | |
414 | return data; | |
415 | } | |
416 | ||
417 | static int rspi_data_out_in(struct rspi_data *rspi, u8 data) | |
418 | { | |
419 | int ret; | |
420 | ||
421 | ret = rspi_data_out(rspi, data); | |
422 | if (ret < 0) | |
423 | return ret; | |
424 | ||
425 | return rspi_data_in(rspi); | |
426 | } | |
427 | ||
a3633fe7 SY |
428 | static void rspi_dma_complete(void *arg) |
429 | { | |
430 | struct rspi_data *rspi = arg; | |
431 | ||
432 | rspi->dma_callbacked = 1; | |
433 | wake_up_interruptible(&rspi->wait); | |
434 | } | |
435 | ||
c132f094 GU |
436 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
437 | unsigned len, struct dma_chan *chan, | |
a3633fe7 SY |
438 | enum dma_transfer_direction dir) |
439 | { | |
440 | sg_init_table(sg, 1); | |
441 | sg_set_buf(sg, buf, len); | |
442 | sg_dma_len(sg) = len; | |
443 | return dma_map_sg(chan->device->dev, sg, 1, dir); | |
444 | } | |
445 | ||
446 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, | |
447 | enum dma_transfer_direction dir) | |
448 | { | |
449 | dma_unmap_sg(chan->device->dev, sg, 1, dir); | |
450 | } | |
451 | ||
452 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) | |
453 | { | |
454 | u16 *dst = buf; | |
455 | const u8 *src = data; | |
456 | ||
457 | while (len) { | |
458 | *dst++ = (u16)(*src++); | |
459 | len--; | |
460 | } | |
461 | } | |
462 | ||
463 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) | |
464 | { | |
465 | u8 *dst = buf; | |
466 | const u16 *src = data; | |
467 | ||
468 | while (len) { | |
469 | *dst++ = (u8)*src++; | |
470 | len--; | |
471 | } | |
472 | } | |
473 | ||
474 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) | |
475 | { | |
476 | struct scatterlist sg; | |
c132f094 | 477 | const void *buf = NULL; |
a3633fe7 | 478 | struct dma_async_tx_descriptor *desc; |
93722206 | 479 | unsigned int len; |
a3633fe7 SY |
480 | int ret = 0; |
481 | ||
482 | if (rspi->dma_width_16bit) { | |
c132f094 | 483 | void *tmp; |
a3633fe7 SY |
484 | /* |
485 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
486 | * buffer. And, the driver converts original data into the | |
487 | * DMAC data as the following format: | |
488 | * original data: 1st byte, 2nd byte ... | |
489 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
490 | */ | |
491 | len = t->len * 2; | |
c132f094 GU |
492 | tmp = kmalloc(len, GFP_KERNEL); |
493 | if (!tmp) | |
a3633fe7 | 494 | return -ENOMEM; |
c132f094 GU |
495 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
496 | buf = tmp; | |
a3633fe7 SY |
497 | } else { |
498 | len = t->len; | |
c132f094 | 499 | buf = t->tx_buf; |
a3633fe7 SY |
500 | } |
501 | ||
502 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { | |
503 | ret = -EFAULT; | |
504 | goto end_nomap; | |
505 | } | |
506 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, | |
507 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
508 | if (!desc) { | |
509 | ret = -EIO; | |
510 | goto end; | |
511 | } | |
512 | ||
513 | /* | |
514 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
515 | * called. So, this driver disables the IRQ while DMA transfer. | |
516 | */ | |
93722206 | 517 | disable_irq(rspi->tx_irq); |
a3633fe7 SY |
518 | |
519 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); | |
520 | rspi_enable_irq(rspi, SPCR_SPTIE); | |
521 | rspi->dma_callbacked = 0; | |
522 | ||
523 | desc->callback = rspi_dma_complete; | |
524 | desc->callback_param = rspi; | |
525 | dmaengine_submit(desc); | |
526 | dma_async_issue_pending(rspi->chan_tx); | |
527 | ||
528 | ret = wait_event_interruptible_timeout(rspi->wait, | |
529 | rspi->dma_callbacked, HZ); | |
530 | if (ret > 0 && rspi->dma_callbacked) | |
531 | ret = 0; | |
532 | else if (!ret) | |
533 | ret = -ETIMEDOUT; | |
534 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
535 | ||
93722206 | 536 | enable_irq(rspi->tx_irq); |
a3633fe7 SY |
537 | |
538 | end: | |
539 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); | |
540 | end_nomap: | |
541 | if (rspi->dma_width_16bit) | |
542 | kfree(buf); | |
543 | ||
544 | return ret; | |
545 | } | |
546 | ||
baf588f4 | 547 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 548 | { |
97b95c11 | 549 | u8 spsr; |
0b2182dd SY |
550 | |
551 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
552 | if (spsr & SPSR_SPRF) | |
74da7686 | 553 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
554 | if (spsr & SPSR_OVRF) |
555 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 556 | RSPI_SPSR); |
a3633fe7 SY |
557 | } |
558 | ||
862d357f GU |
559 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
560 | { | |
561 | rspi_receive_init(rspi); | |
562 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); | |
563 | rspi_write8(rspi, 0, RSPI_SPBFCR); | |
564 | } | |
565 | ||
baf588f4 | 566 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 567 | { |
97b95c11 | 568 | u8 spsr; |
cb52c673 HCM |
569 | |
570 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
571 | if (spsr & SPSR_SPRF) | |
74da7686 | 572 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 573 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 574 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
575 | } |
576 | ||
a3633fe7 SY |
577 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
578 | { | |
579 | struct scatterlist sg, sg_dummy; | |
580 | void *dummy = NULL, *rx_buf = NULL; | |
581 | struct dma_async_tx_descriptor *desc, *desc_dummy; | |
93722206 | 582 | unsigned int len; |
a3633fe7 SY |
583 | int ret = 0; |
584 | ||
585 | if (rspi->dma_width_16bit) { | |
586 | /* | |
587 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
588 | * buffer. And, finally the driver converts the DMAC data into | |
589 | * actual data as the following format: | |
590 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
591 | * actual data: 1st byte, 2nd byte ... | |
592 | */ | |
593 | len = t->len * 2; | |
594 | rx_buf = kmalloc(len, GFP_KERNEL); | |
595 | if (!rx_buf) | |
596 | return -ENOMEM; | |
597 | } else { | |
598 | len = t->len; | |
599 | rx_buf = t->rx_buf; | |
600 | } | |
601 | ||
602 | /* prepare dummy transfer to generate SPI clocks */ | |
603 | dummy = kzalloc(len, GFP_KERNEL); | |
604 | if (!dummy) { | |
605 | ret = -ENOMEM; | |
606 | goto end_nomap; | |
607 | } | |
608 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, | |
609 | DMA_TO_DEVICE)) { | |
610 | ret = -EFAULT; | |
611 | goto end_nomap; | |
612 | } | |
613 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, | |
614 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
615 | if (!desc_dummy) { | |
616 | ret = -EIO; | |
617 | goto end_dummy_mapped; | |
618 | } | |
619 | ||
620 | /* prepare receive transfer */ | |
621 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, | |
622 | DMA_FROM_DEVICE)) { | |
623 | ret = -EFAULT; | |
624 | goto end_dummy_mapped; | |
625 | ||
626 | } | |
627 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, | |
628 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
629 | if (!desc) { | |
630 | ret = -EIO; | |
631 | goto end; | |
632 | } | |
633 | ||
634 | rspi_receive_init(rspi); | |
635 | ||
636 | /* | |
637 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
638 | * called. So, this driver disables the IRQ while DMA transfer. | |
639 | */ | |
93722206 GU |
640 | disable_irq(rspi->tx_irq); |
641 | if (rspi->rx_irq != rspi->tx_irq) | |
642 | disable_irq(rspi->rx_irq); | |
a3633fe7 SY |
643 | |
644 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); | |
645 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
646 | rspi->dma_callbacked = 0; | |
647 | ||
648 | desc->callback = rspi_dma_complete; | |
649 | desc->callback_param = rspi; | |
650 | dmaengine_submit(desc); | |
651 | dma_async_issue_pending(rspi->chan_rx); | |
652 | ||
653 | desc_dummy->callback = NULL; /* No callback */ | |
654 | dmaengine_submit(desc_dummy); | |
655 | dma_async_issue_pending(rspi->chan_tx); | |
656 | ||
657 | ret = wait_event_interruptible_timeout(rspi->wait, | |
658 | rspi->dma_callbacked, HZ); | |
659 | if (ret > 0 && rspi->dma_callbacked) | |
660 | ret = 0; | |
661 | else if (!ret) | |
662 | ret = -ETIMEDOUT; | |
663 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
664 | ||
93722206 GU |
665 | enable_irq(rspi->tx_irq); |
666 | if (rspi->rx_irq != rspi->tx_irq) | |
667 | enable_irq(rspi->rx_irq); | |
a3633fe7 SY |
668 | |
669 | end: | |
670 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); | |
671 | end_dummy_mapped: | |
672 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); | |
673 | end_nomap: | |
674 | if (rspi->dma_width_16bit) { | |
675 | if (!ret) | |
676 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); | |
677 | kfree(rx_buf); | |
678 | } | |
679 | kfree(dummy); | |
680 | ||
681 | return ret; | |
682 | } | |
683 | ||
baf588f4 | 684 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
a3633fe7 SY |
685 | { |
686 | if (t->tx_buf && rspi->chan_tx) | |
687 | return 1; | |
688 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
689 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) | |
690 | return 1; | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
8449fd76 GU |
695 | static int rspi_transfer_out_in(struct rspi_data *rspi, |
696 | struct spi_transfer *xfer) | |
697 | { | |
698 | int remain = xfer->len, ret; | |
699 | const u8 *tx_buf = xfer->tx_buf; | |
700 | u8 *rx_buf = xfer->rx_buf; | |
701 | u8 spcr, data; | |
702 | ||
703 | rspi_receive_init(rspi); | |
704 | ||
705 | spcr = rspi_read8(rspi, RSPI_SPCR); | |
706 | if (rx_buf) | |
707 | spcr &= ~SPCR_TXMD; | |
708 | else | |
709 | spcr |= SPCR_TXMD; | |
710 | rspi_write8(rspi, spcr, RSPI_SPCR); | |
711 | ||
712 | while (remain > 0) { | |
713 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
714 | ret = rspi_data_out(rspi, data); | |
715 | if (ret < 0) | |
716 | return ret; | |
717 | if (rx_buf) { | |
718 | ret = rspi_data_in(rspi); | |
719 | if (ret < 0) | |
720 | return ret; | |
721 | *rx_buf++ = ret; | |
722 | } | |
723 | remain--; | |
724 | } | |
725 | ||
726 | /* Wait for the last transmission */ | |
727 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
79d23495 GU |
732 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
733 | struct spi_transfer *xfer) | |
0b2182dd | 734 | { |
79d23495 | 735 | struct rspi_data *rspi = spi_master_get_devdata(master); |
8449fd76 GU |
736 | int ret; |
737 | ||
738 | if (!rspi_is_dma(rspi, xfer)) | |
739 | return rspi_transfer_out_in(rspi, xfer); | |
0b2182dd | 740 | |
79d23495 | 741 | if (xfer->tx_buf) { |
8449fd76 | 742 | ret = rspi_send_dma(rspi, xfer); |
79d23495 GU |
743 | if (ret < 0) |
744 | return ret; | |
0b2182dd | 745 | } |
8449fd76 GU |
746 | if (xfer->rx_buf) |
747 | return rspi_receive_dma(rspi, xfer); | |
748 | ||
749 | return 0; | |
eb557f75 GU |
750 | } |
751 | ||
862d357f GU |
752 | static int rspi_rz_transfer_out_in(struct rspi_data *rspi, |
753 | struct spi_transfer *xfer) | |
754 | { | |
755 | int remain = xfer->len, ret; | |
756 | const u8 *tx_buf = xfer->tx_buf; | |
757 | u8 *rx_buf = xfer->rx_buf; | |
758 | u8 data; | |
759 | ||
760 | rspi_rz_receive_init(rspi); | |
761 | ||
762 | while (remain > 0) { | |
763 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
764 | ret = rspi_data_out_in(rspi, data); | |
765 | if (ret < 0) | |
766 | return ret; | |
767 | if (rx_buf) | |
768 | *rx_buf++ = ret; | |
769 | remain--; | |
770 | } | |
771 | ||
772 | /* Wait for the last transmission */ | |
773 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | static int rspi_rz_transfer_one(struct spi_master *master, | |
779 | struct spi_device *spi, | |
780 | struct spi_transfer *xfer) | |
781 | { | |
782 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
783 | ||
784 | return rspi_rz_transfer_out_in(rspi, xfer); | |
785 | } | |
786 | ||
340a15e6 GU |
787 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
788 | struct spi_transfer *xfer) | |
eb557f75 | 789 | { |
340a15e6 GU |
790 | int remain = xfer->len, ret; |
791 | const u8 *tx_buf = xfer->tx_buf; | |
792 | u8 *rx_buf = xfer->rx_buf; | |
793 | u8 data; | |
eb557f75 | 794 | |
340a15e6 GU |
795 | qspi_receive_init(rspi); |
796 | ||
797 | while (remain > 0) { | |
798 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
799 | ret = rspi_data_out_in(rspi, data); | |
eb557f75 GU |
800 | if (ret < 0) |
801 | return ret; | |
340a15e6 GU |
802 | if (rx_buf) |
803 | *rx_buf++ = ret; | |
804 | remain--; | |
79d23495 | 805 | } |
340a15e6 GU |
806 | |
807 | /* Wait for the last transmission */ | |
808 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, | |
814 | struct spi_transfer *xfer) | |
815 | { | |
816 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
817 | ||
818 | return qspi_transfer_out_in(rspi, xfer); | |
0b2182dd SY |
819 | } |
820 | ||
821 | static int rspi_setup(struct spi_device *spi) | |
822 | { | |
823 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | |
824 | ||
0b2182dd SY |
825 | rspi->max_speed_hz = spi->max_speed_hz; |
826 | ||
348e5153 GU |
827 | rspi->spcmd = SPCMD_SSLKP; |
828 | if (spi->mode & SPI_CPOL) | |
829 | rspi->spcmd |= SPCMD_CPOL; | |
830 | if (spi->mode & SPI_CPHA) | |
831 | rspi->spcmd |= SPCMD_CPHA; | |
832 | ||
06a7a3cf GU |
833 | /* CMOS output mode and MOSI signal from previous transfer */ |
834 | rspi->sppcr = 0; | |
835 | if (spi->mode & SPI_LOOP) | |
836 | rspi->sppcr |= SPPCR_SPLP; | |
837 | ||
5ce0ba88 | 838 | set_config_register(rspi, 8); |
0b2182dd SY |
839 | |
840 | return 0; | |
841 | } | |
842 | ||
79d23495 | 843 | static void rspi_cleanup(struct spi_device *spi) |
0b2182dd | 844 | { |
79d23495 | 845 | } |
0b2182dd | 846 | |
79d23495 GU |
847 | static int rspi_prepare_message(struct spi_master *master, |
848 | struct spi_message *message) | |
849 | { | |
850 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
0b2182dd | 851 | |
79d23495 | 852 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
853 | return 0; |
854 | } | |
855 | ||
79d23495 GU |
856 | static int rspi_unprepare_message(struct spi_master *master, |
857 | struct spi_message *message) | |
0b2182dd | 858 | { |
79d23495 GU |
859 | struct rspi_data *rspi = spi_master_get_devdata(master); |
860 | ||
861 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); | |
862 | return 0; | |
0b2182dd SY |
863 | } |
864 | ||
93722206 | 865 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
0b2182dd | 866 | { |
c132f094 | 867 | struct rspi_data *rspi = _sr; |
97b95c11 | 868 | u8 spsr; |
0b2182dd | 869 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 870 | u8 disable_irq = 0; |
0b2182dd SY |
871 | |
872 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
873 | if (spsr & SPSR_SPRF) | |
874 | disable_irq |= SPCR_SPRIE; | |
875 | if (spsr & SPSR_SPTEF) | |
876 | disable_irq |= SPCR_SPTIE; | |
877 | ||
878 | if (disable_irq) { | |
879 | ret = IRQ_HANDLED; | |
880 | rspi_disable_irq(rspi, disable_irq); | |
881 | wake_up(&rspi->wait); | |
882 | } | |
883 | ||
884 | return ret; | |
885 | } | |
886 | ||
93722206 GU |
887 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
888 | { | |
889 | struct rspi_data *rspi = _sr; | |
890 | u8 spsr; | |
891 | ||
892 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
893 | if (spsr & SPSR_SPRF) { | |
894 | rspi_disable_irq(rspi, SPCR_SPRIE); | |
895 | wake_up(&rspi->wait); | |
896 | return IRQ_HANDLED; | |
897 | } | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
902 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) | |
903 | { | |
904 | struct rspi_data *rspi = _sr; | |
905 | u8 spsr; | |
906 | ||
907 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
908 | if (spsr & SPSR_SPTEF) { | |
909 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
910 | wake_up(&rspi->wait); | |
911 | return IRQ_HANDLED; | |
912 | } | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
fd4a319b | 917 | static int rspi_request_dma(struct rspi_data *rspi, |
0243c536 | 918 | struct platform_device *pdev) |
a3633fe7 | 919 | { |
baf588f4 | 920 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
e2b05099 | 921 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3633fe7 | 922 | dma_cap_mask_t mask; |
0243c536 SY |
923 | struct dma_slave_config cfg; |
924 | int ret; | |
a3633fe7 | 925 | |
e2b05099 | 926 | if (!res || !rspi_pd) |
0243c536 | 927 | return 0; /* The driver assumes no error. */ |
a3633fe7 SY |
928 | |
929 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; | |
930 | ||
931 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
932 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { | |
933 | dma_cap_zero(mask); | |
934 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
935 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
936 | (void *)rspi_pd->dma_rx_id); | |
937 | if (rspi->chan_rx) { | |
938 | cfg.slave_id = rspi_pd->dma_rx_id; | |
939 | cfg.direction = DMA_DEV_TO_MEM; | |
e2b05099 GL |
940 | cfg.dst_addr = 0; |
941 | cfg.src_addr = res->start + RSPI_SPDR; | |
0243c536 SY |
942 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
943 | if (!ret) | |
944 | dev_info(&pdev->dev, "Use DMA when rx.\n"); | |
945 | else | |
946 | return ret; | |
947 | } | |
a3633fe7 SY |
948 | } |
949 | if (rspi_pd->dma_tx_id) { | |
950 | dma_cap_zero(mask); | |
951 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
952 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
953 | (void *)rspi_pd->dma_tx_id); | |
954 | if (rspi->chan_tx) { | |
955 | cfg.slave_id = rspi_pd->dma_tx_id; | |
956 | cfg.direction = DMA_MEM_TO_DEV; | |
e2b05099 GL |
957 | cfg.dst_addr = res->start + RSPI_SPDR; |
958 | cfg.src_addr = 0; | |
0243c536 SY |
959 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
960 | if (!ret) | |
961 | dev_info(&pdev->dev, "Use DMA when tx\n"); | |
962 | else | |
963 | return ret; | |
964 | } | |
a3633fe7 | 965 | } |
0243c536 SY |
966 | |
967 | return 0; | |
a3633fe7 SY |
968 | } |
969 | ||
fd4a319b | 970 | static void rspi_release_dma(struct rspi_data *rspi) |
a3633fe7 SY |
971 | { |
972 | if (rspi->chan_tx) | |
973 | dma_release_channel(rspi->chan_tx); | |
974 | if (rspi->chan_rx) | |
975 | dma_release_channel(rspi->chan_rx); | |
976 | } | |
977 | ||
fd4a319b | 978 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 979 | { |
5ffbe2d9 | 980 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 981 | |
a3633fe7 | 982 | rspi_release_dma(rspi); |
17fe0d9a | 983 | clk_disable_unprepare(rspi->clk); |
0b2182dd SY |
984 | |
985 | return 0; | |
986 | } | |
987 | ||
93722206 GU |
988 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
989 | irq_handler_t handler, const char *suffix, | |
990 | void *dev_id) | |
991 | { | |
992 | const char *base = dev_name(dev); | |
993 | size_t len = strlen(base) + strlen(suffix) + 2; | |
994 | char *name = devm_kzalloc(dev, len, GFP_KERNEL); | |
995 | if (!name) | |
996 | return -ENOMEM; | |
997 | snprintf(name, len, "%s:%s", base, suffix); | |
998 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); | |
999 | } | |
1000 | ||
fd4a319b | 1001 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
1002 | { |
1003 | struct resource *res; | |
1004 | struct spi_master *master; | |
1005 | struct rspi_data *rspi; | |
93722206 | 1006 | int ret; |
baf588f4 | 1007 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
5ce0ba88 HCM |
1008 | const struct spi_ops *ops; |
1009 | const struct platform_device_id *id_entry = pdev->id_entry; | |
1010 | ||
1011 | ops = (struct spi_ops *)id_entry->driver_data; | |
1012 | /* ops parameter check */ | |
1013 | if (!ops->set_config_register) { | |
1014 | dev_err(&pdev->dev, "there is no set_config_register\n"); | |
1015 | return -ENODEV; | |
1016 | } | |
0b2182dd | 1017 | |
0b2182dd SY |
1018 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
1019 | if (master == NULL) { | |
1020 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
1021 | return -ENOMEM; | |
1022 | } | |
1023 | ||
1024 | rspi = spi_master_get_devdata(master); | |
24b5a82c | 1025 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 1026 | rspi->ops = ops; |
0b2182dd | 1027 | rspi->master = master; |
5d79e9ac LP |
1028 | |
1029 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1030 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
1031 | if (IS_ERR(rspi->addr)) { | |
1032 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
1033 | goto error1; |
1034 | } | |
1035 | ||
29f397b7 | 1036 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
0b2182dd SY |
1037 | if (IS_ERR(rspi->clk)) { |
1038 | dev_err(&pdev->dev, "cannot get clock\n"); | |
1039 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 1040 | goto error1; |
0b2182dd | 1041 | } |
17fe0d9a GU |
1042 | |
1043 | ret = clk_prepare_enable(rspi->clk); | |
1044 | if (ret < 0) { | |
1045 | dev_err(&pdev->dev, "unable to prepare/enable clock\n"); | |
1046 | goto error1; | |
1047 | } | |
0b2182dd | 1048 | |
0b2182dd SY |
1049 | init_waitqueue_head(&rspi->wait); |
1050 | ||
efd85acb GU |
1051 | if (rspi_pd && rspi_pd->num_chipselect) |
1052 | master->num_chipselect = rspi_pd->num_chipselect; | |
1053 | else | |
5ce0ba88 HCM |
1054 | master->num_chipselect = 2; /* default */ |
1055 | ||
0b2182dd SY |
1056 | master->bus_num = pdev->id; |
1057 | master->setup = rspi_setup; | |
eb557f75 | 1058 | master->transfer_one = ops->transfer_one; |
0b2182dd | 1059 | master->cleanup = rspi_cleanup; |
79d23495 GU |
1060 | master->prepare_message = rspi_prepare_message; |
1061 | master->unprepare_message = rspi_unprepare_message; | |
06a7a3cf | 1062 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP; |
0b2182dd | 1063 | |
93722206 GU |
1064 | ret = platform_get_irq_byname(pdev, "rx"); |
1065 | if (ret < 0) { | |
1066 | ret = platform_get_irq_byname(pdev, "mux"); | |
1067 | if (ret < 0) | |
1068 | ret = platform_get_irq(pdev, 0); | |
1069 | if (ret >= 0) | |
1070 | rspi->rx_irq = rspi->tx_irq = ret; | |
1071 | } else { | |
1072 | rspi->rx_irq = ret; | |
1073 | ret = platform_get_irq_byname(pdev, "tx"); | |
1074 | if (ret >= 0) | |
1075 | rspi->tx_irq = ret; | |
1076 | } | |
1077 | if (ret < 0) { | |
1078 | dev_err(&pdev->dev, "platform_get_irq error\n"); | |
1079 | goto error2; | |
1080 | } | |
1081 | ||
1082 | if (rspi->rx_irq == rspi->tx_irq) { | |
1083 | /* Single multiplexed interrupt */ | |
1084 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, | |
1085 | "mux", rspi); | |
1086 | } else { | |
1087 | /* Multi-interrupt mode, only SPRI and SPTI are used */ | |
1088 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, | |
1089 | "rx", rspi); | |
1090 | if (!ret) | |
1091 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, | |
1092 | rspi_irq_tx, "tx", rspi); | |
1093 | } | |
0b2182dd SY |
1094 | if (ret < 0) { |
1095 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 1096 | goto error2; |
0b2182dd SY |
1097 | } |
1098 | ||
0243c536 SY |
1099 | ret = rspi_request_dma(rspi, pdev); |
1100 | if (ret < 0) { | |
1101 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); | |
fcb4ed74 | 1102 | goto error3; |
0243c536 | 1103 | } |
a3633fe7 | 1104 | |
9e03d05e | 1105 | ret = devm_spi_register_master(&pdev->dev, master); |
0b2182dd SY |
1106 | if (ret < 0) { |
1107 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
fcb4ed74 | 1108 | goto error3; |
0b2182dd SY |
1109 | } |
1110 | ||
1111 | dev_info(&pdev->dev, "probed\n"); | |
1112 | ||
1113 | return 0; | |
1114 | ||
fcb4ed74 | 1115 | error3: |
5d79e9ac | 1116 | rspi_release_dma(rspi); |
fcb4ed74 | 1117 | error2: |
17fe0d9a | 1118 | clk_disable_unprepare(rspi->clk); |
0b2182dd SY |
1119 | error1: |
1120 | spi_master_put(master); | |
1121 | ||
1122 | return ret; | |
1123 | } | |
1124 | ||
5ce0ba88 HCM |
1125 | static struct spi_ops rspi_ops = { |
1126 | .set_config_register = rspi_set_config_register, | |
eb557f75 | 1127 | .transfer_one = rspi_transfer_one, |
5ce0ba88 HCM |
1128 | }; |
1129 | ||
862d357f GU |
1130 | static struct spi_ops rspi_rz_ops = { |
1131 | .set_config_register = rspi_rz_set_config_register, | |
1132 | .transfer_one = rspi_rz_transfer_one, | |
1133 | }; | |
1134 | ||
5ce0ba88 HCM |
1135 | static struct spi_ops qspi_ops = { |
1136 | .set_config_register = qspi_set_config_register, | |
eb557f75 | 1137 | .transfer_one = qspi_transfer_one, |
5ce0ba88 HCM |
1138 | }; |
1139 | ||
1140 | static struct platform_device_id spi_driver_ids[] = { | |
1141 | { "rspi", (kernel_ulong_t)&rspi_ops }, | |
862d357f | 1142 | { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, |
5ce0ba88 HCM |
1143 | { "qspi", (kernel_ulong_t)&qspi_ops }, |
1144 | {}, | |
1145 | }; | |
1146 | ||
1147 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1148 | ||
0b2182dd SY |
1149 | static struct platform_driver rspi_driver = { |
1150 | .probe = rspi_probe, | |
fd4a319b | 1151 | .remove = rspi_remove, |
5ce0ba88 | 1152 | .id_table = spi_driver_ids, |
0b2182dd | 1153 | .driver = { |
5ce0ba88 | 1154 | .name = "renesas_spi", |
0b2182dd SY |
1155 | .owner = THIS_MODULE, |
1156 | }, | |
1157 | }; | |
1158 | module_platform_driver(rspi_driver); | |
1159 | ||
1160 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1161 | MODULE_LICENSE("GPL v2"); | |
1162 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1163 | MODULE_ALIAS("platform:rspi"); |