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Commit | Line | Data |
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0b2182dd SY |
1 | /* |
2 | * SH RSPI driver | |
3 | * | |
93722206 | 4 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
0b2182dd SY |
5 | * |
6 | * Based on spi-sh.c: | |
7 | * Copyright (C) 2011 Renesas Solutions Corp. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/errno.h> | |
0b2182dd SY |
28 | #include <linux/interrupt.h> |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/clk.h> | |
a3633fe7 SY |
32 | #include <linux/dmaengine.h> |
33 | #include <linux/dma-mapping.h> | |
426ef76d | 34 | #include <linux/of_device.h> |
a3633fe7 | 35 | #include <linux/sh_dma.h> |
0b2182dd | 36 | #include <linux/spi/spi.h> |
a3633fe7 | 37 | #include <linux/spi/rspi.h> |
0b2182dd | 38 | |
6ab4865b GU |
39 | #define RSPI_SPCR 0x00 /* Control Register */ |
40 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
41 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
42 | #define RSPI_SPSR 0x03 /* Status Register */ | |
43 | #define RSPI_SPDR 0x04 /* Data Register */ | |
44 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
45 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
46 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
47 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
48 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
49 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
50 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
862d357f | 51 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
6ab4865b GU |
52 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
53 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
54 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
55 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
56 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
57 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
58 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
59 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
862d357f GU |
60 | |
61 | /* RSPI on RZ only */ | |
6ab4865b GU |
62 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
63 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 64 | |
862d357f | 65 | /* QSPI only */ |
fbe5072b GU |
66 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
67 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
68 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
69 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
70 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
71 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
5ce0ba88 | 72 | |
6ab4865b GU |
73 | /* SPCR - Control Register */ |
74 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
75 | #define SPCR_SPE 0x40 /* Function Enable */ | |
76 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
77 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
78 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
79 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
80 | /* RSPI on SH only */ | |
81 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
82 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
fbe5072b GU |
83 | /* QSPI on R-Car M2 only */ |
84 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ | |
85 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
86 | |
87 | /* SSLP - Slave Select Polarity Register */ | |
88 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ | |
89 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ | |
90 | ||
91 | /* SPPCR - Pin Control Register */ | |
92 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
93 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 94 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
95 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
96 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
97 | ||
fbe5072b GU |
98 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
99 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
100 | ||
6ab4865b GU |
101 | /* SPSR - Status Register */ |
102 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
103 | #define SPSR_TEND 0x40 /* Transmit End */ | |
104 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
105 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
106 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
107 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
862d357f | 108 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
6ab4865b GU |
109 | |
110 | /* SPSCR - Sequence Control Register */ | |
111 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
112 | ||
113 | /* SPSSR - Sequence Status Register */ | |
114 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
115 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
116 | ||
117 | /* SPDCR - Data Control Register */ | |
118 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
119 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
120 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
121 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
122 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
123 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
124 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
862d357f | 125 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
0b2182dd SY |
126 | #define SPDCR_SLSEL1 0x08 |
127 | #define SPDCR_SLSEL0 0x04 | |
862d357f | 128 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
0b2182dd SY |
129 | #define SPDCR_SPFC1 0x02 |
130 | #define SPDCR_SPFC0 0x01 | |
862d357f | 131 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
0b2182dd | 132 | |
6ab4865b GU |
133 | /* SPCKD - Clock Delay Register */ |
134 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 135 | |
6ab4865b GU |
136 | /* SSLND - Slave Select Negation Delay Register */ |
137 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 138 | |
6ab4865b GU |
139 | /* SPND - Next-Access Delay Register */ |
140 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 141 | |
6ab4865b GU |
142 | /* SPCR2 - Control Register 2 */ |
143 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
144 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
145 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
146 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 147 | |
6ab4865b GU |
148 | /* SPCMDn - Command Registers */ |
149 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
150 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
151 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
152 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
153 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 154 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
5ce0ba88 HCM |
155 | #define SPCMD_SPB_8BIT 0x0000 /* qspi only */ |
156 | #define SPCMD_SPB_16BIT 0x0100 | |
0b2182dd SY |
157 | #define SPCMD_SPB_20BIT 0x0000 |
158 | #define SPCMD_SPB_24BIT 0x0100 | |
159 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 160 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
161 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
162 | #define SPCMD_SPIMOD1 0x0040 | |
163 | #define SPCMD_SPIMOD0 0x0020 | |
164 | #define SPCMD_SPIMOD_SINGLE 0 | |
165 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
166 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
167 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
6ab4865b GU |
168 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
169 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ | |
170 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ | |
171 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
172 | ||
173 | /* SPBFCR - Buffer Control Register */ | |
862d357f GU |
174 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
175 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ | |
6ab4865b GU |
176 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
177 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
5ce0ba88 | 178 | |
2aae80b2 GU |
179 | #define DUMMY_DATA 0x00 |
180 | ||
0b2182dd SY |
181 | struct rspi_data { |
182 | void __iomem *addr; | |
183 | u32 max_speed_hz; | |
184 | struct spi_master *master; | |
0b2182dd | 185 | wait_queue_head_t wait; |
0b2182dd | 186 | struct clk *clk; |
348e5153 | 187 | u16 spcmd; |
06a7a3cf GU |
188 | u8 spsr; |
189 | u8 sppcr; | |
93722206 | 190 | int rx_irq, tx_irq; |
5ce0ba88 | 191 | const struct spi_ops *ops; |
a3633fe7 SY |
192 | |
193 | /* for dmaengine */ | |
a3633fe7 SY |
194 | struct dma_chan *chan_tx; |
195 | struct dma_chan *chan_rx; | |
a3633fe7 SY |
196 | |
197 | unsigned dma_width_16bit:1; | |
198 | unsigned dma_callbacked:1; | |
74da7686 | 199 | unsigned byte_access:1; |
0b2182dd SY |
200 | }; |
201 | ||
baf588f4 | 202 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
203 | { |
204 | iowrite8(data, rspi->addr + offset); | |
205 | } | |
206 | ||
baf588f4 | 207 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
208 | { |
209 | iowrite16(data, rspi->addr + offset); | |
210 | } | |
211 | ||
baf588f4 | 212 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
213 | { |
214 | iowrite32(data, rspi->addr + offset); | |
215 | } | |
216 | ||
baf588f4 | 217 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
218 | { |
219 | return ioread8(rspi->addr + offset); | |
220 | } | |
221 | ||
baf588f4 | 222 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
223 | { |
224 | return ioread16(rspi->addr + offset); | |
225 | } | |
226 | ||
74da7686 GU |
227 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
228 | { | |
229 | if (rspi->byte_access) | |
230 | rspi_write8(rspi, data, RSPI_SPDR); | |
231 | else /* 16 bit */ | |
232 | rspi_write16(rspi, data, RSPI_SPDR); | |
233 | } | |
234 | ||
235 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
236 | { | |
237 | if (rspi->byte_access) | |
238 | return rspi_read8(rspi, RSPI_SPDR); | |
239 | else /* 16 bit */ | |
240 | return rspi_read16(rspi, RSPI_SPDR); | |
241 | } | |
242 | ||
5ce0ba88 HCM |
243 | /* optional functions */ |
244 | struct spi_ops { | |
74da7686 | 245 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
eb557f75 GU |
246 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
247 | struct spi_transfer *xfer); | |
5ce0ba88 HCM |
248 | }; |
249 | ||
250 | /* | |
862d357f | 251 | * functions for RSPI on legacy SH |
5ce0ba88 | 252 | */ |
74da7686 | 253 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 254 | { |
5ce0ba88 HCM |
255 | int spbr; |
256 | ||
06a7a3cf GU |
257 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
258 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
0b2182dd | 259 | |
5ce0ba88 HCM |
260 | /* Sets transfer bit rate */ |
261 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
262 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
263 | ||
74da7686 GU |
264 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
265 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
266 | rspi->byte_access = 0; | |
0b2182dd | 267 | |
5ce0ba88 HCM |
268 | /* Sets RSPCK, SSL, next-access delay value */ |
269 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
270 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
271 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
272 | ||
273 | /* Sets parity, interrupt mask */ | |
274 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
275 | ||
276 | /* Sets SPCMD */ | |
348e5153 | 277 | rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, |
5ce0ba88 HCM |
278 | RSPI_SPCMD0); |
279 | ||
280 | /* Sets RSPI mode */ | |
281 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
282 | ||
283 | return 0; | |
0b2182dd SY |
284 | } |
285 | ||
862d357f GU |
286 | /* |
287 | * functions for RSPI on RZ | |
288 | */ | |
289 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) | |
290 | { | |
291 | int spbr; | |
292 | ||
06a7a3cf GU |
293 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
294 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
862d357f GU |
295 | |
296 | /* Sets transfer bit rate */ | |
297 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
298 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
299 | ||
300 | /* Disable dummy transmission, set byte access */ | |
301 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); | |
302 | rspi->byte_access = 1; | |
303 | ||
304 | /* Sets RSPCK, SSL, next-access delay value */ | |
305 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
306 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
307 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
308 | ||
309 | /* Sets SPCMD */ | |
310 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); | |
311 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
312 | ||
313 | /* Sets RSPI mode */ | |
314 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
5ce0ba88 HCM |
319 | /* |
320 | * functions for QSPI | |
321 | */ | |
74da7686 | 322 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 HCM |
323 | { |
324 | u16 spcmd; | |
325 | int spbr; | |
326 | ||
06a7a3cf GU |
327 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
328 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
5ce0ba88 HCM |
329 | |
330 | /* Sets transfer bit rate */ | |
331 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); | |
332 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
333 | ||
74da7686 GU |
334 | /* Disable dummy transmission, set byte access */ |
335 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
336 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
337 | |
338 | /* Sets RSPCK, SSL, next-access delay value */ | |
339 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
340 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
341 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
342 | ||
343 | /* Data Length Setting */ | |
344 | if (access_size == 8) | |
345 | spcmd = SPCMD_SPB_8BIT; | |
346 | else if (access_size == 16) | |
347 | spcmd = SPCMD_SPB_16BIT; | |
8e1c8096 | 348 | else |
5ce0ba88 HCM |
349 | spcmd = SPCMD_SPB_32BIT; |
350 | ||
348e5153 | 351 | spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; |
5ce0ba88 HCM |
352 | |
353 | /* Resets transfer data length */ | |
354 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
355 | ||
356 | /* Resets transmit and receive buffer */ | |
357 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
358 | /* Sets buffer to allow normal operation */ | |
359 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
360 | ||
361 | /* Sets SPCMD */ | |
362 | rspi_write16(rspi, spcmd, RSPI_SPCMD0); | |
363 | ||
364 | /* Enables SPI function in a master mode */ | |
365 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) | |
371 | ||
baf588f4 | 372 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
373 | { |
374 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
375 | } | |
376 | ||
baf588f4 | 377 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
378 | { |
379 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
380 | } | |
381 | ||
382 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
383 | u8 enable_bit) | |
384 | { | |
385 | int ret; | |
386 | ||
387 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
388 | rspi_enable_irq(rspi, enable_bit); | |
389 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
390 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
391 | return -ETIMEDOUT; | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
35301c99 GU |
396 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
397 | { | |
398 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
399 | dev_err(&rspi->master->dev, "transmit timeout\n"); | |
400 | return -ETIMEDOUT; | |
401 | } | |
402 | rspi_write_data(rspi, data); | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static int rspi_data_in(struct rspi_data *rspi) | |
407 | { | |
408 | u8 data; | |
409 | ||
410 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | |
411 | dev_err(&rspi->master->dev, "receive timeout\n"); | |
412 | return -ETIMEDOUT; | |
413 | } | |
414 | data = rspi_read_data(rspi); | |
415 | return data; | |
416 | } | |
417 | ||
418 | static int rspi_data_out_in(struct rspi_data *rspi, u8 data) | |
419 | { | |
420 | int ret; | |
421 | ||
422 | ret = rspi_data_out(rspi, data); | |
423 | if (ret < 0) | |
424 | return ret; | |
425 | ||
426 | return rspi_data_in(rspi); | |
427 | } | |
428 | ||
a3633fe7 SY |
429 | static void rspi_dma_complete(void *arg) |
430 | { | |
431 | struct rspi_data *rspi = arg; | |
432 | ||
433 | rspi->dma_callbacked = 1; | |
434 | wake_up_interruptible(&rspi->wait); | |
435 | } | |
436 | ||
c132f094 GU |
437 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
438 | unsigned len, struct dma_chan *chan, | |
a3633fe7 SY |
439 | enum dma_transfer_direction dir) |
440 | { | |
441 | sg_init_table(sg, 1); | |
442 | sg_set_buf(sg, buf, len); | |
443 | sg_dma_len(sg) = len; | |
444 | return dma_map_sg(chan->device->dev, sg, 1, dir); | |
445 | } | |
446 | ||
447 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, | |
448 | enum dma_transfer_direction dir) | |
449 | { | |
450 | dma_unmap_sg(chan->device->dev, sg, 1, dir); | |
451 | } | |
452 | ||
453 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) | |
454 | { | |
455 | u16 *dst = buf; | |
456 | const u8 *src = data; | |
457 | ||
458 | while (len) { | |
459 | *dst++ = (u16)(*src++); | |
460 | len--; | |
461 | } | |
462 | } | |
463 | ||
464 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) | |
465 | { | |
466 | u8 *dst = buf; | |
467 | const u16 *src = data; | |
468 | ||
469 | while (len) { | |
470 | *dst++ = (u8)*src++; | |
471 | len--; | |
472 | } | |
473 | } | |
474 | ||
475 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) | |
476 | { | |
477 | struct scatterlist sg; | |
c132f094 | 478 | const void *buf = NULL; |
a3633fe7 | 479 | struct dma_async_tx_descriptor *desc; |
93722206 | 480 | unsigned int len; |
a3633fe7 SY |
481 | int ret = 0; |
482 | ||
483 | if (rspi->dma_width_16bit) { | |
c132f094 | 484 | void *tmp; |
a3633fe7 SY |
485 | /* |
486 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
487 | * buffer. And, the driver converts original data into the | |
488 | * DMAC data as the following format: | |
489 | * original data: 1st byte, 2nd byte ... | |
490 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
491 | */ | |
492 | len = t->len * 2; | |
c132f094 GU |
493 | tmp = kmalloc(len, GFP_KERNEL); |
494 | if (!tmp) | |
a3633fe7 | 495 | return -ENOMEM; |
c132f094 GU |
496 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
497 | buf = tmp; | |
a3633fe7 SY |
498 | } else { |
499 | len = t->len; | |
c132f094 | 500 | buf = t->tx_buf; |
a3633fe7 SY |
501 | } |
502 | ||
503 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { | |
504 | ret = -EFAULT; | |
505 | goto end_nomap; | |
506 | } | |
507 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, | |
508 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
509 | if (!desc) { | |
510 | ret = -EIO; | |
511 | goto end; | |
512 | } | |
513 | ||
514 | /* | |
515 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
516 | * called. So, this driver disables the IRQ while DMA transfer. | |
517 | */ | |
93722206 | 518 | disable_irq(rspi->tx_irq); |
a3633fe7 SY |
519 | |
520 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); | |
521 | rspi_enable_irq(rspi, SPCR_SPTIE); | |
522 | rspi->dma_callbacked = 0; | |
523 | ||
524 | desc->callback = rspi_dma_complete; | |
525 | desc->callback_param = rspi; | |
526 | dmaengine_submit(desc); | |
527 | dma_async_issue_pending(rspi->chan_tx); | |
528 | ||
529 | ret = wait_event_interruptible_timeout(rspi->wait, | |
530 | rspi->dma_callbacked, HZ); | |
531 | if (ret > 0 && rspi->dma_callbacked) | |
532 | ret = 0; | |
533 | else if (!ret) | |
534 | ret = -ETIMEDOUT; | |
535 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
536 | ||
93722206 | 537 | enable_irq(rspi->tx_irq); |
a3633fe7 SY |
538 | |
539 | end: | |
540 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); | |
541 | end_nomap: | |
542 | if (rspi->dma_width_16bit) | |
543 | kfree(buf); | |
544 | ||
545 | return ret; | |
546 | } | |
547 | ||
baf588f4 | 548 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 549 | { |
97b95c11 | 550 | u8 spsr; |
0b2182dd SY |
551 | |
552 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
553 | if (spsr & SPSR_SPRF) | |
74da7686 | 554 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
555 | if (spsr & SPSR_OVRF) |
556 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 557 | RSPI_SPSR); |
a3633fe7 SY |
558 | } |
559 | ||
862d357f GU |
560 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
561 | { | |
562 | rspi_receive_init(rspi); | |
563 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); | |
564 | rspi_write8(rspi, 0, RSPI_SPBFCR); | |
565 | } | |
566 | ||
baf588f4 | 567 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 568 | { |
97b95c11 | 569 | u8 spsr; |
cb52c673 HCM |
570 | |
571 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
572 | if (spsr & SPSR_SPRF) | |
74da7686 | 573 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 574 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 575 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
576 | } |
577 | ||
a3633fe7 SY |
578 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
579 | { | |
580 | struct scatterlist sg, sg_dummy; | |
581 | void *dummy = NULL, *rx_buf = NULL; | |
582 | struct dma_async_tx_descriptor *desc, *desc_dummy; | |
93722206 | 583 | unsigned int len; |
a3633fe7 SY |
584 | int ret = 0; |
585 | ||
586 | if (rspi->dma_width_16bit) { | |
587 | /* | |
588 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
589 | * buffer. And, finally the driver converts the DMAC data into | |
590 | * actual data as the following format: | |
591 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
592 | * actual data: 1st byte, 2nd byte ... | |
593 | */ | |
594 | len = t->len * 2; | |
595 | rx_buf = kmalloc(len, GFP_KERNEL); | |
596 | if (!rx_buf) | |
597 | return -ENOMEM; | |
598 | } else { | |
599 | len = t->len; | |
600 | rx_buf = t->rx_buf; | |
601 | } | |
602 | ||
603 | /* prepare dummy transfer to generate SPI clocks */ | |
604 | dummy = kzalloc(len, GFP_KERNEL); | |
605 | if (!dummy) { | |
606 | ret = -ENOMEM; | |
607 | goto end_nomap; | |
608 | } | |
609 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, | |
610 | DMA_TO_DEVICE)) { | |
611 | ret = -EFAULT; | |
612 | goto end_nomap; | |
613 | } | |
614 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, | |
615 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
616 | if (!desc_dummy) { | |
617 | ret = -EIO; | |
618 | goto end_dummy_mapped; | |
619 | } | |
620 | ||
621 | /* prepare receive transfer */ | |
622 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, | |
623 | DMA_FROM_DEVICE)) { | |
624 | ret = -EFAULT; | |
625 | goto end_dummy_mapped; | |
626 | ||
627 | } | |
628 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, | |
629 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
630 | if (!desc) { | |
631 | ret = -EIO; | |
632 | goto end; | |
633 | } | |
634 | ||
635 | rspi_receive_init(rspi); | |
636 | ||
637 | /* | |
638 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
639 | * called. So, this driver disables the IRQ while DMA transfer. | |
640 | */ | |
93722206 GU |
641 | disable_irq(rspi->tx_irq); |
642 | if (rspi->rx_irq != rspi->tx_irq) | |
643 | disable_irq(rspi->rx_irq); | |
a3633fe7 SY |
644 | |
645 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); | |
646 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
647 | rspi->dma_callbacked = 0; | |
648 | ||
649 | desc->callback = rspi_dma_complete; | |
650 | desc->callback_param = rspi; | |
651 | dmaengine_submit(desc); | |
652 | dma_async_issue_pending(rspi->chan_rx); | |
653 | ||
654 | desc_dummy->callback = NULL; /* No callback */ | |
655 | dmaengine_submit(desc_dummy); | |
656 | dma_async_issue_pending(rspi->chan_tx); | |
657 | ||
658 | ret = wait_event_interruptible_timeout(rspi->wait, | |
659 | rspi->dma_callbacked, HZ); | |
660 | if (ret > 0 && rspi->dma_callbacked) | |
661 | ret = 0; | |
662 | else if (!ret) | |
663 | ret = -ETIMEDOUT; | |
664 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
665 | ||
93722206 GU |
666 | enable_irq(rspi->tx_irq); |
667 | if (rspi->rx_irq != rspi->tx_irq) | |
668 | enable_irq(rspi->rx_irq); | |
a3633fe7 SY |
669 | |
670 | end: | |
671 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); | |
672 | end_dummy_mapped: | |
673 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); | |
674 | end_nomap: | |
675 | if (rspi->dma_width_16bit) { | |
676 | if (!ret) | |
677 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); | |
678 | kfree(rx_buf); | |
679 | } | |
680 | kfree(dummy); | |
681 | ||
682 | return ret; | |
683 | } | |
684 | ||
baf588f4 | 685 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
a3633fe7 SY |
686 | { |
687 | if (t->tx_buf && rspi->chan_tx) | |
688 | return 1; | |
689 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
690 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) | |
691 | return 1; | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
8449fd76 GU |
696 | static int rspi_transfer_out_in(struct rspi_data *rspi, |
697 | struct spi_transfer *xfer) | |
698 | { | |
699 | int remain = xfer->len, ret; | |
700 | const u8 *tx_buf = xfer->tx_buf; | |
701 | u8 *rx_buf = xfer->rx_buf; | |
702 | u8 spcr, data; | |
703 | ||
704 | rspi_receive_init(rspi); | |
705 | ||
706 | spcr = rspi_read8(rspi, RSPI_SPCR); | |
707 | if (rx_buf) | |
708 | spcr &= ~SPCR_TXMD; | |
709 | else | |
710 | spcr |= SPCR_TXMD; | |
711 | rspi_write8(rspi, spcr, RSPI_SPCR); | |
712 | ||
713 | while (remain > 0) { | |
714 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
715 | ret = rspi_data_out(rspi, data); | |
716 | if (ret < 0) | |
717 | return ret; | |
718 | if (rx_buf) { | |
719 | ret = rspi_data_in(rspi); | |
720 | if (ret < 0) | |
721 | return ret; | |
722 | *rx_buf++ = ret; | |
723 | } | |
724 | remain--; | |
725 | } | |
726 | ||
727 | /* Wait for the last transmission */ | |
728 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
79d23495 GU |
733 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
734 | struct spi_transfer *xfer) | |
0b2182dd | 735 | { |
79d23495 | 736 | struct rspi_data *rspi = spi_master_get_devdata(master); |
8449fd76 GU |
737 | int ret; |
738 | ||
739 | if (!rspi_is_dma(rspi, xfer)) | |
740 | return rspi_transfer_out_in(rspi, xfer); | |
0b2182dd | 741 | |
79d23495 | 742 | if (xfer->tx_buf) { |
8449fd76 | 743 | ret = rspi_send_dma(rspi, xfer); |
79d23495 GU |
744 | if (ret < 0) |
745 | return ret; | |
0b2182dd | 746 | } |
8449fd76 GU |
747 | if (xfer->rx_buf) |
748 | return rspi_receive_dma(rspi, xfer); | |
749 | ||
750 | return 0; | |
eb557f75 GU |
751 | } |
752 | ||
862d357f GU |
753 | static int rspi_rz_transfer_out_in(struct rspi_data *rspi, |
754 | struct spi_transfer *xfer) | |
755 | { | |
756 | int remain = xfer->len, ret; | |
757 | const u8 *tx_buf = xfer->tx_buf; | |
758 | u8 *rx_buf = xfer->rx_buf; | |
759 | u8 data; | |
760 | ||
761 | rspi_rz_receive_init(rspi); | |
762 | ||
763 | while (remain > 0) { | |
764 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
765 | ret = rspi_data_out_in(rspi, data); | |
766 | if (ret < 0) | |
767 | return ret; | |
768 | if (rx_buf) | |
769 | *rx_buf++ = ret; | |
770 | remain--; | |
771 | } | |
772 | ||
773 | /* Wait for the last transmission */ | |
774 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
779 | static int rspi_rz_transfer_one(struct spi_master *master, | |
780 | struct spi_device *spi, | |
781 | struct spi_transfer *xfer) | |
782 | { | |
783 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
784 | ||
785 | return rspi_rz_transfer_out_in(rspi, xfer); | |
786 | } | |
787 | ||
340a15e6 GU |
788 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
789 | struct spi_transfer *xfer) | |
eb557f75 | 790 | { |
340a15e6 GU |
791 | int remain = xfer->len, ret; |
792 | const u8 *tx_buf = xfer->tx_buf; | |
793 | u8 *rx_buf = xfer->rx_buf; | |
794 | u8 data; | |
eb557f75 | 795 | |
340a15e6 GU |
796 | qspi_receive_init(rspi); |
797 | ||
798 | while (remain > 0) { | |
799 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
800 | ret = rspi_data_out_in(rspi, data); | |
eb557f75 GU |
801 | if (ret < 0) |
802 | return ret; | |
340a15e6 GU |
803 | if (rx_buf) |
804 | *rx_buf++ = ret; | |
805 | remain--; | |
79d23495 | 806 | } |
340a15e6 GU |
807 | |
808 | /* Wait for the last transmission */ | |
809 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, | |
815 | struct spi_transfer *xfer) | |
816 | { | |
817 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
818 | ||
819 | return qspi_transfer_out_in(rspi, xfer); | |
0b2182dd SY |
820 | } |
821 | ||
822 | static int rspi_setup(struct spi_device *spi) | |
823 | { | |
824 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | |
825 | ||
0b2182dd SY |
826 | rspi->max_speed_hz = spi->max_speed_hz; |
827 | ||
348e5153 GU |
828 | rspi->spcmd = SPCMD_SSLKP; |
829 | if (spi->mode & SPI_CPOL) | |
830 | rspi->spcmd |= SPCMD_CPOL; | |
831 | if (spi->mode & SPI_CPHA) | |
832 | rspi->spcmd |= SPCMD_CPHA; | |
833 | ||
06a7a3cf GU |
834 | /* CMOS output mode and MOSI signal from previous transfer */ |
835 | rspi->sppcr = 0; | |
836 | if (spi->mode & SPI_LOOP) | |
837 | rspi->sppcr |= SPPCR_SPLP; | |
838 | ||
5ce0ba88 | 839 | set_config_register(rspi, 8); |
0b2182dd SY |
840 | |
841 | return 0; | |
842 | } | |
843 | ||
79d23495 | 844 | static void rspi_cleanup(struct spi_device *spi) |
0b2182dd | 845 | { |
79d23495 | 846 | } |
0b2182dd | 847 | |
79d23495 GU |
848 | static int rspi_prepare_message(struct spi_master *master, |
849 | struct spi_message *message) | |
850 | { | |
851 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
0b2182dd | 852 | |
79d23495 | 853 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
854 | return 0; |
855 | } | |
856 | ||
79d23495 GU |
857 | static int rspi_unprepare_message(struct spi_master *master, |
858 | struct spi_message *message) | |
0b2182dd | 859 | { |
79d23495 GU |
860 | struct rspi_data *rspi = spi_master_get_devdata(master); |
861 | ||
862 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); | |
863 | return 0; | |
0b2182dd SY |
864 | } |
865 | ||
93722206 | 866 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
0b2182dd | 867 | { |
c132f094 | 868 | struct rspi_data *rspi = _sr; |
97b95c11 | 869 | u8 spsr; |
0b2182dd | 870 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 871 | u8 disable_irq = 0; |
0b2182dd SY |
872 | |
873 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
874 | if (spsr & SPSR_SPRF) | |
875 | disable_irq |= SPCR_SPRIE; | |
876 | if (spsr & SPSR_SPTEF) | |
877 | disable_irq |= SPCR_SPTIE; | |
878 | ||
879 | if (disable_irq) { | |
880 | ret = IRQ_HANDLED; | |
881 | rspi_disable_irq(rspi, disable_irq); | |
882 | wake_up(&rspi->wait); | |
883 | } | |
884 | ||
885 | return ret; | |
886 | } | |
887 | ||
93722206 GU |
888 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
889 | { | |
890 | struct rspi_data *rspi = _sr; | |
891 | u8 spsr; | |
892 | ||
893 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
894 | if (spsr & SPSR_SPRF) { | |
895 | rspi_disable_irq(rspi, SPCR_SPRIE); | |
896 | wake_up(&rspi->wait); | |
897 | return IRQ_HANDLED; | |
898 | } | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
903 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) | |
904 | { | |
905 | struct rspi_data *rspi = _sr; | |
906 | u8 spsr; | |
907 | ||
908 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
909 | if (spsr & SPSR_SPTEF) { | |
910 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
911 | wake_up(&rspi->wait); | |
912 | return IRQ_HANDLED; | |
913 | } | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
fd4a319b | 918 | static int rspi_request_dma(struct rspi_data *rspi, |
0243c536 | 919 | struct platform_device *pdev) |
a3633fe7 | 920 | { |
baf588f4 | 921 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
e2b05099 | 922 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3633fe7 | 923 | dma_cap_mask_t mask; |
0243c536 SY |
924 | struct dma_slave_config cfg; |
925 | int ret; | |
a3633fe7 | 926 | |
e2b05099 | 927 | if (!res || !rspi_pd) |
0243c536 | 928 | return 0; /* The driver assumes no error. */ |
a3633fe7 SY |
929 | |
930 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; | |
931 | ||
932 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
933 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { | |
934 | dma_cap_zero(mask); | |
935 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
936 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
937 | (void *)rspi_pd->dma_rx_id); | |
938 | if (rspi->chan_rx) { | |
939 | cfg.slave_id = rspi_pd->dma_rx_id; | |
940 | cfg.direction = DMA_DEV_TO_MEM; | |
e2b05099 GL |
941 | cfg.dst_addr = 0; |
942 | cfg.src_addr = res->start + RSPI_SPDR; | |
0243c536 SY |
943 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
944 | if (!ret) | |
945 | dev_info(&pdev->dev, "Use DMA when rx.\n"); | |
946 | else | |
947 | return ret; | |
948 | } | |
a3633fe7 SY |
949 | } |
950 | if (rspi_pd->dma_tx_id) { | |
951 | dma_cap_zero(mask); | |
952 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
953 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
954 | (void *)rspi_pd->dma_tx_id); | |
955 | if (rspi->chan_tx) { | |
956 | cfg.slave_id = rspi_pd->dma_tx_id; | |
957 | cfg.direction = DMA_MEM_TO_DEV; | |
e2b05099 GL |
958 | cfg.dst_addr = res->start + RSPI_SPDR; |
959 | cfg.src_addr = 0; | |
0243c536 SY |
960 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
961 | if (!ret) | |
962 | dev_info(&pdev->dev, "Use DMA when tx\n"); | |
963 | else | |
964 | return ret; | |
965 | } | |
a3633fe7 | 966 | } |
0243c536 SY |
967 | |
968 | return 0; | |
a3633fe7 SY |
969 | } |
970 | ||
fd4a319b | 971 | static void rspi_release_dma(struct rspi_data *rspi) |
a3633fe7 SY |
972 | { |
973 | if (rspi->chan_tx) | |
974 | dma_release_channel(rspi->chan_tx); | |
975 | if (rspi->chan_rx) | |
976 | dma_release_channel(rspi->chan_rx); | |
977 | } | |
978 | ||
fd4a319b | 979 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 980 | { |
5ffbe2d9 | 981 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 982 | |
a3633fe7 | 983 | rspi_release_dma(rspi); |
17fe0d9a | 984 | clk_disable_unprepare(rspi->clk); |
0b2182dd SY |
985 | |
986 | return 0; | |
987 | } | |
988 | ||
426ef76d GU |
989 | static const struct spi_ops rspi_ops = { |
990 | .set_config_register = rspi_set_config_register, | |
991 | .transfer_one = rspi_transfer_one, | |
992 | }; | |
993 | ||
994 | static const struct spi_ops rspi_rz_ops = { | |
995 | .set_config_register = rspi_rz_set_config_register, | |
996 | .transfer_one = rspi_rz_transfer_one, | |
997 | }; | |
998 | ||
999 | static const struct spi_ops qspi_ops = { | |
1000 | .set_config_register = qspi_set_config_register, | |
1001 | .transfer_one = qspi_transfer_one, | |
1002 | }; | |
1003 | ||
1004 | #ifdef CONFIG_OF | |
1005 | static const struct of_device_id rspi_of_match[] = { | |
1006 | /* RSPI on legacy SH */ | |
1007 | { .compatible = "renesas,rspi", .data = &rspi_ops }, | |
1008 | /* RSPI on RZ/A1H */ | |
1009 | { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, | |
1010 | /* QSPI on R-Car Gen2 */ | |
1011 | { .compatible = "renesas,qspi", .data = &qspi_ops }, | |
1012 | { /* sentinel */ } | |
1013 | }; | |
1014 | ||
1015 | MODULE_DEVICE_TABLE(of, rspi_of_match); | |
1016 | ||
1017 | static int rspi_parse_dt(struct device *dev, struct spi_master *master) | |
1018 | { | |
1019 | u32 num_cs; | |
1020 | int error; | |
1021 | ||
1022 | /* Parse DT properties */ | |
1023 | error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); | |
1024 | if (error) { | |
1025 | dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); | |
1026 | return error; | |
1027 | } | |
1028 | ||
1029 | master->num_chipselect = num_cs; | |
1030 | return 0; | |
1031 | } | |
1032 | #else | |
1033 | static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) | |
1034 | { | |
1035 | return -EINVAL; | |
1036 | } | |
1037 | #endif /* CONFIG_OF */ | |
1038 | ||
93722206 GU |
1039 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
1040 | irq_handler_t handler, const char *suffix, | |
1041 | void *dev_id) | |
1042 | { | |
1043 | const char *base = dev_name(dev); | |
1044 | size_t len = strlen(base) + strlen(suffix) + 2; | |
1045 | char *name = devm_kzalloc(dev, len, GFP_KERNEL); | |
1046 | if (!name) | |
1047 | return -ENOMEM; | |
1048 | snprintf(name, len, "%s:%s", base, suffix); | |
1049 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); | |
1050 | } | |
1051 | ||
fd4a319b | 1052 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
1053 | { |
1054 | struct resource *res; | |
1055 | struct spi_master *master; | |
1056 | struct rspi_data *rspi; | |
93722206 | 1057 | int ret; |
426ef76d GU |
1058 | const struct of_device_id *of_id; |
1059 | const struct rspi_plat_data *rspi_pd; | |
5ce0ba88 | 1060 | const struct spi_ops *ops; |
0b2182dd | 1061 | |
0b2182dd SY |
1062 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
1063 | if (master == NULL) { | |
1064 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
1065 | return -ENOMEM; | |
1066 | } | |
1067 | ||
426ef76d GU |
1068 | of_id = of_match_device(rspi_of_match, &pdev->dev); |
1069 | if (of_id) { | |
1070 | ops = of_id->data; | |
1071 | ret = rspi_parse_dt(&pdev->dev, master); | |
1072 | if (ret) | |
1073 | goto error1; | |
1074 | } else { | |
1075 | ops = (struct spi_ops *)pdev->id_entry->driver_data; | |
1076 | rspi_pd = dev_get_platdata(&pdev->dev); | |
1077 | if (rspi_pd && rspi_pd->num_chipselect) | |
1078 | master->num_chipselect = rspi_pd->num_chipselect; | |
1079 | else | |
1080 | master->num_chipselect = 2; /* default */ | |
1081 | }; | |
1082 | ||
1083 | /* ops parameter check */ | |
1084 | if (!ops->set_config_register) { | |
1085 | dev_err(&pdev->dev, "there is no set_config_register\n"); | |
1086 | ret = -ENODEV; | |
1087 | goto error1; | |
1088 | } | |
1089 | ||
0b2182dd | 1090 | rspi = spi_master_get_devdata(master); |
24b5a82c | 1091 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 1092 | rspi->ops = ops; |
0b2182dd | 1093 | rspi->master = master; |
5d79e9ac LP |
1094 | |
1095 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1096 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
1097 | if (IS_ERR(rspi->addr)) { | |
1098 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
1099 | goto error1; |
1100 | } | |
1101 | ||
29f397b7 | 1102 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
0b2182dd SY |
1103 | if (IS_ERR(rspi->clk)) { |
1104 | dev_err(&pdev->dev, "cannot get clock\n"); | |
1105 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 1106 | goto error1; |
0b2182dd | 1107 | } |
17fe0d9a GU |
1108 | |
1109 | ret = clk_prepare_enable(rspi->clk); | |
1110 | if (ret < 0) { | |
1111 | dev_err(&pdev->dev, "unable to prepare/enable clock\n"); | |
1112 | goto error1; | |
1113 | } | |
0b2182dd | 1114 | |
0b2182dd SY |
1115 | init_waitqueue_head(&rspi->wait); |
1116 | ||
0b2182dd SY |
1117 | master->bus_num = pdev->id; |
1118 | master->setup = rspi_setup; | |
eb557f75 | 1119 | master->transfer_one = ops->transfer_one; |
0b2182dd | 1120 | master->cleanup = rspi_cleanup; |
79d23495 GU |
1121 | master->prepare_message = rspi_prepare_message; |
1122 | master->unprepare_message = rspi_unprepare_message; | |
06a7a3cf | 1123 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP; |
426ef76d | 1124 | master->dev.of_node = pdev->dev.of_node; |
0b2182dd | 1125 | |
93722206 GU |
1126 | ret = platform_get_irq_byname(pdev, "rx"); |
1127 | if (ret < 0) { | |
1128 | ret = platform_get_irq_byname(pdev, "mux"); | |
1129 | if (ret < 0) | |
1130 | ret = platform_get_irq(pdev, 0); | |
1131 | if (ret >= 0) | |
1132 | rspi->rx_irq = rspi->tx_irq = ret; | |
1133 | } else { | |
1134 | rspi->rx_irq = ret; | |
1135 | ret = platform_get_irq_byname(pdev, "tx"); | |
1136 | if (ret >= 0) | |
1137 | rspi->tx_irq = ret; | |
1138 | } | |
1139 | if (ret < 0) { | |
1140 | dev_err(&pdev->dev, "platform_get_irq error\n"); | |
1141 | goto error2; | |
1142 | } | |
1143 | ||
1144 | if (rspi->rx_irq == rspi->tx_irq) { | |
1145 | /* Single multiplexed interrupt */ | |
1146 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, | |
1147 | "mux", rspi); | |
1148 | } else { | |
1149 | /* Multi-interrupt mode, only SPRI and SPTI are used */ | |
1150 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, | |
1151 | "rx", rspi); | |
1152 | if (!ret) | |
1153 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, | |
1154 | rspi_irq_tx, "tx", rspi); | |
1155 | } | |
0b2182dd SY |
1156 | if (ret < 0) { |
1157 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 1158 | goto error2; |
0b2182dd SY |
1159 | } |
1160 | ||
0243c536 SY |
1161 | ret = rspi_request_dma(rspi, pdev); |
1162 | if (ret < 0) { | |
1163 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); | |
fcb4ed74 | 1164 | goto error3; |
0243c536 | 1165 | } |
a3633fe7 | 1166 | |
9e03d05e | 1167 | ret = devm_spi_register_master(&pdev->dev, master); |
0b2182dd SY |
1168 | if (ret < 0) { |
1169 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
fcb4ed74 | 1170 | goto error3; |
0b2182dd SY |
1171 | } |
1172 | ||
1173 | dev_info(&pdev->dev, "probed\n"); | |
1174 | ||
1175 | return 0; | |
1176 | ||
fcb4ed74 | 1177 | error3: |
5d79e9ac | 1178 | rspi_release_dma(rspi); |
fcb4ed74 | 1179 | error2: |
17fe0d9a | 1180 | clk_disable_unprepare(rspi->clk); |
0b2182dd SY |
1181 | error1: |
1182 | spi_master_put(master); | |
1183 | ||
1184 | return ret; | |
1185 | } | |
1186 | ||
5ce0ba88 HCM |
1187 | static struct platform_device_id spi_driver_ids[] = { |
1188 | { "rspi", (kernel_ulong_t)&rspi_ops }, | |
862d357f | 1189 | { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, |
5ce0ba88 HCM |
1190 | { "qspi", (kernel_ulong_t)&qspi_ops }, |
1191 | {}, | |
1192 | }; | |
1193 | ||
1194 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1195 | ||
0b2182dd SY |
1196 | static struct platform_driver rspi_driver = { |
1197 | .probe = rspi_probe, | |
fd4a319b | 1198 | .remove = rspi_remove, |
5ce0ba88 | 1199 | .id_table = spi_driver_ids, |
0b2182dd | 1200 | .driver = { |
5ce0ba88 | 1201 | .name = "renesas_spi", |
0b2182dd | 1202 | .owner = THIS_MODULE, |
426ef76d | 1203 | .of_match_table = of_match_ptr(rspi_of_match), |
0b2182dd SY |
1204 | }, |
1205 | }; | |
1206 | module_platform_driver(rspi_driver); | |
1207 | ||
1208 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1209 | MODULE_LICENSE("GPL v2"); | |
1210 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1211 | MODULE_ALIAS("platform:rspi"); |