]>
Commit | Line | Data |
---|---|---|
0b2182dd SY |
1 | /* |
2 | * SH RSPI driver | |
3 | * | |
93722206 | 4 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
880c6d11 | 5 | * Copyright (C) 2014 Glider bvba |
0b2182dd SY |
6 | * |
7 | * Based on spi-sh.c: | |
8 | * Copyright (C) 2011 Renesas Solutions Corp. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/errno.h> | |
0b2182dd SY |
29 | #include <linux/interrupt.h> |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/clk.h> | |
a3633fe7 SY |
33 | #include <linux/dmaengine.h> |
34 | #include <linux/dma-mapping.h> | |
426ef76d | 35 | #include <linux/of_device.h> |
490c9774 | 36 | #include <linux/pm_runtime.h> |
a3633fe7 | 37 | #include <linux/sh_dma.h> |
0b2182dd | 38 | #include <linux/spi/spi.h> |
a3633fe7 | 39 | #include <linux/spi/rspi.h> |
0b2182dd | 40 | |
6ab4865b GU |
41 | #define RSPI_SPCR 0x00 /* Control Register */ |
42 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
43 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
44 | #define RSPI_SPSR 0x03 /* Status Register */ | |
45 | #define RSPI_SPDR 0x04 /* Data Register */ | |
46 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
47 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
48 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
49 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
50 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
51 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
52 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
862d357f | 53 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
6ab4865b GU |
54 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
55 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
56 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
57 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
58 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
59 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
60 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
61 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
880c6d11 GU |
62 | #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) |
63 | #define RSPI_NUM_SPCMD 8 | |
64 | #define RSPI_RZ_NUM_SPCMD 4 | |
65 | #define QSPI_NUM_SPCMD 4 | |
862d357f GU |
66 | |
67 | /* RSPI on RZ only */ | |
6ab4865b GU |
68 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
69 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 70 | |
862d357f | 71 | /* QSPI only */ |
fbe5072b GU |
72 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
73 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
74 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
75 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
76 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
77 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
880c6d11 | 78 | #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) |
5ce0ba88 | 79 | |
6ab4865b GU |
80 | /* SPCR - Control Register */ |
81 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
82 | #define SPCR_SPE 0x40 /* Function Enable */ | |
83 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
84 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
85 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
86 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
87 | /* RSPI on SH only */ | |
88 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
89 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
fbe5072b GU |
90 | /* QSPI on R-Car M2 only */ |
91 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ | |
92 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
93 | |
94 | /* SSLP - Slave Select Polarity Register */ | |
95 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ | |
96 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ | |
97 | ||
98 | /* SPPCR - Pin Control Register */ | |
99 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
100 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 101 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
102 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
103 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
104 | ||
fbe5072b GU |
105 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
106 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
107 | ||
6ab4865b GU |
108 | /* SPSR - Status Register */ |
109 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
110 | #define SPSR_TEND 0x40 /* Transmit End */ | |
111 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
112 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
113 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
114 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
862d357f | 115 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
6ab4865b GU |
116 | |
117 | /* SPSCR - Sequence Control Register */ | |
118 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
119 | ||
120 | /* SPSSR - Sequence Status Register */ | |
121 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
122 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
123 | ||
124 | /* SPDCR - Data Control Register */ | |
125 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
126 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
127 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
128 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
129 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
130 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
131 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
862d357f | 132 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
0b2182dd SY |
133 | #define SPDCR_SLSEL1 0x08 |
134 | #define SPDCR_SLSEL0 0x04 | |
862d357f | 135 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
0b2182dd SY |
136 | #define SPDCR_SPFC1 0x02 |
137 | #define SPDCR_SPFC0 0x01 | |
862d357f | 138 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
0b2182dd | 139 | |
6ab4865b GU |
140 | /* SPCKD - Clock Delay Register */ |
141 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 142 | |
6ab4865b GU |
143 | /* SSLND - Slave Select Negation Delay Register */ |
144 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 145 | |
6ab4865b GU |
146 | /* SPND - Next-Access Delay Register */ |
147 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 148 | |
6ab4865b GU |
149 | /* SPCR2 - Control Register 2 */ |
150 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
151 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
152 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
153 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 154 | |
6ab4865b GU |
155 | /* SPCMDn - Command Registers */ |
156 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
157 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
158 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
159 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
160 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 161 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
880c6d11 | 162 | #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ |
5ce0ba88 | 163 | #define SPCMD_SPB_16BIT 0x0100 |
0b2182dd SY |
164 | #define SPCMD_SPB_20BIT 0x0000 |
165 | #define SPCMD_SPB_24BIT 0x0100 | |
166 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 167 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
168 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
169 | #define SPCMD_SPIMOD1 0x0040 | |
170 | #define SPCMD_SPIMOD0 0x0020 | |
171 | #define SPCMD_SPIMOD_SINGLE 0 | |
172 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
173 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
174 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
6ab4865b GU |
175 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
176 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ | |
177 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ | |
178 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
179 | ||
180 | /* SPBFCR - Buffer Control Register */ | |
862d357f GU |
181 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
182 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ | |
6ab4865b GU |
183 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
184 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
5ce0ba88 | 185 | |
2aae80b2 GU |
186 | #define DUMMY_DATA 0x00 |
187 | ||
0b2182dd SY |
188 | struct rspi_data { |
189 | void __iomem *addr; | |
190 | u32 max_speed_hz; | |
191 | struct spi_master *master; | |
0b2182dd | 192 | wait_queue_head_t wait; |
0b2182dd | 193 | struct clk *clk; |
348e5153 | 194 | u16 spcmd; |
06a7a3cf GU |
195 | u8 spsr; |
196 | u8 sppcr; | |
93722206 | 197 | int rx_irq, tx_irq; |
5ce0ba88 | 198 | const struct spi_ops *ops; |
a3633fe7 SY |
199 | |
200 | /* for dmaengine */ | |
a3633fe7 SY |
201 | struct dma_chan *chan_tx; |
202 | struct dma_chan *chan_rx; | |
a3633fe7 SY |
203 | |
204 | unsigned dma_width_16bit:1; | |
205 | unsigned dma_callbacked:1; | |
74da7686 | 206 | unsigned byte_access:1; |
0b2182dd SY |
207 | }; |
208 | ||
baf588f4 | 209 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
210 | { |
211 | iowrite8(data, rspi->addr + offset); | |
212 | } | |
213 | ||
baf588f4 | 214 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
215 | { |
216 | iowrite16(data, rspi->addr + offset); | |
217 | } | |
218 | ||
baf588f4 | 219 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
220 | { |
221 | iowrite32(data, rspi->addr + offset); | |
222 | } | |
223 | ||
baf588f4 | 224 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
225 | { |
226 | return ioread8(rspi->addr + offset); | |
227 | } | |
228 | ||
baf588f4 | 229 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
230 | { |
231 | return ioread16(rspi->addr + offset); | |
232 | } | |
233 | ||
74da7686 GU |
234 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
235 | { | |
236 | if (rspi->byte_access) | |
237 | rspi_write8(rspi, data, RSPI_SPDR); | |
238 | else /* 16 bit */ | |
239 | rspi_write16(rspi, data, RSPI_SPDR); | |
240 | } | |
241 | ||
242 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
243 | { | |
244 | if (rspi->byte_access) | |
245 | return rspi_read8(rspi, RSPI_SPDR); | |
246 | else /* 16 bit */ | |
247 | return rspi_read16(rspi, RSPI_SPDR); | |
248 | } | |
249 | ||
5ce0ba88 HCM |
250 | /* optional functions */ |
251 | struct spi_ops { | |
74da7686 | 252 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
eb557f75 GU |
253 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
254 | struct spi_transfer *xfer); | |
880c6d11 | 255 | u16 mode_bits; |
5ce0ba88 HCM |
256 | }; |
257 | ||
258 | /* | |
862d357f | 259 | * functions for RSPI on legacy SH |
5ce0ba88 | 260 | */ |
74da7686 | 261 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 262 | { |
5ce0ba88 HCM |
263 | int spbr; |
264 | ||
06a7a3cf GU |
265 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
266 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
0b2182dd | 267 | |
5ce0ba88 | 268 | /* Sets transfer bit rate */ |
3beb61db GU |
269 | spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), |
270 | 2 * rspi->max_speed_hz) - 1; | |
5ce0ba88 HCM |
271 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
272 | ||
74da7686 GU |
273 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
274 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
275 | rspi->byte_access = 0; | |
0b2182dd | 276 | |
5ce0ba88 HCM |
277 | /* Sets RSPCK, SSL, next-access delay value */ |
278 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
279 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
280 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
281 | ||
282 | /* Sets parity, interrupt mask */ | |
283 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
284 | ||
285 | /* Sets SPCMD */ | |
880c6d11 GU |
286 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
287 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
5ce0ba88 HCM |
288 | |
289 | /* Sets RSPI mode */ | |
290 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
291 | ||
292 | return 0; | |
0b2182dd SY |
293 | } |
294 | ||
862d357f GU |
295 | /* |
296 | * functions for RSPI on RZ | |
297 | */ | |
298 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) | |
299 | { | |
300 | int spbr; | |
301 | ||
06a7a3cf GU |
302 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
303 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
862d357f GU |
304 | |
305 | /* Sets transfer bit rate */ | |
3beb61db GU |
306 | spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), |
307 | 2 * rspi->max_speed_hz) - 1; | |
862d357f GU |
308 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
309 | ||
310 | /* Disable dummy transmission, set byte access */ | |
311 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); | |
312 | rspi->byte_access = 1; | |
313 | ||
314 | /* Sets RSPCK, SSL, next-access delay value */ | |
315 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
316 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
317 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
318 | ||
319 | /* Sets SPCMD */ | |
320 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); | |
321 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
322 | ||
323 | /* Sets RSPI mode */ | |
324 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
5ce0ba88 HCM |
329 | /* |
330 | * functions for QSPI | |
331 | */ | |
74da7686 | 332 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 | 333 | { |
5ce0ba88 HCM |
334 | int spbr; |
335 | ||
06a7a3cf GU |
336 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
337 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
5ce0ba88 HCM |
338 | |
339 | /* Sets transfer bit rate */ | |
3beb61db | 340 | spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz); |
5ce0ba88 HCM |
341 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
342 | ||
74da7686 GU |
343 | /* Disable dummy transmission, set byte access */ |
344 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
345 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
346 | |
347 | /* Sets RSPCK, SSL, next-access delay value */ | |
348 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
349 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
350 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
351 | ||
352 | /* Data Length Setting */ | |
353 | if (access_size == 8) | |
880c6d11 | 354 | rspi->spcmd |= SPCMD_SPB_8BIT; |
5ce0ba88 | 355 | else if (access_size == 16) |
880c6d11 | 356 | rspi->spcmd |= SPCMD_SPB_16BIT; |
8e1c8096 | 357 | else |
880c6d11 | 358 | rspi->spcmd |= SPCMD_SPB_32BIT; |
5ce0ba88 | 359 | |
880c6d11 | 360 | rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; |
5ce0ba88 HCM |
361 | |
362 | /* Resets transfer data length */ | |
363 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
364 | ||
365 | /* Resets transmit and receive buffer */ | |
366 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
367 | /* Sets buffer to allow normal operation */ | |
368 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
369 | ||
370 | /* Sets SPCMD */ | |
880c6d11 | 371 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
5ce0ba88 | 372 | |
880c6d11 | 373 | /* Enables SPI function in master mode */ |
5ce0ba88 HCM |
374 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) | |
380 | ||
baf588f4 | 381 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
382 | { |
383 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
384 | } | |
385 | ||
baf588f4 | 386 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
387 | { |
388 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
389 | } | |
390 | ||
391 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
392 | u8 enable_bit) | |
393 | { | |
394 | int ret; | |
395 | ||
396 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
5dd1ad23 GU |
397 | if (rspi->spsr & wait_mask) |
398 | return 0; | |
399 | ||
0b2182dd SY |
400 | rspi_enable_irq(rspi, enable_bit); |
401 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
402 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
403 | return -ETIMEDOUT; | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
5f684c34 GU |
408 | static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi) |
409 | { | |
410 | return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
411 | } | |
412 | ||
413 | static inline int rspi_wait_for_rx_full(struct rspi_data *rspi) | |
414 | { | |
415 | return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE); | |
416 | } | |
417 | ||
35301c99 GU |
418 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
419 | { | |
5f684c34 GU |
420 | int error = rspi_wait_for_tx_empty(rspi); |
421 | if (error < 0) { | |
35301c99 | 422 | dev_err(&rspi->master->dev, "transmit timeout\n"); |
5f684c34 | 423 | return error; |
35301c99 GU |
424 | } |
425 | rspi_write_data(rspi, data); | |
426 | return 0; | |
427 | } | |
428 | ||
429 | static int rspi_data_in(struct rspi_data *rspi) | |
430 | { | |
5f684c34 | 431 | int error; |
35301c99 GU |
432 | u8 data; |
433 | ||
5f684c34 GU |
434 | error = rspi_wait_for_rx_full(rspi); |
435 | if (error < 0) { | |
35301c99 | 436 | dev_err(&rspi->master->dev, "receive timeout\n"); |
5f684c34 | 437 | return error; |
35301c99 GU |
438 | } |
439 | data = rspi_read_data(rspi); | |
440 | return data; | |
441 | } | |
442 | ||
443 | static int rspi_data_out_in(struct rspi_data *rspi, u8 data) | |
444 | { | |
445 | int ret; | |
446 | ||
447 | ret = rspi_data_out(rspi, data); | |
448 | if (ret < 0) | |
449 | return ret; | |
450 | ||
451 | return rspi_data_in(rspi); | |
452 | } | |
453 | ||
a3633fe7 SY |
454 | static void rspi_dma_complete(void *arg) |
455 | { | |
456 | struct rspi_data *rspi = arg; | |
457 | ||
458 | rspi->dma_callbacked = 1; | |
459 | wake_up_interruptible(&rspi->wait); | |
460 | } | |
461 | ||
c132f094 GU |
462 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
463 | unsigned len, struct dma_chan *chan, | |
a3633fe7 SY |
464 | enum dma_transfer_direction dir) |
465 | { | |
466 | sg_init_table(sg, 1); | |
467 | sg_set_buf(sg, buf, len); | |
468 | sg_dma_len(sg) = len; | |
469 | return dma_map_sg(chan->device->dev, sg, 1, dir); | |
470 | } | |
471 | ||
472 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, | |
473 | enum dma_transfer_direction dir) | |
474 | { | |
475 | dma_unmap_sg(chan->device->dev, sg, 1, dir); | |
476 | } | |
477 | ||
478 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) | |
479 | { | |
480 | u16 *dst = buf; | |
481 | const u8 *src = data; | |
482 | ||
483 | while (len) { | |
484 | *dst++ = (u16)(*src++); | |
485 | len--; | |
486 | } | |
487 | } | |
488 | ||
489 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) | |
490 | { | |
491 | u8 *dst = buf; | |
492 | const u16 *src = data; | |
493 | ||
494 | while (len) { | |
495 | *dst++ = (u8)*src++; | |
496 | len--; | |
497 | } | |
498 | } | |
499 | ||
500 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) | |
501 | { | |
502 | struct scatterlist sg; | |
c132f094 | 503 | const void *buf = NULL; |
a3633fe7 | 504 | struct dma_async_tx_descriptor *desc; |
93722206 | 505 | unsigned int len; |
a3633fe7 SY |
506 | int ret = 0; |
507 | ||
508 | if (rspi->dma_width_16bit) { | |
c132f094 | 509 | void *tmp; |
a3633fe7 SY |
510 | /* |
511 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
512 | * buffer. And, the driver converts original data into the | |
513 | * DMAC data as the following format: | |
514 | * original data: 1st byte, 2nd byte ... | |
515 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
516 | */ | |
517 | len = t->len * 2; | |
c132f094 GU |
518 | tmp = kmalloc(len, GFP_KERNEL); |
519 | if (!tmp) | |
a3633fe7 | 520 | return -ENOMEM; |
c132f094 GU |
521 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
522 | buf = tmp; | |
a3633fe7 SY |
523 | } else { |
524 | len = t->len; | |
c132f094 | 525 | buf = t->tx_buf; |
a3633fe7 SY |
526 | } |
527 | ||
528 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { | |
529 | ret = -EFAULT; | |
530 | goto end_nomap; | |
531 | } | |
532 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, | |
533 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
534 | if (!desc) { | |
535 | ret = -EIO; | |
536 | goto end; | |
537 | } | |
538 | ||
539 | /* | |
540 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
541 | * called. So, this driver disables the IRQ while DMA transfer. | |
542 | */ | |
93722206 | 543 | disable_irq(rspi->tx_irq); |
a3633fe7 SY |
544 | |
545 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); | |
546 | rspi_enable_irq(rspi, SPCR_SPTIE); | |
547 | rspi->dma_callbacked = 0; | |
548 | ||
549 | desc->callback = rspi_dma_complete; | |
550 | desc->callback_param = rspi; | |
551 | dmaengine_submit(desc); | |
552 | dma_async_issue_pending(rspi->chan_tx); | |
553 | ||
554 | ret = wait_event_interruptible_timeout(rspi->wait, | |
555 | rspi->dma_callbacked, HZ); | |
556 | if (ret > 0 && rspi->dma_callbacked) | |
557 | ret = 0; | |
558 | else if (!ret) | |
559 | ret = -ETIMEDOUT; | |
560 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
561 | ||
93722206 | 562 | enable_irq(rspi->tx_irq); |
a3633fe7 SY |
563 | |
564 | end: | |
565 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); | |
566 | end_nomap: | |
567 | if (rspi->dma_width_16bit) | |
568 | kfree(buf); | |
569 | ||
570 | return ret; | |
571 | } | |
572 | ||
baf588f4 | 573 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 574 | { |
97b95c11 | 575 | u8 spsr; |
0b2182dd SY |
576 | |
577 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
578 | if (spsr & SPSR_SPRF) | |
74da7686 | 579 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
580 | if (spsr & SPSR_OVRF) |
581 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 582 | RSPI_SPSR); |
a3633fe7 SY |
583 | } |
584 | ||
862d357f GU |
585 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
586 | { | |
587 | rspi_receive_init(rspi); | |
588 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); | |
589 | rspi_write8(rspi, 0, RSPI_SPBFCR); | |
590 | } | |
591 | ||
baf588f4 | 592 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 593 | { |
97b95c11 | 594 | u8 spsr; |
cb52c673 HCM |
595 | |
596 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
597 | if (spsr & SPSR_SPRF) | |
74da7686 | 598 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 599 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 600 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
601 | } |
602 | ||
a3633fe7 SY |
603 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
604 | { | |
605 | struct scatterlist sg, sg_dummy; | |
606 | void *dummy = NULL, *rx_buf = NULL; | |
607 | struct dma_async_tx_descriptor *desc, *desc_dummy; | |
93722206 | 608 | unsigned int len; |
a3633fe7 SY |
609 | int ret = 0; |
610 | ||
611 | if (rspi->dma_width_16bit) { | |
612 | /* | |
613 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
614 | * buffer. And, finally the driver converts the DMAC data into | |
615 | * actual data as the following format: | |
616 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
617 | * actual data: 1st byte, 2nd byte ... | |
618 | */ | |
619 | len = t->len * 2; | |
620 | rx_buf = kmalloc(len, GFP_KERNEL); | |
621 | if (!rx_buf) | |
622 | return -ENOMEM; | |
623 | } else { | |
624 | len = t->len; | |
625 | rx_buf = t->rx_buf; | |
626 | } | |
627 | ||
628 | /* prepare dummy transfer to generate SPI clocks */ | |
629 | dummy = kzalloc(len, GFP_KERNEL); | |
630 | if (!dummy) { | |
631 | ret = -ENOMEM; | |
632 | goto end_nomap; | |
633 | } | |
634 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, | |
635 | DMA_TO_DEVICE)) { | |
636 | ret = -EFAULT; | |
637 | goto end_nomap; | |
638 | } | |
639 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, | |
640 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
641 | if (!desc_dummy) { | |
642 | ret = -EIO; | |
643 | goto end_dummy_mapped; | |
644 | } | |
645 | ||
646 | /* prepare receive transfer */ | |
647 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, | |
648 | DMA_FROM_DEVICE)) { | |
649 | ret = -EFAULT; | |
650 | goto end_dummy_mapped; | |
651 | ||
652 | } | |
653 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, | |
654 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
655 | if (!desc) { | |
656 | ret = -EIO; | |
657 | goto end; | |
658 | } | |
659 | ||
660 | rspi_receive_init(rspi); | |
661 | ||
662 | /* | |
663 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
664 | * called. So, this driver disables the IRQ while DMA transfer. | |
665 | */ | |
93722206 GU |
666 | disable_irq(rspi->tx_irq); |
667 | if (rspi->rx_irq != rspi->tx_irq) | |
668 | disable_irq(rspi->rx_irq); | |
a3633fe7 SY |
669 | |
670 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); | |
671 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
672 | rspi->dma_callbacked = 0; | |
673 | ||
674 | desc->callback = rspi_dma_complete; | |
675 | desc->callback_param = rspi; | |
676 | dmaengine_submit(desc); | |
677 | dma_async_issue_pending(rspi->chan_rx); | |
678 | ||
679 | desc_dummy->callback = NULL; /* No callback */ | |
680 | dmaengine_submit(desc_dummy); | |
681 | dma_async_issue_pending(rspi->chan_tx); | |
682 | ||
683 | ret = wait_event_interruptible_timeout(rspi->wait, | |
684 | rspi->dma_callbacked, HZ); | |
685 | if (ret > 0 && rspi->dma_callbacked) | |
686 | ret = 0; | |
687 | else if (!ret) | |
688 | ret = -ETIMEDOUT; | |
689 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
690 | ||
93722206 GU |
691 | enable_irq(rspi->tx_irq); |
692 | if (rspi->rx_irq != rspi->tx_irq) | |
693 | enable_irq(rspi->rx_irq); | |
a3633fe7 SY |
694 | |
695 | end: | |
696 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); | |
697 | end_dummy_mapped: | |
698 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); | |
699 | end_nomap: | |
700 | if (rspi->dma_width_16bit) { | |
701 | if (!ret) | |
702 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); | |
703 | kfree(rx_buf); | |
704 | } | |
705 | kfree(dummy); | |
706 | ||
707 | return ret; | |
708 | } | |
709 | ||
baf588f4 | 710 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
a3633fe7 SY |
711 | { |
712 | if (t->tx_buf && rspi->chan_tx) | |
713 | return 1; | |
714 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
715 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) | |
716 | return 1; | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
8449fd76 GU |
721 | static int rspi_transfer_out_in(struct rspi_data *rspi, |
722 | struct spi_transfer *xfer) | |
723 | { | |
724 | int remain = xfer->len, ret; | |
725 | const u8 *tx_buf = xfer->tx_buf; | |
726 | u8 *rx_buf = xfer->rx_buf; | |
727 | u8 spcr, data; | |
728 | ||
729 | rspi_receive_init(rspi); | |
730 | ||
731 | spcr = rspi_read8(rspi, RSPI_SPCR); | |
732 | if (rx_buf) | |
733 | spcr &= ~SPCR_TXMD; | |
734 | else | |
735 | spcr |= SPCR_TXMD; | |
736 | rspi_write8(rspi, spcr, RSPI_SPCR); | |
737 | ||
738 | while (remain > 0) { | |
739 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
740 | ret = rspi_data_out(rspi, data); | |
741 | if (ret < 0) | |
742 | return ret; | |
743 | if (rx_buf) { | |
744 | ret = rspi_data_in(rspi); | |
745 | if (ret < 0) | |
746 | return ret; | |
747 | *rx_buf++ = ret; | |
748 | } | |
749 | remain--; | |
750 | } | |
751 | ||
752 | /* Wait for the last transmission */ | |
5f684c34 | 753 | rspi_wait_for_tx_empty(rspi); |
8449fd76 GU |
754 | |
755 | return 0; | |
756 | } | |
757 | ||
79d23495 GU |
758 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
759 | struct spi_transfer *xfer) | |
0b2182dd | 760 | { |
79d23495 | 761 | struct rspi_data *rspi = spi_master_get_devdata(master); |
8449fd76 GU |
762 | int ret; |
763 | ||
764 | if (!rspi_is_dma(rspi, xfer)) | |
765 | return rspi_transfer_out_in(rspi, xfer); | |
0b2182dd | 766 | |
79d23495 | 767 | if (xfer->tx_buf) { |
8449fd76 | 768 | ret = rspi_send_dma(rspi, xfer); |
79d23495 GU |
769 | if (ret < 0) |
770 | return ret; | |
0b2182dd | 771 | } |
8449fd76 GU |
772 | if (xfer->rx_buf) |
773 | return rspi_receive_dma(rspi, xfer); | |
774 | ||
775 | return 0; | |
eb557f75 GU |
776 | } |
777 | ||
862d357f GU |
778 | static int rspi_rz_transfer_out_in(struct rspi_data *rspi, |
779 | struct spi_transfer *xfer) | |
780 | { | |
781 | int remain = xfer->len, ret; | |
782 | const u8 *tx_buf = xfer->tx_buf; | |
783 | u8 *rx_buf = xfer->rx_buf; | |
784 | u8 data; | |
785 | ||
786 | rspi_rz_receive_init(rspi); | |
787 | ||
788 | while (remain > 0) { | |
789 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
790 | ret = rspi_data_out_in(rspi, data); | |
791 | if (ret < 0) | |
792 | return ret; | |
793 | if (rx_buf) | |
794 | *rx_buf++ = ret; | |
795 | remain--; | |
796 | } | |
797 | ||
798 | /* Wait for the last transmission */ | |
5f684c34 | 799 | rspi_wait_for_tx_empty(rspi); |
862d357f GU |
800 | |
801 | return 0; | |
802 | } | |
803 | ||
804 | static int rspi_rz_transfer_one(struct spi_master *master, | |
805 | struct spi_device *spi, | |
806 | struct spi_transfer *xfer) | |
807 | { | |
808 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
809 | ||
810 | return rspi_rz_transfer_out_in(rspi, xfer); | |
811 | } | |
812 | ||
340a15e6 GU |
813 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
814 | struct spi_transfer *xfer) | |
eb557f75 | 815 | { |
340a15e6 GU |
816 | int remain = xfer->len, ret; |
817 | const u8 *tx_buf = xfer->tx_buf; | |
818 | u8 *rx_buf = xfer->rx_buf; | |
819 | u8 data; | |
eb557f75 | 820 | |
340a15e6 GU |
821 | qspi_receive_init(rspi); |
822 | ||
823 | while (remain > 0) { | |
824 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
825 | ret = rspi_data_out_in(rspi, data); | |
eb557f75 GU |
826 | if (ret < 0) |
827 | return ret; | |
340a15e6 GU |
828 | if (rx_buf) |
829 | *rx_buf++ = ret; | |
830 | remain--; | |
79d23495 | 831 | } |
340a15e6 GU |
832 | |
833 | /* Wait for the last transmission */ | |
5f684c34 | 834 | rspi_wait_for_tx_empty(rspi); |
340a15e6 GU |
835 | |
836 | return 0; | |
837 | } | |
838 | ||
880c6d11 GU |
839 | static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) |
840 | { | |
841 | const u8 *buf = xfer->tx_buf; | |
842 | unsigned int i; | |
843 | int ret; | |
844 | ||
845 | for (i = 0; i < xfer->len; i++) { | |
846 | ret = rspi_data_out(rspi, *buf++); | |
847 | if (ret < 0) | |
848 | return ret; | |
849 | } | |
850 | ||
851 | /* Wait for the last transmission */ | |
5f684c34 | 852 | rspi_wait_for_tx_empty(rspi); |
880c6d11 GU |
853 | |
854 | return 0; | |
855 | } | |
856 | ||
857 | static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) | |
858 | { | |
859 | u8 *buf = xfer->rx_buf; | |
860 | unsigned int i; | |
861 | int ret; | |
862 | ||
863 | for (i = 0; i < xfer->len; i++) { | |
864 | ret = rspi_data_in(rspi); | |
865 | if (ret < 0) | |
866 | return ret; | |
867 | *buf++ = ret; | |
868 | } | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
340a15e6 GU |
873 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
874 | struct spi_transfer *xfer) | |
875 | { | |
876 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
877 | ||
ba824d49 GU |
878 | if (spi->mode & SPI_LOOP) { |
879 | return qspi_transfer_out_in(rspi, xfer); | |
880 | } else if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) { | |
880c6d11 GU |
881 | /* Quad or Dual SPI Write */ |
882 | return qspi_transfer_out(rspi, xfer); | |
883 | } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) { | |
884 | /* Quad or Dual SPI Read */ | |
885 | return qspi_transfer_in(rspi, xfer); | |
886 | } else { | |
887 | /* Single SPI Transfer */ | |
888 | return qspi_transfer_out_in(rspi, xfer); | |
889 | } | |
0b2182dd SY |
890 | } |
891 | ||
892 | static int rspi_setup(struct spi_device *spi) | |
893 | { | |
894 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | |
895 | ||
0b2182dd SY |
896 | rspi->max_speed_hz = spi->max_speed_hz; |
897 | ||
348e5153 GU |
898 | rspi->spcmd = SPCMD_SSLKP; |
899 | if (spi->mode & SPI_CPOL) | |
900 | rspi->spcmd |= SPCMD_CPOL; | |
901 | if (spi->mode & SPI_CPHA) | |
902 | rspi->spcmd |= SPCMD_CPHA; | |
903 | ||
06a7a3cf GU |
904 | /* CMOS output mode and MOSI signal from previous transfer */ |
905 | rspi->sppcr = 0; | |
906 | if (spi->mode & SPI_LOOP) | |
907 | rspi->sppcr |= SPPCR_SPLP; | |
908 | ||
5ce0ba88 | 909 | set_config_register(rspi, 8); |
0b2182dd SY |
910 | |
911 | return 0; | |
912 | } | |
913 | ||
880c6d11 GU |
914 | static u16 qspi_transfer_mode(const struct spi_transfer *xfer) |
915 | { | |
916 | if (xfer->tx_buf) | |
917 | switch (xfer->tx_nbits) { | |
918 | case SPI_NBITS_QUAD: | |
919 | return SPCMD_SPIMOD_QUAD; | |
920 | case SPI_NBITS_DUAL: | |
921 | return SPCMD_SPIMOD_DUAL; | |
922 | default: | |
923 | return 0; | |
924 | } | |
925 | if (xfer->rx_buf) | |
926 | switch (xfer->rx_nbits) { | |
927 | case SPI_NBITS_QUAD: | |
928 | return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; | |
929 | case SPI_NBITS_DUAL: | |
930 | return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; | |
931 | default: | |
932 | return 0; | |
933 | } | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | static int qspi_setup_sequencer(struct rspi_data *rspi, | |
939 | const struct spi_message *msg) | |
940 | { | |
941 | const struct spi_transfer *xfer; | |
942 | unsigned int i = 0, len = 0; | |
943 | u16 current_mode = 0xffff, mode; | |
944 | ||
945 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
946 | mode = qspi_transfer_mode(xfer); | |
947 | if (mode == current_mode) { | |
948 | len += xfer->len; | |
949 | continue; | |
950 | } | |
951 | ||
952 | /* Transfer mode change */ | |
953 | if (i) { | |
954 | /* Set transfer data length of previous transfer */ | |
955 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
956 | } | |
957 | ||
958 | if (i >= QSPI_NUM_SPCMD) { | |
959 | dev_err(&msg->spi->dev, | |
960 | "Too many different transfer modes"); | |
961 | return -EINVAL; | |
962 | } | |
963 | ||
964 | /* Program transfer mode for this transfer */ | |
965 | rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); | |
966 | current_mode = mode; | |
967 | len = xfer->len; | |
968 | i++; | |
969 | } | |
970 | if (i) { | |
971 | /* Set final transfer data length and sequence length */ | |
972 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
973 | rspi_write8(rspi, i - 1, RSPI_SPSCR); | |
974 | } | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
79d23495 | 979 | static int rspi_prepare_message(struct spi_master *master, |
880c6d11 | 980 | struct spi_message *msg) |
79d23495 GU |
981 | { |
982 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
880c6d11 | 983 | int ret; |
0b2182dd | 984 | |
880c6d11 GU |
985 | if (msg->spi->mode & |
986 | (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { | |
987 | /* Setup sequencer for messages with multiple transfer modes */ | |
988 | ret = qspi_setup_sequencer(rspi, msg); | |
989 | if (ret < 0) | |
990 | return ret; | |
991 | } | |
992 | ||
993 | /* Enable SPI function in master mode */ | |
79d23495 | 994 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
995 | return 0; |
996 | } | |
997 | ||
79d23495 | 998 | static int rspi_unprepare_message(struct spi_master *master, |
880c6d11 | 999 | struct spi_message *msg) |
0b2182dd | 1000 | { |
79d23495 GU |
1001 | struct rspi_data *rspi = spi_master_get_devdata(master); |
1002 | ||
880c6d11 | 1003 | /* Disable SPI function */ |
79d23495 | 1004 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); |
880c6d11 GU |
1005 | |
1006 | /* Reset sequencer for Single SPI Transfers */ | |
1007 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
1008 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
79d23495 | 1009 | return 0; |
0b2182dd SY |
1010 | } |
1011 | ||
93722206 | 1012 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
0b2182dd | 1013 | { |
c132f094 | 1014 | struct rspi_data *rspi = _sr; |
97b95c11 | 1015 | u8 spsr; |
0b2182dd | 1016 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 1017 | u8 disable_irq = 0; |
0b2182dd SY |
1018 | |
1019 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1020 | if (spsr & SPSR_SPRF) | |
1021 | disable_irq |= SPCR_SPRIE; | |
1022 | if (spsr & SPSR_SPTEF) | |
1023 | disable_irq |= SPCR_SPTIE; | |
1024 | ||
1025 | if (disable_irq) { | |
1026 | ret = IRQ_HANDLED; | |
1027 | rspi_disable_irq(rspi, disable_irq); | |
1028 | wake_up(&rspi->wait); | |
1029 | } | |
1030 | ||
1031 | return ret; | |
1032 | } | |
1033 | ||
93722206 GU |
1034 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
1035 | { | |
1036 | struct rspi_data *rspi = _sr; | |
1037 | u8 spsr; | |
1038 | ||
1039 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1040 | if (spsr & SPSR_SPRF) { | |
1041 | rspi_disable_irq(rspi, SPCR_SPRIE); | |
1042 | wake_up(&rspi->wait); | |
1043 | return IRQ_HANDLED; | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) | |
1050 | { | |
1051 | struct rspi_data *rspi = _sr; | |
1052 | u8 spsr; | |
1053 | ||
1054 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1055 | if (spsr & SPSR_SPTEF) { | |
1056 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
1057 | wake_up(&rspi->wait); | |
1058 | return IRQ_HANDLED; | |
1059 | } | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
fd4a319b | 1064 | static int rspi_request_dma(struct rspi_data *rspi, |
0243c536 | 1065 | struct platform_device *pdev) |
a3633fe7 | 1066 | { |
baf588f4 | 1067 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
e2b05099 | 1068 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3633fe7 | 1069 | dma_cap_mask_t mask; |
0243c536 SY |
1070 | struct dma_slave_config cfg; |
1071 | int ret; | |
a3633fe7 | 1072 | |
e2b05099 | 1073 | if (!res || !rspi_pd) |
0243c536 | 1074 | return 0; /* The driver assumes no error. */ |
a3633fe7 SY |
1075 | |
1076 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; | |
1077 | ||
1078 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
1079 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { | |
1080 | dma_cap_zero(mask); | |
1081 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
1082 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
1083 | (void *)rspi_pd->dma_rx_id); | |
1084 | if (rspi->chan_rx) { | |
1085 | cfg.slave_id = rspi_pd->dma_rx_id; | |
1086 | cfg.direction = DMA_DEV_TO_MEM; | |
e2b05099 GL |
1087 | cfg.dst_addr = 0; |
1088 | cfg.src_addr = res->start + RSPI_SPDR; | |
0243c536 SY |
1089 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
1090 | if (!ret) | |
1091 | dev_info(&pdev->dev, "Use DMA when rx.\n"); | |
1092 | else | |
1093 | return ret; | |
1094 | } | |
a3633fe7 SY |
1095 | } |
1096 | if (rspi_pd->dma_tx_id) { | |
1097 | dma_cap_zero(mask); | |
1098 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
1099 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
1100 | (void *)rspi_pd->dma_tx_id); | |
1101 | if (rspi->chan_tx) { | |
1102 | cfg.slave_id = rspi_pd->dma_tx_id; | |
1103 | cfg.direction = DMA_MEM_TO_DEV; | |
e2b05099 GL |
1104 | cfg.dst_addr = res->start + RSPI_SPDR; |
1105 | cfg.src_addr = 0; | |
0243c536 SY |
1106 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
1107 | if (!ret) | |
1108 | dev_info(&pdev->dev, "Use DMA when tx\n"); | |
1109 | else | |
1110 | return ret; | |
1111 | } | |
a3633fe7 | 1112 | } |
0243c536 SY |
1113 | |
1114 | return 0; | |
a3633fe7 SY |
1115 | } |
1116 | ||
fd4a319b | 1117 | static void rspi_release_dma(struct rspi_data *rspi) |
a3633fe7 SY |
1118 | { |
1119 | if (rspi->chan_tx) | |
1120 | dma_release_channel(rspi->chan_tx); | |
1121 | if (rspi->chan_rx) | |
1122 | dma_release_channel(rspi->chan_rx); | |
1123 | } | |
1124 | ||
fd4a319b | 1125 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 1126 | { |
5ffbe2d9 | 1127 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 1128 | |
a3633fe7 | 1129 | rspi_release_dma(rspi); |
490c9774 | 1130 | pm_runtime_disable(&pdev->dev); |
0b2182dd SY |
1131 | |
1132 | return 0; | |
1133 | } | |
1134 | ||
426ef76d GU |
1135 | static const struct spi_ops rspi_ops = { |
1136 | .set_config_register = rspi_set_config_register, | |
1137 | .transfer_one = rspi_transfer_one, | |
880c6d11 | 1138 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, |
426ef76d GU |
1139 | }; |
1140 | ||
1141 | static const struct spi_ops rspi_rz_ops = { | |
1142 | .set_config_register = rspi_rz_set_config_register, | |
1143 | .transfer_one = rspi_rz_transfer_one, | |
880c6d11 | 1144 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, |
426ef76d GU |
1145 | }; |
1146 | ||
1147 | static const struct spi_ops qspi_ops = { | |
1148 | .set_config_register = qspi_set_config_register, | |
1149 | .transfer_one = qspi_transfer_one, | |
880c6d11 GU |
1150 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | |
1151 | SPI_TX_DUAL | SPI_TX_QUAD | | |
1152 | SPI_RX_DUAL | SPI_RX_QUAD, | |
426ef76d GU |
1153 | }; |
1154 | ||
1155 | #ifdef CONFIG_OF | |
1156 | static const struct of_device_id rspi_of_match[] = { | |
1157 | /* RSPI on legacy SH */ | |
1158 | { .compatible = "renesas,rspi", .data = &rspi_ops }, | |
1159 | /* RSPI on RZ/A1H */ | |
1160 | { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, | |
1161 | /* QSPI on R-Car Gen2 */ | |
1162 | { .compatible = "renesas,qspi", .data = &qspi_ops }, | |
1163 | { /* sentinel */ } | |
1164 | }; | |
1165 | ||
1166 | MODULE_DEVICE_TABLE(of, rspi_of_match); | |
1167 | ||
1168 | static int rspi_parse_dt(struct device *dev, struct spi_master *master) | |
1169 | { | |
1170 | u32 num_cs; | |
1171 | int error; | |
1172 | ||
1173 | /* Parse DT properties */ | |
1174 | error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); | |
1175 | if (error) { | |
1176 | dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); | |
1177 | return error; | |
1178 | } | |
1179 | ||
1180 | master->num_chipselect = num_cs; | |
1181 | return 0; | |
1182 | } | |
1183 | #else | |
64b67def | 1184 | #define rspi_of_match NULL |
426ef76d GU |
1185 | static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) |
1186 | { | |
1187 | return -EINVAL; | |
1188 | } | |
1189 | #endif /* CONFIG_OF */ | |
1190 | ||
93722206 GU |
1191 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
1192 | irq_handler_t handler, const char *suffix, | |
1193 | void *dev_id) | |
1194 | { | |
1195 | const char *base = dev_name(dev); | |
1196 | size_t len = strlen(base) + strlen(suffix) + 2; | |
1197 | char *name = devm_kzalloc(dev, len, GFP_KERNEL); | |
1198 | if (!name) | |
1199 | return -ENOMEM; | |
1200 | snprintf(name, len, "%s:%s", base, suffix); | |
1201 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); | |
1202 | } | |
1203 | ||
fd4a319b | 1204 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
1205 | { |
1206 | struct resource *res; | |
1207 | struct spi_master *master; | |
1208 | struct rspi_data *rspi; | |
93722206 | 1209 | int ret; |
426ef76d GU |
1210 | const struct of_device_id *of_id; |
1211 | const struct rspi_plat_data *rspi_pd; | |
5ce0ba88 | 1212 | const struct spi_ops *ops; |
0b2182dd | 1213 | |
0b2182dd SY |
1214 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
1215 | if (master == NULL) { | |
1216 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
1217 | return -ENOMEM; | |
1218 | } | |
1219 | ||
426ef76d GU |
1220 | of_id = of_match_device(rspi_of_match, &pdev->dev); |
1221 | if (of_id) { | |
1222 | ops = of_id->data; | |
1223 | ret = rspi_parse_dt(&pdev->dev, master); | |
1224 | if (ret) | |
1225 | goto error1; | |
1226 | } else { | |
1227 | ops = (struct spi_ops *)pdev->id_entry->driver_data; | |
1228 | rspi_pd = dev_get_platdata(&pdev->dev); | |
1229 | if (rspi_pd && rspi_pd->num_chipselect) | |
1230 | master->num_chipselect = rspi_pd->num_chipselect; | |
1231 | else | |
1232 | master->num_chipselect = 2; /* default */ | |
1233 | }; | |
1234 | ||
1235 | /* ops parameter check */ | |
1236 | if (!ops->set_config_register) { | |
1237 | dev_err(&pdev->dev, "there is no set_config_register\n"); | |
1238 | ret = -ENODEV; | |
1239 | goto error1; | |
1240 | } | |
1241 | ||
0b2182dd | 1242 | rspi = spi_master_get_devdata(master); |
24b5a82c | 1243 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 1244 | rspi->ops = ops; |
0b2182dd | 1245 | rspi->master = master; |
5d79e9ac LP |
1246 | |
1247 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1248 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
1249 | if (IS_ERR(rspi->addr)) { | |
1250 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
1251 | goto error1; |
1252 | } | |
1253 | ||
29f397b7 | 1254 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
0b2182dd SY |
1255 | if (IS_ERR(rspi->clk)) { |
1256 | dev_err(&pdev->dev, "cannot get clock\n"); | |
1257 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 1258 | goto error1; |
0b2182dd | 1259 | } |
17fe0d9a | 1260 | |
490c9774 | 1261 | pm_runtime_enable(&pdev->dev); |
0b2182dd | 1262 | |
0b2182dd SY |
1263 | init_waitqueue_head(&rspi->wait); |
1264 | ||
0b2182dd SY |
1265 | master->bus_num = pdev->id; |
1266 | master->setup = rspi_setup; | |
490c9774 | 1267 | master->auto_runtime_pm = true; |
eb557f75 | 1268 | master->transfer_one = ops->transfer_one; |
79d23495 GU |
1269 | master->prepare_message = rspi_prepare_message; |
1270 | master->unprepare_message = rspi_unprepare_message; | |
880c6d11 | 1271 | master->mode_bits = ops->mode_bits; |
426ef76d | 1272 | master->dev.of_node = pdev->dev.of_node; |
0b2182dd | 1273 | |
93722206 GU |
1274 | ret = platform_get_irq_byname(pdev, "rx"); |
1275 | if (ret < 0) { | |
1276 | ret = platform_get_irq_byname(pdev, "mux"); | |
1277 | if (ret < 0) | |
1278 | ret = platform_get_irq(pdev, 0); | |
1279 | if (ret >= 0) | |
1280 | rspi->rx_irq = rspi->tx_irq = ret; | |
1281 | } else { | |
1282 | rspi->rx_irq = ret; | |
1283 | ret = platform_get_irq_byname(pdev, "tx"); | |
1284 | if (ret >= 0) | |
1285 | rspi->tx_irq = ret; | |
1286 | } | |
1287 | if (ret < 0) { | |
1288 | dev_err(&pdev->dev, "platform_get_irq error\n"); | |
1289 | goto error2; | |
1290 | } | |
1291 | ||
1292 | if (rspi->rx_irq == rspi->tx_irq) { | |
1293 | /* Single multiplexed interrupt */ | |
1294 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, | |
1295 | "mux", rspi); | |
1296 | } else { | |
1297 | /* Multi-interrupt mode, only SPRI and SPTI are used */ | |
1298 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, | |
1299 | "rx", rspi); | |
1300 | if (!ret) | |
1301 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, | |
1302 | rspi_irq_tx, "tx", rspi); | |
1303 | } | |
0b2182dd SY |
1304 | if (ret < 0) { |
1305 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 1306 | goto error2; |
0b2182dd SY |
1307 | } |
1308 | ||
0243c536 SY |
1309 | ret = rspi_request_dma(rspi, pdev); |
1310 | if (ret < 0) { | |
1311 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); | |
fcb4ed74 | 1312 | goto error3; |
0243c536 | 1313 | } |
a3633fe7 | 1314 | |
9e03d05e | 1315 | ret = devm_spi_register_master(&pdev->dev, master); |
0b2182dd SY |
1316 | if (ret < 0) { |
1317 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
fcb4ed74 | 1318 | goto error3; |
0b2182dd SY |
1319 | } |
1320 | ||
1321 | dev_info(&pdev->dev, "probed\n"); | |
1322 | ||
1323 | return 0; | |
1324 | ||
fcb4ed74 | 1325 | error3: |
5d79e9ac | 1326 | rspi_release_dma(rspi); |
fcb4ed74 | 1327 | error2: |
490c9774 | 1328 | pm_runtime_disable(&pdev->dev); |
0b2182dd SY |
1329 | error1: |
1330 | spi_master_put(master); | |
1331 | ||
1332 | return ret; | |
1333 | } | |
1334 | ||
5ce0ba88 HCM |
1335 | static struct platform_device_id spi_driver_ids[] = { |
1336 | { "rspi", (kernel_ulong_t)&rspi_ops }, | |
862d357f | 1337 | { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, |
5ce0ba88 HCM |
1338 | { "qspi", (kernel_ulong_t)&qspi_ops }, |
1339 | {}, | |
1340 | }; | |
1341 | ||
1342 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1343 | ||
0b2182dd SY |
1344 | static struct platform_driver rspi_driver = { |
1345 | .probe = rspi_probe, | |
fd4a319b | 1346 | .remove = rspi_remove, |
5ce0ba88 | 1347 | .id_table = spi_driver_ids, |
0b2182dd | 1348 | .driver = { |
5ce0ba88 | 1349 | .name = "renesas_spi", |
0b2182dd | 1350 | .owner = THIS_MODULE, |
426ef76d | 1351 | .of_match_table = of_match_ptr(rspi_of_match), |
0b2182dd SY |
1352 | }, |
1353 | }; | |
1354 | module_platform_driver(rspi_driver); | |
1355 | ||
1356 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1357 | MODULE_LICENSE("GPL v2"); | |
1358 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1359 | MODULE_ALIAS("platform:rspi"); |