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Commit | Line | Data |
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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8051effc | 19 | #include <linux/interrupt.h> |
e2dbf5eb GL |
20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | |
d7614de4 | 22 | #include <linux/module.h> |
cf9c86ef | 23 | #include <linux/of.h> |
8051effc | 24 | #include <linux/platform_device.h> |
8051effc | 25 | #include <linux/pm_runtime.h> |
8051effc | 26 | |
e2dbf5eb | 27 | #include <linux/spi/sh_msiof.h> |
8051effc MD |
28 | #include <linux/spi/spi.h> |
29 | #include <linux/spi/spi_bitbang.h> | |
8051effc | 30 | |
8051effc MD |
31 | #include <asm/unaligned.h> |
32 | ||
33 | struct sh_msiof_spi_priv { | |
34 | struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */ | |
35 | void __iomem *mapbase; | |
36 | struct clk *clk; | |
37 | struct platform_device *pdev; | |
38 | struct sh_msiof_spi_info *info; | |
39 | struct completion done; | |
40 | unsigned long flags; | |
41 | int tx_fifo_size; | |
42 | int rx_fifo_size; | |
43 | }; | |
44 | ||
45 | #define TMDR1 0x00 | |
46 | #define TMDR2 0x04 | |
47 | #define TMDR3 0x08 | |
48 | #define RMDR1 0x10 | |
49 | #define RMDR2 0x14 | |
50 | #define RMDR3 0x18 | |
51 | #define TSCR 0x20 | |
52 | #define RSCR 0x22 | |
53 | #define CTR 0x28 | |
54 | #define FCTR 0x30 | |
55 | #define STR 0x40 | |
56 | #define IER 0x44 | |
57 | #define TDR1 0x48 | |
58 | #define TDR2 0x4c | |
59 | #define TFDR 0x50 | |
60 | #define RDR1 0x58 | |
61 | #define RDR2 0x5c | |
62 | #define RFDR 0x60 | |
63 | ||
64 | #define CTR_TSCKE (1 << 15) | |
65 | #define CTR_TFSE (1 << 14) | |
66 | #define CTR_TXE (1 << 9) | |
67 | #define CTR_RXE (1 << 8) | |
68 | ||
69 | #define STR_TEOF (1 << 23) | |
70 | #define STR_REOF (1 << 7) | |
71 | ||
e2dbf5eb | 72 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
73 | { |
74 | switch (reg_offs) { | |
75 | case TSCR: | |
76 | case RSCR: | |
77 | return ioread16(p->mapbase + reg_offs); | |
78 | default: | |
79 | return ioread32(p->mapbase + reg_offs); | |
80 | } | |
81 | } | |
82 | ||
83 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 84 | u32 value) |
8051effc MD |
85 | { |
86 | switch (reg_offs) { | |
87 | case TSCR: | |
88 | case RSCR: | |
89 | iowrite16(value, p->mapbase + reg_offs); | |
90 | break; | |
91 | default: | |
92 | iowrite32(value, p->mapbase + reg_offs); | |
93 | break; | |
94 | } | |
95 | } | |
96 | ||
97 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 98 | u32 clr, u32 set) |
8051effc | 99 | { |
e2dbf5eb GL |
100 | u32 mask = clr | set; |
101 | u32 data; | |
8051effc MD |
102 | int k; |
103 | ||
104 | data = sh_msiof_read(p, CTR); | |
105 | data &= ~clr; | |
106 | data |= set; | |
107 | sh_msiof_write(p, CTR, data); | |
108 | ||
109 | for (k = 100; k > 0; k--) { | |
110 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
111 | break; | |
112 | ||
113 | udelay(10); | |
114 | } | |
115 | ||
116 | return k > 0 ? 0 : -ETIMEDOUT; | |
117 | } | |
118 | ||
119 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
120 | { | |
121 | struct sh_msiof_spi_priv *p = data; | |
122 | ||
123 | /* just disable the interrupt and wake up */ | |
124 | sh_msiof_write(p, IER, 0); | |
125 | complete(&p->done); | |
126 | ||
127 | return IRQ_HANDLED; | |
128 | } | |
129 | ||
130 | static struct { | |
131 | unsigned short div; | |
132 | unsigned short scr; | |
133 | } const sh_msiof_spi_clk_table[] = { | |
134 | { 1, 0x0007 }, | |
135 | { 2, 0x0000 }, | |
136 | { 4, 0x0001 }, | |
137 | { 8, 0x0002 }, | |
138 | { 16, 0x0003 }, | |
139 | { 32, 0x0004 }, | |
140 | { 64, 0x1f00 }, | |
141 | { 128, 0x1f01 }, | |
142 | { 256, 0x1f02 }, | |
143 | { 512, 0x1f03 }, | |
144 | { 1024, 0x1f04 }, | |
145 | }; | |
146 | ||
147 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 148 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
149 | { |
150 | unsigned long div = 1024; | |
151 | size_t k; | |
152 | ||
153 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 154 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
155 | |
156 | /* TODO: make more fine grained */ | |
157 | ||
158 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
159 | if (sh_msiof_spi_clk_table[k].div >= div) | |
160 | break; | |
161 | } | |
162 | ||
163 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
164 | ||
165 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
166 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
167 | } | |
168 | ||
169 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 170 | u32 cpol, u32 cpha, |
50a77998 | 171 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 172 | { |
e2dbf5eb | 173 | u32 tmp; |
8051effc MD |
174 | int edge; |
175 | ||
176 | /* | |
e8708ef7 MP |
177 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
178 | * 0 0 10 10 1 1 | |
179 | * 0 1 10 10 0 0 | |
180 | * 1 0 11 11 0 0 | |
181 | * 1 1 11 11 1 1 | |
8051effc | 182 | */ |
8051effc | 183 | sh_msiof_write(p, FCTR, 0); |
50a77998 TY |
184 | |
185 | tmp = 0; | |
186 | tmp |= !cs_high << 25; | |
187 | tmp |= lsb_first << 24; | |
188 | sh_msiof_write(p, TMDR1, 0xe0000005 | tmp); | |
189 | sh_msiof_write(p, RMDR1, 0x20000005 | tmp); | |
8051effc MD |
190 | |
191 | tmp = 0xa0000000; | |
192 | tmp |= cpol << 30; /* TSCKIZ */ | |
193 | tmp |= cpol << 28; /* RSCKIZ */ | |
194 | ||
e2dbf5eb | 195 | edge = cpol ^ !cpha; |
8051effc MD |
196 | |
197 | tmp |= edge << 27; /* TEDG */ | |
e8708ef7 | 198 | tmp |= edge << 26; /* REDG */ |
8051effc MD |
199 | tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */ |
200 | sh_msiof_write(p, CTR, tmp); | |
201 | } | |
202 | ||
203 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
204 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 205 | u32 bits, u32 words) |
8051effc | 206 | { |
e2dbf5eb | 207 | u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16); |
8051effc MD |
208 | |
209 | if (tx_buf) | |
210 | sh_msiof_write(p, TMDR2, dr2); | |
211 | else | |
212 | sh_msiof_write(p, TMDR2, dr2 | 1); | |
213 | ||
214 | if (rx_buf) | |
215 | sh_msiof_write(p, RMDR2, dr2); | |
216 | ||
217 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
218 | } | |
219 | ||
220 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
221 | { | |
222 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
223 | } | |
224 | ||
225 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
226 | const void *tx_buf, int words, int fs) | |
227 | { | |
e2dbf5eb | 228 | const u8 *buf_8 = tx_buf; |
8051effc MD |
229 | int k; |
230 | ||
231 | for (k = 0; k < words; k++) | |
232 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
233 | } | |
234 | ||
235 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
236 | const void *tx_buf, int words, int fs) | |
237 | { | |
e2dbf5eb | 238 | const u16 *buf_16 = tx_buf; |
8051effc MD |
239 | int k; |
240 | ||
241 | for (k = 0; k < words; k++) | |
242 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
243 | } | |
244 | ||
245 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
246 | const void *tx_buf, int words, int fs) | |
247 | { | |
e2dbf5eb | 248 | const u16 *buf_16 = tx_buf; |
8051effc MD |
249 | int k; |
250 | ||
251 | for (k = 0; k < words; k++) | |
252 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
253 | } | |
254 | ||
255 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
256 | const void *tx_buf, int words, int fs) | |
257 | { | |
e2dbf5eb | 258 | const u32 *buf_32 = tx_buf; |
8051effc MD |
259 | int k; |
260 | ||
261 | for (k = 0; k < words; k++) | |
262 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
263 | } | |
264 | ||
265 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
266 | const void *tx_buf, int words, int fs) | |
267 | { | |
e2dbf5eb | 268 | const u32 *buf_32 = tx_buf; |
8051effc MD |
269 | int k; |
270 | ||
271 | for (k = 0; k < words; k++) | |
272 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
273 | } | |
274 | ||
9dabb3f3 GL |
275 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
276 | const void *tx_buf, int words, int fs) | |
277 | { | |
278 | const u32 *buf_32 = tx_buf; | |
279 | int k; | |
280 | ||
281 | for (k = 0; k < words; k++) | |
282 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
283 | } | |
284 | ||
285 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
286 | const void *tx_buf, int words, int fs) | |
287 | { | |
288 | const u32 *buf_32 = tx_buf; | |
289 | int k; | |
290 | ||
291 | for (k = 0; k < words; k++) | |
292 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
293 | } | |
294 | ||
8051effc MD |
295 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
296 | void *rx_buf, int words, int fs) | |
297 | { | |
e2dbf5eb | 298 | u8 *buf_8 = rx_buf; |
8051effc MD |
299 | int k; |
300 | ||
301 | for (k = 0; k < words; k++) | |
302 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
303 | } | |
304 | ||
305 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
306 | void *rx_buf, int words, int fs) | |
307 | { | |
e2dbf5eb | 308 | u16 *buf_16 = rx_buf; |
8051effc MD |
309 | int k; |
310 | ||
311 | for (k = 0; k < words; k++) | |
312 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
313 | } | |
314 | ||
315 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
316 | void *rx_buf, int words, int fs) | |
317 | { | |
e2dbf5eb | 318 | u16 *buf_16 = rx_buf; |
8051effc MD |
319 | int k; |
320 | ||
321 | for (k = 0; k < words; k++) | |
322 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
323 | } | |
324 | ||
325 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
326 | void *rx_buf, int words, int fs) | |
327 | { | |
e2dbf5eb | 328 | u32 *buf_32 = rx_buf; |
8051effc MD |
329 | int k; |
330 | ||
331 | for (k = 0; k < words; k++) | |
332 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
333 | } | |
334 | ||
335 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
336 | void *rx_buf, int words, int fs) | |
337 | { | |
e2dbf5eb | 338 | u32 *buf_32 = rx_buf; |
8051effc MD |
339 | int k; |
340 | ||
341 | for (k = 0; k < words; k++) | |
342 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
343 | } | |
344 | ||
9dabb3f3 GL |
345 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
346 | void *rx_buf, int words, int fs) | |
347 | { | |
348 | u32 *buf_32 = rx_buf; | |
349 | int k; | |
350 | ||
351 | for (k = 0; k < words; k++) | |
352 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
353 | } | |
354 | ||
355 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
356 | void *rx_buf, int words, int fs) | |
357 | { | |
358 | u32 *buf_32 = rx_buf; | |
359 | int k; | |
360 | ||
361 | for (k = 0; k < words; k++) | |
362 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
363 | } | |
364 | ||
8051effc MD |
365 | static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) |
366 | { | |
367 | int bits; | |
368 | ||
369 | bits = t ? t->bits_per_word : 0; | |
e2dbf5eb GL |
370 | if (!bits) |
371 | bits = spi->bits_per_word; | |
8051effc MD |
372 | return bits; |
373 | } | |
374 | ||
6a85fc5a | 375 | static u32 sh_msiof_spi_hz(struct spi_device *spi, struct spi_transfer *t) |
8051effc | 376 | { |
6a85fc5a | 377 | u32 hz; |
8051effc MD |
378 | |
379 | hz = t ? t->speed_hz : 0; | |
e2dbf5eb GL |
380 | if (!hz) |
381 | hz = spi->max_speed_hz; | |
8051effc MD |
382 | return hz; |
383 | } | |
384 | ||
385 | static int sh_msiof_spi_setup_transfer(struct spi_device *spi, | |
386 | struct spi_transfer *t) | |
387 | { | |
388 | int bits; | |
389 | ||
390 | /* noting to check hz values against since parent clock is disabled */ | |
391 | ||
392 | bits = sh_msiof_spi_bits(spi, t); | |
393 | if (bits < 8) | |
394 | return -EINVAL; | |
395 | if (bits > 32) | |
396 | return -EINVAL; | |
397 | ||
398 | return spi_bitbang_setup_transfer(spi, t); | |
399 | } | |
400 | ||
401 | static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) | |
402 | { | |
403 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
404 | int value; | |
405 | ||
406 | /* chip select is active low unless SPI_CS_HIGH is set */ | |
407 | if (spi->mode & SPI_CS_HIGH) | |
408 | value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0; | |
409 | else | |
410 | value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1; | |
411 | ||
412 | if (is_on == BITBANG_CS_ACTIVE) { | |
413 | if (!test_and_set_bit(0, &p->flags)) { | |
414 | pm_runtime_get_sync(&p->pdev->dev); | |
415 | clk_enable(p->clk); | |
416 | } | |
417 | ||
418 | /* Configure pins before asserting CS */ | |
419 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
420 | !!(spi->mode & SPI_CPHA), | |
421 | !!(spi->mode & SPI_3WIRE), | |
50a77998 TY |
422 | !!(spi->mode & SPI_LSB_FIRST), |
423 | !!(spi->mode & SPI_CS_HIGH)); | |
8051effc MD |
424 | } |
425 | ||
426 | /* use spi->controller data for CS (same strategy as spi_gpio) */ | |
3e6006e4 | 427 | gpio_set_value((uintptr_t)spi->controller_data, value); |
8051effc MD |
428 | |
429 | if (is_on == BITBANG_CS_INACTIVE) { | |
430 | if (test_and_clear_bit(0, &p->flags)) { | |
431 | clk_disable(p->clk); | |
432 | pm_runtime_put(&p->pdev->dev); | |
433 | } | |
434 | } | |
435 | } | |
436 | ||
437 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, | |
438 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
439 | const void *, int, int), | |
440 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
441 | void *, int, int), | |
442 | const void *tx_buf, void *rx_buf, | |
443 | int words, int bits) | |
444 | { | |
445 | int fifo_shift; | |
446 | int ret; | |
447 | ||
448 | /* limit maximum word transfer to rx/tx fifo size */ | |
449 | if (tx_buf) | |
450 | words = min_t(int, words, p->tx_fifo_size); | |
451 | if (rx_buf) | |
452 | words = min_t(int, words, p->rx_fifo_size); | |
453 | ||
454 | /* the fifo contents need shifting */ | |
455 | fifo_shift = 32 - bits; | |
456 | ||
457 | /* setup msiof transfer mode registers */ | |
458 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
459 | ||
460 | /* write tx fifo */ | |
461 | if (tx_buf) | |
462 | tx_fifo(p, tx_buf, words, fifo_shift); | |
463 | ||
464 | /* setup clock and rx/tx signals */ | |
465 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
466 | if (rx_buf) | |
467 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
468 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
469 | ||
470 | /* start by setting frame bit */ | |
16735d02 | 471 | reinit_completion(&p->done); |
8051effc MD |
472 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); |
473 | if (ret) { | |
474 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
475 | goto err; | |
476 | } | |
477 | ||
478 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
479 | wait_for_completion(&p->done); | |
480 | ||
481 | /* read rx fifo */ | |
482 | if (rx_buf) | |
483 | rx_fifo(p, rx_buf, words, fifo_shift); | |
484 | ||
485 | /* clear status bits */ | |
486 | sh_msiof_reset_str(p); | |
487 | ||
a669c11a | 488 | /* shut down frame, rx/tx and clock signals */ |
8051effc MD |
489 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); |
490 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
491 | if (rx_buf) | |
492 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
493 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
494 | if (ret) { | |
495 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
496 | goto err; | |
497 | } | |
498 | ||
499 | return words; | |
500 | ||
501 | err: | |
502 | sh_msiof_write(p, IER, 0); | |
503 | return ret; | |
504 | } | |
505 | ||
506 | static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
507 | { | |
508 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
509 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); | |
510 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
511 | int bits; | |
512 | int bytes_per_word; | |
513 | int bytes_done; | |
514 | int words; | |
515 | int n; | |
9dabb3f3 | 516 | bool swab; |
8051effc MD |
517 | |
518 | bits = sh_msiof_spi_bits(spi, t); | |
519 | ||
9dabb3f3 GL |
520 | if (bits <= 8 && t->len > 15 && !(t->len & 3)) { |
521 | bits = 32; | |
522 | swab = true; | |
523 | } else { | |
524 | swab = false; | |
525 | } | |
526 | ||
8051effc MD |
527 | /* setup bytes per word and fifo read/write functions */ |
528 | if (bits <= 8) { | |
529 | bytes_per_word = 1; | |
530 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
531 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
532 | } else if (bits <= 16) { | |
533 | bytes_per_word = 2; | |
534 | if ((unsigned long)t->tx_buf & 0x01) | |
535 | tx_fifo = sh_msiof_spi_write_fifo_16u; | |
536 | else | |
537 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
538 | ||
539 | if ((unsigned long)t->rx_buf & 0x01) | |
540 | rx_fifo = sh_msiof_spi_read_fifo_16u; | |
541 | else | |
542 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
543 | } else if (swab) { |
544 | bytes_per_word = 4; | |
545 | if ((unsigned long)t->tx_buf & 0x03) | |
546 | tx_fifo = sh_msiof_spi_write_fifo_s32u; | |
547 | else | |
548 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
549 | ||
550 | if ((unsigned long)t->rx_buf & 0x03) | |
551 | rx_fifo = sh_msiof_spi_read_fifo_s32u; | |
552 | else | |
553 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
554 | } else { |
555 | bytes_per_word = 4; | |
556 | if ((unsigned long)t->tx_buf & 0x03) | |
557 | tx_fifo = sh_msiof_spi_write_fifo_32u; | |
558 | else | |
559 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
560 | ||
561 | if ((unsigned long)t->rx_buf & 0x03) | |
562 | rx_fifo = sh_msiof_spi_read_fifo_32u; | |
563 | else | |
564 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
565 | } | |
566 | ||
567 | /* setup clocks (clock already enabled in chipselect()) */ | |
568 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), | |
569 | sh_msiof_spi_hz(spi, t)); | |
570 | ||
571 | /* transfer in fifo sized chunks */ | |
572 | words = t->len / bytes_per_word; | |
573 | bytes_done = 0; | |
574 | ||
575 | while (bytes_done < t->len) { | |
8a6afb9a GL |
576 | void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL; |
577 | const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL; | |
8051effc | 578 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, |
8a6afb9a GL |
579 | tx_buf, |
580 | rx_buf, | |
8051effc MD |
581 | words, bits); |
582 | if (n < 0) | |
583 | break; | |
584 | ||
585 | bytes_done += n * bytes_per_word; | |
586 | words -= n; | |
587 | } | |
588 | ||
589 | return bytes_done; | |
590 | } | |
591 | ||
592 | static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, | |
593 | u32 word, u8 bits) | |
594 | { | |
595 | BUG(); /* unused but needed by bitbang code */ | |
596 | return 0; | |
597 | } | |
598 | ||
cf9c86ef BH |
599 | #ifdef CONFIG_OF |
600 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
601 | { | |
602 | struct sh_msiof_spi_info *info; | |
603 | struct device_node *np = dev->of_node; | |
604 | u32 num_cs = 0; | |
605 | ||
606 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
607 | if (!info) { | |
608 | dev_err(dev, "failed to allocate setup data\n"); | |
609 | return NULL; | |
610 | } | |
611 | ||
612 | /* Parse the MSIOF properties */ | |
613 | of_property_read_u32(np, "num-cs", &num_cs); | |
614 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
615 | &info->tx_fifo_override); | |
616 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
617 | &info->rx_fifo_override); | |
618 | ||
619 | info->num_chipselect = num_cs; | |
620 | ||
621 | return info; | |
622 | } | |
623 | #else | |
624 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
625 | { | |
626 | return NULL; | |
627 | } | |
628 | #endif | |
629 | ||
8051effc MD |
630 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
631 | { | |
632 | struct resource *r; | |
633 | struct spi_master *master; | |
634 | struct sh_msiof_spi_priv *p; | |
8051effc MD |
635 | int i; |
636 | int ret; | |
637 | ||
638 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
639 | if (master == NULL) { | |
640 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 641 | return -ENOMEM; |
8051effc MD |
642 | } |
643 | ||
644 | p = spi_master_get_devdata(master); | |
645 | ||
646 | platform_set_drvdata(pdev, p); | |
cf9c86ef BH |
647 | if (pdev->dev.of_node) |
648 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); | |
649 | else | |
8074cf06 | 650 | p->info = dev_get_platdata(&pdev->dev); |
cf9c86ef BH |
651 | |
652 | if (!p->info) { | |
653 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
654 | ret = -ENXIO; | |
655 | goto err1; | |
656 | } | |
657 | ||
8051effc MD |
658 | init_completion(&p->done); |
659 | ||
b4dd05de | 660 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 661 | if (IS_ERR(p->clk)) { |
078b6ead | 662 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
663 | ret = PTR_ERR(p->clk); |
664 | goto err1; | |
665 | } | |
666 | ||
8051effc | 667 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
668 | if (i < 0) { |
669 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 670 | ret = -ENOENT; |
b4dd05de | 671 | goto err1; |
8051effc | 672 | } |
b4dd05de LP |
673 | |
674 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
675 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
676 | if (IS_ERR(p->mapbase)) { | |
677 | ret = PTR_ERR(p->mapbase); | |
678 | goto err1; | |
8051effc MD |
679 | } |
680 | ||
b4dd05de LP |
681 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
682 | dev_name(&pdev->dev), p); | |
8051effc MD |
683 | if (ret) { |
684 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 685 | goto err1; |
8051effc MD |
686 | } |
687 | ||
5c32d29f LP |
688 | ret = clk_prepare(p->clk); |
689 | if (ret < 0) { | |
690 | dev_err(&pdev->dev, "unable to prepare clock\n"); | |
691 | goto err1; | |
8051effc MD |
692 | } |
693 | ||
694 | p->pdev = pdev; | |
695 | pm_runtime_enable(&pdev->dev); | |
696 | ||
697 | /* The standard version of MSIOF use 64 word FIFOs */ | |
698 | p->tx_fifo_size = 64; | |
699 | p->rx_fifo_size = 64; | |
700 | ||
701 | /* Platform data may override FIFO sizes */ | |
702 | if (p->info->tx_fifo_override) | |
703 | p->tx_fifo_size = p->info->tx_fifo_override; | |
704 | if (p->info->rx_fifo_override) | |
705 | p->rx_fifo_size = p->info->rx_fifo_override; | |
706 | ||
707 | /* init master and bitbang code */ | |
708 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
709 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
710 | master->flags = 0; | |
711 | master->bus_num = pdev->id; | |
f7c05e83 | 712 | master->dev.of_node = pdev->dev.of_node; |
8051effc MD |
713 | master->num_chipselect = p->info->num_chipselect; |
714 | master->setup = spi_bitbang_setup; | |
715 | master->cleanup = spi_bitbang_cleanup; | |
716 | ||
717 | p->bitbang.master = master; | |
718 | p->bitbang.chipselect = sh_msiof_spi_chipselect; | |
719 | p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer; | |
720 | p->bitbang.txrx_bufs = sh_msiof_spi_txrx; | |
721 | p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; | |
722 | p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; | |
723 | p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word; | |
724 | p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word; | |
725 | ||
726 | ret = spi_bitbang_start(&p->bitbang); | |
727 | if (ret == 0) | |
728 | return 0; | |
729 | ||
730 | pm_runtime_disable(&pdev->dev); | |
5c32d29f | 731 | clk_unprepare(p->clk); |
8051effc MD |
732 | err1: |
733 | spi_master_put(master); | |
8051effc MD |
734 | return ret; |
735 | } | |
736 | ||
737 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
738 | { | |
739 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
740 | int ret; | |
741 | ||
742 | ret = spi_bitbang_stop(&p->bitbang); | |
743 | if (!ret) { | |
744 | pm_runtime_disable(&pdev->dev); | |
5c32d29f | 745 | clk_unprepare(p->clk); |
8051effc MD |
746 | spi_master_put(p->bitbang.master); |
747 | } | |
748 | return ret; | |
749 | } | |
750 | ||
cf9c86ef BH |
751 | #ifdef CONFIG_OF |
752 | static const struct of_device_id sh_msiof_match[] = { | |
753 | { .compatible = "renesas,sh-msiof", }, | |
754 | { .compatible = "renesas,sh-mobile-msiof", }, | |
755 | {}, | |
756 | }; | |
757 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
cf9c86ef BH |
758 | #endif |
759 | ||
8051effc MD |
760 | static struct platform_driver sh_msiof_spi_drv = { |
761 | .probe = sh_msiof_spi_probe, | |
762 | .remove = sh_msiof_spi_remove, | |
763 | .driver = { | |
764 | .name = "spi_sh_msiof", | |
765 | .owner = THIS_MODULE, | |
691ee4ed | 766 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
767 | }, |
768 | }; | |
940ab889 | 769 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
770 | |
771 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
772 | MODULE_AUTHOR("Magnus Damm"); | |
773 | MODULE_LICENSE("GPL v2"); | |
774 | MODULE_ALIAS("platform:spi_sh_msiof"); |