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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8051effc | 19 | #include <linux/interrupt.h> |
e2dbf5eb GL |
20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | |
d7614de4 | 22 | #include <linux/module.h> |
cf9c86ef | 23 | #include <linux/of.h> |
50a7e23f | 24 | #include <linux/of_device.h> |
8051effc | 25 | #include <linux/platform_device.h> |
8051effc | 26 | #include <linux/pm_runtime.h> |
8051effc | 27 | |
e2dbf5eb | 28 | #include <linux/spi/sh_msiof.h> |
8051effc MD |
29 | #include <linux/spi/spi.h> |
30 | #include <linux/spi/spi_bitbang.h> | |
8051effc | 31 | |
8051effc MD |
32 | #include <asm/unaligned.h> |
33 | ||
50a7e23f GU |
34 | |
35 | struct sh_msiof_chipdata { | |
36 | u16 tx_fifo_size; | |
37 | u16 rx_fifo_size; | |
beb74bb0 | 38 | u16 master_flags; |
50a7e23f GU |
39 | }; |
40 | ||
8051effc MD |
41 | struct sh_msiof_spi_priv { |
42 | struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */ | |
43 | void __iomem *mapbase; | |
44 | struct clk *clk; | |
45 | struct platform_device *pdev; | |
50a7e23f | 46 | const struct sh_msiof_chipdata *chipdata; |
8051effc MD |
47 | struct sh_msiof_spi_info *info; |
48 | struct completion done; | |
49 | unsigned long flags; | |
50 | int tx_fifo_size; | |
51 | int rx_fifo_size; | |
52 | }; | |
53 | ||
01cfef57 GU |
54 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
55 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
56 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
57 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
58 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
59 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
60 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
61 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
62 | #define CTR 0x28 /* Control Register */ | |
63 | #define FCTR 0x30 /* FIFO Control Register */ | |
64 | #define STR 0x40 /* Status Register */ | |
65 | #define IER 0x44 /* Interrupt Enable Register */ | |
66 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
67 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
68 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
69 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
70 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
71 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
72 | ||
73 | /* TMDR1 and RMDR1 */ | |
74 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
75 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
76 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
77 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
78 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
79 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
80 | #define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ | |
81 | #define MDR1_FLD_SHIFT 2 | |
82 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
83 | /* TMDR1 */ | |
84 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
85 | ||
86 | /* TMDR2 and RMDR2 */ | |
87 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
88 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
89 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
90 | ||
91 | /* TSCR and RSCR */ | |
92 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
93 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
94 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
95 | #define SCR_BRDV_DIV_2 0x0000 | |
96 | #define SCR_BRDV_DIV_4 0x0001 | |
97 | #define SCR_BRDV_DIV_8 0x0002 | |
98 | #define SCR_BRDV_DIV_16 0x0003 | |
99 | #define SCR_BRDV_DIV_32 0x0004 | |
100 | #define SCR_BRDV_DIV_1 0x0007 | |
101 | ||
102 | /* CTR */ | |
103 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
104 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
105 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
106 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
107 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
108 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
109 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
110 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
111 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
112 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
113 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
114 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
115 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
116 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
117 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
118 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
119 | ||
120 | /* STR and IER */ | |
121 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ | |
122 | #define STR_REOF 0x00000080 /* Frame Reception End */ | |
123 | ||
124 | ||
e2dbf5eb | 125 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
126 | { |
127 | switch (reg_offs) { | |
128 | case TSCR: | |
129 | case RSCR: | |
130 | return ioread16(p->mapbase + reg_offs); | |
131 | default: | |
132 | return ioread32(p->mapbase + reg_offs); | |
133 | } | |
134 | } | |
135 | ||
136 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 137 | u32 value) |
8051effc MD |
138 | { |
139 | switch (reg_offs) { | |
140 | case TSCR: | |
141 | case RSCR: | |
142 | iowrite16(value, p->mapbase + reg_offs); | |
143 | break; | |
144 | default: | |
145 | iowrite32(value, p->mapbase + reg_offs); | |
146 | break; | |
147 | } | |
148 | } | |
149 | ||
150 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 151 | u32 clr, u32 set) |
8051effc | 152 | { |
e2dbf5eb GL |
153 | u32 mask = clr | set; |
154 | u32 data; | |
8051effc MD |
155 | int k; |
156 | ||
157 | data = sh_msiof_read(p, CTR); | |
158 | data &= ~clr; | |
159 | data |= set; | |
160 | sh_msiof_write(p, CTR, data); | |
161 | ||
162 | for (k = 100; k > 0; k--) { | |
163 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
164 | break; | |
165 | ||
166 | udelay(10); | |
167 | } | |
168 | ||
169 | return k > 0 ? 0 : -ETIMEDOUT; | |
170 | } | |
171 | ||
172 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
173 | { | |
174 | struct sh_msiof_spi_priv *p = data; | |
175 | ||
176 | /* just disable the interrupt and wake up */ | |
177 | sh_msiof_write(p, IER, 0); | |
178 | complete(&p->done); | |
179 | ||
180 | return IRQ_HANDLED; | |
181 | } | |
182 | ||
183 | static struct { | |
184 | unsigned short div; | |
185 | unsigned short scr; | |
186 | } const sh_msiof_spi_clk_table[] = { | |
01cfef57 GU |
187 | { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, |
188 | { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, | |
189 | { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, | |
190 | { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, | |
191 | { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, | |
192 | { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, | |
193 | { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, | |
194 | { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, | |
195 | { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, | |
196 | { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, | |
197 | { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, | |
8051effc MD |
198 | }; |
199 | ||
200 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 201 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
202 | { |
203 | unsigned long div = 1024; | |
204 | size_t k; | |
205 | ||
206 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 207 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
208 | |
209 | /* TODO: make more fine grained */ | |
210 | ||
211 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
212 | if (sh_msiof_spi_clk_table[k].div >= div) | |
213 | break; | |
214 | } | |
215 | ||
216 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
217 | ||
218 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
beb74bb0 GU |
219 | if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
220 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
8051effc MD |
221 | } |
222 | ||
223 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 224 | u32 cpol, u32 cpha, |
50a77998 | 225 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 226 | { |
e2dbf5eb | 227 | u32 tmp; |
8051effc MD |
228 | int edge; |
229 | ||
230 | /* | |
e8708ef7 MP |
231 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
232 | * 0 0 10 10 1 1 | |
233 | * 0 1 10 10 0 0 | |
234 | * 1 0 11 11 0 0 | |
235 | * 1 1 11 11 1 1 | |
8051effc | 236 | */ |
8051effc | 237 | sh_msiof_write(p, FCTR, 0); |
50a77998 | 238 | |
01cfef57 GU |
239 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
240 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
241 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
242 | sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); | |
beb74bb0 GU |
243 | if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { |
244 | /* These bits are reserved if RX needs TX */ | |
245 | tmp &= ~0x0000ffff; | |
246 | } | |
01cfef57 | 247 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 248 | |
01cfef57 GU |
249 | tmp = 0; |
250 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
251 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 252 | |
e2dbf5eb | 253 | edge = cpol ^ !cpha; |
8051effc | 254 | |
01cfef57 GU |
255 | tmp |= edge << CTR_TEDG_SHIFT; |
256 | tmp |= edge << CTR_REDG_SHIFT; | |
257 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
258 | sh_msiof_write(p, CTR, tmp); |
259 | } | |
260 | ||
261 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
262 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 263 | u32 bits, u32 words) |
8051effc | 264 | { |
01cfef57 | 265 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 266 | |
beb74bb0 | 267 | if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
268 | sh_msiof_write(p, TMDR2, dr2); |
269 | else | |
01cfef57 | 270 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
271 | |
272 | if (rx_buf) | |
273 | sh_msiof_write(p, RMDR2, dr2); | |
274 | ||
275 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
276 | } | |
277 | ||
278 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
279 | { | |
280 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
281 | } | |
282 | ||
283 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
284 | const void *tx_buf, int words, int fs) | |
285 | { | |
e2dbf5eb | 286 | const u8 *buf_8 = tx_buf; |
8051effc MD |
287 | int k; |
288 | ||
289 | for (k = 0; k < words; k++) | |
290 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
291 | } | |
292 | ||
293 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
294 | const void *tx_buf, int words, int fs) | |
295 | { | |
e2dbf5eb | 296 | const u16 *buf_16 = tx_buf; |
8051effc MD |
297 | int k; |
298 | ||
299 | for (k = 0; k < words; k++) | |
300 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
301 | } | |
302 | ||
303 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
304 | const void *tx_buf, int words, int fs) | |
305 | { | |
e2dbf5eb | 306 | const u16 *buf_16 = tx_buf; |
8051effc MD |
307 | int k; |
308 | ||
309 | for (k = 0; k < words; k++) | |
310 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
311 | } | |
312 | ||
313 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
314 | const void *tx_buf, int words, int fs) | |
315 | { | |
e2dbf5eb | 316 | const u32 *buf_32 = tx_buf; |
8051effc MD |
317 | int k; |
318 | ||
319 | for (k = 0; k < words; k++) | |
320 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
321 | } | |
322 | ||
323 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
324 | const void *tx_buf, int words, int fs) | |
325 | { | |
e2dbf5eb | 326 | const u32 *buf_32 = tx_buf; |
8051effc MD |
327 | int k; |
328 | ||
329 | for (k = 0; k < words; k++) | |
330 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
331 | } | |
332 | ||
9dabb3f3 GL |
333 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
334 | const void *tx_buf, int words, int fs) | |
335 | { | |
336 | const u32 *buf_32 = tx_buf; | |
337 | int k; | |
338 | ||
339 | for (k = 0; k < words; k++) | |
340 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
341 | } | |
342 | ||
343 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
344 | const void *tx_buf, int words, int fs) | |
345 | { | |
346 | const u32 *buf_32 = tx_buf; | |
347 | int k; | |
348 | ||
349 | for (k = 0; k < words; k++) | |
350 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
351 | } | |
352 | ||
8051effc MD |
353 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
354 | void *rx_buf, int words, int fs) | |
355 | { | |
e2dbf5eb | 356 | u8 *buf_8 = rx_buf; |
8051effc MD |
357 | int k; |
358 | ||
359 | for (k = 0; k < words; k++) | |
360 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
361 | } | |
362 | ||
363 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
364 | void *rx_buf, int words, int fs) | |
365 | { | |
e2dbf5eb | 366 | u16 *buf_16 = rx_buf; |
8051effc MD |
367 | int k; |
368 | ||
369 | for (k = 0; k < words; k++) | |
370 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
371 | } | |
372 | ||
373 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
374 | void *rx_buf, int words, int fs) | |
375 | { | |
e2dbf5eb | 376 | u16 *buf_16 = rx_buf; |
8051effc MD |
377 | int k; |
378 | ||
379 | for (k = 0; k < words; k++) | |
380 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
381 | } | |
382 | ||
383 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
384 | void *rx_buf, int words, int fs) | |
385 | { | |
e2dbf5eb | 386 | u32 *buf_32 = rx_buf; |
8051effc MD |
387 | int k; |
388 | ||
389 | for (k = 0; k < words; k++) | |
390 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
391 | } | |
392 | ||
393 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
394 | void *rx_buf, int words, int fs) | |
395 | { | |
e2dbf5eb | 396 | u32 *buf_32 = rx_buf; |
8051effc MD |
397 | int k; |
398 | ||
399 | for (k = 0; k < words; k++) | |
400 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
401 | } | |
402 | ||
9dabb3f3 GL |
403 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
404 | void *rx_buf, int words, int fs) | |
405 | { | |
406 | u32 *buf_32 = rx_buf; | |
407 | int k; | |
408 | ||
409 | for (k = 0; k < words; k++) | |
410 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
411 | } | |
412 | ||
413 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
414 | void *rx_buf, int words, int fs) | |
415 | { | |
416 | u32 *buf_32 = rx_buf; | |
417 | int k; | |
418 | ||
419 | for (k = 0; k < words; k++) | |
420 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
421 | } | |
422 | ||
8051effc MD |
423 | static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) |
424 | { | |
425 | int bits; | |
426 | ||
427 | bits = t ? t->bits_per_word : 0; | |
e2dbf5eb GL |
428 | if (!bits) |
429 | bits = spi->bits_per_word; | |
8051effc MD |
430 | return bits; |
431 | } | |
432 | ||
6a85fc5a | 433 | static u32 sh_msiof_spi_hz(struct spi_device *spi, struct spi_transfer *t) |
8051effc | 434 | { |
6a85fc5a | 435 | u32 hz; |
8051effc MD |
436 | |
437 | hz = t ? t->speed_hz : 0; | |
e2dbf5eb GL |
438 | if (!hz) |
439 | hz = spi->max_speed_hz; | |
8051effc MD |
440 | return hz; |
441 | } | |
442 | ||
443 | static int sh_msiof_spi_setup_transfer(struct spi_device *spi, | |
444 | struct spi_transfer *t) | |
445 | { | |
446 | int bits; | |
447 | ||
448 | /* noting to check hz values against since parent clock is disabled */ | |
449 | ||
450 | bits = sh_msiof_spi_bits(spi, t); | |
451 | if (bits < 8) | |
452 | return -EINVAL; | |
453 | if (bits > 32) | |
454 | return -EINVAL; | |
455 | ||
456 | return spi_bitbang_setup_transfer(spi, t); | |
457 | } | |
458 | ||
8d19534a GU |
459 | static int sh_msiof_spi_setup(struct spi_device *spi) |
460 | { | |
461 | struct device_node *np = spi->master->dev.of_node; | |
462 | ||
463 | if (!np) { | |
464 | /* | |
465 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
466 | * if any. otherwise let HW control CS | |
467 | */ | |
468 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
469 | } | |
470 | ||
471 | return spi_bitbang_setup(spi); | |
472 | } | |
473 | ||
8051effc MD |
474 | static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) |
475 | { | |
476 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
477 | int value; | |
478 | ||
479 | /* chip select is active low unless SPI_CS_HIGH is set */ | |
480 | if (spi->mode & SPI_CS_HIGH) | |
481 | value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0; | |
482 | else | |
483 | value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1; | |
484 | ||
485 | if (is_on == BITBANG_CS_ACTIVE) { | |
486 | if (!test_and_set_bit(0, &p->flags)) { | |
487 | pm_runtime_get_sync(&p->pdev->dev); | |
488 | clk_enable(p->clk); | |
489 | } | |
490 | ||
491 | /* Configure pins before asserting CS */ | |
492 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
493 | !!(spi->mode & SPI_CPHA), | |
494 | !!(spi->mode & SPI_3WIRE), | |
50a77998 TY |
495 | !!(spi->mode & SPI_LSB_FIRST), |
496 | !!(spi->mode & SPI_CS_HIGH)); | |
8051effc MD |
497 | } |
498 | ||
8d19534a GU |
499 | if (spi->cs_gpio >= 0) |
500 | gpio_set_value(spi->cs_gpio, value); | |
8051effc MD |
501 | |
502 | if (is_on == BITBANG_CS_INACTIVE) { | |
503 | if (test_and_clear_bit(0, &p->flags)) { | |
504 | clk_disable(p->clk); | |
505 | pm_runtime_put(&p->pdev->dev); | |
506 | } | |
507 | } | |
508 | } | |
509 | ||
510 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, | |
511 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
512 | const void *, int, int), | |
513 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
514 | void *, int, int), | |
515 | const void *tx_buf, void *rx_buf, | |
516 | int words, int bits) | |
517 | { | |
518 | int fifo_shift; | |
519 | int ret; | |
520 | ||
521 | /* limit maximum word transfer to rx/tx fifo size */ | |
522 | if (tx_buf) | |
523 | words = min_t(int, words, p->tx_fifo_size); | |
524 | if (rx_buf) | |
525 | words = min_t(int, words, p->rx_fifo_size); | |
526 | ||
527 | /* the fifo contents need shifting */ | |
528 | fifo_shift = 32 - bits; | |
529 | ||
530 | /* setup msiof transfer mode registers */ | |
531 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
532 | ||
533 | /* write tx fifo */ | |
534 | if (tx_buf) | |
535 | tx_fifo(p, tx_buf, words, fifo_shift); | |
536 | ||
537 | /* setup clock and rx/tx signals */ | |
538 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
539 | if (rx_buf) | |
540 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
541 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
542 | ||
543 | /* start by setting frame bit */ | |
16735d02 | 544 | reinit_completion(&p->done); |
8051effc MD |
545 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); |
546 | if (ret) { | |
547 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
548 | goto err; | |
549 | } | |
550 | ||
551 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
552 | wait_for_completion(&p->done); | |
553 | ||
554 | /* read rx fifo */ | |
555 | if (rx_buf) | |
556 | rx_fifo(p, rx_buf, words, fifo_shift); | |
557 | ||
558 | /* clear status bits */ | |
559 | sh_msiof_reset_str(p); | |
560 | ||
a669c11a | 561 | /* shut down frame, rx/tx and clock signals */ |
8051effc MD |
562 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); |
563 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
564 | if (rx_buf) | |
565 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
566 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
567 | if (ret) { | |
568 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
569 | goto err; | |
570 | } | |
571 | ||
572 | return words; | |
573 | ||
574 | err: | |
575 | sh_msiof_write(p, IER, 0); | |
576 | return ret; | |
577 | } | |
578 | ||
579 | static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
580 | { | |
581 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
582 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); | |
583 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
584 | int bits; | |
585 | int bytes_per_word; | |
586 | int bytes_done; | |
587 | int words; | |
588 | int n; | |
9dabb3f3 | 589 | bool swab; |
8051effc MD |
590 | |
591 | bits = sh_msiof_spi_bits(spi, t); | |
592 | ||
9dabb3f3 GL |
593 | if (bits <= 8 && t->len > 15 && !(t->len & 3)) { |
594 | bits = 32; | |
595 | swab = true; | |
596 | } else { | |
597 | swab = false; | |
598 | } | |
599 | ||
8051effc MD |
600 | /* setup bytes per word and fifo read/write functions */ |
601 | if (bits <= 8) { | |
602 | bytes_per_word = 1; | |
603 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
604 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
605 | } else if (bits <= 16) { | |
606 | bytes_per_word = 2; | |
607 | if ((unsigned long)t->tx_buf & 0x01) | |
608 | tx_fifo = sh_msiof_spi_write_fifo_16u; | |
609 | else | |
610 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
611 | ||
612 | if ((unsigned long)t->rx_buf & 0x01) | |
613 | rx_fifo = sh_msiof_spi_read_fifo_16u; | |
614 | else | |
615 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
616 | } else if (swab) { |
617 | bytes_per_word = 4; | |
618 | if ((unsigned long)t->tx_buf & 0x03) | |
619 | tx_fifo = sh_msiof_spi_write_fifo_s32u; | |
620 | else | |
621 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
622 | ||
623 | if ((unsigned long)t->rx_buf & 0x03) | |
624 | rx_fifo = sh_msiof_spi_read_fifo_s32u; | |
625 | else | |
626 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
627 | } else { |
628 | bytes_per_word = 4; | |
629 | if ((unsigned long)t->tx_buf & 0x03) | |
630 | tx_fifo = sh_msiof_spi_write_fifo_32u; | |
631 | else | |
632 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
633 | ||
634 | if ((unsigned long)t->rx_buf & 0x03) | |
635 | rx_fifo = sh_msiof_spi_read_fifo_32u; | |
636 | else | |
637 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
638 | } | |
639 | ||
640 | /* setup clocks (clock already enabled in chipselect()) */ | |
641 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), | |
642 | sh_msiof_spi_hz(spi, t)); | |
643 | ||
644 | /* transfer in fifo sized chunks */ | |
645 | words = t->len / bytes_per_word; | |
646 | bytes_done = 0; | |
647 | ||
648 | while (bytes_done < t->len) { | |
8a6afb9a GL |
649 | void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL; |
650 | const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL; | |
8051effc | 651 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, |
8a6afb9a GL |
652 | tx_buf, |
653 | rx_buf, | |
8051effc MD |
654 | words, bits); |
655 | if (n < 0) | |
656 | break; | |
657 | ||
658 | bytes_done += n * bytes_per_word; | |
659 | words -= n; | |
660 | } | |
661 | ||
662 | return bytes_done; | |
663 | } | |
664 | ||
665 | static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, | |
666 | u32 word, u8 bits) | |
667 | { | |
668 | BUG(); /* unused but needed by bitbang code */ | |
669 | return 0; | |
670 | } | |
671 | ||
50a7e23f GU |
672 | static const struct sh_msiof_chipdata sh_data = { |
673 | .tx_fifo_size = 64, | |
674 | .rx_fifo_size = 64, | |
beb74bb0 GU |
675 | .master_flags = 0, |
676 | }; | |
677 | ||
678 | static const struct sh_msiof_chipdata r8a779x_data = { | |
679 | .tx_fifo_size = 64, | |
680 | .rx_fifo_size = 256, | |
681 | .master_flags = SPI_MASTER_MUST_TX, | |
50a7e23f GU |
682 | }; |
683 | ||
684 | static const struct of_device_id sh_msiof_match[] = { | |
685 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, | |
686 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, | |
beb74bb0 GU |
687 | { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, |
688 | { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, | |
50a7e23f GU |
689 | {}, |
690 | }; | |
691 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
692 | ||
cf9c86ef BH |
693 | #ifdef CONFIG_OF |
694 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
695 | { | |
696 | struct sh_msiof_spi_info *info; | |
697 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 698 | u32 num_cs = 1; |
cf9c86ef BH |
699 | |
700 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
701 | if (!info) { | |
702 | dev_err(dev, "failed to allocate setup data\n"); | |
703 | return NULL; | |
704 | } | |
705 | ||
706 | /* Parse the MSIOF properties */ | |
707 | of_property_read_u32(np, "num-cs", &num_cs); | |
708 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
709 | &info->tx_fifo_override); | |
710 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
711 | &info->rx_fifo_override); | |
712 | ||
713 | info->num_chipselect = num_cs; | |
714 | ||
715 | return info; | |
716 | } | |
717 | #else | |
718 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
719 | { | |
720 | return NULL; | |
721 | } | |
722 | #endif | |
723 | ||
8051effc MD |
724 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
725 | { | |
726 | struct resource *r; | |
727 | struct spi_master *master; | |
50a7e23f | 728 | const struct of_device_id *of_id; |
8051effc | 729 | struct sh_msiof_spi_priv *p; |
8051effc MD |
730 | int i; |
731 | int ret; | |
732 | ||
733 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
734 | if (master == NULL) { | |
735 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 736 | return -ENOMEM; |
8051effc MD |
737 | } |
738 | ||
739 | p = spi_master_get_devdata(master); | |
740 | ||
741 | platform_set_drvdata(pdev, p); | |
50a7e23f GU |
742 | |
743 | of_id = of_match_device(sh_msiof_match, &pdev->dev); | |
744 | if (of_id) { | |
745 | p->chipdata = of_id->data; | |
cf9c86ef | 746 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f GU |
747 | } else { |
748 | p->chipdata = (const void *)pdev->id_entry->driver_data; | |
8074cf06 | 749 | p->info = dev_get_platdata(&pdev->dev); |
50a7e23f | 750 | } |
cf9c86ef BH |
751 | |
752 | if (!p->info) { | |
753 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
754 | ret = -ENXIO; | |
755 | goto err1; | |
756 | } | |
757 | ||
8051effc MD |
758 | init_completion(&p->done); |
759 | ||
b4dd05de | 760 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 761 | if (IS_ERR(p->clk)) { |
078b6ead | 762 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
763 | ret = PTR_ERR(p->clk); |
764 | goto err1; | |
765 | } | |
766 | ||
8051effc | 767 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
768 | if (i < 0) { |
769 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 770 | ret = -ENOENT; |
b4dd05de | 771 | goto err1; |
8051effc | 772 | } |
b4dd05de LP |
773 | |
774 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
775 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
776 | if (IS_ERR(p->mapbase)) { | |
777 | ret = PTR_ERR(p->mapbase); | |
778 | goto err1; | |
8051effc MD |
779 | } |
780 | ||
b4dd05de LP |
781 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
782 | dev_name(&pdev->dev), p); | |
8051effc MD |
783 | if (ret) { |
784 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 785 | goto err1; |
8051effc MD |
786 | } |
787 | ||
5c32d29f LP |
788 | ret = clk_prepare(p->clk); |
789 | if (ret < 0) { | |
790 | dev_err(&pdev->dev, "unable to prepare clock\n"); | |
791 | goto err1; | |
8051effc MD |
792 | } |
793 | ||
794 | p->pdev = pdev; | |
795 | pm_runtime_enable(&pdev->dev); | |
796 | ||
8051effc | 797 | /* Platform data may override FIFO sizes */ |
50a7e23f GU |
798 | p->tx_fifo_size = p->chipdata->tx_fifo_size; |
799 | p->rx_fifo_size = p->chipdata->rx_fifo_size; | |
8051effc MD |
800 | if (p->info->tx_fifo_override) |
801 | p->tx_fifo_size = p->info->tx_fifo_override; | |
802 | if (p->info->rx_fifo_override) | |
803 | p->rx_fifo_size = p->info->rx_fifo_override; | |
804 | ||
805 | /* init master and bitbang code */ | |
806 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
807 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
beb74bb0 | 808 | master->flags = p->chipdata->master_flags; |
8051effc | 809 | master->bus_num = pdev->id; |
f7c05e83 | 810 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 811 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 812 | master->setup = sh_msiof_spi_setup; |
8051effc MD |
813 | master->cleanup = spi_bitbang_cleanup; |
814 | ||
815 | p->bitbang.master = master; | |
816 | p->bitbang.chipselect = sh_msiof_spi_chipselect; | |
817 | p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer; | |
818 | p->bitbang.txrx_bufs = sh_msiof_spi_txrx; | |
819 | p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; | |
820 | p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; | |
821 | p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word; | |
822 | p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word; | |
823 | ||
824 | ret = spi_bitbang_start(&p->bitbang); | |
825 | if (ret == 0) | |
826 | return 0; | |
827 | ||
828 | pm_runtime_disable(&pdev->dev); | |
5c32d29f | 829 | clk_unprepare(p->clk); |
8051effc MD |
830 | err1: |
831 | spi_master_put(master); | |
8051effc MD |
832 | return ret; |
833 | } | |
834 | ||
835 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
836 | { | |
837 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
838 | int ret; | |
839 | ||
840 | ret = spi_bitbang_stop(&p->bitbang); | |
841 | if (!ret) { | |
842 | pm_runtime_disable(&pdev->dev); | |
5c32d29f | 843 | clk_unprepare(p->clk); |
8051effc MD |
844 | spi_master_put(p->bitbang.master); |
845 | } | |
846 | return ret; | |
847 | } | |
848 | ||
50a7e23f GU |
849 | static struct platform_device_id spi_driver_ids[] = { |
850 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, | |
beb74bb0 GU |
851 | { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, |
852 | { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, | |
cf9c86ef BH |
853 | {}, |
854 | }; | |
50a7e23f | 855 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 856 | |
8051effc MD |
857 | static struct platform_driver sh_msiof_spi_drv = { |
858 | .probe = sh_msiof_spi_probe, | |
859 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 860 | .id_table = spi_driver_ids, |
8051effc MD |
861 | .driver = { |
862 | .name = "spi_sh_msiof", | |
863 | .owner = THIS_MODULE, | |
691ee4ed | 864 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
865 | }, |
866 | }; | |
940ab889 | 867 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
868 | |
869 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
870 | MODULE_AUTHOR("Magnus Damm"); | |
871 | MODULE_LICENSE("GPL v2"); | |
872 | MODULE_ALIAS("platform:spi_sh_msiof"); |