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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
8051effc | 19 | #include <linux/interrupt.h> |
e2dbf5eb GL |
20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> | |
d7614de4 | 22 | #include <linux/module.h> |
cf9c86ef | 23 | #include <linux/of.h> |
50a7e23f | 24 | #include <linux/of_device.h> |
8051effc | 25 | #include <linux/platform_device.h> |
8051effc | 26 | #include <linux/pm_runtime.h> |
8051effc | 27 | |
e2dbf5eb | 28 | #include <linux/spi/sh_msiof.h> |
8051effc MD |
29 | #include <linux/spi/spi.h> |
30 | #include <linux/spi/spi_bitbang.h> | |
8051effc | 31 | |
8051effc MD |
32 | #include <asm/unaligned.h> |
33 | ||
50a7e23f GU |
34 | |
35 | struct sh_msiof_chipdata { | |
36 | u16 tx_fifo_size; | |
37 | u16 rx_fifo_size; | |
beb74bb0 | 38 | u16 master_flags; |
50a7e23f GU |
39 | }; |
40 | ||
8051effc MD |
41 | struct sh_msiof_spi_priv { |
42 | struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */ | |
43 | void __iomem *mapbase; | |
44 | struct clk *clk; | |
45 | struct platform_device *pdev; | |
50a7e23f | 46 | const struct sh_msiof_chipdata *chipdata; |
8051effc MD |
47 | struct sh_msiof_spi_info *info; |
48 | struct completion done; | |
8051effc MD |
49 | int tx_fifo_size; |
50 | int rx_fifo_size; | |
51 | }; | |
52 | ||
01cfef57 GU |
53 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
54 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
55 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
56 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
57 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
58 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
59 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
60 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
61 | #define CTR 0x28 /* Control Register */ | |
62 | #define FCTR 0x30 /* FIFO Control Register */ | |
63 | #define STR 0x40 /* Status Register */ | |
64 | #define IER 0x44 /* Interrupt Enable Register */ | |
65 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
66 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
67 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
68 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
69 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
70 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
71 | ||
72 | /* TMDR1 and RMDR1 */ | |
73 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
74 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
75 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
76 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
77 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
78 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
79 | #define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ | |
80 | #define MDR1_FLD_SHIFT 2 | |
81 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
82 | /* TMDR1 */ | |
83 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
84 | ||
85 | /* TMDR2 and RMDR2 */ | |
86 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
87 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
88 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
89 | ||
90 | /* TSCR and RSCR */ | |
91 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
92 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
93 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
94 | #define SCR_BRDV_DIV_2 0x0000 | |
95 | #define SCR_BRDV_DIV_4 0x0001 | |
96 | #define SCR_BRDV_DIV_8 0x0002 | |
97 | #define SCR_BRDV_DIV_16 0x0003 | |
98 | #define SCR_BRDV_DIV_32 0x0004 | |
99 | #define SCR_BRDV_DIV_1 0x0007 | |
100 | ||
101 | /* CTR */ | |
102 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
103 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
104 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
105 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
106 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
107 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
108 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
109 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
110 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
111 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
112 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
113 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
114 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
115 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
116 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
117 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
118 | ||
119 | /* STR and IER */ | |
120 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ | |
121 | #define STR_REOF 0x00000080 /* Frame Reception End */ | |
122 | ||
123 | ||
e2dbf5eb | 124 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
125 | { |
126 | switch (reg_offs) { | |
127 | case TSCR: | |
128 | case RSCR: | |
129 | return ioread16(p->mapbase + reg_offs); | |
130 | default: | |
131 | return ioread32(p->mapbase + reg_offs); | |
132 | } | |
133 | } | |
134 | ||
135 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 136 | u32 value) |
8051effc MD |
137 | { |
138 | switch (reg_offs) { | |
139 | case TSCR: | |
140 | case RSCR: | |
141 | iowrite16(value, p->mapbase + reg_offs); | |
142 | break; | |
143 | default: | |
144 | iowrite32(value, p->mapbase + reg_offs); | |
145 | break; | |
146 | } | |
147 | } | |
148 | ||
149 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 150 | u32 clr, u32 set) |
8051effc | 151 | { |
e2dbf5eb GL |
152 | u32 mask = clr | set; |
153 | u32 data; | |
8051effc MD |
154 | int k; |
155 | ||
156 | data = sh_msiof_read(p, CTR); | |
157 | data &= ~clr; | |
158 | data |= set; | |
159 | sh_msiof_write(p, CTR, data); | |
160 | ||
161 | for (k = 100; k > 0; k--) { | |
162 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
163 | break; | |
164 | ||
165 | udelay(10); | |
166 | } | |
167 | ||
168 | return k > 0 ? 0 : -ETIMEDOUT; | |
169 | } | |
170 | ||
171 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
172 | { | |
173 | struct sh_msiof_spi_priv *p = data; | |
174 | ||
175 | /* just disable the interrupt and wake up */ | |
176 | sh_msiof_write(p, IER, 0); | |
177 | complete(&p->done); | |
178 | ||
179 | return IRQ_HANDLED; | |
180 | } | |
181 | ||
182 | static struct { | |
183 | unsigned short div; | |
184 | unsigned short scr; | |
185 | } const sh_msiof_spi_clk_table[] = { | |
01cfef57 GU |
186 | { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, |
187 | { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, | |
188 | { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, | |
189 | { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, | |
190 | { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, | |
191 | { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, | |
192 | { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, | |
193 | { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, | |
194 | { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, | |
195 | { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, | |
196 | { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, | |
8051effc MD |
197 | }; |
198 | ||
199 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 200 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
201 | { |
202 | unsigned long div = 1024; | |
203 | size_t k; | |
204 | ||
205 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 206 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
207 | |
208 | /* TODO: make more fine grained */ | |
209 | ||
210 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
211 | if (sh_msiof_spi_clk_table[k].div >= div) | |
212 | break; | |
213 | } | |
214 | ||
215 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
216 | ||
217 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
beb74bb0 GU |
218 | if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
219 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
8051effc MD |
220 | } |
221 | ||
222 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 223 | u32 cpol, u32 cpha, |
50a77998 | 224 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 225 | { |
e2dbf5eb | 226 | u32 tmp; |
8051effc MD |
227 | int edge; |
228 | ||
229 | /* | |
e8708ef7 MP |
230 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
231 | * 0 0 10 10 1 1 | |
232 | * 0 1 10 10 0 0 | |
233 | * 1 0 11 11 0 0 | |
234 | * 1 1 11 11 1 1 | |
8051effc | 235 | */ |
8051effc | 236 | sh_msiof_write(p, FCTR, 0); |
50a77998 | 237 | |
01cfef57 GU |
238 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
239 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
240 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
241 | sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); | |
beb74bb0 GU |
242 | if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { |
243 | /* These bits are reserved if RX needs TX */ | |
244 | tmp &= ~0x0000ffff; | |
245 | } | |
01cfef57 | 246 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 247 | |
01cfef57 GU |
248 | tmp = 0; |
249 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
250 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 251 | |
e2dbf5eb | 252 | edge = cpol ^ !cpha; |
8051effc | 253 | |
01cfef57 GU |
254 | tmp |= edge << CTR_TEDG_SHIFT; |
255 | tmp |= edge << CTR_REDG_SHIFT; | |
256 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
257 | sh_msiof_write(p, CTR, tmp); |
258 | } | |
259 | ||
260 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
261 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 262 | u32 bits, u32 words) |
8051effc | 263 | { |
01cfef57 | 264 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 265 | |
beb74bb0 | 266 | if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
267 | sh_msiof_write(p, TMDR2, dr2); |
268 | else | |
01cfef57 | 269 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
270 | |
271 | if (rx_buf) | |
272 | sh_msiof_write(p, RMDR2, dr2); | |
273 | ||
274 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
275 | } | |
276 | ||
277 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
278 | { | |
279 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
280 | } | |
281 | ||
282 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
283 | const void *tx_buf, int words, int fs) | |
284 | { | |
e2dbf5eb | 285 | const u8 *buf_8 = tx_buf; |
8051effc MD |
286 | int k; |
287 | ||
288 | for (k = 0; k < words; k++) | |
289 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
290 | } | |
291 | ||
292 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
293 | const void *tx_buf, int words, int fs) | |
294 | { | |
e2dbf5eb | 295 | const u16 *buf_16 = tx_buf; |
8051effc MD |
296 | int k; |
297 | ||
298 | for (k = 0; k < words; k++) | |
299 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
300 | } | |
301 | ||
302 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
303 | const void *tx_buf, int words, int fs) | |
304 | { | |
e2dbf5eb | 305 | const u16 *buf_16 = tx_buf; |
8051effc MD |
306 | int k; |
307 | ||
308 | for (k = 0; k < words; k++) | |
309 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
310 | } | |
311 | ||
312 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
313 | const void *tx_buf, int words, int fs) | |
314 | { | |
e2dbf5eb | 315 | const u32 *buf_32 = tx_buf; |
8051effc MD |
316 | int k; |
317 | ||
318 | for (k = 0; k < words; k++) | |
319 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
320 | } | |
321 | ||
322 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
323 | const void *tx_buf, int words, int fs) | |
324 | { | |
e2dbf5eb | 325 | const u32 *buf_32 = tx_buf; |
8051effc MD |
326 | int k; |
327 | ||
328 | for (k = 0; k < words; k++) | |
329 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
330 | } | |
331 | ||
9dabb3f3 GL |
332 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
333 | const void *tx_buf, int words, int fs) | |
334 | { | |
335 | const u32 *buf_32 = tx_buf; | |
336 | int k; | |
337 | ||
338 | for (k = 0; k < words; k++) | |
339 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
340 | } | |
341 | ||
342 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
343 | const void *tx_buf, int words, int fs) | |
344 | { | |
345 | const u32 *buf_32 = tx_buf; | |
346 | int k; | |
347 | ||
348 | for (k = 0; k < words; k++) | |
349 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
350 | } | |
351 | ||
8051effc MD |
352 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
353 | void *rx_buf, int words, int fs) | |
354 | { | |
e2dbf5eb | 355 | u8 *buf_8 = rx_buf; |
8051effc MD |
356 | int k; |
357 | ||
358 | for (k = 0; k < words; k++) | |
359 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
360 | } | |
361 | ||
362 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
363 | void *rx_buf, int words, int fs) | |
364 | { | |
e2dbf5eb | 365 | u16 *buf_16 = rx_buf; |
8051effc MD |
366 | int k; |
367 | ||
368 | for (k = 0; k < words; k++) | |
369 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
370 | } | |
371 | ||
372 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
373 | void *rx_buf, int words, int fs) | |
374 | { | |
e2dbf5eb | 375 | u16 *buf_16 = rx_buf; |
8051effc MD |
376 | int k; |
377 | ||
378 | for (k = 0; k < words; k++) | |
379 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
380 | } | |
381 | ||
382 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
383 | void *rx_buf, int words, int fs) | |
384 | { | |
e2dbf5eb | 385 | u32 *buf_32 = rx_buf; |
8051effc MD |
386 | int k; |
387 | ||
388 | for (k = 0; k < words; k++) | |
389 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
390 | } | |
391 | ||
392 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
393 | void *rx_buf, int words, int fs) | |
394 | { | |
e2dbf5eb | 395 | u32 *buf_32 = rx_buf; |
8051effc MD |
396 | int k; |
397 | ||
398 | for (k = 0; k < words; k++) | |
399 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
400 | } | |
401 | ||
9dabb3f3 GL |
402 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
403 | void *rx_buf, int words, int fs) | |
404 | { | |
405 | u32 *buf_32 = rx_buf; | |
406 | int k; | |
407 | ||
408 | for (k = 0; k < words; k++) | |
409 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
410 | } | |
411 | ||
412 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
413 | void *rx_buf, int words, int fs) | |
414 | { | |
415 | u32 *buf_32 = rx_buf; | |
416 | int k; | |
417 | ||
418 | for (k = 0; k < words; k++) | |
419 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
420 | } | |
421 | ||
8051effc MD |
422 | static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t) |
423 | { | |
424 | int bits; | |
425 | ||
426 | bits = t ? t->bits_per_word : 0; | |
e2dbf5eb GL |
427 | if (!bits) |
428 | bits = spi->bits_per_word; | |
8051effc MD |
429 | return bits; |
430 | } | |
431 | ||
6a85fc5a | 432 | static u32 sh_msiof_spi_hz(struct spi_device *spi, struct spi_transfer *t) |
8051effc | 433 | { |
6a85fc5a | 434 | u32 hz; |
8051effc MD |
435 | |
436 | hz = t ? t->speed_hz : 0; | |
e2dbf5eb GL |
437 | if (!hz) |
438 | hz = spi->max_speed_hz; | |
8051effc MD |
439 | return hz; |
440 | } | |
441 | ||
442 | static int sh_msiof_spi_setup_transfer(struct spi_device *spi, | |
443 | struct spi_transfer *t) | |
444 | { | |
445 | int bits; | |
446 | ||
447 | /* noting to check hz values against since parent clock is disabled */ | |
448 | ||
449 | bits = sh_msiof_spi_bits(spi, t); | |
450 | if (bits < 8) | |
451 | return -EINVAL; | |
452 | if (bits > 32) | |
453 | return -EINVAL; | |
454 | ||
455 | return spi_bitbang_setup_transfer(spi, t); | |
456 | } | |
457 | ||
8d19534a GU |
458 | static int sh_msiof_spi_setup(struct spi_device *spi) |
459 | { | |
460 | struct device_node *np = spi->master->dev.of_node; | |
c833ff73 | 461 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); |
8d19534a GU |
462 | |
463 | if (!np) { | |
464 | /* | |
465 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
466 | * if any. otherwise let HW control CS | |
467 | */ | |
468 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
469 | } | |
470 | ||
c833ff73 GU |
471 | /* Configure pins before deasserting CS */ |
472 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
473 | !!(spi->mode & SPI_CPHA), | |
474 | !!(spi->mode & SPI_3WIRE), | |
475 | !!(spi->mode & SPI_LSB_FIRST), | |
476 | !!(spi->mode & SPI_CS_HIGH)); | |
477 | ||
8d19534a GU |
478 | return spi_bitbang_setup(spi); |
479 | } | |
480 | ||
c833ff73 GU |
481 | static int sh_msiof_prepare_message(struct spi_master *master, |
482 | struct spi_message *msg) | |
483 | { | |
484 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); | |
485 | const struct spi_device *spi = msg->spi; | |
486 | ||
487 | pm_runtime_get_sync(&p->pdev->dev); | |
488 | clk_enable(p->clk); | |
489 | ||
490 | /* Configure pins before asserting CS */ | |
491 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
492 | !!(spi->mode & SPI_CPHA), | |
493 | !!(spi->mode & SPI_3WIRE), | |
494 | !!(spi->mode & SPI_LSB_FIRST), | |
495 | !!(spi->mode & SPI_CS_HIGH)); | |
496 | return 0; | |
497 | } | |
498 | ||
499 | static int sh_msiof_unprepare_message(struct spi_master *master, | |
500 | struct spi_message *msg) | |
501 | { | |
502 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); | |
503 | ||
504 | clk_disable(p->clk); | |
505 | pm_runtime_put(&p->pdev->dev); | |
506 | return 0; | |
507 | } | |
508 | ||
8051effc MD |
509 | static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on) |
510 | { | |
8051effc MD |
511 | int value; |
512 | ||
513 | /* chip select is active low unless SPI_CS_HIGH is set */ | |
514 | if (spi->mode & SPI_CS_HIGH) | |
515 | value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0; | |
516 | else | |
517 | value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1; | |
518 | ||
8d19534a GU |
519 | if (spi->cs_gpio >= 0) |
520 | gpio_set_value(spi->cs_gpio, value); | |
8051effc MD |
521 | } |
522 | ||
523 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, | |
524 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
525 | const void *, int, int), | |
526 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
527 | void *, int, int), | |
528 | const void *tx_buf, void *rx_buf, | |
529 | int words, int bits) | |
530 | { | |
531 | int fifo_shift; | |
532 | int ret; | |
533 | ||
534 | /* limit maximum word transfer to rx/tx fifo size */ | |
535 | if (tx_buf) | |
536 | words = min_t(int, words, p->tx_fifo_size); | |
537 | if (rx_buf) | |
538 | words = min_t(int, words, p->rx_fifo_size); | |
539 | ||
540 | /* the fifo contents need shifting */ | |
541 | fifo_shift = 32 - bits; | |
542 | ||
543 | /* setup msiof transfer mode registers */ | |
544 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
545 | ||
546 | /* write tx fifo */ | |
547 | if (tx_buf) | |
548 | tx_fifo(p, tx_buf, words, fifo_shift); | |
549 | ||
550 | /* setup clock and rx/tx signals */ | |
551 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
552 | if (rx_buf) | |
553 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
554 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
555 | ||
556 | /* start by setting frame bit */ | |
16735d02 | 557 | reinit_completion(&p->done); |
8051effc MD |
558 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); |
559 | if (ret) { | |
560 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
561 | goto err; | |
562 | } | |
563 | ||
564 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
565 | wait_for_completion(&p->done); | |
566 | ||
567 | /* read rx fifo */ | |
568 | if (rx_buf) | |
569 | rx_fifo(p, rx_buf, words, fifo_shift); | |
570 | ||
571 | /* clear status bits */ | |
572 | sh_msiof_reset_str(p); | |
573 | ||
a669c11a | 574 | /* shut down frame, rx/tx and clock signals */ |
8051effc MD |
575 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); |
576 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
577 | if (rx_buf) | |
578 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
579 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
580 | if (ret) { | |
581 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
582 | goto err; | |
583 | } | |
584 | ||
585 | return words; | |
586 | ||
587 | err: | |
588 | sh_msiof_write(p, IER, 0); | |
589 | return ret; | |
590 | } | |
591 | ||
592 | static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
593 | { | |
594 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); | |
595 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); | |
596 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
597 | int bits; | |
598 | int bytes_per_word; | |
599 | int bytes_done; | |
600 | int words; | |
601 | int n; | |
9dabb3f3 | 602 | bool swab; |
8051effc MD |
603 | |
604 | bits = sh_msiof_spi_bits(spi, t); | |
605 | ||
9dabb3f3 GL |
606 | if (bits <= 8 && t->len > 15 && !(t->len & 3)) { |
607 | bits = 32; | |
608 | swab = true; | |
609 | } else { | |
610 | swab = false; | |
611 | } | |
612 | ||
8051effc MD |
613 | /* setup bytes per word and fifo read/write functions */ |
614 | if (bits <= 8) { | |
615 | bytes_per_word = 1; | |
616 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
617 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
618 | } else if (bits <= 16) { | |
619 | bytes_per_word = 2; | |
620 | if ((unsigned long)t->tx_buf & 0x01) | |
621 | tx_fifo = sh_msiof_spi_write_fifo_16u; | |
622 | else | |
623 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
624 | ||
625 | if ((unsigned long)t->rx_buf & 0x01) | |
626 | rx_fifo = sh_msiof_spi_read_fifo_16u; | |
627 | else | |
628 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
629 | } else if (swab) { |
630 | bytes_per_word = 4; | |
631 | if ((unsigned long)t->tx_buf & 0x03) | |
632 | tx_fifo = sh_msiof_spi_write_fifo_s32u; | |
633 | else | |
634 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
635 | ||
636 | if ((unsigned long)t->rx_buf & 0x03) | |
637 | rx_fifo = sh_msiof_spi_read_fifo_s32u; | |
638 | else | |
639 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
640 | } else { |
641 | bytes_per_word = 4; | |
642 | if ((unsigned long)t->tx_buf & 0x03) | |
643 | tx_fifo = sh_msiof_spi_write_fifo_32u; | |
644 | else | |
645 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
646 | ||
647 | if ((unsigned long)t->rx_buf & 0x03) | |
648 | rx_fifo = sh_msiof_spi_read_fifo_32u; | |
649 | else | |
650 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
651 | } | |
652 | ||
653 | /* setup clocks (clock already enabled in chipselect()) */ | |
654 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), | |
655 | sh_msiof_spi_hz(spi, t)); | |
656 | ||
657 | /* transfer in fifo sized chunks */ | |
658 | words = t->len / bytes_per_word; | |
659 | bytes_done = 0; | |
660 | ||
661 | while (bytes_done < t->len) { | |
8a6afb9a GL |
662 | void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL; |
663 | const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL; | |
8051effc | 664 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, |
8a6afb9a GL |
665 | tx_buf, |
666 | rx_buf, | |
8051effc MD |
667 | words, bits); |
668 | if (n < 0) | |
669 | break; | |
670 | ||
671 | bytes_done += n * bytes_per_word; | |
672 | words -= n; | |
673 | } | |
674 | ||
675 | return bytes_done; | |
676 | } | |
677 | ||
678 | static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs, | |
679 | u32 word, u8 bits) | |
680 | { | |
681 | BUG(); /* unused but needed by bitbang code */ | |
682 | return 0; | |
683 | } | |
684 | ||
50a7e23f GU |
685 | static const struct sh_msiof_chipdata sh_data = { |
686 | .tx_fifo_size = 64, | |
687 | .rx_fifo_size = 64, | |
beb74bb0 GU |
688 | .master_flags = 0, |
689 | }; | |
690 | ||
691 | static const struct sh_msiof_chipdata r8a779x_data = { | |
692 | .tx_fifo_size = 64, | |
693 | .rx_fifo_size = 256, | |
694 | .master_flags = SPI_MASTER_MUST_TX, | |
50a7e23f GU |
695 | }; |
696 | ||
697 | static const struct of_device_id sh_msiof_match[] = { | |
698 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, | |
699 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, | |
beb74bb0 GU |
700 | { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, |
701 | { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, | |
50a7e23f GU |
702 | {}, |
703 | }; | |
704 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
705 | ||
cf9c86ef BH |
706 | #ifdef CONFIG_OF |
707 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
708 | { | |
709 | struct sh_msiof_spi_info *info; | |
710 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 711 | u32 num_cs = 1; |
cf9c86ef BH |
712 | |
713 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
714 | if (!info) { | |
715 | dev_err(dev, "failed to allocate setup data\n"); | |
716 | return NULL; | |
717 | } | |
718 | ||
719 | /* Parse the MSIOF properties */ | |
720 | of_property_read_u32(np, "num-cs", &num_cs); | |
721 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
722 | &info->tx_fifo_override); | |
723 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
724 | &info->rx_fifo_override); | |
725 | ||
726 | info->num_chipselect = num_cs; | |
727 | ||
728 | return info; | |
729 | } | |
730 | #else | |
731 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
732 | { | |
733 | return NULL; | |
734 | } | |
735 | #endif | |
736 | ||
8051effc MD |
737 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
738 | { | |
739 | struct resource *r; | |
740 | struct spi_master *master; | |
50a7e23f | 741 | const struct of_device_id *of_id; |
8051effc | 742 | struct sh_msiof_spi_priv *p; |
8051effc MD |
743 | int i; |
744 | int ret; | |
745 | ||
746 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
747 | if (master == NULL) { | |
748 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 749 | return -ENOMEM; |
8051effc MD |
750 | } |
751 | ||
752 | p = spi_master_get_devdata(master); | |
753 | ||
754 | platform_set_drvdata(pdev, p); | |
50a7e23f GU |
755 | |
756 | of_id = of_match_device(sh_msiof_match, &pdev->dev); | |
757 | if (of_id) { | |
758 | p->chipdata = of_id->data; | |
cf9c86ef | 759 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f GU |
760 | } else { |
761 | p->chipdata = (const void *)pdev->id_entry->driver_data; | |
8074cf06 | 762 | p->info = dev_get_platdata(&pdev->dev); |
50a7e23f | 763 | } |
cf9c86ef BH |
764 | |
765 | if (!p->info) { | |
766 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
767 | ret = -ENXIO; | |
768 | goto err1; | |
769 | } | |
770 | ||
8051effc MD |
771 | init_completion(&p->done); |
772 | ||
b4dd05de | 773 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 774 | if (IS_ERR(p->clk)) { |
078b6ead | 775 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
776 | ret = PTR_ERR(p->clk); |
777 | goto err1; | |
778 | } | |
779 | ||
8051effc | 780 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
781 | if (i < 0) { |
782 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 783 | ret = -ENOENT; |
b4dd05de | 784 | goto err1; |
8051effc | 785 | } |
b4dd05de LP |
786 | |
787 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
788 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
789 | if (IS_ERR(p->mapbase)) { | |
790 | ret = PTR_ERR(p->mapbase); | |
791 | goto err1; | |
8051effc MD |
792 | } |
793 | ||
b4dd05de LP |
794 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
795 | dev_name(&pdev->dev), p); | |
8051effc MD |
796 | if (ret) { |
797 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 798 | goto err1; |
8051effc MD |
799 | } |
800 | ||
5c32d29f LP |
801 | ret = clk_prepare(p->clk); |
802 | if (ret < 0) { | |
803 | dev_err(&pdev->dev, "unable to prepare clock\n"); | |
804 | goto err1; | |
8051effc MD |
805 | } |
806 | ||
807 | p->pdev = pdev; | |
808 | pm_runtime_enable(&pdev->dev); | |
809 | ||
8051effc | 810 | /* Platform data may override FIFO sizes */ |
50a7e23f GU |
811 | p->tx_fifo_size = p->chipdata->tx_fifo_size; |
812 | p->rx_fifo_size = p->chipdata->rx_fifo_size; | |
8051effc MD |
813 | if (p->info->tx_fifo_override) |
814 | p->tx_fifo_size = p->info->tx_fifo_override; | |
815 | if (p->info->rx_fifo_override) | |
816 | p->rx_fifo_size = p->info->rx_fifo_override; | |
817 | ||
818 | /* init master and bitbang code */ | |
819 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
820 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
beb74bb0 | 821 | master->flags = p->chipdata->master_flags; |
8051effc | 822 | master->bus_num = pdev->id; |
f7c05e83 | 823 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 824 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 825 | master->setup = sh_msiof_spi_setup; |
8051effc | 826 | master->cleanup = spi_bitbang_cleanup; |
c833ff73 GU |
827 | master->prepare_message = sh_msiof_prepare_message; |
828 | master->unprepare_message = sh_msiof_unprepare_message; | |
8051effc MD |
829 | |
830 | p->bitbang.master = master; | |
831 | p->bitbang.chipselect = sh_msiof_spi_chipselect; | |
832 | p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer; | |
833 | p->bitbang.txrx_bufs = sh_msiof_spi_txrx; | |
834 | p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word; | |
835 | p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word; | |
836 | p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word; | |
837 | p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word; | |
838 | ||
839 | ret = spi_bitbang_start(&p->bitbang); | |
840 | if (ret == 0) | |
841 | return 0; | |
842 | ||
843 | pm_runtime_disable(&pdev->dev); | |
5c32d29f | 844 | clk_unprepare(p->clk); |
8051effc MD |
845 | err1: |
846 | spi_master_put(master); | |
8051effc MD |
847 | return ret; |
848 | } | |
849 | ||
850 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
851 | { | |
852 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
853 | int ret; | |
854 | ||
855 | ret = spi_bitbang_stop(&p->bitbang); | |
856 | if (!ret) { | |
857 | pm_runtime_disable(&pdev->dev); | |
5c32d29f | 858 | clk_unprepare(p->clk); |
8051effc MD |
859 | spi_master_put(p->bitbang.master); |
860 | } | |
861 | return ret; | |
862 | } | |
863 | ||
50a7e23f GU |
864 | static struct platform_device_id spi_driver_ids[] = { |
865 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, | |
beb74bb0 GU |
866 | { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, |
867 | { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, | |
cf9c86ef BH |
868 | {}, |
869 | }; | |
50a7e23f | 870 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 871 | |
8051effc MD |
872 | static struct platform_driver sh_msiof_spi_drv = { |
873 | .probe = sh_msiof_spi_probe, | |
874 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 875 | .id_table = spi_driver_ids, |
8051effc MD |
876 | .driver = { |
877 | .name = "spi_sh_msiof", | |
878 | .owner = THIS_MODULE, | |
691ee4ed | 879 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
880 | }, |
881 | }; | |
940ab889 | 882 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
883 | |
884 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
885 | MODULE_AUTHOR("Magnus Damm"); | |
886 | MODULE_LICENSE("GPL v2"); | |
887 | MODULE_ALIAS("platform:spi_sh_msiof"); |