]>
Commit | Line | Data |
---|---|---|
b5f65179 MR |
1 | /* |
2 | * Copyright (C) 2012 - 2014 Allwinner Tech | |
3 | * Pan Nan <pannan@allwinnertech.com> | |
4 | * | |
5 | * Copyright (C) 2014 Maxime Ripard | |
6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pm_runtime.h> | |
b5f65179 MR |
22 | |
23 | #include <linux/spi/spi.h> | |
24 | ||
25 | #define SUN4I_FIFO_DEPTH 64 | |
26 | ||
27 | #define SUN4I_RXDATA_REG 0x00 | |
28 | ||
29 | #define SUN4I_TXDATA_REG 0x04 | |
30 | ||
31 | #define SUN4I_CTL_REG 0x08 | |
32 | #define SUN4I_CTL_ENABLE BIT(0) | |
33 | #define SUN4I_CTL_MASTER BIT(1) | |
34 | #define SUN4I_CTL_CPHA BIT(2) | |
35 | #define SUN4I_CTL_CPOL BIT(3) | |
36 | #define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) | |
37 | #define SUN4I_CTL_LMTF BIT(6) | |
38 | #define SUN4I_CTL_TF_RST BIT(8) | |
39 | #define SUN4I_CTL_RF_RST BIT(9) | |
40 | #define SUN4I_CTL_XCH BIT(10) | |
41 | #define SUN4I_CTL_CS_MASK 0x3000 | |
42 | #define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) | |
43 | #define SUN4I_CTL_DHB BIT(15) | |
44 | #define SUN4I_CTL_CS_MANUAL BIT(16) | |
45 | #define SUN4I_CTL_CS_LEVEL BIT(17) | |
46 | #define SUN4I_CTL_TP BIT(18) | |
47 | ||
48 | #define SUN4I_INT_CTL_REG 0x0c | |
49 | #define SUN4I_INT_CTL_TC BIT(16) | |
50 | ||
51 | #define SUN4I_INT_STA_REG 0x10 | |
52 | ||
53 | #define SUN4I_DMA_CTL_REG 0x14 | |
54 | ||
55 | #define SUN4I_WAIT_REG 0x18 | |
56 | ||
57 | #define SUN4I_CLK_CTL_REG 0x1c | |
58 | #define SUN4I_CLK_CTL_CDR2_MASK 0xff | |
59 | #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) | |
60 | #define SUN4I_CLK_CTL_CDR1_MASK 0xf | |
61 | #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) | |
62 | #define SUN4I_CLK_CTL_DRS BIT(12) | |
63 | ||
64 | #define SUN4I_BURST_CNT_REG 0x20 | |
65 | #define SUN4I_BURST_CNT(cnt) ((cnt) & 0xffffff) | |
66 | ||
67 | #define SUN4I_XMIT_CNT_REG 0x24 | |
68 | #define SUN4I_XMIT_CNT(cnt) ((cnt) & 0xffffff) | |
69 | ||
70 | #define SUN4I_FIFO_STA_REG 0x28 | |
71 | #define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f | |
72 | #define SUN4I_FIFO_STA_RF_CNT_BITS 0 | |
73 | #define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f | |
74 | #define SUN4I_FIFO_STA_TF_CNT_BITS 16 | |
75 | ||
76 | struct sun4i_spi { | |
77 | struct spi_master *master; | |
78 | void __iomem *base_addr; | |
79 | struct clk *hclk; | |
80 | struct clk *mclk; | |
81 | ||
82 | struct completion done; | |
83 | ||
84 | const u8 *tx_buf; | |
85 | u8 *rx_buf; | |
86 | int len; | |
87 | }; | |
88 | ||
89 | static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg) | |
90 | { | |
91 | return readl(sspi->base_addr + reg); | |
92 | } | |
93 | ||
94 | static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value) | |
95 | { | |
96 | writel(value, sspi->base_addr + reg); | |
97 | } | |
98 | ||
99 | static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len) | |
100 | { | |
101 | u32 reg, cnt; | |
102 | u8 byte; | |
103 | ||
104 | /* See how much data is available */ | |
105 | reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG); | |
106 | reg &= SUN4I_FIFO_STA_RF_CNT_MASK; | |
107 | cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS; | |
108 | ||
109 | if (len > cnt) | |
110 | len = cnt; | |
111 | ||
112 | while (len--) { | |
113 | byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); | |
114 | if (sspi->rx_buf) | |
115 | *sspi->rx_buf++ = byte; | |
116 | } | |
117 | } | |
118 | ||
119 | static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len) | |
120 | { | |
121 | u8 byte; | |
122 | ||
123 | if (len > sspi->len) | |
124 | len = sspi->len; | |
125 | ||
126 | while (len--) { | |
127 | byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; | |
128 | writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG); | |
129 | sspi->len--; | |
130 | } | |
131 | } | |
132 | ||
133 | static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) | |
134 | { | |
135 | struct sun4i_spi *sspi = spi_master_get_devdata(spi->master); | |
136 | u32 reg; | |
137 | ||
138 | reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); | |
139 | ||
140 | reg &= ~SUN4I_CTL_CS_MASK; | |
141 | reg |= SUN4I_CTL_CS(spi->chip_select); | |
142 | ||
218e0b57 MW |
143 | /* We want to control the chip select manually */ |
144 | reg |= SUN4I_CTL_CS_MANUAL; | |
145 | ||
b5f65179 MR |
146 | if (enable) |
147 | reg |= SUN4I_CTL_CS_LEVEL; | |
148 | else | |
149 | reg &= ~SUN4I_CTL_CS_LEVEL; | |
150 | ||
151 | /* | |
152 | * Even though this looks irrelevant since we are supposed to | |
153 | * be controlling the chip select manually, this bit also | |
154 | * controls the levels of the chip select for inactive | |
155 | * devices. | |
156 | * | |
157 | * If we don't set it, the chip select level will go low by | |
158 | * default when the device is idle, which is not really | |
159 | * expected in the common case where the chip select is active | |
160 | * low. | |
161 | */ | |
162 | if (spi->mode & SPI_CS_HIGH) | |
163 | reg &= ~SUN4I_CTL_CS_ACTIVE_LOW; | |
164 | else | |
165 | reg |= SUN4I_CTL_CS_ACTIVE_LOW; | |
166 | ||
167 | sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); | |
168 | } | |
169 | ||
170 | static int sun4i_spi_transfer_one(struct spi_master *master, | |
171 | struct spi_device *spi, | |
172 | struct spi_transfer *tfr) | |
173 | { | |
174 | struct sun4i_spi *sspi = spi_master_get_devdata(master); | |
175 | unsigned int mclk_rate, div, timeout; | |
176 | unsigned int tx_len = 0; | |
177 | int ret = 0; | |
178 | u32 reg; | |
179 | ||
180 | /* We don't support transfer larger than the FIFO */ | |
181 | if (tfr->len > SUN4I_FIFO_DEPTH) | |
6d9fe44b MS |
182 | return -EMSGSIZE; |
183 | ||
184 | if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH) | |
185 | return -EMSGSIZE; | |
b5f65179 MR |
186 | |
187 | reinit_completion(&sspi->done); | |
188 | sspi->tx_buf = tfr->tx_buf; | |
189 | sspi->rx_buf = tfr->rx_buf; | |
190 | sspi->len = tfr->len; | |
191 | ||
192 | /* Clear pending interrupts */ | |
193 | sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0); | |
194 | ||
195 | ||
196 | reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); | |
197 | ||
198 | /* Reset FIFOs */ | |
199 | sun4i_spi_write(sspi, SUN4I_CTL_REG, | |
200 | reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST); | |
201 | ||
202 | /* | |
203 | * Setup the transfer control register: Chip Select, | |
204 | * polarities, etc. | |
205 | */ | |
206 | if (spi->mode & SPI_CPOL) | |
207 | reg |= SUN4I_CTL_CPOL; | |
208 | else | |
209 | reg &= ~SUN4I_CTL_CPOL; | |
210 | ||
211 | if (spi->mode & SPI_CPHA) | |
212 | reg |= SUN4I_CTL_CPHA; | |
213 | else | |
214 | reg &= ~SUN4I_CTL_CPHA; | |
215 | ||
216 | if (spi->mode & SPI_LSB_FIRST) | |
217 | reg |= SUN4I_CTL_LMTF; | |
218 | else | |
219 | reg &= ~SUN4I_CTL_LMTF; | |
220 | ||
221 | ||
222 | /* | |
223 | * If it's a TX only transfer, we don't want to fill the RX | |
224 | * FIFO with bogus data | |
225 | */ | |
226 | if (sspi->rx_buf) | |
227 | reg &= ~SUN4I_CTL_DHB; | |
228 | else | |
229 | reg |= SUN4I_CTL_DHB; | |
230 | ||
b5f65179 MR |
231 | sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); |
232 | ||
233 | /* Ensure that we have a parent clock fast enough */ | |
234 | mclk_rate = clk_get_rate(sspi->mclk); | |
47284e3e MW |
235 | if (mclk_rate < (2 * tfr->speed_hz)) { |
236 | clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); | |
b5f65179 MR |
237 | mclk_rate = clk_get_rate(sspi->mclk); |
238 | } | |
239 | ||
240 | /* | |
241 | * Setup clock divider. | |
242 | * | |
243 | * We have two choices there. Either we can use the clock | |
244 | * divide rate 1, which is calculated thanks to this formula: | |
245 | * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) | |
246 | * Or we can use CDR2, which is calculated with the formula: | |
247 | * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) | |
248 | * Wether we use the former or the latter is set through the | |
249 | * DRS bit. | |
250 | * | |
251 | * First try CDR2, and if we can't reach the expected | |
252 | * frequency, fall back to CDR1. | |
253 | */ | |
47284e3e | 254 | div = mclk_rate / (2 * tfr->speed_hz); |
b5f65179 MR |
255 | if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { |
256 | if (div > 0) | |
257 | div--; | |
258 | ||
259 | reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; | |
260 | } else { | |
47284e3e | 261 | div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); |
b5f65179 MR |
262 | reg = SUN4I_CLK_CTL_CDR1(div); |
263 | } | |
264 | ||
265 | sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); | |
266 | ||
267 | /* Setup the transfer now... */ | |
268 | if (sspi->tx_buf) | |
269 | tx_len = tfr->len; | |
270 | ||
271 | /* Setup the counters */ | |
272 | sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len)); | |
273 | sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len)); | |
274 | ||
6d9fe44b MS |
275 | /* |
276 | * Fill the TX FIFO | |
277 | * Filling the FIFO fully causes timeout for some reason | |
278 | * at least on spi2 on A10s | |
279 | */ | |
280 | sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1); | |
b5f65179 MR |
281 | |
282 | /* Enable the interrupts */ | |
283 | sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC); | |
284 | ||
285 | /* Start the transfer */ | |
286 | reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); | |
287 | sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH); | |
288 | ||
289 | timeout = wait_for_completion_timeout(&sspi->done, | |
290 | msecs_to_jiffies(1000)); | |
291 | if (!timeout) { | |
292 | ret = -ETIMEDOUT; | |
293 | goto out; | |
294 | } | |
295 | ||
296 | sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH); | |
297 | ||
298 | out: | |
299 | sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0); | |
300 | ||
301 | return ret; | |
302 | } | |
303 | ||
304 | static irqreturn_t sun4i_spi_handler(int irq, void *dev_id) | |
305 | { | |
306 | struct sun4i_spi *sspi = dev_id; | |
307 | u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG); | |
308 | ||
309 | /* Transfer complete */ | |
310 | if (status & SUN4I_INT_CTL_TC) { | |
311 | sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC); | |
312 | complete(&sspi->done); | |
313 | return IRQ_HANDLED; | |
314 | } | |
315 | ||
316 | return IRQ_NONE; | |
317 | } | |
318 | ||
319 | static int sun4i_spi_runtime_resume(struct device *dev) | |
320 | { | |
321 | struct spi_master *master = dev_get_drvdata(dev); | |
322 | struct sun4i_spi *sspi = spi_master_get_devdata(master); | |
323 | int ret; | |
324 | ||
325 | ret = clk_prepare_enable(sspi->hclk); | |
326 | if (ret) { | |
327 | dev_err(dev, "Couldn't enable AHB clock\n"); | |
328 | goto out; | |
329 | } | |
330 | ||
331 | ret = clk_prepare_enable(sspi->mclk); | |
332 | if (ret) { | |
333 | dev_err(dev, "Couldn't enable module clock\n"); | |
334 | goto err; | |
335 | } | |
336 | ||
337 | sun4i_spi_write(sspi, SUN4I_CTL_REG, | |
338 | SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); | |
339 | ||
340 | return 0; | |
341 | ||
342 | err: | |
343 | clk_disable_unprepare(sspi->hclk); | |
344 | out: | |
345 | return ret; | |
346 | } | |
347 | ||
348 | static int sun4i_spi_runtime_suspend(struct device *dev) | |
349 | { | |
350 | struct spi_master *master = dev_get_drvdata(dev); | |
351 | struct sun4i_spi *sspi = spi_master_get_devdata(master); | |
352 | ||
353 | clk_disable_unprepare(sspi->mclk); | |
354 | clk_disable_unprepare(sspi->hclk); | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static int sun4i_spi_probe(struct platform_device *pdev) | |
360 | { | |
361 | struct spi_master *master; | |
362 | struct sun4i_spi *sspi; | |
363 | struct resource *res; | |
364 | int ret = 0, irq; | |
365 | ||
366 | master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi)); | |
367 | if (!master) { | |
368 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
369 | return -ENOMEM; | |
370 | } | |
371 | ||
372 | platform_set_drvdata(pdev, master); | |
373 | sspi = spi_master_get_devdata(master); | |
374 | ||
375 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
376 | sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); | |
377 | if (IS_ERR(sspi->base_addr)) { | |
378 | ret = PTR_ERR(sspi->base_addr); | |
379 | goto err_free_master; | |
380 | } | |
381 | ||
382 | irq = platform_get_irq(pdev, 0); | |
383 | if (irq < 0) { | |
384 | dev_err(&pdev->dev, "No spi IRQ specified\n"); | |
385 | ret = -ENXIO; | |
386 | goto err_free_master; | |
387 | } | |
388 | ||
389 | ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler, | |
390 | 0, "sun4i-spi", sspi); | |
391 | if (ret) { | |
392 | dev_err(&pdev->dev, "Cannot request IRQ\n"); | |
393 | goto err_free_master; | |
394 | } | |
395 | ||
396 | sspi->master = master; | |
397 | master->set_cs = sun4i_spi_set_cs; | |
398 | master->transfer_one = sun4i_spi_transfer_one; | |
399 | master->num_chipselect = 4; | |
400 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; | |
ba47644d | 401 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
b5f65179 MR |
402 | master->dev.of_node = pdev->dev.of_node; |
403 | master->auto_runtime_pm = true; | |
404 | ||
405 | sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); | |
406 | if (IS_ERR(sspi->hclk)) { | |
407 | dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); | |
408 | ret = PTR_ERR(sspi->hclk); | |
409 | goto err_free_master; | |
410 | } | |
411 | ||
412 | sspi->mclk = devm_clk_get(&pdev->dev, "mod"); | |
413 | if (IS_ERR(sspi->mclk)) { | |
414 | dev_err(&pdev->dev, "Unable to acquire module clock\n"); | |
415 | ret = PTR_ERR(sspi->mclk); | |
416 | goto err_free_master; | |
417 | } | |
418 | ||
419 | init_completion(&sspi->done); | |
420 | ||
421 | /* | |
422 | * This wake-up/shutdown pattern is to be able to have the | |
423 | * device woken up, even if runtime_pm is disabled | |
424 | */ | |
425 | ret = sun4i_spi_runtime_resume(&pdev->dev); | |
426 | if (ret) { | |
427 | dev_err(&pdev->dev, "Couldn't resume the device\n"); | |
428 | goto err_free_master; | |
429 | } | |
430 | ||
431 | pm_runtime_set_active(&pdev->dev); | |
432 | pm_runtime_enable(&pdev->dev); | |
433 | pm_runtime_idle(&pdev->dev); | |
434 | ||
435 | ret = devm_spi_register_master(&pdev->dev, master); | |
436 | if (ret) { | |
437 | dev_err(&pdev->dev, "cannot register SPI master\n"); | |
438 | goto err_pm_disable; | |
439 | } | |
440 | ||
441 | return 0; | |
442 | ||
443 | err_pm_disable: | |
444 | pm_runtime_disable(&pdev->dev); | |
445 | sun4i_spi_runtime_suspend(&pdev->dev); | |
446 | err_free_master: | |
447 | spi_master_put(master); | |
448 | return ret; | |
449 | } | |
450 | ||
451 | static int sun4i_spi_remove(struct platform_device *pdev) | |
452 | { | |
453 | pm_runtime_disable(&pdev->dev); | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
458 | static const struct of_device_id sun4i_spi_match[] = { | |
459 | { .compatible = "allwinner,sun4i-a10-spi", }, | |
460 | {} | |
461 | }; | |
462 | MODULE_DEVICE_TABLE(of, sun4i_spi_match); | |
463 | ||
464 | static const struct dev_pm_ops sun4i_spi_pm_ops = { | |
465 | .runtime_resume = sun4i_spi_runtime_resume, | |
466 | .runtime_suspend = sun4i_spi_runtime_suspend, | |
467 | }; | |
468 | ||
469 | static struct platform_driver sun4i_spi_driver = { | |
470 | .probe = sun4i_spi_probe, | |
471 | .remove = sun4i_spi_remove, | |
472 | .driver = { | |
473 | .name = "sun4i-spi", | |
b5f65179 MR |
474 | .of_match_table = sun4i_spi_match, |
475 | .pm = &sun4i_spi_pm_ops, | |
476 | }, | |
477 | }; | |
478 | module_platform_driver(sun4i_spi_driver); | |
479 | ||
480 | MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); | |
481 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
482 | MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver"); | |
483 | MODULE_LICENSE("GPL"); |