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ae918c02 | 1 | /* |
ae918c02 AK |
2 | * Xilinx SPI controller driver (master mode only) |
3 | * | |
4 | * Author: MontaVista Software, Inc. | |
5 | * source@mvista.com | |
6 | * | |
8fd8821b GL |
7 | * Copyright (c) 2010 Secret Lab Technologies, Ltd. |
8 | * Copyright (c) 2009 Intel Corporation | |
9 | * 2002-2007 (c) MontaVista Software, Inc. | |
10 | ||
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
ae918c02 AK |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
ae918c02 | 17 | #include <linux/interrupt.h> |
eae6cb31 | 18 | #include <linux/of.h> |
8fd8821b | 19 | #include <linux/platform_device.h> |
ae918c02 AK |
20 | #include <linux/spi/spi.h> |
21 | #include <linux/spi/spi_bitbang.h> | |
d5af91a1 | 22 | #include <linux/spi/xilinx_spi.h> |
eae6cb31 | 23 | #include <linux/io.h> |
d5af91a1 | 24 | |
fc3ba952 | 25 | #define XILINX_SPI_NAME "xilinx_spi" |
ae918c02 AK |
26 | |
27 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | |
28 | * Product Specification", DS464 | |
29 | */ | |
c9da2e12 | 30 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
ae918c02 | 31 | |
082339bc | 32 | #define XSPI_CR_LOOP 0x01 |
ae918c02 AK |
33 | #define XSPI_CR_ENABLE 0x02 |
34 | #define XSPI_CR_MASTER_MODE 0x04 | |
35 | #define XSPI_CR_CPOL 0x08 | |
36 | #define XSPI_CR_CPHA 0x10 | |
bca690db | 37 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ |
0240f945 | 38 | XSPI_CR_LSB_FIRST | XSPI_CR_LOOP) |
ae918c02 AK |
39 | #define XSPI_CR_TXFIFO_RESET 0x20 |
40 | #define XSPI_CR_RXFIFO_RESET 0x40 | |
41 | #define XSPI_CR_MANUAL_SSELECT 0x80 | |
42 | #define XSPI_CR_TRANS_INHIBIT 0x100 | |
c9da2e12 | 43 | #define XSPI_CR_LSB_FIRST 0x200 |
ae918c02 | 44 | |
c9da2e12 | 45 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
ae918c02 AK |
46 | |
47 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ | |
48 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ | |
49 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ | |
50 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ | |
51 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ | |
52 | ||
c9da2e12 RR |
53 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
54 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ | |
ae918c02 AK |
55 | |
56 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ | |
57 | ||
58 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 | |
59 | * IPIF registers are 32 bit | |
60 | */ | |
61 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ | |
62 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 | |
63 | ||
64 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ | |
65 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ | |
66 | ||
67 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ | |
68 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while | |
69 | * disabled */ | |
70 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ | |
71 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ | |
72 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ | |
73 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ | |
c9da2e12 | 74 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
ae918c02 AK |
75 | |
76 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ | |
77 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ | |
78 | ||
79 | struct xilinx_spi { | |
80 | /* bitbang has to be first */ | |
81 | struct spi_bitbang bitbang; | |
82 | struct completion done; | |
ae918c02 AK |
83 | void __iomem *regs; /* virt. address of the control registers */ |
84 | ||
9ca1273b | 85 | int irq; |
ae918c02 | 86 | |
ae918c02 AK |
87 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
88 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | |
89 | int remaining_bytes; /* the number of bytes left to transfer */ | |
c9da2e12 | 90 | u8 bits_per_word; |
4c9a7614 | 91 | int buffer_size; /* buffer size in words */ |
f9c6ef6c | 92 | u32 cs_inactive; /* Level of the CS pins when inactive*/ |
6ff8672a JH |
93 | unsigned int (*read_fn)(void __iomem *); |
94 | void (*write_fn)(u32, void __iomem *); | |
95 | void (*tx_fn)(struct xilinx_spi *); | |
96 | void (*rx_fn)(struct xilinx_spi *); | |
ae918c02 AK |
97 | }; |
98 | ||
97782149 PM |
99 | static void xspi_write32(u32 val, void __iomem *addr) |
100 | { | |
101 | iowrite32(val, addr); | |
102 | } | |
103 | ||
104 | static unsigned int xspi_read32(void __iomem *addr) | |
105 | { | |
106 | return ioread32(addr); | |
107 | } | |
108 | ||
109 | static void xspi_write32_be(u32 val, void __iomem *addr) | |
110 | { | |
111 | iowrite32be(val, addr); | |
112 | } | |
113 | ||
114 | static unsigned int xspi_read32_be(void __iomem *addr) | |
115 | { | |
116 | return ioread32be(addr); | |
117 | } | |
118 | ||
c9da2e12 RR |
119 | static void xspi_tx8(struct xilinx_spi *xspi) |
120 | { | |
121 | xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); | |
122 | xspi->tx_ptr++; | |
123 | } | |
124 | ||
125 | static void xspi_tx16(struct xilinx_spi *xspi) | |
126 | { | |
127 | xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | |
128 | xspi->tx_ptr += 2; | |
129 | } | |
130 | ||
131 | static void xspi_tx32(struct xilinx_spi *xspi) | |
132 | { | |
133 | xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); | |
134 | xspi->tx_ptr += 4; | |
135 | } | |
136 | ||
137 | static void xspi_rx8(struct xilinx_spi *xspi) | |
138 | { | |
139 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
140 | if (xspi->rx_ptr) { | |
141 | *xspi->rx_ptr = data & 0xff; | |
142 | xspi->rx_ptr++; | |
143 | } | |
144 | } | |
145 | ||
146 | static void xspi_rx16(struct xilinx_spi *xspi) | |
147 | { | |
148 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
149 | if (xspi->rx_ptr) { | |
150 | *(u16 *)(xspi->rx_ptr) = data & 0xffff; | |
151 | xspi->rx_ptr += 2; | |
152 | } | |
153 | } | |
154 | ||
155 | static void xspi_rx32(struct xilinx_spi *xspi) | |
156 | { | |
157 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
158 | if (xspi->rx_ptr) { | |
159 | *(u32 *)(xspi->rx_ptr) = data; | |
160 | xspi->rx_ptr += 4; | |
161 | } | |
162 | } | |
163 | ||
86fc5935 | 164 | static void xspi_init_hw(struct xilinx_spi *xspi) |
ae918c02 | 165 | { |
86fc5935 | 166 | void __iomem *regs_base = xspi->regs; |
d9f58812 | 167 | u32 inhibit; |
86fc5935 | 168 | |
ae918c02 | 169 | /* Reset the SPI device */ |
86fc5935 RR |
170 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
171 | regs_base + XIPIF_V123B_RESETR_OFFSET); | |
899929ba RR |
172 | /* Enable the transmit empty interrupt, which we use to determine |
173 | * progress on the transmission. | |
174 | */ | |
175 | xspi->write_fn(XSPI_INTR_TX_EMPTY, | |
176 | regs_base + XIPIF_V123B_IIER_OFFSET); | |
ae918c02 | 177 | /* Enable the global IPIF interrupt */ |
d9f58812 | 178 | if (xspi->irq >= 0) { |
5fe11cc0 RR |
179 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, |
180 | regs_base + XIPIF_V123B_DGIER_OFFSET); | |
d9f58812 RR |
181 | inhibit = XSPI_CR_TRANS_INHIBIT; |
182 | } else { | |
5fe11cc0 | 183 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); |
d9f58812 RR |
184 | inhibit = 0; |
185 | } | |
ae918c02 | 186 | /* Deselect the slave on the SPI bus */ |
86fc5935 | 187 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
ae918c02 AK |
188 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
189 | * put SPI controller into master mode, and enable it */ | |
d9f58812 | 190 | xspi->write_fn(inhibit | XSPI_CR_MANUAL_SSELECT | |
c9da2e12 RR |
191 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | |
192 | XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); | |
ae918c02 AK |
193 | } |
194 | ||
195 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |
196 | { | |
197 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
f9c6ef6c RR |
198 | u16 cr; |
199 | u32 cs; | |
ae918c02 AK |
200 | |
201 | if (is_on == BITBANG_CS_INACTIVE) { | |
202 | /* Deselect the slave on the SPI bus */ | |
f9c6ef6c RR |
203 | xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); |
204 | return; | |
ae918c02 | 205 | } |
f9c6ef6c RR |
206 | |
207 | /* Set the SPI clock phase and polarity */ | |
208 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; | |
209 | if (spi->mode & SPI_CPHA) | |
210 | cr |= XSPI_CR_CPHA; | |
211 | if (spi->mode & SPI_CPOL) | |
212 | cr |= XSPI_CR_CPOL; | |
213 | if (spi->mode & SPI_LSB_FIRST) | |
214 | cr |= XSPI_CR_LSB_FIRST; | |
215 | if (spi->mode & SPI_LOOP) | |
216 | cr |= XSPI_CR_LOOP; | |
217 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | |
218 | ||
219 | /* We do not check spi->max_speed_hz here as the SPI clock | |
220 | * frequency is not software programmable (the IP block design | |
221 | * parameter) | |
222 | */ | |
223 | ||
224 | cs = xspi->cs_inactive; | |
225 | cs ^= BIT(spi->chip_select); | |
226 | ||
227 | /* Activate the chip select */ | |
228 | xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); | |
ae918c02 AK |
229 | } |
230 | ||
231 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | |
9bf46f6d | 232 | * custom txrx_bufs(). |
ae918c02 AK |
233 | */ |
234 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | |
235 | struct spi_transfer *t) | |
236 | { | |
f9c6ef6c RR |
237 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
238 | ||
239 | if (spi->mode & SPI_CS_HIGH) | |
240 | xspi->cs_inactive &= ~BIT(spi->chip_select); | |
241 | else | |
242 | xspi->cs_inactive |= BIT(spi->chip_select); | |
243 | ||
ae918c02 AK |
244 | return 0; |
245 | } | |
246 | ||
4c9a7614 | 247 | static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi, int n_words) |
ae918c02 | 248 | { |
4c9a7614 | 249 | xspi->remaining_bytes -= n_words * xspi->bits_per_word / 8; |
ae918c02 | 250 | |
4c9a7614 | 251 | while (n_words--) |
86fc5935 | 252 | if (xspi->tx_ptr) |
c9da2e12 | 253 | xspi->tx_fn(xspi); |
86fc5935 RR |
254 | else |
255 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
4c9a7614 | 256 | return; |
ae918c02 AK |
257 | } |
258 | ||
259 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) | |
260 | { | |
261 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
ae918c02 AK |
262 | |
263 | /* We get here with transmitter inhibited */ | |
264 | ||
265 | xspi->tx_ptr = t->tx_buf; | |
266 | xspi->rx_ptr = t->rx_buf; | |
267 | xspi->remaining_bytes = t->len; | |
16735d02 | 268 | reinit_completion(&xspi->done); |
ae918c02 | 269 | |
a87cbca0 | 270 | while (xspi->remaining_bytes) { |
d9f58812 | 271 | u16 cr = 0; |
c5d348df | 272 | int n_words; |
68c315bb | 273 | |
4c9a7614 RR |
274 | n_words = (xspi->remaining_bytes * 8) / xspi->bits_per_word; |
275 | n_words = min(n_words, xspi->buffer_size); | |
276 | ||
277 | xilinx_spi_fill_tx_fifo(xspi, n_words); | |
68c315bb PC |
278 | |
279 | /* Start the transfer by not inhibiting the transmitter any | |
280 | * longer | |
281 | */ | |
68c315bb | 282 | |
d9f58812 RR |
283 | if (xspi->irq >= 0) { |
284 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & | |
285 | ~XSPI_CR_TRANS_INHIBIT; | |
286 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | |
5fe11cc0 | 287 | wait_for_completion(&xspi->done); |
d9f58812 | 288 | } else |
5fe11cc0 RR |
289 | while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) & |
290 | XSPI_SR_TX_EMPTY_MASK)) | |
291 | ; | |
68c315bb PC |
292 | |
293 | /* A transmit has just completed. Process received data and | |
294 | * check for more data to transmit. Always inhibit the | |
295 | * transmitter while the Isr refills the transmit register/FIFO, | |
296 | * or make sure it is stopped if we're done. | |
297 | */ | |
d9f58812 RR |
298 | if (xspi->irq >= 0) |
299 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | |
68c315bb PC |
300 | xspi->regs + XSPI_CR_OFFSET); |
301 | ||
302 | /* Read out all the data from the Rx FIFO */ | |
c5d348df | 303 | while (n_words--) |
68c315bb | 304 | xspi->rx_fn(xspi); |
68c315bb | 305 | } |
ae918c02 | 306 | |
ae918c02 AK |
307 | return t->len - xspi->remaining_bytes; |
308 | } | |
309 | ||
310 | ||
311 | /* This driver supports single master mode only. Hence Tx FIFO Empty | |
312 | * is the only interrupt we care about. | |
313 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode | |
314 | * Fault are not to happen. | |
315 | */ | |
316 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |
317 | { | |
318 | struct xilinx_spi *xspi = dev_id; | |
319 | u32 ipif_isr; | |
320 | ||
321 | /* Get the IPIF interrupts, and clear them immediately */ | |
86fc5935 RR |
322 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
323 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
ae918c02 AK |
324 | |
325 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ | |
68c315bb | 326 | complete(&xspi->done); |
ae918c02 AK |
327 | } |
328 | ||
329 | return IRQ_HANDLED; | |
330 | } | |
331 | ||
4c9a7614 RR |
332 | static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) |
333 | { | |
334 | u8 sr; | |
335 | int n_words = 0; | |
336 | ||
337 | /* | |
338 | * Before the buffer_size detection we reset the core | |
339 | * to make sure we start with a clean state. | |
340 | */ | |
341 | xspi->write_fn(XIPIF_V123B_RESET_MASK, | |
342 | xspi->regs + XIPIF_V123B_RESETR_OFFSET); | |
343 | ||
344 | /* Fill the Tx FIFO with as many words as possible */ | |
345 | do { | |
346 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
347 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
348 | n_words++; | |
349 | } while (!(sr & XSPI_SR_TX_FULL_MASK)); | |
350 | ||
351 | return n_words; | |
352 | } | |
353 | ||
eae6cb31 GL |
354 | static const struct of_device_id xilinx_spi_of_match[] = { |
355 | { .compatible = "xlnx,xps-spi-2.00.a", }, | |
356 | { .compatible = "xlnx,xps-spi-2.00.b", }, | |
357 | {} | |
358 | }; | |
359 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); | |
eae6cb31 | 360 | |
7cb2abd0 | 361 | static int xilinx_spi_probe(struct platform_device *pdev) |
ae918c02 | 362 | { |
ae918c02 | 363 | struct xilinx_spi *xspi; |
d81c0bbb | 364 | struct xspi_platform_data *pdata; |
ad3fdbca | 365 | struct resource *res; |
7b3b7432 | 366 | int ret, num_cs = 0, bits_per_word = 8; |
d81c0bbb | 367 | struct spi_master *master; |
082339bc | 368 | u32 tmp; |
d81c0bbb MB |
369 | u8 i; |
370 | ||
8074cf06 | 371 | pdata = dev_get_platdata(&pdev->dev); |
d81c0bbb MB |
372 | if (pdata) { |
373 | num_cs = pdata->num_chipselect; | |
374 | bits_per_word = pdata->bits_per_word; | |
be3acdff MS |
375 | } else { |
376 | of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits", | |
377 | &num_cs); | |
d81c0bbb | 378 | } |
ae918c02 | 379 | |
d81c0bbb | 380 | if (!num_cs) { |
7cb2abd0 MB |
381 | dev_err(&pdev->dev, |
382 | "Missing slave select configuration data\n"); | |
d81c0bbb MB |
383 | return -EINVAL; |
384 | } | |
385 | ||
7cb2abd0 | 386 | master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); |
d5af91a1 | 387 | if (!master) |
d81c0bbb | 388 | return -ENODEV; |
ae918c02 | 389 | |
e7db06b5 | 390 | /* the spi->mode bits understood by this driver: */ |
f9c6ef6c RR |
391 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | |
392 | SPI_CS_HIGH; | |
e7db06b5 | 393 | |
ae918c02 | 394 | xspi = spi_master_get_devdata(master); |
f9c6ef6c | 395 | xspi->cs_inactive = 0xffffffff; |
94c69f76 | 396 | xspi->bitbang.master = master; |
ae918c02 AK |
397 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
398 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; | |
399 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; | |
ae918c02 AK |
400 | init_completion(&xspi->done); |
401 | ||
ad3fdbca MS |
402 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
403 | xspi->regs = devm_ioremap_resource(&pdev->dev, res); | |
c40537d0 MB |
404 | if (IS_ERR(xspi->regs)) { |
405 | ret = PTR_ERR(xspi->regs); | |
ae918c02 | 406 | goto put_master; |
ae918c02 AK |
407 | } |
408 | ||
4b153a21 | 409 | master->bus_num = pdev->id; |
91565c40 | 410 | master->num_chipselect = num_cs; |
7cb2abd0 | 411 | master->dev.of_node = pdev->dev.of_node; |
082339bc MS |
412 | |
413 | /* | |
414 | * Detect endianess on the IP via loop bit in CR. Detection | |
415 | * must be done before reset is sent because incorrect reset | |
416 | * value generates error interrupt. | |
417 | * Setup little endian helper functions first and try to use them | |
418 | * and check if bit was correctly setup or not. | |
419 | */ | |
420 | xspi->read_fn = xspi_read32; | |
421 | xspi->write_fn = xspi_write32; | |
422 | ||
423 | xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); | |
424 | tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
425 | tmp &= XSPI_CR_LOOP; | |
426 | if (tmp != XSPI_CR_LOOP) { | |
97782149 PM |
427 | xspi->read_fn = xspi_read32_be; |
428 | xspi->write_fn = xspi_write32_be; | |
86fc5935 | 429 | } |
082339bc | 430 | |
9bf46f6d | 431 | master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); |
91565c40 | 432 | xspi->bits_per_word = bits_per_word; |
c9da2e12 RR |
433 | if (xspi->bits_per_word == 8) { |
434 | xspi->tx_fn = xspi_tx8; | |
435 | xspi->rx_fn = xspi_rx8; | |
436 | } else if (xspi->bits_per_word == 16) { | |
437 | xspi->tx_fn = xspi_tx16; | |
438 | xspi->rx_fn = xspi_rx16; | |
439 | } else if (xspi->bits_per_word == 32) { | |
440 | xspi->tx_fn = xspi_tx32; | |
441 | xspi->rx_fn = xspi_rx32; | |
d81c0bbb MB |
442 | } else { |
443 | ret = -EINVAL; | |
c40537d0 | 444 | goto put_master; |
d81c0bbb | 445 | } |
ae918c02 | 446 | |
4c9a7614 RR |
447 | xspi->buffer_size = xilinx_spi_find_buffer_size(xspi); |
448 | ||
7b3b7432 | 449 | xspi->irq = platform_get_irq(pdev, 0); |
5fe11cc0 RR |
450 | if (xspi->irq >= 0) { |
451 | /* Register for SPI Interrupt */ | |
452 | ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, | |
453 | dev_name(&pdev->dev), xspi); | |
454 | if (ret) | |
455 | goto put_master; | |
7b3b7432 MS |
456 | } |
457 | ||
5fe11cc0 RR |
458 | /* SPI controller initializations */ |
459 | xspi_init_hw(xspi); | |
ae918c02 | 460 | |
d5af91a1 RR |
461 | ret = spi_bitbang_start(&xspi->bitbang); |
462 | if (ret) { | |
7cb2abd0 | 463 | dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); |
7b3b7432 | 464 | goto put_master; |
eae6cb31 GL |
465 | } |
466 | ||
7cb2abd0 | 467 | dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", |
ad3fdbca | 468 | (unsigned long long)res->start, xspi->regs, xspi->irq); |
8fd8821b | 469 | |
eae6cb31 GL |
470 | if (pdata) { |
471 | for (i = 0; i < pdata->num_devices; i++) | |
472 | spi_new_device(master, pdata->devices + i); | |
473 | } | |
8fd8821b | 474 | |
7cb2abd0 | 475 | platform_set_drvdata(pdev, master); |
8fd8821b | 476 | return 0; |
ae918c02 | 477 | |
ae918c02 AK |
478 | put_master: |
479 | spi_master_put(master); | |
d81c0bbb MB |
480 | |
481 | return ret; | |
8fd8821b GL |
482 | } |
483 | ||
7cb2abd0 | 484 | static int xilinx_spi_remove(struct platform_device *pdev) |
8fd8821b | 485 | { |
7cb2abd0 | 486 | struct spi_master *master = platform_get_drvdata(pdev); |
d81c0bbb | 487 | struct xilinx_spi *xspi = spi_master_get_devdata(master); |
7b3b7432 | 488 | void __iomem *regs_base = xspi->regs; |
ae918c02 AK |
489 | |
490 | spi_bitbang_stop(&xspi->bitbang); | |
7b3b7432 MS |
491 | |
492 | /* Disable all the interrupts just in case */ | |
493 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); | |
494 | /* Disable the global IPIF interrupt */ | |
495 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ff82c587 | 496 | |
d5af91a1 | 497 | spi_master_put(xspi->bitbang.master); |
8fd8821b GL |
498 | |
499 | return 0; | |
500 | } | |
501 | ||
502 | /* work with hotplug and coldplug */ | |
503 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); | |
504 | ||
505 | static struct platform_driver xilinx_spi_driver = { | |
506 | .probe = xilinx_spi_probe, | |
fd4a319b | 507 | .remove = xilinx_spi_remove, |
8fd8821b GL |
508 | .driver = { |
509 | .name = XILINX_SPI_NAME, | |
eae6cb31 | 510 | .of_match_table = xilinx_spi_of_match, |
8fd8821b GL |
511 | }, |
512 | }; | |
940ab889 | 513 | module_platform_driver(xilinx_spi_driver); |
8fd8821b | 514 | |
ae918c02 AK |
515 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
516 | MODULE_DESCRIPTION("Xilinx SPI driver"); | |
517 | MODULE_LICENSE("GPL"); |