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Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
131b17d4 | 16 | #include <linux/io.h> |
a5f6abd4 | 17 | #include <linux/ioport.h> |
131b17d4 | 18 | #include <linux/irq.h> |
a5f6abd4 WB |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/workqueue.h> | |
a5f6abd4 | 25 | |
a5f6abd4 | 26 | #include <asm/dma.h> |
131b17d4 | 27 | #include <asm/portmux.h> |
a5f6abd4 | 28 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
29 | #include <asm/cacheflush.h> |
30 | ||
a32c691d BW |
31 | #define DRV_NAME "bfin-spi" |
32 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 33 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
34 | #define DRV_VERSION "1.0" |
35 | ||
36 | MODULE_AUTHOR(DRV_AUTHOR); | |
37 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
38 | MODULE_LICENSE("GPL"); |
39 | ||
bb90eb00 BW |
40 | #define START_STATE ((void *)0) |
41 | #define RUNNING_STATE ((void *)1) | |
42 | #define DONE_STATE ((void *)2) | |
43 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 44 | |
b9f139a7 | 45 | struct master_data; |
9c4542c7 MF |
46 | |
47 | struct transfer_ops { | |
b9f139a7 MF |
48 | void (*write) (struct master_data *); |
49 | void (*read) (struct master_data *); | |
50 | void (*duplex) (struct master_data *); | |
9c4542c7 MF |
51 | }; |
52 | ||
b9f139a7 | 53 | struct master_data { |
a5f6abd4 WB |
54 | /* Driver model hookup */ |
55 | struct platform_device *pdev; | |
56 | ||
57 | /* SPI framework hookup */ | |
58 | struct spi_master *master; | |
59 | ||
bb90eb00 | 60 | /* Regs base of SPI controller */ |
f452126c | 61 | void __iomem *regs_base; |
bb90eb00 | 62 | |
003d9226 BW |
63 | /* Pin request list */ |
64 | u16 *pin_req; | |
65 | ||
a5f6abd4 WB |
66 | /* BFIN hookup */ |
67 | struct bfin5xx_spi_master *master_info; | |
68 | ||
69 | /* Driver message queue */ | |
70 | struct workqueue_struct *workqueue; | |
71 | struct work_struct pump_messages; | |
72 | spinlock_t lock; | |
73 | struct list_head queue; | |
74 | int busy; | |
f4f50c3f | 75 | bool running; |
a5f6abd4 WB |
76 | |
77 | /* Message Transfer pump */ | |
78 | struct tasklet_struct pump_transfers; | |
79 | ||
80 | /* Current message transfer state info */ | |
81 | struct spi_message *cur_msg; | |
82 | struct spi_transfer *cur_transfer; | |
b9f139a7 | 83 | struct slave_data *cur_chip; |
a5f6abd4 WB |
84 | size_t len_in_bytes; |
85 | size_t len; | |
86 | void *tx; | |
87 | void *tx_end; | |
88 | void *rx; | |
89 | void *rx_end; | |
bb90eb00 BW |
90 | |
91 | /* DMA stuffs */ | |
92 | int dma_channel; | |
a5f6abd4 | 93 | int dma_mapped; |
bb90eb00 | 94 | int dma_requested; |
a5f6abd4 WB |
95 | dma_addr_t rx_dma; |
96 | dma_addr_t tx_dma; | |
bb90eb00 | 97 | |
f6a6d966 YL |
98 | int irq_requested; |
99 | int spi_irq; | |
100 | ||
a5f6abd4 WB |
101 | size_t rx_map_len; |
102 | size_t tx_map_len; | |
103 | u8 n_bytes; | |
b052fd0a BS |
104 | u16 ctrl_reg; |
105 | u16 flag_reg; | |
106 | ||
fad91c89 | 107 | int cs_change; |
9c4542c7 | 108 | const struct transfer_ops *ops; |
a5f6abd4 WB |
109 | }; |
110 | ||
b9f139a7 | 111 | struct slave_data { |
a5f6abd4 WB |
112 | u16 ctl_reg; |
113 | u16 baud; | |
114 | u16 flag; | |
115 | ||
116 | u8 chip_select_num; | |
117 | u8 n_bytes; | |
88b40369 | 118 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
119 | u8 enable_dma; |
120 | u8 bits_per_word; /* 8 or 16 */ | |
62310e51 | 121 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 122 | u32 cs_gpio; |
93b61bdd | 123 | u16 idle_tx_val; |
f6a6d966 | 124 | u8 pio_interrupt; /* use spi data irq */ |
9c4542c7 | 125 | const struct transfer_ops *ops; |
a5f6abd4 WB |
126 | }; |
127 | ||
bb90eb00 | 128 | #define DEFINE_SPI_REG(reg, off) \ |
b9f139a7 | 129 | static inline u16 read_##reg(struct master_data *drv_data) \ |
bb90eb00 | 130 | { return bfin_read16(drv_data->regs_base + off); } \ |
b9f139a7 | 131 | static inline void write_##reg(struct master_data *drv_data, u16 v) \ |
bb90eb00 BW |
132 | { bfin_write16(drv_data->regs_base + off, v); } |
133 | ||
134 | DEFINE_SPI_REG(CTRL, 0x00) | |
135 | DEFINE_SPI_REG(FLAG, 0x04) | |
136 | DEFINE_SPI_REG(STAT, 0x08) | |
137 | DEFINE_SPI_REG(TDBR, 0x0C) | |
138 | DEFINE_SPI_REG(RDBR, 0x10) | |
139 | DEFINE_SPI_REG(BAUD, 0x14) | |
140 | DEFINE_SPI_REG(SHAW, 0x18) | |
141 | ||
b9f139a7 | 142 | static void bfin_spi_enable(struct master_data *drv_data) |
a5f6abd4 WB |
143 | { |
144 | u16 cr; | |
145 | ||
bb90eb00 BW |
146 | cr = read_CTRL(drv_data); |
147 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
148 | } |
149 | ||
b9f139a7 | 150 | static void bfin_spi_disable(struct master_data *drv_data) |
a5f6abd4 WB |
151 | { |
152 | u16 cr; | |
153 | ||
bb90eb00 BW |
154 | cr = read_CTRL(drv_data); |
155 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
156 | } |
157 | ||
158 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
159 | static u16 hz_to_spi_baud(u32 speed_hz) | |
160 | { | |
161 | u_long sclk = get_sclk(); | |
162 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
163 | ||
164 | if ((sclk % (2 * speed_hz)) > 0) | |
165 | spi_baud++; | |
166 | ||
7513e006 MH |
167 | if (spi_baud < MIN_SPI_BAUD_VAL) |
168 | spi_baud = MIN_SPI_BAUD_VAL; | |
169 | ||
a5f6abd4 WB |
170 | return spi_baud; |
171 | } | |
172 | ||
b9f139a7 | 173 | static int bfin_spi_flush(struct master_data *drv_data) |
a5f6abd4 WB |
174 | { |
175 | unsigned long limit = loops_per_jiffy << 1; | |
176 | ||
177 | /* wait for stop and clear stat */ | |
b4bd2aba | 178 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 179 | cpu_relax(); |
a5f6abd4 | 180 | |
bb90eb00 | 181 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
182 | |
183 | return limit; | |
184 | } | |
185 | ||
fad91c89 | 186 | /* Chip select operation functions for cs_change flag */ |
b9f139a7 | 187 | static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 188 | { |
d3cc71f7 | 189 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 190 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 191 | |
8221610e | 192 | flag &= ~chip->flag; |
fad91c89 | 193 | |
42c78b2b MH |
194 | write_FLAG(drv_data, flag); |
195 | } else { | |
196 | gpio_set_value(chip->cs_gpio, 0); | |
197 | } | |
fad91c89 BW |
198 | } |
199 | ||
b9f139a7 | 200 | static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 201 | { |
d3cc71f7 | 202 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 203 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 204 | |
8221610e | 205 | flag |= chip->flag; |
fad91c89 | 206 | |
42c78b2b MH |
207 | write_FLAG(drv_data, flag); |
208 | } else { | |
209 | gpio_set_value(chip->cs_gpio, 1); | |
210 | } | |
62310e51 BW |
211 | |
212 | /* Move delay here for consistency */ | |
213 | if (chip->cs_chg_udelay) | |
214 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
215 | } |
216 | ||
8221610e | 217 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
b9f139a7 | 218 | static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip) |
8221610e | 219 | { |
d3cc71f7 BS |
220 | if (chip->chip_select_num < MAX_CTRL_CS) { |
221 | u16 flag = read_FLAG(drv_data); | |
8221610e | 222 | |
d3cc71f7 | 223 | flag |= (chip->flag >> 8); |
8221610e | 224 | |
d3cc71f7 BS |
225 | write_FLAG(drv_data, flag); |
226 | } | |
8221610e BS |
227 | } |
228 | ||
b9f139a7 | 229 | static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip) |
8221610e | 230 | { |
d3cc71f7 BS |
231 | if (chip->chip_select_num < MAX_CTRL_CS) { |
232 | u16 flag = read_FLAG(drv_data); | |
8221610e | 233 | |
d3cc71f7 | 234 | flag &= ~(chip->flag >> 8); |
8221610e | 235 | |
d3cc71f7 BS |
236 | write_FLAG(drv_data, flag); |
237 | } | |
8221610e BS |
238 | } |
239 | ||
a5f6abd4 | 240 | /* stop controller and re-config current chip*/ |
b9f139a7 | 241 | static void bfin_spi_restore_state(struct master_data *drv_data) |
a5f6abd4 | 242 | { |
b9f139a7 | 243 | struct slave_data *chip = drv_data->cur_chip; |
12e17c42 | 244 | |
a5f6abd4 | 245 | /* Clear status and disable clock */ |
bb90eb00 | 246 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 247 | bfin_spi_disable(drv_data); |
88b40369 | 248 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 249 | |
9677b0de BS |
250 | SSYNC(); |
251 | ||
5fec5b5a | 252 | /* Load the registers */ |
bb90eb00 | 253 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 254 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
255 | |
256 | bfin_spi_enable(drv_data); | |
138f97cd | 257 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
258 | } |
259 | ||
93b61bdd | 260 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
b9f139a7 | 261 | static inline void bfin_spi_dummy_read(struct master_data *drv_data) |
a5f6abd4 | 262 | { |
93b61bdd | 263 | (void) read_RDBR(drv_data); |
a5f6abd4 WB |
264 | } |
265 | ||
b9f139a7 | 266 | static void bfin_spi_u8_writer(struct master_data *drv_data) |
a5f6abd4 | 267 | { |
93b61bdd WM |
268 | /* clear RXS (we check for RXS inside the loop) */ |
269 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 270 | |
a5f6abd4 | 271 | while (drv_data->tx < drv_data->tx_end) { |
93b61bdd WM |
272 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
273 | /* wait until transfer finished. | |
274 | checking SPIF or TXS may not guarantee transfer completion */ | |
275 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
d8c05008 | 276 | cpu_relax(); |
93b61bdd WM |
277 | /* discard RX data and clear RXS */ |
278 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 279 | } |
a5f6abd4 WB |
280 | } |
281 | ||
b9f139a7 | 282 | static void bfin_spi_u8_reader(struct master_data *drv_data) |
a5f6abd4 | 283 | { |
93b61bdd | 284 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 285 | |
93b61bdd | 286 | /* discard old RX data and clear RXS */ |
138f97cd | 287 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 288 | |
93b61bdd WM |
289 | while (drv_data->rx < drv_data->rx_end) { |
290 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 291 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 292 | cpu_relax(); |
93b61bdd | 293 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 | 294 | } |
a5f6abd4 WB |
295 | } |
296 | ||
b9f139a7 | 297 | static void bfin_spi_u8_duplex(struct master_data *drv_data) |
a5f6abd4 | 298 | { |
93b61bdd WM |
299 | /* discard old RX data and clear RXS */ |
300 | bfin_spi_dummy_read(drv_data); | |
301 | ||
a5f6abd4 | 302 | while (drv_data->rx < drv_data->rx_end) { |
93b61bdd | 303 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 304 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 305 | cpu_relax(); |
93b61bdd | 306 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 WB |
307 | } |
308 | } | |
309 | ||
9c4542c7 MF |
310 | static const struct transfer_ops bfin_transfer_ops_u8 = { |
311 | .write = bfin_spi_u8_writer, | |
312 | .read = bfin_spi_u8_reader, | |
313 | .duplex = bfin_spi_u8_duplex, | |
314 | }; | |
315 | ||
b9f139a7 | 316 | static void bfin_spi_u16_writer(struct master_data *drv_data) |
a5f6abd4 | 317 | { |
93b61bdd WM |
318 | /* clear RXS (we check for RXS inside the loop) */ |
319 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 320 | |
a5f6abd4 | 321 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 322 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 323 | drv_data->tx += 2; |
93b61bdd WM |
324 | /* wait until transfer finished. |
325 | checking SPIF or TXS may not guarantee transfer completion */ | |
326 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
327 | cpu_relax(); | |
328 | /* discard RX data and clear RXS */ | |
329 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 330 | } |
a5f6abd4 WB |
331 | } |
332 | ||
b9f139a7 | 333 | static void bfin_spi_u16_reader(struct master_data *drv_data) |
a5f6abd4 | 334 | { |
93b61bdd | 335 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 336 | |
93b61bdd | 337 | /* discard old RX data and clear RXS */ |
138f97cd | 338 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 339 | |
93b61bdd WM |
340 | while (drv_data->rx < drv_data->rx_end) { |
341 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 342 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 343 | cpu_relax(); |
bb90eb00 | 344 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
345 | drv_data->rx += 2; |
346 | } | |
a5f6abd4 WB |
347 | } |
348 | ||
b9f139a7 | 349 | static void bfin_spi_u16_duplex(struct master_data *drv_data) |
a5f6abd4 | 350 | { |
93b61bdd WM |
351 | /* discard old RX data and clear RXS */ |
352 | bfin_spi_dummy_read(drv_data); | |
353 | ||
354 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 355 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 356 | drv_data->tx += 2; |
bb90eb00 | 357 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 358 | cpu_relax(); |
bb90eb00 | 359 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 360 | drv_data->rx += 2; |
a5f6abd4 WB |
361 | } |
362 | } | |
363 | ||
9c4542c7 MF |
364 | static const struct transfer_ops bfin_transfer_ops_u16 = { |
365 | .write = bfin_spi_u16_writer, | |
366 | .read = bfin_spi_u16_reader, | |
367 | .duplex = bfin_spi_u16_duplex, | |
368 | }; | |
369 | ||
a5f6abd4 | 370 | /* test if ther is more transfer to be done */ |
b9f139a7 | 371 | static void *bfin_spi_next_transfer(struct master_data *drv_data) |
a5f6abd4 WB |
372 | { |
373 | struct spi_message *msg = drv_data->cur_msg; | |
374 | struct spi_transfer *trans = drv_data->cur_transfer; | |
375 | ||
376 | /* Move to next transfer */ | |
377 | if (trans->transfer_list.next != &msg->transfers) { | |
378 | drv_data->cur_transfer = | |
379 | list_entry(trans->transfer_list.next, | |
380 | struct spi_transfer, transfer_list); | |
381 | return RUNNING_STATE; | |
382 | } else | |
383 | return DONE_STATE; | |
384 | } | |
385 | ||
386 | /* | |
387 | * caller already set message->status; | |
388 | * dma and pio irqs are blocked give finished message back | |
389 | */ | |
b9f139a7 | 390 | static void bfin_spi_giveback(struct master_data *drv_data) |
a5f6abd4 | 391 | { |
b9f139a7 | 392 | struct slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
393 | struct spi_transfer *last_transfer; |
394 | unsigned long flags; | |
395 | struct spi_message *msg; | |
396 | ||
397 | spin_lock_irqsave(&drv_data->lock, flags); | |
398 | msg = drv_data->cur_msg; | |
399 | drv_data->cur_msg = NULL; | |
400 | drv_data->cur_transfer = NULL; | |
401 | drv_data->cur_chip = NULL; | |
402 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
403 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
404 | ||
405 | last_transfer = list_entry(msg->transfers.prev, | |
406 | struct spi_transfer, transfer_list); | |
407 | ||
408 | msg->state = NULL; | |
409 | ||
fad91c89 | 410 | if (!drv_data->cs_change) |
138f97cd | 411 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 412 | |
b9b2a76a YL |
413 | /* Not stop spi in autobuffer mode */ |
414 | if (drv_data->tx_dma != 0xFFFF) | |
415 | bfin_spi_disable(drv_data); | |
416 | ||
a5f6abd4 WB |
417 | if (msg->complete) |
418 | msg->complete(msg->context); | |
419 | } | |
420 | ||
f6a6d966 YL |
421 | /* spi data irq handler */ |
422 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
423 | { | |
b9f139a7 MF |
424 | struct master_data *drv_data = dev_id; |
425 | struct slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
426 | struct spi_message *msg = drv_data->cur_msg; |
427 | int n_bytes = drv_data->n_bytes; | |
428 | ||
429 | /* wait until transfer finished. */ | |
430 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
431 | cpu_relax(); | |
432 | ||
433 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
434 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
435 | /* last read */ | |
436 | if (drv_data->rx) { | |
437 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
438 | if (n_bytes == 2) | |
439 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
440 | else if (n_bytes == 1) | |
441 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
442 | drv_data->rx += n_bytes; | |
443 | } | |
444 | ||
445 | msg->actual_length += drv_data->len_in_bytes; | |
446 | if (drv_data->cs_change) | |
447 | bfin_spi_cs_deactive(drv_data, chip); | |
448 | /* Move to next transfer */ | |
449 | msg->state = bfin_spi_next_transfer(drv_data); | |
450 | ||
451 | disable_irq(drv_data->spi_irq); | |
452 | ||
453 | /* Schedule transfer tasklet */ | |
454 | tasklet_schedule(&drv_data->pump_transfers); | |
455 | return IRQ_HANDLED; | |
456 | } | |
457 | ||
458 | if (drv_data->rx && drv_data->tx) { | |
459 | /* duplex */ | |
460 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
461 | if (drv_data->n_bytes == 2) { | |
462 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
463 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
464 | } else if (drv_data->n_bytes == 1) { | |
465 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
466 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
467 | } | |
468 | } else if (drv_data->rx) { | |
469 | /* read */ | |
470 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
471 | if (drv_data->n_bytes == 2) | |
472 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
473 | else if (drv_data->n_bytes == 1) | |
474 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
475 | write_TDBR(drv_data, chip->idle_tx_val); | |
476 | } else if (drv_data->tx) { | |
477 | /* write */ | |
478 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
479 | bfin_spi_dummy_read(drv_data); | |
480 | if (drv_data->n_bytes == 2) | |
481 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
482 | else if (drv_data->n_bytes == 1) | |
483 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
484 | } | |
485 | ||
486 | if (drv_data->tx) | |
487 | drv_data->tx += n_bytes; | |
488 | if (drv_data->rx) | |
489 | drv_data->rx += n_bytes; | |
490 | ||
491 | return IRQ_HANDLED; | |
492 | } | |
493 | ||
138f97cd | 494 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 495 | { |
b9f139a7 MF |
496 | struct master_data *drv_data = dev_id; |
497 | struct slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 498 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 499 | unsigned long timeout; |
d24bd1d0 | 500 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 501 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 502 | |
d24bd1d0 MF |
503 | dev_dbg(&drv_data->pdev->dev, |
504 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
505 | dmastat, spistat); | |
506 | ||
bb90eb00 | 507 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
508 | |
509 | /* | |
d6fe89b0 BW |
510 | * wait for the last transaction shifted out. HRM states: |
511 | * at this point there may still be data in the SPI DMA FIFO waiting | |
512 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
513 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
514 | */ |
515 | if (drv_data->tx != NULL) { | |
90008a64 MF |
516 | while ((read_STAT(drv_data) & BIT_STAT_TXS) || |
517 | (read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 518 | cpu_relax(); |
a5f6abd4 WB |
519 | } |
520 | ||
aaaf939c MF |
521 | dev_dbg(&drv_data->pdev->dev, |
522 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
523 | dmastat, read_STAT(drv_data)); | |
524 | ||
525 | timeout = jiffies + HZ; | |
90008a64 | 526 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
aaaf939c MF |
527 | if (!time_before(jiffies, timeout)) { |
528 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
529 | break; | |
530 | } else | |
531 | cpu_relax(); | |
a5f6abd4 | 532 | |
90008a64 | 533 | if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) { |
04b95d2f MF |
534 | msg->state = ERROR_STATE; |
535 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
536 | } else { | |
537 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 538 | |
04b95d2f | 539 | if (drv_data->cs_change) |
138f97cd | 540 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 541 | |
04b95d2f | 542 | /* Move to next transfer */ |
138f97cd | 543 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 544 | } |
a5f6abd4 WB |
545 | |
546 | /* Schedule transfer tasklet */ | |
547 | tasklet_schedule(&drv_data->pump_transfers); | |
548 | ||
549 | /* free the irq handler before next transfer */ | |
88b40369 BW |
550 | dev_dbg(&drv_data->pdev->dev, |
551 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
552 | drv_data->dma_channel); |
553 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
554 | |
555 | return IRQ_HANDLED; | |
556 | } | |
557 | ||
138f97cd | 558 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 559 | { |
b9f139a7 | 560 | struct master_data *drv_data = (struct master_data *)data; |
a5f6abd4 WB |
561 | struct spi_message *message = NULL; |
562 | struct spi_transfer *transfer = NULL; | |
563 | struct spi_transfer *previous = NULL; | |
b9f139a7 | 564 | struct slave_data *chip = NULL; |
88b40369 BW |
565 | u8 width; |
566 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 567 | u32 tranf_success = 1; |
8eeb12e5 | 568 | u8 full_duplex = 0; |
a5f6abd4 WB |
569 | |
570 | /* Get current state information */ | |
571 | message = drv_data->cur_msg; | |
572 | transfer = drv_data->cur_transfer; | |
573 | chip = drv_data->cur_chip; | |
092e1fda | 574 | |
a5f6abd4 WB |
575 | /* |
576 | * if msg is error or done, report it back using complete() callback | |
577 | */ | |
578 | ||
579 | /* Handle for abort */ | |
580 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 581 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 582 | message->status = -EIO; |
138f97cd | 583 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
584 | return; |
585 | } | |
586 | ||
587 | /* Handle end of message */ | |
588 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 589 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 590 | message->status = 0; |
138f97cd | 591 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
592 | return; |
593 | } | |
594 | ||
595 | /* Delay if requested at end of transfer */ | |
596 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 597 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
598 | previous = list_entry(transfer->transfer_list.prev, |
599 | struct spi_transfer, transfer_list); | |
600 | if (previous->delay_usecs) | |
601 | udelay(previous->delay_usecs); | |
602 | } | |
603 | ||
ab09e040 | 604 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 605 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
606 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
607 | message->status = -EIO; | |
138f97cd | 608 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
609 | return; |
610 | } | |
611 | ||
93b61bdd WM |
612 | if (transfer->len == 0) { |
613 | /* Move to next transfer of this msg */ | |
614 | message->state = bfin_spi_next_transfer(drv_data); | |
615 | /* Schedule next transfer tasklet */ | |
616 | tasklet_schedule(&drv_data->pump_transfers); | |
617 | } | |
618 | ||
a5f6abd4 WB |
619 | if (transfer->tx_buf != NULL) { |
620 | drv_data->tx = (void *)transfer->tx_buf; | |
621 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
622 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
623 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
624 | } else { |
625 | drv_data->tx = NULL; | |
626 | } | |
627 | ||
628 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 629 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
630 | drv_data->rx = transfer->rx_buf; |
631 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
632 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
633 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
634 | } else { |
635 | drv_data->rx = NULL; | |
636 | } | |
637 | ||
638 | drv_data->rx_dma = transfer->rx_dma; | |
639 | drv_data->tx_dma = transfer->tx_dma; | |
640 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 641 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 642 | |
092e1fda BW |
643 | /* Bits per word setup */ |
644 | switch (transfer->bits_per_word) { | |
645 | case 8: | |
646 | drv_data->n_bytes = 1; | |
647 | width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 648 | drv_data->ops = &bfin_transfer_ops_u8; |
092e1fda BW |
649 | break; |
650 | ||
651 | case 16: | |
652 | drv_data->n_bytes = 2; | |
653 | width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 654 | drv_data->ops = &bfin_transfer_ops_u16; |
092e1fda BW |
655 | break; |
656 | ||
657 | default: | |
658 | /* No change, the same as default setting */ | |
f6a6d966 | 659 | transfer->bits_per_word = chip->bits_per_word; |
092e1fda BW |
660 | drv_data->n_bytes = chip->n_bytes; |
661 | width = chip->width; | |
9c4542c7 | 662 | drv_data->ops = chip->ops; |
092e1fda BW |
663 | break; |
664 | } | |
665 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
666 | cr |= (width << 8); | |
667 | write_CTRL(drv_data, cr); | |
668 | ||
a5f6abd4 WB |
669 | if (width == CFG_SPI_WORDSIZE16) { |
670 | drv_data->len = (transfer->len) >> 1; | |
671 | } else { | |
672 | drv_data->len = transfer->len; | |
673 | } | |
4fb98efa | 674 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 MF |
675 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
676 | drv_data->ops, chip->ops, &bfin_transfer_ops_u8); | |
a5f6abd4 | 677 | |
a5f6abd4 WB |
678 | message->state = RUNNING_STATE; |
679 | dma_config = 0; | |
680 | ||
092e1fda BW |
681 | /* Speed setup (surely valid because already checked) */ |
682 | if (transfer->speed_hz) | |
683 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
684 | else | |
685 | write_BAUD(drv_data, chip->baud); | |
686 | ||
bb90eb00 BW |
687 | write_STAT(drv_data, BIT_STAT_CLR); |
688 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
b9b2a76a | 689 | if (drv_data->cs_change) |
138f97cd | 690 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 691 | |
88b40369 BW |
692 | dev_dbg(&drv_data->pdev->dev, |
693 | "now pumping a transfer: width is %d, len is %d\n", | |
694 | width, transfer->len); | |
a5f6abd4 WB |
695 | |
696 | /* | |
8cf5858c VM |
697 | * Try to map dma buffer and do a dma transfer. If successful use, |
698 | * different way to r/w according to the enable_dma settings and if | |
699 | * we are not doing a full duplex transfer (since the hardware does | |
700 | * not support full duplex DMA transfers). | |
a5f6abd4 | 701 | */ |
8eeb12e5 VM |
702 | if (!full_duplex && drv_data->cur_chip->enable_dma |
703 | && drv_data->len > 6) { | |
a5f6abd4 | 704 | |
11d6f599 | 705 | unsigned long dma_start_addr, flags; |
7aec3566 | 706 | |
bb90eb00 BW |
707 | disable_dma(drv_data->dma_channel); |
708 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
709 | |
710 | /* config dma channel */ | |
88b40369 | 711 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 712 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 | 713 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 | 714 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
715 | dma_width = WDSIZE_16; |
716 | } else { | |
bb90eb00 | 717 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
718 | dma_width = WDSIZE_8; |
719 | } | |
720 | ||
3f479a65 | 721 | /* poll for SPI completion before start */ |
bb90eb00 | 722 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 723 | cpu_relax(); |
3f479a65 | 724 | |
a5f6abd4 WB |
725 | /* dirty hack for autobuffer DMA mode */ |
726 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
727 | dev_dbg(&drv_data->pdev->dev, |
728 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
729 | |
730 | /* no irq in autobuffer mode */ | |
731 | dma_config = | |
732 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
733 | set_dma_config(drv_data->dma_channel, dma_config); |
734 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 735 | (unsigned long)drv_data->tx); |
bb90eb00 | 736 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 737 | |
07612e5f | 738 | /* start SPI transfer */ |
11d6f599 | 739 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
740 | |
741 | /* just return here, there can only be one transfer | |
742 | * in this mode | |
743 | */ | |
a5f6abd4 | 744 | message->status = 0; |
138f97cd | 745 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
746 | return; |
747 | } | |
748 | ||
749 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 750 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
751 | if (drv_data->rx != NULL) { |
752 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
753 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
754 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 755 | |
8cf5858c | 756 | /* invalidate caches, if needed */ |
67834fa9 | 757 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
758 | invalidate_dcache_range((unsigned long) drv_data->rx, |
759 | (unsigned long) (drv_data->rx + | |
ace32865 | 760 | drv_data->len_in_bytes)); |
8cf5858c | 761 | |
7aec3566 MF |
762 | dma_config |= WNR; |
763 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 764 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 765 | |
a5f6abd4 | 766 | } else if (drv_data->tx != NULL) { |
88b40369 | 767 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 768 | |
8cf5858c | 769 | /* flush caches, if needed */ |
67834fa9 | 770 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
771 | flush_dcache_range((unsigned long) drv_data->tx, |
772 | (unsigned long) (drv_data->tx + | |
ace32865 | 773 | drv_data->len_in_bytes)); |
8cf5858c | 774 | |
7aec3566 | 775 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 776 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
777 | |
778 | } else | |
779 | BUG(); | |
780 | ||
11d6f599 MF |
781 | /* oh man, here there be monsters ... and i dont mean the |
782 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
783 | * your data, kick your dog, and love it all. do *not* try | |
784 | * and change these lines unless you (1) heavily test DMA | |
785 | * with SPI flashes on a loaded system (e.g. ping floods), | |
786 | * (2) know just how broken the DMA engine interaction with | |
787 | * the SPI peripheral is, and (3) have someone else to blame | |
788 | * when you screw it all up anyways. | |
789 | */ | |
7aec3566 | 790 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
791 | set_dma_config(drv_data->dma_channel, dma_config); |
792 | local_irq_save(flags); | |
a963ea83 | 793 | SSYNC(); |
11d6f599 | 794 | write_CTRL(drv_data, cr); |
a963ea83 | 795 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
796 | dma_enable_irq(drv_data->dma_channel); |
797 | local_irq_restore(flags); | |
07612e5f | 798 | |
f6a6d966 YL |
799 | return; |
800 | } | |
a5f6abd4 | 801 | |
f6a6d966 YL |
802 | if (chip->pio_interrupt) { |
803 | /* use write mode. spi irq should have been disabled */ | |
804 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
93b61bdd WM |
805 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
806 | ||
f6a6d966 YL |
807 | /* discard old RX data and clear RXS */ |
808 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 809 | |
f6a6d966 YL |
810 | /* start transfer */ |
811 | if (drv_data->tx == NULL) | |
812 | write_TDBR(drv_data, chip->idle_tx_val); | |
813 | else { | |
814 | if (transfer->bits_per_word == 8) | |
815 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
816 | else if (transfer->bits_per_word == 16) | |
817 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
818 | drv_data->tx += drv_data->n_bytes; | |
819 | } | |
a5f6abd4 | 820 | |
f6a6d966 YL |
821 | /* once TDBR is empty, interrupt is triggered */ |
822 | enable_irq(drv_data->spi_irq); | |
823 | return; | |
824 | } | |
a5f6abd4 | 825 | |
f6a6d966 YL |
826 | /* IO mode */ |
827 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
828 | ||
829 | /* we always use SPI_WRITE mode. SPI_READ mode | |
830 | seems to have problems with setting up the | |
831 | output value in TDBR prior to the transfer. */ | |
832 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); | |
833 | ||
834 | if (full_duplex) { | |
835 | /* full duplex mode */ | |
836 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
837 | (drv_data->rx_end - drv_data->rx)); | |
838 | dev_dbg(&drv_data->pdev->dev, | |
839 | "IO duplex: cr is 0x%x\n", cr); | |
840 | ||
9c4542c7 | 841 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
842 | |
843 | if (drv_data->tx != drv_data->tx_end) | |
844 | tranf_success = 0; | |
845 | } else if (drv_data->tx != NULL) { | |
846 | /* write only half duplex */ | |
847 | dev_dbg(&drv_data->pdev->dev, | |
848 | "IO write: cr is 0x%x\n", cr); | |
849 | ||
9c4542c7 | 850 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
851 | |
852 | if (drv_data->tx != drv_data->tx_end) | |
853 | tranf_success = 0; | |
854 | } else if (drv_data->rx != NULL) { | |
855 | /* read only half duplex */ | |
856 | dev_dbg(&drv_data->pdev->dev, | |
857 | "IO read: cr is 0x%x\n", cr); | |
858 | ||
9c4542c7 | 859 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
860 | if (drv_data->rx != drv_data->rx_end) |
861 | tranf_success = 0; | |
862 | } | |
a5f6abd4 | 863 | |
f6a6d966 YL |
864 | if (!tranf_success) { |
865 | dev_dbg(&drv_data->pdev->dev, | |
866 | "IO write error!\n"); | |
867 | message->state = ERROR_STATE; | |
868 | } else { | |
869 | /* Update total byte transfered */ | |
870 | message->actual_length += drv_data->len_in_bytes; | |
871 | /* Move to next transfer of this msg */ | |
872 | message->state = bfin_spi_next_transfer(drv_data); | |
873 | if (drv_data->cs_change) | |
874 | bfin_spi_cs_deactive(drv_data, chip); | |
a5f6abd4 | 875 | } |
f6a6d966 YL |
876 | |
877 | /* Schedule next transfer tasklet */ | |
878 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
879 | } |
880 | ||
881 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 882 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 883 | { |
b9f139a7 | 884 | struct master_data *drv_data; |
a5f6abd4 WB |
885 | unsigned long flags; |
886 | ||
b9f139a7 | 887 | drv_data = container_of(work, struct master_data, pump_messages); |
131b17d4 | 888 | |
a5f6abd4 WB |
889 | /* Lock queue and check for queue work */ |
890 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 891 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
892 | /* pumper kicked off but no work to do */ |
893 | drv_data->busy = 0; | |
894 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
895 | return; | |
896 | } | |
897 | ||
898 | /* Make sure we are not already running a message */ | |
899 | if (drv_data->cur_msg) { | |
900 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
901 | return; | |
902 | } | |
903 | ||
904 | /* Extract head of queue */ | |
905 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
906 | struct spi_message, queue); | |
5fec5b5a BW |
907 | |
908 | /* Setup the SSP using the per chip configuration */ | |
909 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 910 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 911 | |
a5f6abd4 WB |
912 | list_del_init(&drv_data->cur_msg->queue); |
913 | ||
914 | /* Initial message state */ | |
915 | drv_data->cur_msg->state = START_STATE; | |
916 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
917 | struct spi_transfer, transfer_list); | |
918 | ||
5fec5b5a BW |
919 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
920 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
921 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
922 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
923 | |
924 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
925 | "the first transfer len is %d\n", |
926 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
927 | |
928 | /* Mark as busy and launch transfers */ | |
929 | tasklet_schedule(&drv_data->pump_transfers); | |
930 | ||
931 | drv_data->busy = 1; | |
932 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
933 | } | |
934 | ||
935 | /* | |
936 | * got a msg to transfer, queue it in drv_data->queue. | |
937 | * And kick off message pumper | |
938 | */ | |
138f97cd | 939 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 940 | { |
b9f139a7 | 941 | struct master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
942 | unsigned long flags; |
943 | ||
944 | spin_lock_irqsave(&drv_data->lock, flags); | |
945 | ||
f4f50c3f | 946 | if (!drv_data->running) { |
a5f6abd4 WB |
947 | spin_unlock_irqrestore(&drv_data->lock, flags); |
948 | return -ESHUTDOWN; | |
949 | } | |
950 | ||
951 | msg->actual_length = 0; | |
952 | msg->status = -EINPROGRESS; | |
953 | msg->state = START_STATE; | |
954 | ||
88b40369 | 955 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
956 | list_add_tail(&msg->queue, &drv_data->queue); |
957 | ||
f4f50c3f | 958 | if (drv_data->running && !drv_data->busy) |
a5f6abd4 WB |
959 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
960 | ||
961 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
12e17c42 SZ |
966 | #define MAX_SPI_SSEL 7 |
967 | ||
4160bde2 | 968 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
969 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
970 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
971 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
972 | ||
973 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
974 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
975 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
976 | ||
977 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
978 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
979 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
980 | }; | |
981 | ||
ab09e040 | 982 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 983 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 984 | { |
ac01e97d | 985 | struct bfin5xx_spi_chip *chip_info; |
b9f139a7 MF |
986 | struct slave_data *chip = NULL; |
987 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
ac01e97d | 988 | int ret = -EINVAL; |
a5f6abd4 | 989 | |
a5f6abd4 | 990 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) |
ac01e97d | 991 | goto error; |
a5f6abd4 WB |
992 | |
993 | /* Only alloc (or use chip_info) on first setup */ | |
ac01e97d | 994 | chip_info = NULL; |
a5f6abd4 WB |
995 | chip = spi_get_ctldata(spi); |
996 | if (chip == NULL) { | |
ac01e97d DM |
997 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
998 | if (!chip) { | |
999 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
1000 | ret = -ENOMEM; | |
1001 | goto error; | |
1002 | } | |
a5f6abd4 WB |
1003 | |
1004 | chip->enable_dma = 0; | |
1005 | chip_info = spi->controller_data; | |
1006 | } | |
1007 | ||
1008 | /* chip_info isn't always needed */ | |
1009 | if (chip_info) { | |
2ed35516 MF |
1010 | /* Make sure people stop trying to set fields via ctl_reg |
1011 | * when they should actually be using common SPI framework. | |
90008a64 | 1012 | * Currently we let through: WOM EMISO PSSE GM SZ. |
2ed35516 MF |
1013 | * Not sure if a user actually needs/uses any of these, |
1014 | * but let's assume (for now) they do. | |
1015 | */ | |
90008a64 MF |
1016 | if (chip_info->ctl_reg & ~(BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | \ |
1017 | BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ)) { | |
2ed35516 MF |
1018 | dev_err(&spi->dev, "do not set bits in ctl_reg " |
1019 | "that the SPI framework manages\n"); | |
ac01e97d | 1020 | goto error; |
2ed35516 MF |
1021 | } |
1022 | ||
a5f6abd4 WB |
1023 | chip->enable_dma = chip_info->enable_dma != 0 |
1024 | && drv_data->master_info->enable_dma; | |
1025 | chip->ctl_reg = chip_info->ctl_reg; | |
1026 | chip->bits_per_word = chip_info->bits_per_word; | |
a5f6abd4 | 1027 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
93b61bdd | 1028 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1029 | chip->pio_interrupt = chip_info->pio_interrupt; |
a5f6abd4 WB |
1030 | } |
1031 | ||
1032 | /* translate common spi framework into our register */ | |
1033 | if (spi->mode & SPI_CPOL) | |
90008a64 | 1034 | chip->ctl_reg |= BIT_CTL_CPOL; |
a5f6abd4 | 1035 | if (spi->mode & SPI_CPHA) |
90008a64 | 1036 | chip->ctl_reg |= BIT_CTL_CPHA; |
a5f6abd4 | 1037 | if (spi->mode & SPI_LSB_FIRST) |
90008a64 | 1038 | chip->ctl_reg |= BIT_CTL_LSBF; |
a5f6abd4 | 1039 | /* we dont support running in slave mode (yet?) */ |
90008a64 | 1040 | chip->ctl_reg |= BIT_CTL_MASTER; |
a5f6abd4 | 1041 | |
a5f6abd4 WB |
1042 | /* |
1043 | * Notice: for blackfin, the speed_hz is the value of register | |
1044 | * SPI_BAUD, not the real baudrate | |
1045 | */ | |
1046 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
a5f6abd4 | 1047 | chip->chip_select_num = spi->chip_select; |
d3cc71f7 BS |
1048 | if (chip->chip_select_num < MAX_CTRL_CS) |
1049 | chip->flag = (1 << spi->chip_select) << 8; | |
1050 | else | |
1051 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; | |
a5f6abd4 WB |
1052 | |
1053 | switch (chip->bits_per_word) { | |
1054 | case 8: | |
1055 | chip->n_bytes = 1; | |
1056 | chip->width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 1057 | chip->ops = &bfin_transfer_ops_u8; |
a5f6abd4 WB |
1058 | break; |
1059 | ||
1060 | case 16: | |
1061 | chip->n_bytes = 2; | |
1062 | chip->width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 1063 | chip->ops = &bfin_transfer_ops_u16; |
a5f6abd4 WB |
1064 | break; |
1065 | ||
1066 | default: | |
1067 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1068 | chip->bits_per_word); | |
ac01e97d DM |
1069 | goto error; |
1070 | } | |
1071 | ||
f6a6d966 YL |
1072 | if (chip->enable_dma && chip->pio_interrupt) { |
1073 | dev_err(&spi->dev, "enable_dma is set, " | |
1074 | "do not set pio_interrupt\n"); | |
1075 | goto error; | |
1076 | } | |
ac01e97d DM |
1077 | /* |
1078 | * if any one SPI chip is registered and wants DMA, request the | |
1079 | * DMA channel for it | |
1080 | */ | |
1081 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1082 | /* register dma irq handler */ | |
1083 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1084 | if (ret) { | |
1085 | dev_err(&spi->dev, | |
1086 | "Unable to request BlackFin SPI DMA channel\n"); | |
1087 | goto error; | |
1088 | } | |
1089 | drv_data->dma_requested = 1; | |
1090 | ||
1091 | ret = set_dma_callback(drv_data->dma_channel, | |
1092 | bfin_spi_dma_irq_handler, drv_data); | |
1093 | if (ret) { | |
1094 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1095 | goto error; | |
1096 | } | |
1097 | dma_disable_irq(drv_data->dma_channel); | |
1098 | } | |
1099 | ||
f6a6d966 YL |
1100 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1101 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
1102 | IRQF_DISABLED, "BFIN_SPI", drv_data); | |
1103 | if (ret) { | |
1104 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1105 | goto error; | |
1106 | } | |
1107 | drv_data->irq_requested = 1; | |
1108 | /* we use write mode, spi irq has to be disabled here */ | |
1109 | disable_irq(drv_data->spi_irq); | |
1110 | } | |
1111 | ||
d3cc71f7 | 1112 | if (chip->chip_select_num >= MAX_CTRL_CS) { |
ac01e97d DM |
1113 | ret = gpio_request(chip->cs_gpio, spi->modalias); |
1114 | if (ret) { | |
1115 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1116 | goto pin_error; | |
1117 | } | |
1118 | gpio_direction_output(chip->cs_gpio, 1); | |
a5f6abd4 WB |
1119 | } |
1120 | ||
898eb71c | 1121 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1122 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1123 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1124 | chip->ctl_reg, chip->flag); |
1125 | ||
1126 | spi_set_ctldata(spi, chip); | |
1127 | ||
12e17c42 | 1128 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
d3cc71f7 | 1129 | if (chip->chip_select_num < MAX_CTRL_CS) { |
ac01e97d DM |
1130 | ret = peripheral_request(ssel[spi->master->bus_num] |
1131 | [chip->chip_select_num-1], spi->modalias); | |
1132 | if (ret) { | |
1133 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1134 | goto pin_error; | |
1135 | } | |
1136 | } | |
12e17c42 | 1137 | |
8221610e | 1138 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1139 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1140 | |
a5f6abd4 | 1141 | return 0; |
ac01e97d DM |
1142 | |
1143 | pin_error: | |
d3cc71f7 | 1144 | if (chip->chip_select_num >= MAX_CTRL_CS) |
ac01e97d DM |
1145 | gpio_free(chip->cs_gpio); |
1146 | else | |
1147 | peripheral_free(ssel[spi->master->bus_num] | |
1148 | [chip->chip_select_num - 1]); | |
1149 | error: | |
1150 | if (chip) { | |
1151 | if (drv_data->dma_requested) | |
1152 | free_dma(drv_data->dma_channel); | |
1153 | drv_data->dma_requested = 0; | |
1154 | ||
1155 | kfree(chip); | |
1156 | /* prevent free 'chip' twice */ | |
1157 | spi_set_ctldata(spi, NULL); | |
1158 | } | |
1159 | ||
1160 | return ret; | |
a5f6abd4 WB |
1161 | } |
1162 | ||
1163 | /* | |
1164 | * callback for spi framework. | |
1165 | * clean driver specific data | |
1166 | */ | |
138f97cd | 1167 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1168 | { |
b9f139a7 MF |
1169 | struct slave_data *chip = spi_get_ctldata(spi); |
1170 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1171 | |
e7d02e3c MF |
1172 | if (!chip) |
1173 | return; | |
1174 | ||
d3cc71f7 | 1175 | if (chip->chip_select_num < MAX_CTRL_CS) { |
12e17c42 SZ |
1176 | peripheral_free(ssel[spi->master->bus_num] |
1177 | [chip->chip_select_num-1]); | |
8221610e | 1178 | bfin_spi_cs_disable(drv_data, chip); |
d3cc71f7 | 1179 | } else |
42c78b2b MH |
1180 | gpio_free(chip->cs_gpio); |
1181 | ||
a5f6abd4 | 1182 | kfree(chip); |
ac01e97d DM |
1183 | /* prevent free 'chip' twice */ |
1184 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1185 | } |
1186 | ||
b9f139a7 | 1187 | static inline int bfin_spi_init_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1188 | { |
1189 | INIT_LIST_HEAD(&drv_data->queue); | |
1190 | spin_lock_init(&drv_data->lock); | |
1191 | ||
f4f50c3f | 1192 | drv_data->running = false; |
a5f6abd4 WB |
1193 | drv_data->busy = 0; |
1194 | ||
1195 | /* init transfer tasklet */ | |
1196 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1197 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1198 | |
1199 | /* init messages workqueue */ | |
138f97cd | 1200 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1201 | drv_data->workqueue = create_singlethread_workqueue( |
1202 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1203 | if (drv_data->workqueue == NULL) |
1204 | return -EBUSY; | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
b9f139a7 | 1209 | static inline int bfin_spi_start_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1210 | { |
1211 | unsigned long flags; | |
1212 | ||
1213 | spin_lock_irqsave(&drv_data->lock, flags); | |
1214 | ||
f4f50c3f | 1215 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1216 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1217 | return -EBUSY; | |
1218 | } | |
1219 | ||
f4f50c3f | 1220 | drv_data->running = true; |
a5f6abd4 WB |
1221 | drv_data->cur_msg = NULL; |
1222 | drv_data->cur_transfer = NULL; | |
1223 | drv_data->cur_chip = NULL; | |
1224 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1225 | ||
1226 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
b9f139a7 | 1231 | static inline int bfin_spi_stop_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1232 | { |
1233 | unsigned long flags; | |
1234 | unsigned limit = 500; | |
1235 | int status = 0; | |
1236 | ||
1237 | spin_lock_irqsave(&drv_data->lock, flags); | |
1238 | ||
1239 | /* | |
1240 | * This is a bit lame, but is optimized for the common execution path. | |
1241 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1242 | * execution path (pump_messages) would be required to call wake_up or | |
1243 | * friends on every SPI message. Do this instead | |
1244 | */ | |
f4f50c3f | 1245 | drv_data->running = false; |
a5f6abd4 WB |
1246 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { |
1247 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1248 | msleep(10); | |
1249 | spin_lock_irqsave(&drv_data->lock, flags); | |
1250 | } | |
1251 | ||
1252 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1253 | status = -EBUSY; | |
1254 | ||
1255 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1256 | ||
1257 | return status; | |
1258 | } | |
1259 | ||
b9f139a7 | 1260 | static inline int bfin_spi_destroy_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1261 | { |
1262 | int status; | |
1263 | ||
138f97cd | 1264 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1265 | if (status != 0) |
1266 | return status; | |
1267 | ||
1268 | destroy_workqueue(drv_data->workqueue); | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
138f97cd | 1273 | static int __init bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1274 | { |
1275 | struct device *dev = &pdev->dev; | |
1276 | struct bfin5xx_spi_master *platform_info; | |
1277 | struct spi_master *master; | |
2a045131 | 1278 | struct master_data *drv_data; |
a32c691d | 1279 | struct resource *res; |
a5f6abd4 WB |
1280 | int status = 0; |
1281 | ||
1282 | platform_info = dev->platform_data; | |
1283 | ||
1284 | /* Allocate master with space for drv_data */ | |
2a045131 | 1285 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1286 | if (!master) { |
1287 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1288 | return -ENOMEM; | |
1289 | } | |
131b17d4 | 1290 | |
a5f6abd4 WB |
1291 | drv_data = spi_master_get_devdata(master); |
1292 | drv_data->master = master; | |
1293 | drv_data->master_info = platform_info; | |
1294 | drv_data->pdev = pdev; | |
003d9226 | 1295 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1296 | |
e7db06b5 DB |
1297 | /* the spi->mode bits supported by this driver: */ |
1298 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
1299 | ||
a5f6abd4 WB |
1300 | master->bus_num = pdev->id; |
1301 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1302 | master->cleanup = bfin_spi_cleanup; |
1303 | master->setup = bfin_spi_setup; | |
1304 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1305 | |
a32c691d BW |
1306 | /* Find and map our resources */ |
1307 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1308 | if (res == NULL) { | |
1309 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1310 | status = -ENOENT; | |
1311 | goto out_error_get_res; | |
1312 | } | |
1313 | ||
74947b89 | 1314 | drv_data->regs_base = ioremap(res->start, resource_size(res)); |
f452126c | 1315 | if (drv_data->regs_base == NULL) { |
a32c691d BW |
1316 | dev_err(dev, "Cannot map IO\n"); |
1317 | status = -ENXIO; | |
1318 | goto out_error_ioremap; | |
1319 | } | |
1320 | ||
f6a6d966 YL |
1321 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1322 | if (res == NULL) { | |
a32c691d BW |
1323 | dev_err(dev, "No DMA channel specified\n"); |
1324 | status = -ENOENT; | |
f6a6d966 YL |
1325 | goto out_error_free_io; |
1326 | } | |
1327 | drv_data->dma_channel = res->start; | |
1328 | ||
1329 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1330 | if (drv_data->spi_irq < 0) { | |
1331 | dev_err(dev, "No spi pio irq specified\n"); | |
1332 | status = -ENOENT; | |
1333 | goto out_error_free_io; | |
a32c691d BW |
1334 | } |
1335 | ||
a5f6abd4 | 1336 | /* Initial and start queue */ |
138f97cd | 1337 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1338 | if (status != 0) { |
a32c691d | 1339 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1340 | goto out_error_queue_alloc; |
1341 | } | |
a32c691d | 1342 | |
138f97cd | 1343 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1344 | if (status != 0) { |
a32c691d | 1345 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1346 | goto out_error_queue_alloc; |
1347 | } | |
1348 | ||
f9e522ca VM |
1349 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1350 | if (status != 0) { | |
1351 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1352 | goto out_error_queue_alloc; | |
1353 | } | |
1354 | ||
bb8beecd WM |
1355 | /* Reset SPI registers. If these registers were used by the boot loader, |
1356 | * the sky may fall on your head if you enable the dma controller. | |
1357 | */ | |
1358 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1359 | write_FLAG(drv_data, 0xFF00); | |
1360 | ||
a5f6abd4 WB |
1361 | /* Register with the SPI framework */ |
1362 | platform_set_drvdata(pdev, drv_data); | |
1363 | status = spi_register_master(master); | |
1364 | if (status != 0) { | |
a32c691d | 1365 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1366 | goto out_error_queue_alloc; |
1367 | } | |
a32c691d | 1368 | |
f452126c | 1369 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1370 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1371 | drv_data->dma_channel); | |
a5f6abd4 WB |
1372 | return status; |
1373 | ||
cc2f81a6 | 1374 | out_error_queue_alloc: |
138f97cd | 1375 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1376 | out_error_free_io: |
bb90eb00 | 1377 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1378 | out_error_ioremap: |
1379 | out_error_get_res: | |
a5f6abd4 | 1380 | spi_master_put(master); |
cc2f81a6 | 1381 | |
a5f6abd4 WB |
1382 | return status; |
1383 | } | |
1384 | ||
1385 | /* stop hardware and remove the driver */ | |
138f97cd | 1386 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1387 | { |
b9f139a7 | 1388 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1389 | int status = 0; |
1390 | ||
1391 | if (!drv_data) | |
1392 | return 0; | |
1393 | ||
1394 | /* Remove the queue */ | |
138f97cd | 1395 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1396 | if (status != 0) |
1397 | return status; | |
1398 | ||
1399 | /* Disable the SSP at the peripheral and SOC level */ | |
1400 | bfin_spi_disable(drv_data); | |
1401 | ||
1402 | /* Release DMA */ | |
1403 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1404 | if (dma_channel_active(drv_data->dma_channel)) |
1405 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1406 | } |
1407 | ||
f6a6d966 YL |
1408 | if (drv_data->irq_requested) { |
1409 | free_irq(drv_data->spi_irq, drv_data); | |
1410 | drv_data->irq_requested = 0; | |
1411 | } | |
1412 | ||
a5f6abd4 WB |
1413 | /* Disconnect from the SPI framework */ |
1414 | spi_unregister_master(drv_data->master); | |
1415 | ||
003d9226 | 1416 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1417 | |
a5f6abd4 WB |
1418 | /* Prevent double remove */ |
1419 | platform_set_drvdata(pdev, NULL); | |
1420 | ||
1421 | return 0; | |
1422 | } | |
1423 | ||
1424 | #ifdef CONFIG_PM | |
138f97cd | 1425 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 | 1426 | { |
b9f139a7 | 1427 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1428 | int status = 0; |
1429 | ||
138f97cd | 1430 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1431 | if (status != 0) |
1432 | return status; | |
1433 | ||
b052fd0a BS |
1434 | drv_data->ctrl_reg = read_CTRL(drv_data); |
1435 | drv_data->flag_reg = read_FLAG(drv_data); | |
1436 | ||
1437 | /* | |
1438 | * reset SPI_CTL and SPI_FLG registers | |
1439 | */ | |
1440 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1441 | write_FLAG(drv_data, 0xFF00); | |
a5f6abd4 WB |
1442 | |
1443 | return 0; | |
1444 | } | |
1445 | ||
138f97cd | 1446 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 | 1447 | { |
b9f139a7 | 1448 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1449 | int status = 0; |
1450 | ||
b052fd0a BS |
1451 | write_CTRL(drv_data, drv_data->ctrl_reg); |
1452 | write_FLAG(drv_data, drv_data->flag_reg); | |
a5f6abd4 WB |
1453 | |
1454 | /* Start the queue running */ | |
138f97cd | 1455 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1456 | if (status != 0) { |
1457 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1458 | return status; | |
1459 | } | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | #else | |
138f97cd MF |
1464 | #define bfin_spi_suspend NULL |
1465 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1466 | #endif /* CONFIG_PM */ |
1467 | ||
7e38c3c4 | 1468 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1469 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1470 | .driver = { |
a32c691d | 1471 | .name = DRV_NAME, |
88b40369 BW |
1472 | .owner = THIS_MODULE, |
1473 | }, | |
138f97cd MF |
1474 | .suspend = bfin_spi_suspend, |
1475 | .resume = bfin_spi_resume, | |
1476 | .remove = __devexit_p(bfin_spi_remove), | |
a5f6abd4 WB |
1477 | }; |
1478 | ||
138f97cd | 1479 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1480 | { |
138f97cd | 1481 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1482 | } |
138f97cd | 1483 | module_init(bfin_spi_init); |
a5f6abd4 | 1484 | |
138f97cd | 1485 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1486 | { |
138f97cd | 1487 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1488 | } |
138f97cd | 1489 | module_exit(bfin_spi_exit); |