]>
Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
131b17d4 | 16 | #include <linux/io.h> |
a5f6abd4 | 17 | #include <linux/ioport.h> |
131b17d4 | 18 | #include <linux/irq.h> |
a5f6abd4 WB |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/workqueue.h> | |
a5f6abd4 | 25 | |
a5f6abd4 | 26 | #include <asm/dma.h> |
131b17d4 | 27 | #include <asm/portmux.h> |
a5f6abd4 | 28 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
29 | #include <asm/cacheflush.h> |
30 | ||
a32c691d BW |
31 | #define DRV_NAME "bfin-spi" |
32 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 33 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
34 | #define DRV_VERSION "1.0" |
35 | ||
36 | MODULE_AUTHOR(DRV_AUTHOR); | |
37 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
38 | MODULE_LICENSE("GPL"); |
39 | ||
bb90eb00 BW |
40 | #define START_STATE ((void *)0) |
41 | #define RUNNING_STATE ((void *)1) | |
42 | #define DONE_STATE ((void *)2) | |
43 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 44 | |
b9f139a7 | 45 | struct master_data; |
9c4542c7 MF |
46 | |
47 | struct transfer_ops { | |
b9f139a7 MF |
48 | void (*write) (struct master_data *); |
49 | void (*read) (struct master_data *); | |
50 | void (*duplex) (struct master_data *); | |
9c4542c7 MF |
51 | }; |
52 | ||
b9f139a7 | 53 | struct master_data { |
a5f6abd4 WB |
54 | /* Driver model hookup */ |
55 | struct platform_device *pdev; | |
56 | ||
57 | /* SPI framework hookup */ | |
58 | struct spi_master *master; | |
59 | ||
bb90eb00 | 60 | /* Regs base of SPI controller */ |
f452126c | 61 | void __iomem *regs_base; |
bb90eb00 | 62 | |
003d9226 BW |
63 | /* Pin request list */ |
64 | u16 *pin_req; | |
65 | ||
a5f6abd4 WB |
66 | /* BFIN hookup */ |
67 | struct bfin5xx_spi_master *master_info; | |
68 | ||
69 | /* Driver message queue */ | |
70 | struct workqueue_struct *workqueue; | |
71 | struct work_struct pump_messages; | |
72 | spinlock_t lock; | |
73 | struct list_head queue; | |
74 | int busy; | |
f4f50c3f | 75 | bool running; |
a5f6abd4 WB |
76 | |
77 | /* Message Transfer pump */ | |
78 | struct tasklet_struct pump_transfers; | |
79 | ||
80 | /* Current message transfer state info */ | |
81 | struct spi_message *cur_msg; | |
82 | struct spi_transfer *cur_transfer; | |
b9f139a7 | 83 | struct slave_data *cur_chip; |
a5f6abd4 WB |
84 | size_t len_in_bytes; |
85 | size_t len; | |
86 | void *tx; | |
87 | void *tx_end; | |
88 | void *rx; | |
89 | void *rx_end; | |
bb90eb00 BW |
90 | |
91 | /* DMA stuffs */ | |
92 | int dma_channel; | |
a5f6abd4 | 93 | int dma_mapped; |
bb90eb00 | 94 | int dma_requested; |
a5f6abd4 WB |
95 | dma_addr_t rx_dma; |
96 | dma_addr_t tx_dma; | |
bb90eb00 | 97 | |
f6a6d966 YL |
98 | int irq_requested; |
99 | int spi_irq; | |
100 | ||
a5f6abd4 WB |
101 | size_t rx_map_len; |
102 | size_t tx_map_len; | |
103 | u8 n_bytes; | |
b052fd0a BS |
104 | u16 ctrl_reg; |
105 | u16 flag_reg; | |
106 | ||
fad91c89 | 107 | int cs_change; |
9c4542c7 | 108 | const struct transfer_ops *ops; |
a5f6abd4 WB |
109 | }; |
110 | ||
b9f139a7 | 111 | struct slave_data { |
a5f6abd4 WB |
112 | u16 ctl_reg; |
113 | u16 baud; | |
114 | u16 flag; | |
115 | ||
116 | u8 chip_select_num; | |
117 | u8 n_bytes; | |
88b40369 | 118 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
119 | u8 enable_dma; |
120 | u8 bits_per_word; /* 8 or 16 */ | |
62310e51 | 121 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 122 | u32 cs_gpio; |
93b61bdd | 123 | u16 idle_tx_val; |
f6a6d966 | 124 | u8 pio_interrupt; /* use spi data irq */ |
9c4542c7 | 125 | const struct transfer_ops *ops; |
a5f6abd4 WB |
126 | }; |
127 | ||
bb90eb00 | 128 | #define DEFINE_SPI_REG(reg, off) \ |
b9f139a7 | 129 | static inline u16 read_##reg(struct master_data *drv_data) \ |
bb90eb00 | 130 | { return bfin_read16(drv_data->regs_base + off); } \ |
b9f139a7 | 131 | static inline void write_##reg(struct master_data *drv_data, u16 v) \ |
bb90eb00 BW |
132 | { bfin_write16(drv_data->regs_base + off, v); } |
133 | ||
134 | DEFINE_SPI_REG(CTRL, 0x00) | |
135 | DEFINE_SPI_REG(FLAG, 0x04) | |
136 | DEFINE_SPI_REG(STAT, 0x08) | |
137 | DEFINE_SPI_REG(TDBR, 0x0C) | |
138 | DEFINE_SPI_REG(RDBR, 0x10) | |
139 | DEFINE_SPI_REG(BAUD, 0x14) | |
140 | DEFINE_SPI_REG(SHAW, 0x18) | |
141 | ||
b9f139a7 | 142 | static void bfin_spi_enable(struct master_data *drv_data) |
a5f6abd4 WB |
143 | { |
144 | u16 cr; | |
145 | ||
bb90eb00 BW |
146 | cr = read_CTRL(drv_data); |
147 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
148 | } |
149 | ||
b9f139a7 | 150 | static void bfin_spi_disable(struct master_data *drv_data) |
a5f6abd4 WB |
151 | { |
152 | u16 cr; | |
153 | ||
bb90eb00 BW |
154 | cr = read_CTRL(drv_data); |
155 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
156 | } |
157 | ||
158 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
159 | static u16 hz_to_spi_baud(u32 speed_hz) | |
160 | { | |
161 | u_long sclk = get_sclk(); | |
162 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
163 | ||
164 | if ((sclk % (2 * speed_hz)) > 0) | |
165 | spi_baud++; | |
166 | ||
7513e006 MH |
167 | if (spi_baud < MIN_SPI_BAUD_VAL) |
168 | spi_baud = MIN_SPI_BAUD_VAL; | |
169 | ||
a5f6abd4 WB |
170 | return spi_baud; |
171 | } | |
172 | ||
b9f139a7 | 173 | static int bfin_spi_flush(struct master_data *drv_data) |
a5f6abd4 WB |
174 | { |
175 | unsigned long limit = loops_per_jiffy << 1; | |
176 | ||
177 | /* wait for stop and clear stat */ | |
b4bd2aba | 178 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 179 | cpu_relax(); |
a5f6abd4 | 180 | |
bb90eb00 | 181 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
182 | |
183 | return limit; | |
184 | } | |
185 | ||
fad91c89 | 186 | /* Chip select operation functions for cs_change flag */ |
b9f139a7 | 187 | static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 188 | { |
d3cc71f7 | 189 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 190 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 191 | |
8221610e | 192 | flag &= ~chip->flag; |
fad91c89 | 193 | |
42c78b2b MH |
194 | write_FLAG(drv_data, flag); |
195 | } else { | |
196 | gpio_set_value(chip->cs_gpio, 0); | |
197 | } | |
fad91c89 BW |
198 | } |
199 | ||
b9f139a7 | 200 | static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 201 | { |
d3cc71f7 | 202 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 203 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 204 | |
8221610e | 205 | flag |= chip->flag; |
fad91c89 | 206 | |
42c78b2b MH |
207 | write_FLAG(drv_data, flag); |
208 | } else { | |
209 | gpio_set_value(chip->cs_gpio, 1); | |
210 | } | |
62310e51 BW |
211 | |
212 | /* Move delay here for consistency */ | |
213 | if (chip->cs_chg_udelay) | |
214 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
215 | } |
216 | ||
8221610e | 217 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
b9f139a7 | 218 | static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip) |
8221610e | 219 | { |
d3cc71f7 BS |
220 | if (chip->chip_select_num < MAX_CTRL_CS) { |
221 | u16 flag = read_FLAG(drv_data); | |
8221610e | 222 | |
d3cc71f7 | 223 | flag |= (chip->flag >> 8); |
8221610e | 224 | |
d3cc71f7 BS |
225 | write_FLAG(drv_data, flag); |
226 | } | |
8221610e BS |
227 | } |
228 | ||
b9f139a7 | 229 | static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip) |
8221610e | 230 | { |
d3cc71f7 BS |
231 | if (chip->chip_select_num < MAX_CTRL_CS) { |
232 | u16 flag = read_FLAG(drv_data); | |
8221610e | 233 | |
d3cc71f7 | 234 | flag &= ~(chip->flag >> 8); |
8221610e | 235 | |
d3cc71f7 BS |
236 | write_FLAG(drv_data, flag); |
237 | } | |
8221610e BS |
238 | } |
239 | ||
a5f6abd4 | 240 | /* stop controller and re-config current chip*/ |
b9f139a7 | 241 | static void bfin_spi_restore_state(struct master_data *drv_data) |
a5f6abd4 | 242 | { |
b9f139a7 | 243 | struct slave_data *chip = drv_data->cur_chip; |
12e17c42 | 244 | |
a5f6abd4 | 245 | /* Clear status and disable clock */ |
bb90eb00 | 246 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 247 | bfin_spi_disable(drv_data); |
88b40369 | 248 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 249 | |
5fec5b5a | 250 | /* Load the registers */ |
bb90eb00 | 251 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 252 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
253 | |
254 | bfin_spi_enable(drv_data); | |
138f97cd | 255 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
256 | } |
257 | ||
93b61bdd | 258 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
b9f139a7 | 259 | static inline void bfin_spi_dummy_read(struct master_data *drv_data) |
a5f6abd4 | 260 | { |
93b61bdd | 261 | (void) read_RDBR(drv_data); |
a5f6abd4 WB |
262 | } |
263 | ||
b9f139a7 | 264 | static void bfin_spi_u8_writer(struct master_data *drv_data) |
a5f6abd4 | 265 | { |
93b61bdd WM |
266 | /* clear RXS (we check for RXS inside the loop) */ |
267 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 268 | |
a5f6abd4 | 269 | while (drv_data->tx < drv_data->tx_end) { |
93b61bdd WM |
270 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
271 | /* wait until transfer finished. | |
272 | checking SPIF or TXS may not guarantee transfer completion */ | |
273 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
d8c05008 | 274 | cpu_relax(); |
93b61bdd WM |
275 | /* discard RX data and clear RXS */ |
276 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 277 | } |
a5f6abd4 WB |
278 | } |
279 | ||
b9f139a7 | 280 | static void bfin_spi_u8_reader(struct master_data *drv_data) |
a5f6abd4 | 281 | { |
93b61bdd | 282 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 283 | |
93b61bdd | 284 | /* discard old RX data and clear RXS */ |
138f97cd | 285 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 286 | |
93b61bdd WM |
287 | while (drv_data->rx < drv_data->rx_end) { |
288 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 289 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 290 | cpu_relax(); |
93b61bdd | 291 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 | 292 | } |
a5f6abd4 WB |
293 | } |
294 | ||
b9f139a7 | 295 | static void bfin_spi_u8_duplex(struct master_data *drv_data) |
a5f6abd4 | 296 | { |
93b61bdd WM |
297 | /* discard old RX data and clear RXS */ |
298 | bfin_spi_dummy_read(drv_data); | |
299 | ||
a5f6abd4 | 300 | while (drv_data->rx < drv_data->rx_end) { |
93b61bdd | 301 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 302 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 303 | cpu_relax(); |
93b61bdd | 304 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 WB |
305 | } |
306 | } | |
307 | ||
9c4542c7 MF |
308 | static const struct transfer_ops bfin_transfer_ops_u8 = { |
309 | .write = bfin_spi_u8_writer, | |
310 | .read = bfin_spi_u8_reader, | |
311 | .duplex = bfin_spi_u8_duplex, | |
312 | }; | |
313 | ||
b9f139a7 | 314 | static void bfin_spi_u16_writer(struct master_data *drv_data) |
a5f6abd4 | 315 | { |
93b61bdd WM |
316 | /* clear RXS (we check for RXS inside the loop) */ |
317 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 318 | |
a5f6abd4 | 319 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 320 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 321 | drv_data->tx += 2; |
93b61bdd WM |
322 | /* wait until transfer finished. |
323 | checking SPIF or TXS may not guarantee transfer completion */ | |
324 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
325 | cpu_relax(); | |
326 | /* discard RX data and clear RXS */ | |
327 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 328 | } |
a5f6abd4 WB |
329 | } |
330 | ||
b9f139a7 | 331 | static void bfin_spi_u16_reader(struct master_data *drv_data) |
a5f6abd4 | 332 | { |
93b61bdd | 333 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 334 | |
93b61bdd | 335 | /* discard old RX data and clear RXS */ |
138f97cd | 336 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 337 | |
93b61bdd WM |
338 | while (drv_data->rx < drv_data->rx_end) { |
339 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 340 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 341 | cpu_relax(); |
bb90eb00 | 342 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
343 | drv_data->rx += 2; |
344 | } | |
a5f6abd4 WB |
345 | } |
346 | ||
b9f139a7 | 347 | static void bfin_spi_u16_duplex(struct master_data *drv_data) |
a5f6abd4 | 348 | { |
93b61bdd WM |
349 | /* discard old RX data and clear RXS */ |
350 | bfin_spi_dummy_read(drv_data); | |
351 | ||
352 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 353 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 354 | drv_data->tx += 2; |
bb90eb00 | 355 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 356 | cpu_relax(); |
bb90eb00 | 357 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 358 | drv_data->rx += 2; |
a5f6abd4 WB |
359 | } |
360 | } | |
361 | ||
9c4542c7 MF |
362 | static const struct transfer_ops bfin_transfer_ops_u16 = { |
363 | .write = bfin_spi_u16_writer, | |
364 | .read = bfin_spi_u16_reader, | |
365 | .duplex = bfin_spi_u16_duplex, | |
366 | }; | |
367 | ||
a5f6abd4 | 368 | /* test if ther is more transfer to be done */ |
b9f139a7 | 369 | static void *bfin_spi_next_transfer(struct master_data *drv_data) |
a5f6abd4 WB |
370 | { |
371 | struct spi_message *msg = drv_data->cur_msg; | |
372 | struct spi_transfer *trans = drv_data->cur_transfer; | |
373 | ||
374 | /* Move to next transfer */ | |
375 | if (trans->transfer_list.next != &msg->transfers) { | |
376 | drv_data->cur_transfer = | |
377 | list_entry(trans->transfer_list.next, | |
378 | struct spi_transfer, transfer_list); | |
379 | return RUNNING_STATE; | |
380 | } else | |
381 | return DONE_STATE; | |
382 | } | |
383 | ||
384 | /* | |
385 | * caller already set message->status; | |
386 | * dma and pio irqs are blocked give finished message back | |
387 | */ | |
b9f139a7 | 388 | static void bfin_spi_giveback(struct master_data *drv_data) |
a5f6abd4 | 389 | { |
b9f139a7 | 390 | struct slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
391 | struct spi_transfer *last_transfer; |
392 | unsigned long flags; | |
393 | struct spi_message *msg; | |
394 | ||
395 | spin_lock_irqsave(&drv_data->lock, flags); | |
396 | msg = drv_data->cur_msg; | |
397 | drv_data->cur_msg = NULL; | |
398 | drv_data->cur_transfer = NULL; | |
399 | drv_data->cur_chip = NULL; | |
400 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
401 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
402 | ||
403 | last_transfer = list_entry(msg->transfers.prev, | |
404 | struct spi_transfer, transfer_list); | |
405 | ||
406 | msg->state = NULL; | |
407 | ||
fad91c89 | 408 | if (!drv_data->cs_change) |
138f97cd | 409 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 410 | |
b9b2a76a YL |
411 | /* Not stop spi in autobuffer mode */ |
412 | if (drv_data->tx_dma != 0xFFFF) | |
413 | bfin_spi_disable(drv_data); | |
414 | ||
a5f6abd4 WB |
415 | if (msg->complete) |
416 | msg->complete(msg->context); | |
417 | } | |
418 | ||
f6a6d966 YL |
419 | /* spi data irq handler */ |
420 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
421 | { | |
b9f139a7 MF |
422 | struct master_data *drv_data = dev_id; |
423 | struct slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
424 | struct spi_message *msg = drv_data->cur_msg; |
425 | int n_bytes = drv_data->n_bytes; | |
426 | ||
427 | /* wait until transfer finished. */ | |
428 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
429 | cpu_relax(); | |
430 | ||
431 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
432 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
433 | /* last read */ | |
434 | if (drv_data->rx) { | |
435 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
436 | if (n_bytes == 2) | |
437 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
438 | else if (n_bytes == 1) | |
439 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
440 | drv_data->rx += n_bytes; | |
441 | } | |
442 | ||
443 | msg->actual_length += drv_data->len_in_bytes; | |
444 | if (drv_data->cs_change) | |
445 | bfin_spi_cs_deactive(drv_data, chip); | |
446 | /* Move to next transfer */ | |
447 | msg->state = bfin_spi_next_transfer(drv_data); | |
448 | ||
449 | disable_irq(drv_data->spi_irq); | |
450 | ||
451 | /* Schedule transfer tasklet */ | |
452 | tasklet_schedule(&drv_data->pump_transfers); | |
453 | return IRQ_HANDLED; | |
454 | } | |
455 | ||
456 | if (drv_data->rx && drv_data->tx) { | |
457 | /* duplex */ | |
458 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
459 | if (drv_data->n_bytes == 2) { | |
460 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
461 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
462 | } else if (drv_data->n_bytes == 1) { | |
463 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
464 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
465 | } | |
466 | } else if (drv_data->rx) { | |
467 | /* read */ | |
468 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
469 | if (drv_data->n_bytes == 2) | |
470 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
471 | else if (drv_data->n_bytes == 1) | |
472 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
473 | write_TDBR(drv_data, chip->idle_tx_val); | |
474 | } else if (drv_data->tx) { | |
475 | /* write */ | |
476 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
477 | bfin_spi_dummy_read(drv_data); | |
478 | if (drv_data->n_bytes == 2) | |
479 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
480 | else if (drv_data->n_bytes == 1) | |
481 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
482 | } | |
483 | ||
484 | if (drv_data->tx) | |
485 | drv_data->tx += n_bytes; | |
486 | if (drv_data->rx) | |
487 | drv_data->rx += n_bytes; | |
488 | ||
489 | return IRQ_HANDLED; | |
490 | } | |
491 | ||
138f97cd | 492 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 493 | { |
b9f139a7 MF |
494 | struct master_data *drv_data = dev_id; |
495 | struct slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 496 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 497 | unsigned long timeout; |
d24bd1d0 | 498 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 499 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 500 | |
d24bd1d0 MF |
501 | dev_dbg(&drv_data->pdev->dev, |
502 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
503 | dmastat, spistat); | |
504 | ||
bb90eb00 | 505 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
506 | |
507 | /* | |
d6fe89b0 BW |
508 | * wait for the last transaction shifted out. HRM states: |
509 | * at this point there may still be data in the SPI DMA FIFO waiting | |
510 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
511 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
512 | */ |
513 | if (drv_data->tx != NULL) { | |
90008a64 MF |
514 | while ((read_STAT(drv_data) & BIT_STAT_TXS) || |
515 | (read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 516 | cpu_relax(); |
a5f6abd4 WB |
517 | } |
518 | ||
aaaf939c MF |
519 | dev_dbg(&drv_data->pdev->dev, |
520 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
521 | dmastat, read_STAT(drv_data)); | |
522 | ||
523 | timeout = jiffies + HZ; | |
90008a64 | 524 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
aaaf939c MF |
525 | if (!time_before(jiffies, timeout)) { |
526 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
527 | break; | |
528 | } else | |
529 | cpu_relax(); | |
a5f6abd4 | 530 | |
90008a64 | 531 | if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) { |
04b95d2f MF |
532 | msg->state = ERROR_STATE; |
533 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
534 | } else { | |
535 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 536 | |
04b95d2f | 537 | if (drv_data->cs_change) |
138f97cd | 538 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 539 | |
04b95d2f | 540 | /* Move to next transfer */ |
138f97cd | 541 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 542 | } |
a5f6abd4 WB |
543 | |
544 | /* Schedule transfer tasklet */ | |
545 | tasklet_schedule(&drv_data->pump_transfers); | |
546 | ||
547 | /* free the irq handler before next transfer */ | |
88b40369 BW |
548 | dev_dbg(&drv_data->pdev->dev, |
549 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
550 | drv_data->dma_channel); |
551 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
552 | |
553 | return IRQ_HANDLED; | |
554 | } | |
555 | ||
138f97cd | 556 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 557 | { |
b9f139a7 | 558 | struct master_data *drv_data = (struct master_data *)data; |
a5f6abd4 WB |
559 | struct spi_message *message = NULL; |
560 | struct spi_transfer *transfer = NULL; | |
561 | struct spi_transfer *previous = NULL; | |
b9f139a7 | 562 | struct slave_data *chip = NULL; |
88b40369 BW |
563 | u8 width; |
564 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 565 | u32 tranf_success = 1; |
8eeb12e5 | 566 | u8 full_duplex = 0; |
a5f6abd4 WB |
567 | |
568 | /* Get current state information */ | |
569 | message = drv_data->cur_msg; | |
570 | transfer = drv_data->cur_transfer; | |
571 | chip = drv_data->cur_chip; | |
092e1fda | 572 | |
a5f6abd4 WB |
573 | /* |
574 | * if msg is error or done, report it back using complete() callback | |
575 | */ | |
576 | ||
577 | /* Handle for abort */ | |
578 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 579 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 580 | message->status = -EIO; |
138f97cd | 581 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
582 | return; |
583 | } | |
584 | ||
585 | /* Handle end of message */ | |
586 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 587 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 588 | message->status = 0; |
138f97cd | 589 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
590 | return; |
591 | } | |
592 | ||
593 | /* Delay if requested at end of transfer */ | |
594 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 595 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
596 | previous = list_entry(transfer->transfer_list.prev, |
597 | struct spi_transfer, transfer_list); | |
598 | if (previous->delay_usecs) | |
599 | udelay(previous->delay_usecs); | |
600 | } | |
601 | ||
ab09e040 | 602 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 603 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
604 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
605 | message->status = -EIO; | |
138f97cd | 606 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
607 | return; |
608 | } | |
609 | ||
93b61bdd WM |
610 | if (transfer->len == 0) { |
611 | /* Move to next transfer of this msg */ | |
612 | message->state = bfin_spi_next_transfer(drv_data); | |
613 | /* Schedule next transfer tasklet */ | |
614 | tasklet_schedule(&drv_data->pump_transfers); | |
615 | } | |
616 | ||
a5f6abd4 WB |
617 | if (transfer->tx_buf != NULL) { |
618 | drv_data->tx = (void *)transfer->tx_buf; | |
619 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
620 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
621 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
622 | } else { |
623 | drv_data->tx = NULL; | |
624 | } | |
625 | ||
626 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 627 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
628 | drv_data->rx = transfer->rx_buf; |
629 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
630 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
631 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
632 | } else { |
633 | drv_data->rx = NULL; | |
634 | } | |
635 | ||
636 | drv_data->rx_dma = transfer->rx_dma; | |
637 | drv_data->tx_dma = transfer->tx_dma; | |
638 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 639 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 640 | |
092e1fda BW |
641 | /* Bits per word setup */ |
642 | switch (transfer->bits_per_word) { | |
643 | case 8: | |
644 | drv_data->n_bytes = 1; | |
645 | width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 646 | drv_data->ops = &bfin_transfer_ops_u8; |
092e1fda BW |
647 | break; |
648 | ||
649 | case 16: | |
650 | drv_data->n_bytes = 2; | |
651 | width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 652 | drv_data->ops = &bfin_transfer_ops_u16; |
092e1fda BW |
653 | break; |
654 | ||
655 | default: | |
656 | /* No change, the same as default setting */ | |
f6a6d966 | 657 | transfer->bits_per_word = chip->bits_per_word; |
092e1fda BW |
658 | drv_data->n_bytes = chip->n_bytes; |
659 | width = chip->width; | |
9c4542c7 | 660 | drv_data->ops = chip->ops; |
092e1fda BW |
661 | break; |
662 | } | |
663 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
664 | cr |= (width << 8); | |
665 | write_CTRL(drv_data, cr); | |
666 | ||
a5f6abd4 WB |
667 | if (width == CFG_SPI_WORDSIZE16) { |
668 | drv_data->len = (transfer->len) >> 1; | |
669 | } else { | |
670 | drv_data->len = transfer->len; | |
671 | } | |
4fb98efa | 672 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 MF |
673 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
674 | drv_data->ops, chip->ops, &bfin_transfer_ops_u8); | |
a5f6abd4 | 675 | |
a5f6abd4 WB |
676 | message->state = RUNNING_STATE; |
677 | dma_config = 0; | |
678 | ||
092e1fda BW |
679 | /* Speed setup (surely valid because already checked) */ |
680 | if (transfer->speed_hz) | |
681 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
682 | else | |
683 | write_BAUD(drv_data, chip->baud); | |
684 | ||
bb90eb00 BW |
685 | write_STAT(drv_data, BIT_STAT_CLR); |
686 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
b9b2a76a | 687 | if (drv_data->cs_change) |
138f97cd | 688 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 689 | |
88b40369 BW |
690 | dev_dbg(&drv_data->pdev->dev, |
691 | "now pumping a transfer: width is %d, len is %d\n", | |
692 | width, transfer->len); | |
a5f6abd4 WB |
693 | |
694 | /* | |
8cf5858c VM |
695 | * Try to map dma buffer and do a dma transfer. If successful use, |
696 | * different way to r/w according to the enable_dma settings and if | |
697 | * we are not doing a full duplex transfer (since the hardware does | |
698 | * not support full duplex DMA transfers). | |
a5f6abd4 | 699 | */ |
8eeb12e5 VM |
700 | if (!full_duplex && drv_data->cur_chip->enable_dma |
701 | && drv_data->len > 6) { | |
a5f6abd4 | 702 | |
11d6f599 | 703 | unsigned long dma_start_addr, flags; |
7aec3566 | 704 | |
bb90eb00 BW |
705 | disable_dma(drv_data->dma_channel); |
706 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
707 | |
708 | /* config dma channel */ | |
88b40369 | 709 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 710 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 | 711 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 | 712 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
713 | dma_width = WDSIZE_16; |
714 | } else { | |
bb90eb00 | 715 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
716 | dma_width = WDSIZE_8; |
717 | } | |
718 | ||
3f479a65 | 719 | /* poll for SPI completion before start */ |
bb90eb00 | 720 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 721 | cpu_relax(); |
3f479a65 | 722 | |
a5f6abd4 WB |
723 | /* dirty hack for autobuffer DMA mode */ |
724 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
725 | dev_dbg(&drv_data->pdev->dev, |
726 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
727 | |
728 | /* no irq in autobuffer mode */ | |
729 | dma_config = | |
730 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
731 | set_dma_config(drv_data->dma_channel, dma_config); |
732 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 733 | (unsigned long)drv_data->tx); |
bb90eb00 | 734 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 735 | |
07612e5f | 736 | /* start SPI transfer */ |
11d6f599 | 737 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
738 | |
739 | /* just return here, there can only be one transfer | |
740 | * in this mode | |
741 | */ | |
a5f6abd4 | 742 | message->status = 0; |
138f97cd | 743 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
744 | return; |
745 | } | |
746 | ||
747 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 748 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
749 | if (drv_data->rx != NULL) { |
750 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
751 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
752 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 753 | |
8cf5858c | 754 | /* invalidate caches, if needed */ |
67834fa9 | 755 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
756 | invalidate_dcache_range((unsigned long) drv_data->rx, |
757 | (unsigned long) (drv_data->rx + | |
ace32865 | 758 | drv_data->len_in_bytes)); |
8cf5858c | 759 | |
7aec3566 MF |
760 | dma_config |= WNR; |
761 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 762 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 763 | |
a5f6abd4 | 764 | } else if (drv_data->tx != NULL) { |
88b40369 | 765 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 766 | |
8cf5858c | 767 | /* flush caches, if needed */ |
67834fa9 | 768 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
769 | flush_dcache_range((unsigned long) drv_data->tx, |
770 | (unsigned long) (drv_data->tx + | |
ace32865 | 771 | drv_data->len_in_bytes)); |
8cf5858c | 772 | |
7aec3566 | 773 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 774 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
775 | |
776 | } else | |
777 | BUG(); | |
778 | ||
11d6f599 MF |
779 | /* oh man, here there be monsters ... and i dont mean the |
780 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
781 | * your data, kick your dog, and love it all. do *not* try | |
782 | * and change these lines unless you (1) heavily test DMA | |
783 | * with SPI flashes on a loaded system (e.g. ping floods), | |
784 | * (2) know just how broken the DMA engine interaction with | |
785 | * the SPI peripheral is, and (3) have someone else to blame | |
786 | * when you screw it all up anyways. | |
787 | */ | |
7aec3566 | 788 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
789 | set_dma_config(drv_data->dma_channel, dma_config); |
790 | local_irq_save(flags); | |
a963ea83 | 791 | SSYNC(); |
11d6f599 | 792 | write_CTRL(drv_data, cr); |
a963ea83 | 793 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
794 | dma_enable_irq(drv_data->dma_channel); |
795 | local_irq_restore(flags); | |
07612e5f | 796 | |
f6a6d966 YL |
797 | return; |
798 | } | |
a5f6abd4 | 799 | |
f6a6d966 YL |
800 | if (chip->pio_interrupt) { |
801 | /* use write mode. spi irq should have been disabled */ | |
802 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
93b61bdd WM |
803 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
804 | ||
f6a6d966 YL |
805 | /* discard old RX data and clear RXS */ |
806 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 807 | |
f6a6d966 YL |
808 | /* start transfer */ |
809 | if (drv_data->tx == NULL) | |
810 | write_TDBR(drv_data, chip->idle_tx_val); | |
811 | else { | |
812 | if (transfer->bits_per_word == 8) | |
813 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
814 | else if (transfer->bits_per_word == 16) | |
815 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
816 | drv_data->tx += drv_data->n_bytes; | |
817 | } | |
a5f6abd4 | 818 | |
f6a6d966 YL |
819 | /* once TDBR is empty, interrupt is triggered */ |
820 | enable_irq(drv_data->spi_irq); | |
821 | return; | |
822 | } | |
a5f6abd4 | 823 | |
f6a6d966 YL |
824 | /* IO mode */ |
825 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
826 | ||
827 | /* we always use SPI_WRITE mode. SPI_READ mode | |
828 | seems to have problems with setting up the | |
829 | output value in TDBR prior to the transfer. */ | |
830 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); | |
831 | ||
832 | if (full_duplex) { | |
833 | /* full duplex mode */ | |
834 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
835 | (drv_data->rx_end - drv_data->rx)); | |
836 | dev_dbg(&drv_data->pdev->dev, | |
837 | "IO duplex: cr is 0x%x\n", cr); | |
838 | ||
9c4542c7 | 839 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
840 | |
841 | if (drv_data->tx != drv_data->tx_end) | |
842 | tranf_success = 0; | |
843 | } else if (drv_data->tx != NULL) { | |
844 | /* write only half duplex */ | |
845 | dev_dbg(&drv_data->pdev->dev, | |
846 | "IO write: cr is 0x%x\n", cr); | |
847 | ||
9c4542c7 | 848 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
849 | |
850 | if (drv_data->tx != drv_data->tx_end) | |
851 | tranf_success = 0; | |
852 | } else if (drv_data->rx != NULL) { | |
853 | /* read only half duplex */ | |
854 | dev_dbg(&drv_data->pdev->dev, | |
855 | "IO read: cr is 0x%x\n", cr); | |
856 | ||
9c4542c7 | 857 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
858 | if (drv_data->rx != drv_data->rx_end) |
859 | tranf_success = 0; | |
860 | } | |
a5f6abd4 | 861 | |
f6a6d966 YL |
862 | if (!tranf_success) { |
863 | dev_dbg(&drv_data->pdev->dev, | |
864 | "IO write error!\n"); | |
865 | message->state = ERROR_STATE; | |
866 | } else { | |
867 | /* Update total byte transfered */ | |
868 | message->actual_length += drv_data->len_in_bytes; | |
869 | /* Move to next transfer of this msg */ | |
870 | message->state = bfin_spi_next_transfer(drv_data); | |
871 | if (drv_data->cs_change) | |
872 | bfin_spi_cs_deactive(drv_data, chip); | |
a5f6abd4 | 873 | } |
f6a6d966 YL |
874 | |
875 | /* Schedule next transfer tasklet */ | |
876 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
877 | } |
878 | ||
879 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 880 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 881 | { |
b9f139a7 | 882 | struct master_data *drv_data; |
a5f6abd4 WB |
883 | unsigned long flags; |
884 | ||
b9f139a7 | 885 | drv_data = container_of(work, struct master_data, pump_messages); |
131b17d4 | 886 | |
a5f6abd4 WB |
887 | /* Lock queue and check for queue work */ |
888 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 889 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
890 | /* pumper kicked off but no work to do */ |
891 | drv_data->busy = 0; | |
892 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
893 | return; | |
894 | } | |
895 | ||
896 | /* Make sure we are not already running a message */ | |
897 | if (drv_data->cur_msg) { | |
898 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
899 | return; | |
900 | } | |
901 | ||
902 | /* Extract head of queue */ | |
903 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
904 | struct spi_message, queue); | |
5fec5b5a BW |
905 | |
906 | /* Setup the SSP using the per chip configuration */ | |
907 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 908 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 909 | |
a5f6abd4 WB |
910 | list_del_init(&drv_data->cur_msg->queue); |
911 | ||
912 | /* Initial message state */ | |
913 | drv_data->cur_msg->state = START_STATE; | |
914 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
915 | struct spi_transfer, transfer_list); | |
916 | ||
5fec5b5a BW |
917 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
918 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
919 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
920 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
921 | |
922 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
923 | "the first transfer len is %d\n", |
924 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
925 | |
926 | /* Mark as busy and launch transfers */ | |
927 | tasklet_schedule(&drv_data->pump_transfers); | |
928 | ||
929 | drv_data->busy = 1; | |
930 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
931 | } | |
932 | ||
933 | /* | |
934 | * got a msg to transfer, queue it in drv_data->queue. | |
935 | * And kick off message pumper | |
936 | */ | |
138f97cd | 937 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 938 | { |
b9f139a7 | 939 | struct master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
940 | unsigned long flags; |
941 | ||
942 | spin_lock_irqsave(&drv_data->lock, flags); | |
943 | ||
f4f50c3f | 944 | if (!drv_data->running) { |
a5f6abd4 WB |
945 | spin_unlock_irqrestore(&drv_data->lock, flags); |
946 | return -ESHUTDOWN; | |
947 | } | |
948 | ||
949 | msg->actual_length = 0; | |
950 | msg->status = -EINPROGRESS; | |
951 | msg->state = START_STATE; | |
952 | ||
88b40369 | 953 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
954 | list_add_tail(&msg->queue, &drv_data->queue); |
955 | ||
f4f50c3f | 956 | if (drv_data->running && !drv_data->busy) |
a5f6abd4 WB |
957 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
958 | ||
959 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
12e17c42 SZ |
964 | #define MAX_SPI_SSEL 7 |
965 | ||
4160bde2 | 966 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
967 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
968 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
969 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
970 | ||
971 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
972 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
973 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
974 | ||
975 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
976 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
977 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
978 | }; | |
979 | ||
ab09e040 | 980 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 981 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 982 | { |
ac01e97d | 983 | struct bfin5xx_spi_chip *chip_info; |
b9f139a7 MF |
984 | struct slave_data *chip = NULL; |
985 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
ac01e97d | 986 | int ret = -EINVAL; |
a5f6abd4 | 987 | |
a5f6abd4 | 988 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) |
ac01e97d | 989 | goto error; |
a5f6abd4 WB |
990 | |
991 | /* Only alloc (or use chip_info) on first setup */ | |
ac01e97d | 992 | chip_info = NULL; |
a5f6abd4 WB |
993 | chip = spi_get_ctldata(spi); |
994 | if (chip == NULL) { | |
ac01e97d DM |
995 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
996 | if (!chip) { | |
997 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
998 | ret = -ENOMEM; | |
999 | goto error; | |
1000 | } | |
a5f6abd4 WB |
1001 | |
1002 | chip->enable_dma = 0; | |
1003 | chip_info = spi->controller_data; | |
1004 | } | |
1005 | ||
1006 | /* chip_info isn't always needed */ | |
1007 | if (chip_info) { | |
2ed35516 MF |
1008 | /* Make sure people stop trying to set fields via ctl_reg |
1009 | * when they should actually be using common SPI framework. | |
90008a64 | 1010 | * Currently we let through: WOM EMISO PSSE GM SZ. |
2ed35516 MF |
1011 | * Not sure if a user actually needs/uses any of these, |
1012 | * but let's assume (for now) they do. | |
1013 | */ | |
90008a64 MF |
1014 | if (chip_info->ctl_reg & ~(BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | \ |
1015 | BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ)) { | |
2ed35516 MF |
1016 | dev_err(&spi->dev, "do not set bits in ctl_reg " |
1017 | "that the SPI framework manages\n"); | |
ac01e97d | 1018 | goto error; |
2ed35516 MF |
1019 | } |
1020 | ||
a5f6abd4 WB |
1021 | chip->enable_dma = chip_info->enable_dma != 0 |
1022 | && drv_data->master_info->enable_dma; | |
1023 | chip->ctl_reg = chip_info->ctl_reg; | |
1024 | chip->bits_per_word = chip_info->bits_per_word; | |
a5f6abd4 | 1025 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
93b61bdd | 1026 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1027 | chip->pio_interrupt = chip_info->pio_interrupt; |
a5f6abd4 WB |
1028 | } |
1029 | ||
1030 | /* translate common spi framework into our register */ | |
1031 | if (spi->mode & SPI_CPOL) | |
90008a64 | 1032 | chip->ctl_reg |= BIT_CTL_CPOL; |
a5f6abd4 | 1033 | if (spi->mode & SPI_CPHA) |
90008a64 | 1034 | chip->ctl_reg |= BIT_CTL_CPHA; |
a5f6abd4 | 1035 | if (spi->mode & SPI_LSB_FIRST) |
90008a64 | 1036 | chip->ctl_reg |= BIT_CTL_LSBF; |
a5f6abd4 | 1037 | /* we dont support running in slave mode (yet?) */ |
90008a64 | 1038 | chip->ctl_reg |= BIT_CTL_MASTER; |
a5f6abd4 | 1039 | |
a5f6abd4 WB |
1040 | /* |
1041 | * Notice: for blackfin, the speed_hz is the value of register | |
1042 | * SPI_BAUD, not the real baudrate | |
1043 | */ | |
1044 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
a5f6abd4 | 1045 | chip->chip_select_num = spi->chip_select; |
d3cc71f7 BS |
1046 | if (chip->chip_select_num < MAX_CTRL_CS) |
1047 | chip->flag = (1 << spi->chip_select) << 8; | |
1048 | else | |
1049 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; | |
a5f6abd4 WB |
1050 | |
1051 | switch (chip->bits_per_word) { | |
1052 | case 8: | |
1053 | chip->n_bytes = 1; | |
1054 | chip->width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 1055 | chip->ops = &bfin_transfer_ops_u8; |
a5f6abd4 WB |
1056 | break; |
1057 | ||
1058 | case 16: | |
1059 | chip->n_bytes = 2; | |
1060 | chip->width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 1061 | chip->ops = &bfin_transfer_ops_u16; |
a5f6abd4 WB |
1062 | break; |
1063 | ||
1064 | default: | |
1065 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1066 | chip->bits_per_word); | |
ac01e97d DM |
1067 | goto error; |
1068 | } | |
1069 | ||
f6a6d966 YL |
1070 | if (chip->enable_dma && chip->pio_interrupt) { |
1071 | dev_err(&spi->dev, "enable_dma is set, " | |
1072 | "do not set pio_interrupt\n"); | |
1073 | goto error; | |
1074 | } | |
ac01e97d DM |
1075 | /* |
1076 | * if any one SPI chip is registered and wants DMA, request the | |
1077 | * DMA channel for it | |
1078 | */ | |
1079 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1080 | /* register dma irq handler */ | |
1081 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1082 | if (ret) { | |
1083 | dev_err(&spi->dev, | |
1084 | "Unable to request BlackFin SPI DMA channel\n"); | |
1085 | goto error; | |
1086 | } | |
1087 | drv_data->dma_requested = 1; | |
1088 | ||
1089 | ret = set_dma_callback(drv_data->dma_channel, | |
1090 | bfin_spi_dma_irq_handler, drv_data); | |
1091 | if (ret) { | |
1092 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1093 | goto error; | |
1094 | } | |
1095 | dma_disable_irq(drv_data->dma_channel); | |
1096 | } | |
1097 | ||
f6a6d966 YL |
1098 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1099 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
1100 | IRQF_DISABLED, "BFIN_SPI", drv_data); | |
1101 | if (ret) { | |
1102 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1103 | goto error; | |
1104 | } | |
1105 | drv_data->irq_requested = 1; | |
1106 | /* we use write mode, spi irq has to be disabled here */ | |
1107 | disable_irq(drv_data->spi_irq); | |
1108 | } | |
1109 | ||
d3cc71f7 | 1110 | if (chip->chip_select_num >= MAX_CTRL_CS) { |
ac01e97d DM |
1111 | ret = gpio_request(chip->cs_gpio, spi->modalias); |
1112 | if (ret) { | |
1113 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1114 | goto pin_error; | |
1115 | } | |
1116 | gpio_direction_output(chip->cs_gpio, 1); | |
a5f6abd4 WB |
1117 | } |
1118 | ||
898eb71c | 1119 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1120 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1121 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1122 | chip->ctl_reg, chip->flag); |
1123 | ||
1124 | spi_set_ctldata(spi, chip); | |
1125 | ||
12e17c42 | 1126 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
d3cc71f7 | 1127 | if (chip->chip_select_num < MAX_CTRL_CS) { |
ac01e97d DM |
1128 | ret = peripheral_request(ssel[spi->master->bus_num] |
1129 | [chip->chip_select_num-1], spi->modalias); | |
1130 | if (ret) { | |
1131 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1132 | goto pin_error; | |
1133 | } | |
1134 | } | |
12e17c42 | 1135 | |
8221610e | 1136 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1137 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1138 | |
a5f6abd4 | 1139 | return 0; |
ac01e97d DM |
1140 | |
1141 | pin_error: | |
d3cc71f7 | 1142 | if (chip->chip_select_num >= MAX_CTRL_CS) |
ac01e97d DM |
1143 | gpio_free(chip->cs_gpio); |
1144 | else | |
1145 | peripheral_free(ssel[spi->master->bus_num] | |
1146 | [chip->chip_select_num - 1]); | |
1147 | error: | |
1148 | if (chip) { | |
1149 | if (drv_data->dma_requested) | |
1150 | free_dma(drv_data->dma_channel); | |
1151 | drv_data->dma_requested = 0; | |
1152 | ||
1153 | kfree(chip); | |
1154 | /* prevent free 'chip' twice */ | |
1155 | spi_set_ctldata(spi, NULL); | |
1156 | } | |
1157 | ||
1158 | return ret; | |
a5f6abd4 WB |
1159 | } |
1160 | ||
1161 | /* | |
1162 | * callback for spi framework. | |
1163 | * clean driver specific data | |
1164 | */ | |
138f97cd | 1165 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1166 | { |
b9f139a7 MF |
1167 | struct slave_data *chip = spi_get_ctldata(spi); |
1168 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1169 | |
e7d02e3c MF |
1170 | if (!chip) |
1171 | return; | |
1172 | ||
d3cc71f7 | 1173 | if (chip->chip_select_num < MAX_CTRL_CS) { |
12e17c42 SZ |
1174 | peripheral_free(ssel[spi->master->bus_num] |
1175 | [chip->chip_select_num-1]); | |
8221610e | 1176 | bfin_spi_cs_disable(drv_data, chip); |
d3cc71f7 | 1177 | } else |
42c78b2b MH |
1178 | gpio_free(chip->cs_gpio); |
1179 | ||
a5f6abd4 | 1180 | kfree(chip); |
ac01e97d DM |
1181 | /* prevent free 'chip' twice */ |
1182 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1183 | } |
1184 | ||
b9f139a7 | 1185 | static inline int bfin_spi_init_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1186 | { |
1187 | INIT_LIST_HEAD(&drv_data->queue); | |
1188 | spin_lock_init(&drv_data->lock); | |
1189 | ||
f4f50c3f | 1190 | drv_data->running = false; |
a5f6abd4 WB |
1191 | drv_data->busy = 0; |
1192 | ||
1193 | /* init transfer tasklet */ | |
1194 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1195 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1196 | |
1197 | /* init messages workqueue */ | |
138f97cd | 1198 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1199 | drv_data->workqueue = create_singlethread_workqueue( |
1200 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1201 | if (drv_data->workqueue == NULL) |
1202 | return -EBUSY; | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
b9f139a7 | 1207 | static inline int bfin_spi_start_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1208 | { |
1209 | unsigned long flags; | |
1210 | ||
1211 | spin_lock_irqsave(&drv_data->lock, flags); | |
1212 | ||
f4f50c3f | 1213 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1214 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1215 | return -EBUSY; | |
1216 | } | |
1217 | ||
f4f50c3f | 1218 | drv_data->running = true; |
a5f6abd4 WB |
1219 | drv_data->cur_msg = NULL; |
1220 | drv_data->cur_transfer = NULL; | |
1221 | drv_data->cur_chip = NULL; | |
1222 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1223 | ||
1224 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1225 | ||
1226 | return 0; | |
1227 | } | |
1228 | ||
b9f139a7 | 1229 | static inline int bfin_spi_stop_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1230 | { |
1231 | unsigned long flags; | |
1232 | unsigned limit = 500; | |
1233 | int status = 0; | |
1234 | ||
1235 | spin_lock_irqsave(&drv_data->lock, flags); | |
1236 | ||
1237 | /* | |
1238 | * This is a bit lame, but is optimized for the common execution path. | |
1239 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1240 | * execution path (pump_messages) would be required to call wake_up or | |
1241 | * friends on every SPI message. Do this instead | |
1242 | */ | |
f4f50c3f | 1243 | drv_data->running = false; |
a5f6abd4 WB |
1244 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { |
1245 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1246 | msleep(10); | |
1247 | spin_lock_irqsave(&drv_data->lock, flags); | |
1248 | } | |
1249 | ||
1250 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1251 | status = -EBUSY; | |
1252 | ||
1253 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1254 | ||
1255 | return status; | |
1256 | } | |
1257 | ||
b9f139a7 | 1258 | static inline int bfin_spi_destroy_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1259 | { |
1260 | int status; | |
1261 | ||
138f97cd | 1262 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1263 | if (status != 0) |
1264 | return status; | |
1265 | ||
1266 | destroy_workqueue(drv_data->workqueue); | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
138f97cd | 1271 | static int __init bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1272 | { |
1273 | struct device *dev = &pdev->dev; | |
1274 | struct bfin5xx_spi_master *platform_info; | |
1275 | struct spi_master *master; | |
2a045131 | 1276 | struct master_data *drv_data; |
a32c691d | 1277 | struct resource *res; |
a5f6abd4 WB |
1278 | int status = 0; |
1279 | ||
1280 | platform_info = dev->platform_data; | |
1281 | ||
1282 | /* Allocate master with space for drv_data */ | |
2a045131 | 1283 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1284 | if (!master) { |
1285 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1286 | return -ENOMEM; | |
1287 | } | |
131b17d4 | 1288 | |
a5f6abd4 WB |
1289 | drv_data = spi_master_get_devdata(master); |
1290 | drv_data->master = master; | |
1291 | drv_data->master_info = platform_info; | |
1292 | drv_data->pdev = pdev; | |
003d9226 | 1293 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1294 | |
e7db06b5 DB |
1295 | /* the spi->mode bits supported by this driver: */ |
1296 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
1297 | ||
a5f6abd4 WB |
1298 | master->bus_num = pdev->id; |
1299 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1300 | master->cleanup = bfin_spi_cleanup; |
1301 | master->setup = bfin_spi_setup; | |
1302 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1303 | |
a32c691d BW |
1304 | /* Find and map our resources */ |
1305 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1306 | if (res == NULL) { | |
1307 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1308 | status = -ENOENT; | |
1309 | goto out_error_get_res; | |
1310 | } | |
1311 | ||
74947b89 | 1312 | drv_data->regs_base = ioremap(res->start, resource_size(res)); |
f452126c | 1313 | if (drv_data->regs_base == NULL) { |
a32c691d BW |
1314 | dev_err(dev, "Cannot map IO\n"); |
1315 | status = -ENXIO; | |
1316 | goto out_error_ioremap; | |
1317 | } | |
1318 | ||
f6a6d966 YL |
1319 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1320 | if (res == NULL) { | |
a32c691d BW |
1321 | dev_err(dev, "No DMA channel specified\n"); |
1322 | status = -ENOENT; | |
f6a6d966 YL |
1323 | goto out_error_free_io; |
1324 | } | |
1325 | drv_data->dma_channel = res->start; | |
1326 | ||
1327 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1328 | if (drv_data->spi_irq < 0) { | |
1329 | dev_err(dev, "No spi pio irq specified\n"); | |
1330 | status = -ENOENT; | |
1331 | goto out_error_free_io; | |
a32c691d BW |
1332 | } |
1333 | ||
a5f6abd4 | 1334 | /* Initial and start queue */ |
138f97cd | 1335 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1336 | if (status != 0) { |
a32c691d | 1337 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1338 | goto out_error_queue_alloc; |
1339 | } | |
a32c691d | 1340 | |
138f97cd | 1341 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1342 | if (status != 0) { |
a32c691d | 1343 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1344 | goto out_error_queue_alloc; |
1345 | } | |
1346 | ||
f9e522ca VM |
1347 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1348 | if (status != 0) { | |
1349 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1350 | goto out_error_queue_alloc; | |
1351 | } | |
1352 | ||
bb8beecd WM |
1353 | /* Reset SPI registers. If these registers were used by the boot loader, |
1354 | * the sky may fall on your head if you enable the dma controller. | |
1355 | */ | |
1356 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1357 | write_FLAG(drv_data, 0xFF00); | |
1358 | ||
a5f6abd4 WB |
1359 | /* Register with the SPI framework */ |
1360 | platform_set_drvdata(pdev, drv_data); | |
1361 | status = spi_register_master(master); | |
1362 | if (status != 0) { | |
a32c691d | 1363 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1364 | goto out_error_queue_alloc; |
1365 | } | |
a32c691d | 1366 | |
f452126c | 1367 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1368 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1369 | drv_data->dma_channel); | |
a5f6abd4 WB |
1370 | return status; |
1371 | ||
cc2f81a6 | 1372 | out_error_queue_alloc: |
138f97cd | 1373 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1374 | out_error_free_io: |
bb90eb00 | 1375 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1376 | out_error_ioremap: |
1377 | out_error_get_res: | |
a5f6abd4 | 1378 | spi_master_put(master); |
cc2f81a6 | 1379 | |
a5f6abd4 WB |
1380 | return status; |
1381 | } | |
1382 | ||
1383 | /* stop hardware and remove the driver */ | |
138f97cd | 1384 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1385 | { |
b9f139a7 | 1386 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1387 | int status = 0; |
1388 | ||
1389 | if (!drv_data) | |
1390 | return 0; | |
1391 | ||
1392 | /* Remove the queue */ | |
138f97cd | 1393 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1394 | if (status != 0) |
1395 | return status; | |
1396 | ||
1397 | /* Disable the SSP at the peripheral and SOC level */ | |
1398 | bfin_spi_disable(drv_data); | |
1399 | ||
1400 | /* Release DMA */ | |
1401 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1402 | if (dma_channel_active(drv_data->dma_channel)) |
1403 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1404 | } |
1405 | ||
f6a6d966 YL |
1406 | if (drv_data->irq_requested) { |
1407 | free_irq(drv_data->spi_irq, drv_data); | |
1408 | drv_data->irq_requested = 0; | |
1409 | } | |
1410 | ||
a5f6abd4 WB |
1411 | /* Disconnect from the SPI framework */ |
1412 | spi_unregister_master(drv_data->master); | |
1413 | ||
003d9226 | 1414 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1415 | |
a5f6abd4 WB |
1416 | /* Prevent double remove */ |
1417 | platform_set_drvdata(pdev, NULL); | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | #ifdef CONFIG_PM | |
138f97cd | 1423 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 | 1424 | { |
b9f139a7 | 1425 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1426 | int status = 0; |
1427 | ||
138f97cd | 1428 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1429 | if (status != 0) |
1430 | return status; | |
1431 | ||
b052fd0a BS |
1432 | drv_data->ctrl_reg = read_CTRL(drv_data); |
1433 | drv_data->flag_reg = read_FLAG(drv_data); | |
1434 | ||
1435 | /* | |
1436 | * reset SPI_CTL and SPI_FLG registers | |
1437 | */ | |
1438 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1439 | write_FLAG(drv_data, 0xFF00); | |
a5f6abd4 WB |
1440 | |
1441 | return 0; | |
1442 | } | |
1443 | ||
138f97cd | 1444 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 | 1445 | { |
b9f139a7 | 1446 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1447 | int status = 0; |
1448 | ||
b052fd0a BS |
1449 | write_CTRL(drv_data, drv_data->ctrl_reg); |
1450 | write_FLAG(drv_data, drv_data->flag_reg); | |
a5f6abd4 WB |
1451 | |
1452 | /* Start the queue running */ | |
138f97cd | 1453 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1454 | if (status != 0) { |
1455 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1456 | return status; | |
1457 | } | |
1458 | ||
1459 | return 0; | |
1460 | } | |
1461 | #else | |
138f97cd MF |
1462 | #define bfin_spi_suspend NULL |
1463 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1464 | #endif /* CONFIG_PM */ |
1465 | ||
7e38c3c4 | 1466 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1467 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1468 | .driver = { |
a32c691d | 1469 | .name = DRV_NAME, |
88b40369 BW |
1470 | .owner = THIS_MODULE, |
1471 | }, | |
138f97cd MF |
1472 | .suspend = bfin_spi_suspend, |
1473 | .resume = bfin_spi_resume, | |
1474 | .remove = __devexit_p(bfin_spi_remove), | |
a5f6abd4 WB |
1475 | }; |
1476 | ||
138f97cd | 1477 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1478 | { |
138f97cd | 1479 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1480 | } |
138f97cd | 1481 | module_init(bfin_spi_init); |
a5f6abd4 | 1482 | |
138f97cd | 1483 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1484 | { |
138f97cd | 1485 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1486 | } |
138f97cd | 1487 | module_exit(bfin_spi_exit); |