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a5f6abd4 | 1 | /* |
131b17d4 BW |
2 | * File: drivers/spi/bfin5xx_spi.c |
3 | * Maintainer: | |
4 | * Bryan Wu <bryan.wu@analog.com> | |
5 | * Original Author: | |
6 | * Luke Yang (Analog Devices Inc.) | |
a5f6abd4 | 7 | * |
131b17d4 BW |
8 | * Created: March. 10th 2006 |
9 | * Description: SPI controller driver for Blackfin BF5xx | |
10 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
a5f6abd4 WB |
11 | * |
12 | * Modified: | |
13 | * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang) | |
14 | * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang) | |
131b17d4 | 15 | * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu) |
a32c691d BW |
16 | * July 30, 2007 add platfrom_resource interface to support multi-port |
17 | * SPI controller (Bryan Wu) | |
a5f6abd4 | 18 | * |
131b17d4 | 19 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 WB |
20 | * |
21 | * This program is free software ; you can redistribute it and/or modify | |
22 | * it under the terms of the GNU General Public License as published by | |
23 | * the Free Software Foundation ; either version 2, or (at your option) | |
24 | * any later version. | |
25 | * | |
26 | * This program is distributed in the hope that it will be useful, | |
27 | * but WITHOUT ANY WARRANTY ; without even the implied warranty of | |
28 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
29 | * GNU General Public License for more details. | |
30 | * | |
31 | * You should have received a copy of the GNU General Public License | |
32 | * along with this program ; see the file COPYING. | |
33 | * If not, write to the Free Software Foundation, | |
34 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
35 | */ | |
36 | ||
37 | #include <linux/init.h> | |
38 | #include <linux/module.h> | |
131b17d4 | 39 | #include <linux/delay.h> |
a5f6abd4 | 40 | #include <linux/device.h> |
131b17d4 | 41 | #include <linux/io.h> |
a5f6abd4 | 42 | #include <linux/ioport.h> |
131b17d4 | 43 | #include <linux/irq.h> |
a5f6abd4 WB |
44 | #include <linux/errno.h> |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/platform_device.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | #include <linux/spi/spi.h> | |
49 | #include <linux/workqueue.h> | |
a5f6abd4 | 50 | |
a5f6abd4 | 51 | #include <asm/dma.h> |
131b17d4 | 52 | #include <asm/portmux.h> |
a5f6abd4 WB |
53 | #include <asm/bfin5xx_spi.h> |
54 | ||
a32c691d BW |
55 | #define DRV_NAME "bfin-spi" |
56 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
57 | #define DRV_DESC "Blackfin BF5xx on-chip SPI Contoller Driver" | |
58 | #define DRV_VERSION "1.0" | |
59 | ||
60 | MODULE_AUTHOR(DRV_AUTHOR); | |
61 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
62 | MODULE_LICENSE("GPL"); |
63 | ||
bb90eb00 | 64 | #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0) |
a5f6abd4 | 65 | |
bb90eb00 BW |
66 | #define START_STATE ((void *)0) |
67 | #define RUNNING_STATE ((void *)1) | |
68 | #define DONE_STATE ((void *)2) | |
69 | #define ERROR_STATE ((void *)-1) | |
70 | #define QUEUE_RUNNING 0 | |
71 | #define QUEUE_STOPPED 1 | |
a5f6abd4 WB |
72 | |
73 | struct driver_data { | |
74 | /* Driver model hookup */ | |
75 | struct platform_device *pdev; | |
76 | ||
77 | /* SPI framework hookup */ | |
78 | struct spi_master *master; | |
79 | ||
bb90eb00 | 80 | /* Regs base of SPI controller */ |
f452126c | 81 | void __iomem *regs_base; |
bb90eb00 | 82 | |
a5f6abd4 WB |
83 | /* BFIN hookup */ |
84 | struct bfin5xx_spi_master *master_info; | |
85 | ||
86 | /* Driver message queue */ | |
87 | struct workqueue_struct *workqueue; | |
88 | struct work_struct pump_messages; | |
89 | spinlock_t lock; | |
90 | struct list_head queue; | |
91 | int busy; | |
92 | int run; | |
93 | ||
94 | /* Message Transfer pump */ | |
95 | struct tasklet_struct pump_transfers; | |
96 | ||
97 | /* Current message transfer state info */ | |
98 | struct spi_message *cur_msg; | |
99 | struct spi_transfer *cur_transfer; | |
100 | struct chip_data *cur_chip; | |
101 | size_t len_in_bytes; | |
102 | size_t len; | |
103 | void *tx; | |
104 | void *tx_end; | |
105 | void *rx; | |
106 | void *rx_end; | |
bb90eb00 BW |
107 | |
108 | /* DMA stuffs */ | |
109 | int dma_channel; | |
a5f6abd4 | 110 | int dma_mapped; |
bb90eb00 | 111 | int dma_requested; |
a5f6abd4 WB |
112 | dma_addr_t rx_dma; |
113 | dma_addr_t tx_dma; | |
bb90eb00 | 114 | |
a5f6abd4 WB |
115 | size_t rx_map_len; |
116 | size_t tx_map_len; | |
117 | u8 n_bytes; | |
fad91c89 | 118 | int cs_change; |
a5f6abd4 WB |
119 | void (*write) (struct driver_data *); |
120 | void (*read) (struct driver_data *); | |
121 | void (*duplex) (struct driver_data *); | |
122 | }; | |
123 | ||
124 | struct chip_data { | |
125 | u16 ctl_reg; | |
126 | u16 baud; | |
127 | u16 flag; | |
128 | ||
129 | u8 chip_select_num; | |
130 | u8 n_bytes; | |
88b40369 | 131 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
132 | u8 enable_dma; |
133 | u8 bits_per_word; /* 8 or 16 */ | |
134 | u8 cs_change_per_word; | |
62310e51 | 135 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
a5f6abd4 WB |
136 | void (*write) (struct driver_data *); |
137 | void (*read) (struct driver_data *); | |
138 | void (*duplex) (struct driver_data *); | |
139 | }; | |
140 | ||
bb90eb00 BW |
141 | #define DEFINE_SPI_REG(reg, off) \ |
142 | static inline u16 read_##reg(struct driver_data *drv_data) \ | |
143 | { return bfin_read16(drv_data->regs_base + off); } \ | |
144 | static inline void write_##reg(struct driver_data *drv_data, u16 v) \ | |
145 | { bfin_write16(drv_data->regs_base + off, v); } | |
146 | ||
147 | DEFINE_SPI_REG(CTRL, 0x00) | |
148 | DEFINE_SPI_REG(FLAG, 0x04) | |
149 | DEFINE_SPI_REG(STAT, 0x08) | |
150 | DEFINE_SPI_REG(TDBR, 0x0C) | |
151 | DEFINE_SPI_REG(RDBR, 0x10) | |
152 | DEFINE_SPI_REG(BAUD, 0x14) | |
153 | DEFINE_SPI_REG(SHAW, 0x18) | |
154 | ||
88b40369 | 155 | static void bfin_spi_enable(struct driver_data *drv_data) |
a5f6abd4 WB |
156 | { |
157 | u16 cr; | |
158 | ||
bb90eb00 BW |
159 | cr = read_CTRL(drv_data); |
160 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
161 | } |
162 | ||
88b40369 | 163 | static void bfin_spi_disable(struct driver_data *drv_data) |
a5f6abd4 WB |
164 | { |
165 | u16 cr; | |
166 | ||
bb90eb00 BW |
167 | cr = read_CTRL(drv_data); |
168 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
169 | } |
170 | ||
171 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
172 | static u16 hz_to_spi_baud(u32 speed_hz) | |
173 | { | |
174 | u_long sclk = get_sclk(); | |
175 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
176 | ||
177 | if ((sclk % (2 * speed_hz)) > 0) | |
178 | spi_baud++; | |
179 | ||
a5f6abd4 WB |
180 | return spi_baud; |
181 | } | |
182 | ||
183 | static int flush(struct driver_data *drv_data) | |
184 | { | |
185 | unsigned long limit = loops_per_jiffy << 1; | |
186 | ||
187 | /* wait for stop and clear stat */ | |
bb90eb00 | 188 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--) |
d8c05008 | 189 | cpu_relax(); |
a5f6abd4 | 190 | |
bb90eb00 | 191 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
192 | |
193 | return limit; | |
194 | } | |
195 | ||
fad91c89 | 196 | /* Chip select operation functions for cs_change flag */ |
bb90eb00 | 197 | static void cs_active(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 198 | { |
bb90eb00 | 199 | u16 flag = read_FLAG(drv_data); |
fad91c89 BW |
200 | |
201 | flag |= chip->flag; | |
202 | flag &= ~(chip->flag << 8); | |
203 | ||
bb90eb00 | 204 | write_FLAG(drv_data, flag); |
fad91c89 BW |
205 | } |
206 | ||
bb90eb00 | 207 | static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 208 | { |
bb90eb00 | 209 | u16 flag = read_FLAG(drv_data); |
fad91c89 BW |
210 | |
211 | flag |= (chip->flag << 8); | |
212 | ||
bb90eb00 | 213 | write_FLAG(drv_data, flag); |
62310e51 BW |
214 | |
215 | /* Move delay here for consistency */ | |
216 | if (chip->cs_chg_udelay) | |
217 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
218 | } |
219 | ||
7c4ef094 | 220 | #define MAX_SPI_SSEL 7 |
5fec5b5a | 221 | |
a5f6abd4 | 222 | /* stop controller and re-config current chip*/ |
5fec5b5a | 223 | static int restore_state(struct driver_data *drv_data) |
a5f6abd4 WB |
224 | { |
225 | struct chip_data *chip = drv_data->cur_chip; | |
5fec5b5a | 226 | int ret = 0; |
12e17c42 | 227 | |
a5f6abd4 | 228 | /* Clear status and disable clock */ |
bb90eb00 | 229 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 230 | bfin_spi_disable(drv_data); |
88b40369 | 231 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 232 | |
5fec5b5a | 233 | /* Load the registers */ |
bb90eb00 | 234 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
235 | chip->ctl_reg &= (~BIT_CTL_TIMOD); |
236 | chip->ctl_reg |= (chip->width << 8); | |
bb90eb00 | 237 | write_CTRL(drv_data, chip->ctl_reg); |
cc487e73 SZ |
238 | |
239 | bfin_spi_enable(drv_data); | |
07612e5f | 240 | cs_active(drv_data, chip); |
5fec5b5a | 241 | |
5fec5b5a BW |
242 | if (ret) |
243 | dev_dbg(&drv_data->pdev->dev, | |
244 | ": request chip select number %d failed\n", | |
245 | chip->chip_select_num); | |
246 | ||
247 | return ret; | |
a5f6abd4 WB |
248 | } |
249 | ||
250 | /* used to kick off transfer in rx mode */ | |
bb90eb00 | 251 | static unsigned short dummy_read(struct driver_data *drv_data) |
a5f6abd4 WB |
252 | { |
253 | unsigned short tmp; | |
bb90eb00 | 254 | tmp = read_RDBR(drv_data); |
a5f6abd4 WB |
255 | return tmp; |
256 | } | |
257 | ||
258 | static void null_writer(struct driver_data *drv_data) | |
259 | { | |
260 | u8 n_bytes = drv_data->n_bytes; | |
261 | ||
262 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 BW |
263 | write_TDBR(drv_data, 0); |
264 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 265 | cpu_relax(); |
a5f6abd4 WB |
266 | drv_data->tx += n_bytes; |
267 | } | |
268 | } | |
269 | ||
270 | static void null_reader(struct driver_data *drv_data) | |
271 | { | |
272 | u8 n_bytes = drv_data->n_bytes; | |
bb90eb00 | 273 | dummy_read(drv_data); |
a5f6abd4 WB |
274 | |
275 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 276 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 277 | cpu_relax(); |
bb90eb00 | 278 | dummy_read(drv_data); |
a5f6abd4 WB |
279 | drv_data->rx += n_bytes; |
280 | } | |
281 | } | |
282 | ||
283 | static void u8_writer(struct driver_data *drv_data) | |
284 | { | |
131b17d4 | 285 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 286 | "cr8-s is 0x%x\n", read_STAT(drv_data)); |
cc487e73 | 287 | |
3f479a65 | 288 | /* poll for SPI completion before start */ |
bb90eb00 | 289 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 290 | cpu_relax(); |
3f479a65 | 291 | |
a5f6abd4 | 292 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 BW |
293 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
294 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 295 | cpu_relax(); |
a5f6abd4 WB |
296 | ++drv_data->tx; |
297 | } | |
a5f6abd4 WB |
298 | } |
299 | ||
300 | static void u8_cs_chg_writer(struct driver_data *drv_data) | |
301 | { | |
302 | struct chip_data *chip = drv_data->cur_chip; | |
303 | ||
3f479a65 | 304 | /* poll for SPI completion before start */ |
bb90eb00 | 305 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 306 | cpu_relax(); |
3f479a65 | 307 | |
a5f6abd4 | 308 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 309 | cs_active(drv_data, chip); |
a5f6abd4 | 310 | |
bb90eb00 BW |
311 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
312 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 313 | cpu_relax(); |
62310e51 | 314 | |
bb90eb00 | 315 | cs_deactive(drv_data, chip); |
5fec5b5a | 316 | |
a5f6abd4 WB |
317 | ++drv_data->tx; |
318 | } | |
a5f6abd4 WB |
319 | } |
320 | ||
321 | static void u8_reader(struct driver_data *drv_data) | |
322 | { | |
131b17d4 | 323 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 324 | "cr-8 is 0x%x\n", read_STAT(drv_data)); |
a5f6abd4 | 325 | |
3f479a65 | 326 | /* poll for SPI completion before start */ |
bb90eb00 | 327 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 328 | cpu_relax(); |
3f479a65 | 329 | |
a5f6abd4 | 330 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 331 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 332 | |
bb90eb00 | 333 | dummy_read(drv_data); |
cc487e73 | 334 | |
a5f6abd4 | 335 | while (drv_data->rx < drv_data->rx_end - 1) { |
bb90eb00 | 336 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 337 | cpu_relax(); |
bb90eb00 | 338 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
339 | ++drv_data->rx; |
340 | } | |
341 | ||
bb90eb00 | 342 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 343 | cpu_relax(); |
bb90eb00 | 344 | *(u8 *) (drv_data->rx) = read_SHAW(drv_data); |
a5f6abd4 WB |
345 | ++drv_data->rx; |
346 | } | |
347 | ||
348 | static void u8_cs_chg_reader(struct driver_data *drv_data) | |
349 | { | |
350 | struct chip_data *chip = drv_data->cur_chip; | |
351 | ||
3f479a65 | 352 | /* poll for SPI completion before start */ |
bb90eb00 | 353 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 354 | cpu_relax(); |
3f479a65 | 355 | |
cc487e73 | 356 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 357 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 358 | |
bb90eb00 BW |
359 | cs_active(drv_data, chip); |
360 | dummy_read(drv_data); | |
cc487e73 SZ |
361 | |
362 | while (drv_data->rx < drv_data->rx_end - 1) { | |
bb90eb00 | 363 | cs_deactive(drv_data, chip); |
5fec5b5a | 364 | |
bb90eb00 | 365 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 366 | cpu_relax(); |
bb90eb00 BW |
367 | cs_active(drv_data, chip); |
368 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
a5f6abd4 WB |
369 | ++drv_data->rx; |
370 | } | |
bb90eb00 | 371 | cs_deactive(drv_data, chip); |
5fec5b5a | 372 | |
bb90eb00 | 373 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 374 | cpu_relax(); |
bb90eb00 | 375 | *(u8 *) (drv_data->rx) = read_SHAW(drv_data); |
cc487e73 | 376 | ++drv_data->rx; |
a5f6abd4 WB |
377 | } |
378 | ||
379 | static void u8_duplex(struct driver_data *drv_data) | |
380 | { | |
3f479a65 | 381 | /* poll for SPI completion before start */ |
bb90eb00 | 382 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 383 | cpu_relax(); |
3f479a65 | 384 | |
a5f6abd4 WB |
385 | /* in duplex mode, clk is triggered by writing of TDBR */ |
386 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 BW |
387 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
388 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 389 | cpu_relax(); |
bb90eb00 | 390 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 391 | cpu_relax(); |
bb90eb00 | 392 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
393 | ++drv_data->rx; |
394 | ++drv_data->tx; | |
395 | } | |
396 | } | |
397 | ||
398 | static void u8_cs_chg_duplex(struct driver_data *drv_data) | |
399 | { | |
400 | struct chip_data *chip = drv_data->cur_chip; | |
401 | ||
3f479a65 | 402 | /* poll for SPI completion before start */ |
bb90eb00 | 403 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 404 | cpu_relax(); |
3f479a65 | 405 | |
a5f6abd4 | 406 | while (drv_data->rx < drv_data->rx_end) { |
bb90eb00 | 407 | cs_active(drv_data, chip); |
5fec5b5a | 408 | |
bb90eb00 BW |
409 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
410 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 411 | cpu_relax(); |
bb90eb00 | 412 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 413 | cpu_relax(); |
bb90eb00 | 414 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
62310e51 | 415 | |
bb90eb00 | 416 | cs_deactive(drv_data, chip); |
5fec5b5a | 417 | |
a5f6abd4 WB |
418 | ++drv_data->rx; |
419 | ++drv_data->tx; | |
420 | } | |
a5f6abd4 WB |
421 | } |
422 | ||
423 | static void u16_writer(struct driver_data *drv_data) | |
424 | { | |
131b17d4 | 425 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 426 | "cr16 is 0x%x\n", read_STAT(drv_data)); |
88b40369 | 427 | |
3f479a65 | 428 | /* poll for SPI completion before start */ |
bb90eb00 | 429 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 430 | cpu_relax(); |
3f479a65 | 431 | |
a5f6abd4 | 432 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 BW |
433 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
434 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 435 | cpu_relax(); |
a5f6abd4 WB |
436 | drv_data->tx += 2; |
437 | } | |
a5f6abd4 WB |
438 | } |
439 | ||
440 | static void u16_cs_chg_writer(struct driver_data *drv_data) | |
441 | { | |
442 | struct chip_data *chip = drv_data->cur_chip; | |
443 | ||
3f479a65 | 444 | /* poll for SPI completion before start */ |
bb90eb00 | 445 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 446 | cpu_relax(); |
3f479a65 | 447 | |
a5f6abd4 | 448 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 449 | cs_active(drv_data, chip); |
a5f6abd4 | 450 | |
bb90eb00 BW |
451 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
452 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 453 | cpu_relax(); |
62310e51 | 454 | |
bb90eb00 | 455 | cs_deactive(drv_data, chip); |
5fec5b5a | 456 | |
a5f6abd4 WB |
457 | drv_data->tx += 2; |
458 | } | |
a5f6abd4 WB |
459 | } |
460 | ||
461 | static void u16_reader(struct driver_data *drv_data) | |
462 | { | |
88b40369 | 463 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 464 | "cr-16 is 0x%x\n", read_STAT(drv_data)); |
cc487e73 | 465 | |
3f479a65 | 466 | /* poll for SPI completion before start */ |
bb90eb00 | 467 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 468 | cpu_relax(); |
3f479a65 | 469 | |
cc487e73 | 470 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 471 | write_TDBR(drv_data, 0xFFFF); |
cc487e73 | 472 | |
bb90eb00 | 473 | dummy_read(drv_data); |
a5f6abd4 WB |
474 | |
475 | while (drv_data->rx < (drv_data->rx_end - 2)) { | |
bb90eb00 | 476 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 477 | cpu_relax(); |
bb90eb00 | 478 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
479 | drv_data->rx += 2; |
480 | } | |
481 | ||
bb90eb00 | 482 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 483 | cpu_relax(); |
bb90eb00 | 484 | *(u16 *) (drv_data->rx) = read_SHAW(drv_data); |
a5f6abd4 WB |
485 | drv_data->rx += 2; |
486 | } | |
487 | ||
488 | static void u16_cs_chg_reader(struct driver_data *drv_data) | |
489 | { | |
490 | struct chip_data *chip = drv_data->cur_chip; | |
491 | ||
3f479a65 | 492 | /* poll for SPI completion before start */ |
bb90eb00 | 493 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 494 | cpu_relax(); |
3f479a65 | 495 | |
cc487e73 | 496 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 497 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 498 | |
bb90eb00 BW |
499 | cs_active(drv_data, chip); |
500 | dummy_read(drv_data); | |
cc487e73 | 501 | |
c3061abb | 502 | while (drv_data->rx < drv_data->rx_end - 2) { |
bb90eb00 | 503 | cs_deactive(drv_data, chip); |
5fec5b5a | 504 | |
bb90eb00 | 505 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 506 | cpu_relax(); |
bb90eb00 BW |
507 | cs_active(drv_data, chip); |
508 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
a5f6abd4 WB |
509 | drv_data->rx += 2; |
510 | } | |
bb90eb00 | 511 | cs_deactive(drv_data, chip); |
cc487e73 | 512 | |
bb90eb00 | 513 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 514 | cpu_relax(); |
bb90eb00 | 515 | *(u16 *) (drv_data->rx) = read_SHAW(drv_data); |
cc487e73 | 516 | drv_data->rx += 2; |
a5f6abd4 WB |
517 | } |
518 | ||
519 | static void u16_duplex(struct driver_data *drv_data) | |
520 | { | |
3f479a65 | 521 | /* poll for SPI completion before start */ |
bb90eb00 | 522 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 523 | cpu_relax(); |
3f479a65 | 524 | |
a5f6abd4 WB |
525 | /* in duplex mode, clk is triggered by writing of TDBR */ |
526 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 BW |
527 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
528 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 529 | cpu_relax(); |
bb90eb00 | 530 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 531 | cpu_relax(); |
bb90eb00 | 532 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
533 | drv_data->rx += 2; |
534 | drv_data->tx += 2; | |
535 | } | |
536 | } | |
537 | ||
538 | static void u16_cs_chg_duplex(struct driver_data *drv_data) | |
539 | { | |
540 | struct chip_data *chip = drv_data->cur_chip; | |
541 | ||
3f479a65 | 542 | /* poll for SPI completion before start */ |
bb90eb00 | 543 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 544 | cpu_relax(); |
3f479a65 | 545 | |
a5f6abd4 | 546 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 547 | cs_active(drv_data, chip); |
a5f6abd4 | 548 | |
bb90eb00 BW |
549 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
550 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 551 | cpu_relax(); |
bb90eb00 | 552 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 553 | cpu_relax(); |
bb90eb00 | 554 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
62310e51 | 555 | |
bb90eb00 | 556 | cs_deactive(drv_data, chip); |
5fec5b5a | 557 | |
a5f6abd4 WB |
558 | drv_data->rx += 2; |
559 | drv_data->tx += 2; | |
560 | } | |
a5f6abd4 WB |
561 | } |
562 | ||
563 | /* test if ther is more transfer to be done */ | |
564 | static void *next_transfer(struct driver_data *drv_data) | |
565 | { | |
566 | struct spi_message *msg = drv_data->cur_msg; | |
567 | struct spi_transfer *trans = drv_data->cur_transfer; | |
568 | ||
569 | /* Move to next transfer */ | |
570 | if (trans->transfer_list.next != &msg->transfers) { | |
571 | drv_data->cur_transfer = | |
572 | list_entry(trans->transfer_list.next, | |
573 | struct spi_transfer, transfer_list); | |
574 | return RUNNING_STATE; | |
575 | } else | |
576 | return DONE_STATE; | |
577 | } | |
578 | ||
579 | /* | |
580 | * caller already set message->status; | |
581 | * dma and pio irqs are blocked give finished message back | |
582 | */ | |
583 | static void giveback(struct driver_data *drv_data) | |
584 | { | |
fad91c89 | 585 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
586 | struct spi_transfer *last_transfer; |
587 | unsigned long flags; | |
588 | struct spi_message *msg; | |
589 | ||
590 | spin_lock_irqsave(&drv_data->lock, flags); | |
591 | msg = drv_data->cur_msg; | |
592 | drv_data->cur_msg = NULL; | |
593 | drv_data->cur_transfer = NULL; | |
594 | drv_data->cur_chip = NULL; | |
595 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
596 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
597 | ||
598 | last_transfer = list_entry(msg->transfers.prev, | |
599 | struct spi_transfer, transfer_list); | |
600 | ||
601 | msg->state = NULL; | |
602 | ||
603 | /* disable chip select signal. And not stop spi in autobuffer mode */ | |
604 | if (drv_data->tx_dma != 0xFFFF) { | |
bb90eb00 | 605 | cs_deactive(drv_data, chip); |
a5f6abd4 WB |
606 | bfin_spi_disable(drv_data); |
607 | } | |
608 | ||
fad91c89 | 609 | if (!drv_data->cs_change) |
bb90eb00 | 610 | cs_deactive(drv_data, chip); |
fad91c89 | 611 | |
a5f6abd4 WB |
612 | if (msg->complete) |
613 | msg->complete(msg->context); | |
614 | } | |
615 | ||
88b40369 | 616 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 WB |
617 | { |
618 | struct driver_data *drv_data = (struct driver_data *)dev_id; | |
fad91c89 | 619 | struct chip_data *chip = drv_data->cur_chip; |
bb90eb00 | 620 | struct spi_message *msg = drv_data->cur_msg; |
a5f6abd4 | 621 | |
88b40369 | 622 | dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); |
bb90eb00 | 623 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 | 624 | |
d6fe89b0 | 625 | /* Wait for DMA to complete */ |
bb90eb00 | 626 | while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN) |
d8c05008 | 627 | cpu_relax(); |
d6fe89b0 | 628 | |
a5f6abd4 | 629 | /* |
d6fe89b0 BW |
630 | * wait for the last transaction shifted out. HRM states: |
631 | * at this point there may still be data in the SPI DMA FIFO waiting | |
632 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
633 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
634 | */ |
635 | if (drv_data->tx != NULL) { | |
bb90eb00 BW |
636 | while ((read_STAT(drv_data) & TXS) || |
637 | (read_STAT(drv_data) & TXS)) | |
d8c05008 | 638 | cpu_relax(); |
a5f6abd4 WB |
639 | } |
640 | ||
bb90eb00 | 641 | while (!(read_STAT(drv_data) & SPIF)) |
d8c05008 | 642 | cpu_relax(); |
a5f6abd4 | 643 | |
a5f6abd4 WB |
644 | msg->actual_length += drv_data->len_in_bytes; |
645 | ||
fad91c89 | 646 | if (drv_data->cs_change) |
bb90eb00 | 647 | cs_deactive(drv_data, chip); |
fad91c89 | 648 | |
a5f6abd4 WB |
649 | /* Move to next transfer */ |
650 | msg->state = next_transfer(drv_data); | |
651 | ||
652 | /* Schedule transfer tasklet */ | |
653 | tasklet_schedule(&drv_data->pump_transfers); | |
654 | ||
655 | /* free the irq handler before next transfer */ | |
88b40369 BW |
656 | dev_dbg(&drv_data->pdev->dev, |
657 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
658 | drv_data->dma_channel); |
659 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
660 | |
661 | return IRQ_HANDLED; | |
662 | } | |
663 | ||
664 | static void pump_transfers(unsigned long data) | |
665 | { | |
666 | struct driver_data *drv_data = (struct driver_data *)data; | |
667 | struct spi_message *message = NULL; | |
668 | struct spi_transfer *transfer = NULL; | |
669 | struct spi_transfer *previous = NULL; | |
670 | struct chip_data *chip = NULL; | |
88b40369 BW |
671 | u8 width; |
672 | u16 cr, dma_width, dma_config; | |
a5f6abd4 WB |
673 | u32 tranf_success = 1; |
674 | ||
675 | /* Get current state information */ | |
676 | message = drv_data->cur_msg; | |
677 | transfer = drv_data->cur_transfer; | |
678 | chip = drv_data->cur_chip; | |
a5f6abd4 WB |
679 | /* |
680 | * if msg is error or done, report it back using complete() callback | |
681 | */ | |
682 | ||
683 | /* Handle for abort */ | |
684 | if (message->state == ERROR_STATE) { | |
685 | message->status = -EIO; | |
686 | giveback(drv_data); | |
687 | return; | |
688 | } | |
689 | ||
690 | /* Handle end of message */ | |
691 | if (message->state == DONE_STATE) { | |
692 | message->status = 0; | |
693 | giveback(drv_data); | |
694 | return; | |
695 | } | |
696 | ||
697 | /* Delay if requested at end of transfer */ | |
698 | if (message->state == RUNNING_STATE) { | |
699 | previous = list_entry(transfer->transfer_list.prev, | |
700 | struct spi_transfer, transfer_list); | |
701 | if (previous->delay_usecs) | |
702 | udelay(previous->delay_usecs); | |
703 | } | |
704 | ||
705 | /* Setup the transfer state based on the type of transfer */ | |
706 | if (flush(drv_data) == 0) { | |
707 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
708 | message->status = -EIO; | |
709 | giveback(drv_data); | |
710 | return; | |
711 | } | |
712 | ||
713 | if (transfer->tx_buf != NULL) { | |
714 | drv_data->tx = (void *)transfer->tx_buf; | |
715 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
716 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
717 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
718 | } else { |
719 | drv_data->tx = NULL; | |
720 | } | |
721 | ||
722 | if (transfer->rx_buf != NULL) { | |
723 | drv_data->rx = transfer->rx_buf; | |
724 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
725 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
726 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
727 | } else { |
728 | drv_data->rx = NULL; | |
729 | } | |
730 | ||
731 | drv_data->rx_dma = transfer->rx_dma; | |
732 | drv_data->tx_dma = transfer->tx_dma; | |
733 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 734 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 WB |
735 | |
736 | width = chip->width; | |
737 | if (width == CFG_SPI_WORDSIZE16) { | |
738 | drv_data->len = (transfer->len) >> 1; | |
739 | } else { | |
740 | drv_data->len = transfer->len; | |
741 | } | |
742 | drv_data->write = drv_data->tx ? chip->write : null_writer; | |
743 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
744 | drv_data->duplex = chip->duplex ? chip->duplex : null_writer; | |
131b17d4 BW |
745 | dev_dbg(&drv_data->pdev->dev, "transfer: ", |
746 | "drv_data->write is %p, chip->write is %p, null_wr is %p\n", | |
747 | drv_data->write, chip->write, null_writer); | |
a5f6abd4 WB |
748 | |
749 | /* speed and width has been set on per message */ | |
750 | message->state = RUNNING_STATE; | |
751 | dma_config = 0; | |
752 | ||
bb90eb00 BW |
753 | write_STAT(drv_data, BIT_STAT_CLR); |
754 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
755 | cs_active(drv_data, chip); | |
a5f6abd4 | 756 | |
88b40369 BW |
757 | dev_dbg(&drv_data->pdev->dev, |
758 | "now pumping a transfer: width is %d, len is %d\n", | |
759 | width, transfer->len); | |
a5f6abd4 WB |
760 | |
761 | /* | |
762 | * Try to map dma buffer and do a dma transfer if | |
763 | * successful use different way to r/w according to | |
764 | * drv_data->cur_chip->enable_dma | |
765 | */ | |
766 | if (drv_data->cur_chip->enable_dma && drv_data->len > 6) { | |
767 | ||
bb90eb00 BW |
768 | disable_dma(drv_data->dma_channel); |
769 | clear_dma_irqstat(drv_data->dma_channel); | |
07612e5f | 770 | bfin_spi_disable(drv_data); |
a5f6abd4 WB |
771 | |
772 | /* config dma channel */ | |
88b40369 | 773 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
a5f6abd4 | 774 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 BW |
775 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
776 | set_dma_x_modify(drv_data->dma_channel, 2); | |
a5f6abd4 WB |
777 | dma_width = WDSIZE_16; |
778 | } else { | |
bb90eb00 BW |
779 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
780 | set_dma_x_modify(drv_data->dma_channel, 1); | |
a5f6abd4 WB |
781 | dma_width = WDSIZE_8; |
782 | } | |
783 | ||
3f479a65 | 784 | /* poll for SPI completion before start */ |
bb90eb00 | 785 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 786 | cpu_relax(); |
3f479a65 | 787 | |
a5f6abd4 WB |
788 | /* dirty hack for autobuffer DMA mode */ |
789 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
790 | dev_dbg(&drv_data->pdev->dev, |
791 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
792 | |
793 | /* no irq in autobuffer mode */ | |
794 | dma_config = | |
795 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
796 | set_dma_config(drv_data->dma_channel, dma_config); |
797 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 798 | (unsigned long)drv_data->tx); |
bb90eb00 | 799 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 800 | |
07612e5f SZ |
801 | /* start SPI transfer */ |
802 | write_CTRL(drv_data, | |
803 | (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE)); | |
804 | ||
805 | /* just return here, there can only be one transfer | |
806 | * in this mode | |
807 | */ | |
a5f6abd4 WB |
808 | message->status = 0; |
809 | giveback(drv_data); | |
810 | return; | |
811 | } | |
812 | ||
813 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
814 | if (drv_data->rx != NULL) { | |
815 | /* set transfer mode, and enable SPI */ | |
88b40369 | 816 | dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n"); |
a5f6abd4 | 817 | |
a5f6abd4 | 818 | /* clear tx reg soformer data is not shifted out */ |
bb90eb00 | 819 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 820 | |
bb90eb00 | 821 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 WB |
822 | |
823 | /* start dma */ | |
bb90eb00 | 824 | dma_enable_irq(drv_data->dma_channel); |
a5f6abd4 | 825 | dma_config = (WNR | RESTART | dma_width | DI_EN); |
bb90eb00 BW |
826 | set_dma_config(drv_data->dma_channel, dma_config); |
827 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 828 | (unsigned long)drv_data->rx); |
bb90eb00 | 829 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 830 | |
07612e5f SZ |
831 | /* start SPI transfer */ |
832 | write_CTRL(drv_data, | |
833 | (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE)); | |
834 | ||
a5f6abd4 | 835 | } else if (drv_data->tx != NULL) { |
88b40369 | 836 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 WB |
837 | |
838 | /* start dma */ | |
bb90eb00 | 839 | dma_enable_irq(drv_data->dma_channel); |
a5f6abd4 | 840 | dma_config = (RESTART | dma_width | DI_EN); |
bb90eb00 BW |
841 | set_dma_config(drv_data->dma_channel, dma_config); |
842 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 843 | (unsigned long)drv_data->tx); |
bb90eb00 | 844 | enable_dma(drv_data->dma_channel); |
07612e5f SZ |
845 | |
846 | /* start SPI transfer */ | |
847 | write_CTRL(drv_data, | |
848 | (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
849 | } |
850 | } else { | |
851 | /* IO mode write then read */ | |
88b40369 | 852 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
a5f6abd4 | 853 | |
a5f6abd4 WB |
854 | if (drv_data->tx != NULL && drv_data->rx != NULL) { |
855 | /* full duplex mode */ | |
856 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
857 | (drv_data->rx_end - drv_data->rx)); | |
88b40369 BW |
858 | dev_dbg(&drv_data->pdev->dev, |
859 | "IO duplex: cr is 0x%x\n", cr); | |
a5f6abd4 | 860 | |
cc487e73 | 861 | /* set SPI transfer mode */ |
bb90eb00 | 862 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
a5f6abd4 WB |
863 | |
864 | drv_data->duplex(drv_data); | |
865 | ||
866 | if (drv_data->tx != drv_data->tx_end) | |
867 | tranf_success = 0; | |
868 | } else if (drv_data->tx != NULL) { | |
869 | /* write only half duplex */ | |
131b17d4 | 870 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 871 | "IO write: cr is 0x%x\n", cr); |
a5f6abd4 | 872 | |
cc487e73 | 873 | /* set SPI transfer mode */ |
bb90eb00 | 874 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
a5f6abd4 WB |
875 | |
876 | drv_data->write(drv_data); | |
877 | ||
878 | if (drv_data->tx != drv_data->tx_end) | |
879 | tranf_success = 0; | |
880 | } else if (drv_data->rx != NULL) { | |
881 | /* read only half duplex */ | |
131b17d4 | 882 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 883 | "IO read: cr is 0x%x\n", cr); |
a5f6abd4 | 884 | |
cc487e73 | 885 | /* set SPI transfer mode */ |
bb90eb00 | 886 | write_CTRL(drv_data, (cr | CFG_SPI_READ)); |
a5f6abd4 WB |
887 | |
888 | drv_data->read(drv_data); | |
889 | if (drv_data->rx != drv_data->rx_end) | |
890 | tranf_success = 0; | |
891 | } | |
892 | ||
893 | if (!tranf_success) { | |
131b17d4 | 894 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 895 | "IO write error!\n"); |
a5f6abd4 WB |
896 | message->state = ERROR_STATE; |
897 | } else { | |
898 | /* Update total byte transfered */ | |
899 | message->actual_length += drv_data->len; | |
900 | ||
901 | /* Move to next transfer of this msg */ | |
902 | message->state = next_transfer(drv_data); | |
903 | } | |
904 | ||
905 | /* Schedule next transfer tasklet */ | |
906 | tasklet_schedule(&drv_data->pump_transfers); | |
907 | ||
908 | } | |
909 | } | |
910 | ||
911 | /* pop a msg from queue and kick off real transfer */ | |
912 | static void pump_messages(struct work_struct *work) | |
913 | { | |
131b17d4 | 914 | struct driver_data *drv_data; |
a5f6abd4 WB |
915 | unsigned long flags; |
916 | ||
131b17d4 BW |
917 | drv_data = container_of(work, struct driver_data, pump_messages); |
918 | ||
a5f6abd4 WB |
919 | /* Lock queue and check for queue work */ |
920 | spin_lock_irqsave(&drv_data->lock, flags); | |
921 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
922 | /* pumper kicked off but no work to do */ | |
923 | drv_data->busy = 0; | |
924 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
925 | return; | |
926 | } | |
927 | ||
928 | /* Make sure we are not already running a message */ | |
929 | if (drv_data->cur_msg) { | |
930 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
931 | return; | |
932 | } | |
933 | ||
934 | /* Extract head of queue */ | |
935 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
936 | struct spi_message, queue); | |
5fec5b5a BW |
937 | |
938 | /* Setup the SSP using the per chip configuration */ | |
939 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
940 | if (restore_state(drv_data)) { | |
941 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
942 | return; | |
943 | }; | |
944 | ||
a5f6abd4 WB |
945 | list_del_init(&drv_data->cur_msg->queue); |
946 | ||
947 | /* Initial message state */ | |
948 | drv_data->cur_msg->state = START_STATE; | |
949 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
950 | struct spi_transfer, transfer_list); | |
951 | ||
5fec5b5a BW |
952 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
953 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
954 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
955 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
956 | |
957 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
958 | "the first transfer len is %d\n", |
959 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
960 | |
961 | /* Mark as busy and launch transfers */ | |
962 | tasklet_schedule(&drv_data->pump_transfers); | |
963 | ||
964 | drv_data->busy = 1; | |
965 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
966 | } | |
967 | ||
968 | /* | |
969 | * got a msg to transfer, queue it in drv_data->queue. | |
970 | * And kick off message pumper | |
971 | */ | |
972 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
973 | { | |
974 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
975 | unsigned long flags; | |
976 | ||
977 | spin_lock_irqsave(&drv_data->lock, flags); | |
978 | ||
979 | if (drv_data->run == QUEUE_STOPPED) { | |
980 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
981 | return -ESHUTDOWN; | |
982 | } | |
983 | ||
984 | msg->actual_length = 0; | |
985 | msg->status = -EINPROGRESS; | |
986 | msg->state = START_STATE; | |
987 | ||
88b40369 | 988 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
989 | list_add_tail(&msg->queue, &drv_data->queue); |
990 | ||
991 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
992 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
993 | ||
994 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
12e17c42 SZ |
999 | #define MAX_SPI_SSEL 7 |
1000 | ||
1001 | static u16 ssel[3][MAX_SPI_SSEL] = { | |
1002 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, | |
1003 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
1004 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
1005 | ||
1006 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
1007 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
1008 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
1009 | ||
1010 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
1011 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
1012 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
1013 | }; | |
1014 | ||
a5f6abd4 WB |
1015 | /* first setup for new devices */ |
1016 | static int setup(struct spi_device *spi) | |
1017 | { | |
1018 | struct bfin5xx_spi_chip *chip_info = NULL; | |
1019 | struct chip_data *chip; | |
1020 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1021 | u8 spi_flg; | |
1022 | ||
1023 | /* Abort device setup if requested features are not supported */ | |
1024 | if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) { | |
1025 | dev_err(&spi->dev, "requested mode not fully supported\n"); | |
1026 | return -EINVAL; | |
1027 | } | |
1028 | ||
1029 | /* Zero (the default) here means 8 bits */ | |
1030 | if (!spi->bits_per_word) | |
1031 | spi->bits_per_word = 8; | |
1032 | ||
1033 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) | |
1034 | return -EINVAL; | |
1035 | ||
1036 | /* Only alloc (or use chip_info) on first setup */ | |
1037 | chip = spi_get_ctldata(spi); | |
1038 | if (chip == NULL) { | |
1039 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1040 | if (!chip) | |
1041 | return -ENOMEM; | |
1042 | ||
1043 | chip->enable_dma = 0; | |
1044 | chip_info = spi->controller_data; | |
1045 | } | |
1046 | ||
1047 | /* chip_info isn't always needed */ | |
1048 | if (chip_info) { | |
2ed35516 MF |
1049 | /* Make sure people stop trying to set fields via ctl_reg |
1050 | * when they should actually be using common SPI framework. | |
1051 | * Currently we let through: WOM EMISO PSSE GM SZ TIMOD. | |
1052 | * Not sure if a user actually needs/uses any of these, | |
1053 | * but let's assume (for now) they do. | |
1054 | */ | |
1055 | if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) { | |
1056 | dev_err(&spi->dev, "do not set bits in ctl_reg " | |
1057 | "that the SPI framework manages\n"); | |
1058 | return -EINVAL; | |
1059 | } | |
1060 | ||
a5f6abd4 WB |
1061 | chip->enable_dma = chip_info->enable_dma != 0 |
1062 | && drv_data->master_info->enable_dma; | |
1063 | chip->ctl_reg = chip_info->ctl_reg; | |
1064 | chip->bits_per_word = chip_info->bits_per_word; | |
1065 | chip->cs_change_per_word = chip_info->cs_change_per_word; | |
1066 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
1067 | } | |
1068 | ||
1069 | /* translate common spi framework into our register */ | |
1070 | if (spi->mode & SPI_CPOL) | |
1071 | chip->ctl_reg |= CPOL; | |
1072 | if (spi->mode & SPI_CPHA) | |
1073 | chip->ctl_reg |= CPHA; | |
1074 | if (spi->mode & SPI_LSB_FIRST) | |
1075 | chip->ctl_reg |= LSBF; | |
1076 | /* we dont support running in slave mode (yet?) */ | |
1077 | chip->ctl_reg |= MSTR; | |
1078 | ||
1079 | /* | |
1080 | * if any one SPI chip is registered and wants DMA, request the | |
1081 | * DMA channel for it | |
1082 | */ | |
bb90eb00 | 1083 | if (chip->enable_dma && !drv_data->dma_requested) { |
a5f6abd4 | 1084 | /* register dma irq handler */ |
bb90eb00 | 1085 | if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) { |
88b40369 BW |
1086 | dev_dbg(&spi->dev, |
1087 | "Unable to request BlackFin SPI DMA channel\n"); | |
a5f6abd4 WB |
1088 | return -ENODEV; |
1089 | } | |
bb90eb00 BW |
1090 | if (set_dma_callback(drv_data->dma_channel, |
1091 | (void *)dma_irq_handler, drv_data) < 0) { | |
88b40369 | 1092 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
a5f6abd4 WB |
1093 | return -EPERM; |
1094 | } | |
bb90eb00 BW |
1095 | dma_disable_irq(drv_data->dma_channel); |
1096 | drv_data->dma_requested = 1; | |
a5f6abd4 WB |
1097 | } |
1098 | ||
1099 | /* | |
1100 | * Notice: for blackfin, the speed_hz is the value of register | |
1101 | * SPI_BAUD, not the real baudrate | |
1102 | */ | |
1103 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
1104 | spi_flg = ~(1 << (spi->chip_select)); | |
1105 | chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select)); | |
1106 | chip->chip_select_num = spi->chip_select; | |
1107 | ||
1108 | switch (chip->bits_per_word) { | |
1109 | case 8: | |
1110 | chip->n_bytes = 1; | |
1111 | chip->width = CFG_SPI_WORDSIZE8; | |
1112 | chip->read = chip->cs_change_per_word ? | |
1113 | u8_cs_chg_reader : u8_reader; | |
1114 | chip->write = chip->cs_change_per_word ? | |
1115 | u8_cs_chg_writer : u8_writer; | |
1116 | chip->duplex = chip->cs_change_per_word ? | |
1117 | u8_cs_chg_duplex : u8_duplex; | |
1118 | break; | |
1119 | ||
1120 | case 16: | |
1121 | chip->n_bytes = 2; | |
1122 | chip->width = CFG_SPI_WORDSIZE16; | |
1123 | chip->read = chip->cs_change_per_word ? | |
1124 | u16_cs_chg_reader : u16_reader; | |
1125 | chip->write = chip->cs_change_per_word ? | |
1126 | u16_cs_chg_writer : u16_writer; | |
1127 | chip->duplex = chip->cs_change_per_word ? | |
1128 | u16_cs_chg_duplex : u16_duplex; | |
1129 | break; | |
1130 | ||
1131 | default: | |
1132 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1133 | chip->bits_per_word); | |
1134 | kfree(chip); | |
1135 | return -ENODEV; | |
1136 | } | |
1137 | ||
898eb71c | 1138 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1139 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1140 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1141 | chip->ctl_reg, chip->flag); |
1142 | ||
1143 | spi_set_ctldata(spi, chip); | |
1144 | ||
12e17c42 SZ |
1145 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
1146 | if ((chip->chip_select_num > 0) | |
1147 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1148 | peripheral_request(ssel[spi->master->bus_num] | |
1149 | [chip->chip_select_num-1], DRV_NAME); | |
1150 | ||
07612e5f SZ |
1151 | cs_deactive(drv_data, chip); |
1152 | ||
a5f6abd4 WB |
1153 | return 0; |
1154 | } | |
1155 | ||
1156 | /* | |
1157 | * callback for spi framework. | |
1158 | * clean driver specific data | |
1159 | */ | |
88b40369 | 1160 | static void cleanup(struct spi_device *spi) |
a5f6abd4 | 1161 | { |
27bb9e79 | 1162 | struct chip_data *chip = spi_get_ctldata(spi); |
a5f6abd4 | 1163 | |
12e17c42 SZ |
1164 | if ((chip->chip_select_num > 0) |
1165 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1166 | peripheral_free(ssel[spi->master->bus_num] | |
1167 | [chip->chip_select_num-1]); | |
1168 | ||
a5f6abd4 WB |
1169 | kfree(chip); |
1170 | } | |
1171 | ||
1172 | static inline int init_queue(struct driver_data *drv_data) | |
1173 | { | |
1174 | INIT_LIST_HEAD(&drv_data->queue); | |
1175 | spin_lock_init(&drv_data->lock); | |
1176 | ||
1177 | drv_data->run = QUEUE_STOPPED; | |
1178 | drv_data->busy = 0; | |
1179 | ||
1180 | /* init transfer tasklet */ | |
1181 | tasklet_init(&drv_data->pump_transfers, | |
1182 | pump_transfers, (unsigned long)drv_data); | |
1183 | ||
1184 | /* init messages workqueue */ | |
1185 | INIT_WORK(&drv_data->pump_messages, pump_messages); | |
1186 | drv_data->workqueue = | |
49dce689 | 1187 | create_singlethread_workqueue(drv_data->master->dev.parent->bus_id); |
a5f6abd4 WB |
1188 | if (drv_data->workqueue == NULL) |
1189 | return -EBUSY; | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | static inline int start_queue(struct driver_data *drv_data) | |
1195 | { | |
1196 | unsigned long flags; | |
1197 | ||
1198 | spin_lock_irqsave(&drv_data->lock, flags); | |
1199 | ||
1200 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1201 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1202 | return -EBUSY; | |
1203 | } | |
1204 | ||
1205 | drv_data->run = QUEUE_RUNNING; | |
1206 | drv_data->cur_msg = NULL; | |
1207 | drv_data->cur_transfer = NULL; | |
1208 | drv_data->cur_chip = NULL; | |
1209 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1210 | ||
1211 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | static inline int stop_queue(struct driver_data *drv_data) | |
1217 | { | |
1218 | unsigned long flags; | |
1219 | unsigned limit = 500; | |
1220 | int status = 0; | |
1221 | ||
1222 | spin_lock_irqsave(&drv_data->lock, flags); | |
1223 | ||
1224 | /* | |
1225 | * This is a bit lame, but is optimized for the common execution path. | |
1226 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1227 | * execution path (pump_messages) would be required to call wake_up or | |
1228 | * friends on every SPI message. Do this instead | |
1229 | */ | |
1230 | drv_data->run = QUEUE_STOPPED; | |
1231 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1232 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1233 | msleep(10); | |
1234 | spin_lock_irqsave(&drv_data->lock, flags); | |
1235 | } | |
1236 | ||
1237 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1238 | status = -EBUSY; | |
1239 | ||
1240 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1241 | ||
1242 | return status; | |
1243 | } | |
1244 | ||
1245 | static inline int destroy_queue(struct driver_data *drv_data) | |
1246 | { | |
1247 | int status; | |
1248 | ||
1249 | status = stop_queue(drv_data); | |
1250 | if (status != 0) | |
1251 | return status; | |
1252 | ||
1253 | destroy_workqueue(drv_data->workqueue); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
7c4ef094 | 1258 | static int setup_pin_mux(int action, int bus_num) |
cc2f81a6 MH |
1259 | { |
1260 | ||
7c4ef094 SZ |
1261 | u16 pin_req[3][4] = { |
1262 | {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | |
1263 | {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | |
1264 | {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0}, | |
1265 | }; | |
cc2f81a6 MH |
1266 | |
1267 | if (action) { | |
7c4ef094 | 1268 | if (peripheral_request_list(pin_req[bus_num], DRV_NAME)) |
cc2f81a6 MH |
1269 | return -EFAULT; |
1270 | } else { | |
7c4ef094 | 1271 | peripheral_free_list(pin_req[bus_num]); |
cc2f81a6 MH |
1272 | } |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
a5f6abd4 WB |
1277 | static int __init bfin5xx_spi_probe(struct platform_device *pdev) |
1278 | { | |
1279 | struct device *dev = &pdev->dev; | |
1280 | struct bfin5xx_spi_master *platform_info; | |
1281 | struct spi_master *master; | |
1282 | struct driver_data *drv_data = 0; | |
a32c691d | 1283 | struct resource *res; |
a5f6abd4 WB |
1284 | int status = 0; |
1285 | ||
1286 | platform_info = dev->platform_data; | |
1287 | ||
1288 | /* Allocate master with space for drv_data */ | |
1289 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1290 | if (!master) { | |
1291 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1292 | return -ENOMEM; | |
1293 | } | |
131b17d4 | 1294 | |
a5f6abd4 WB |
1295 | drv_data = spi_master_get_devdata(master); |
1296 | drv_data->master = master; | |
1297 | drv_data->master_info = platform_info; | |
1298 | drv_data->pdev = pdev; | |
1299 | ||
1300 | master->bus_num = pdev->id; | |
1301 | master->num_chipselect = platform_info->num_chipselect; | |
1302 | master->cleanup = cleanup; | |
1303 | master->setup = setup; | |
1304 | master->transfer = transfer; | |
1305 | ||
a32c691d BW |
1306 | /* Find and map our resources */ |
1307 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1308 | if (res == NULL) { | |
1309 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1310 | status = -ENOENT; | |
1311 | goto out_error_get_res; | |
1312 | } | |
1313 | ||
f452126c BW |
1314 | drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1)); |
1315 | if (drv_data->regs_base == NULL) { | |
a32c691d BW |
1316 | dev_err(dev, "Cannot map IO\n"); |
1317 | status = -ENXIO; | |
1318 | goto out_error_ioremap; | |
1319 | } | |
1320 | ||
bb90eb00 BW |
1321 | drv_data->dma_channel = platform_get_irq(pdev, 0); |
1322 | if (drv_data->dma_channel < 0) { | |
a32c691d BW |
1323 | dev_err(dev, "No DMA channel specified\n"); |
1324 | status = -ENOENT; | |
1325 | goto out_error_no_dma_ch; | |
1326 | } | |
1327 | ||
a5f6abd4 WB |
1328 | /* Initial and start queue */ |
1329 | status = init_queue(drv_data); | |
1330 | if (status != 0) { | |
a32c691d | 1331 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1332 | goto out_error_queue_alloc; |
1333 | } | |
a32c691d | 1334 | |
a5f6abd4 WB |
1335 | status = start_queue(drv_data); |
1336 | if (status != 0) { | |
a32c691d | 1337 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1338 | goto out_error_queue_alloc; |
1339 | } | |
1340 | ||
1341 | /* Register with the SPI framework */ | |
1342 | platform_set_drvdata(pdev, drv_data); | |
1343 | status = spi_register_master(master); | |
1344 | if (status != 0) { | |
a32c691d | 1345 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1346 | goto out_error_queue_alloc; |
1347 | } | |
a32c691d | 1348 | |
7c4ef094 SZ |
1349 | if (setup_pin_mux(1, master->bus_num)) { |
1350 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1351 | goto out_error; | |
1352 | } | |
1353 | ||
f452126c | 1354 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1355 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1356 | drv_data->dma_channel); | |
a5f6abd4 WB |
1357 | return status; |
1358 | ||
cc2f81a6 | 1359 | out_error_queue_alloc: |
a5f6abd4 | 1360 | destroy_queue(drv_data); |
a32c691d | 1361 | out_error_no_dma_ch: |
bb90eb00 | 1362 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1363 | out_error_ioremap: |
1364 | out_error_get_res: | |
cc2f81a6 | 1365 | out_error: |
a5f6abd4 | 1366 | spi_master_put(master); |
cc2f81a6 | 1367 | |
a5f6abd4 WB |
1368 | return status; |
1369 | } | |
1370 | ||
1371 | /* stop hardware and remove the driver */ | |
1372 | static int __devexit bfin5xx_spi_remove(struct platform_device *pdev) | |
1373 | { | |
1374 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1375 | int status = 0; | |
1376 | ||
1377 | if (!drv_data) | |
1378 | return 0; | |
1379 | ||
1380 | /* Remove the queue */ | |
1381 | status = destroy_queue(drv_data); | |
1382 | if (status != 0) | |
1383 | return status; | |
1384 | ||
1385 | /* Disable the SSP at the peripheral and SOC level */ | |
1386 | bfin_spi_disable(drv_data); | |
1387 | ||
1388 | /* Release DMA */ | |
1389 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1390 | if (dma_channel_active(drv_data->dma_channel)) |
1391 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1392 | } |
1393 | ||
1394 | /* Disconnect from the SPI framework */ | |
1395 | spi_unregister_master(drv_data->master); | |
1396 | ||
7c4ef094 | 1397 | setup_pin_mux(0, drv_data->master->bus_num); |
cc2f81a6 | 1398 | |
a5f6abd4 WB |
1399 | /* Prevent double remove */ |
1400 | platform_set_drvdata(pdev, NULL); | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
1405 | #ifdef CONFIG_PM | |
1406 | static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1407 | { | |
1408 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1409 | int status = 0; | |
1410 | ||
1411 | status = stop_queue(drv_data); | |
1412 | if (status != 0) | |
1413 | return status; | |
1414 | ||
1415 | /* stop hardware */ | |
1416 | bfin_spi_disable(drv_data); | |
1417 | ||
1418 | return 0; | |
1419 | } | |
1420 | ||
1421 | static int bfin5xx_spi_resume(struct platform_device *pdev) | |
1422 | { | |
1423 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1424 | int status = 0; | |
1425 | ||
1426 | /* Enable the SPI interface */ | |
1427 | bfin_spi_enable(drv_data); | |
1428 | ||
1429 | /* Start the queue running */ | |
1430 | status = start_queue(drv_data); | |
1431 | if (status != 0) { | |
1432 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1433 | return status; | |
1434 | } | |
1435 | ||
1436 | return 0; | |
1437 | } | |
1438 | #else | |
1439 | #define bfin5xx_spi_suspend NULL | |
1440 | #define bfin5xx_spi_resume NULL | |
1441 | #endif /* CONFIG_PM */ | |
1442 | ||
fc3ba952 | 1443 | MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */ |
a5f6abd4 | 1444 | static struct platform_driver bfin5xx_spi_driver = { |
fc3ba952 | 1445 | .driver = { |
a32c691d | 1446 | .name = DRV_NAME, |
88b40369 BW |
1447 | .owner = THIS_MODULE, |
1448 | }, | |
1449 | .suspend = bfin5xx_spi_suspend, | |
1450 | .resume = bfin5xx_spi_resume, | |
1451 | .remove = __devexit_p(bfin5xx_spi_remove), | |
a5f6abd4 WB |
1452 | }; |
1453 | ||
1454 | static int __init bfin5xx_spi_init(void) | |
1455 | { | |
88b40369 | 1456 | return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe); |
a5f6abd4 | 1457 | } |
a5f6abd4 WB |
1458 | module_init(bfin5xx_spi_init); |
1459 | ||
1460 | static void __exit bfin5xx_spi_exit(void) | |
1461 | { | |
1462 | platform_driver_unregister(&bfin5xx_spi_driver); | |
1463 | } | |
a5f6abd4 | 1464 | module_exit(bfin5xx_spi_exit); |