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Merge branch 'opw-next' into staging-next
[mirror_ubuntu-artful-kernel.git] / drivers / staging / cxt1e1 / comet.c
CommitLineData
50ee11fe
BB		 1/* Copyright (C) 2003-2005 SBE, Inc.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
694a9807
JP		 14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
f74a9d65 16#include <linux/io.h>
50ee11fe
BB		 17#include <linux/hdlc.h>
18#include "pmcc4_sysdep.h"
19#include "sbecom_inline_linux.h"
20#include "libsbew.h"
21#include "pmcc4.h"
22#include "comet.h"
23#include "comet_tables.h"
24
b8b73994 25extern int cxt1e1_log_level;
50ee11fe
BB		 26
27#define COMET_NUM_SAMPLES 24 /* Number of entries in the waveform table */
28#define COMET_NUM_UNITS 5 /* Number of points per entry in table */
29
30/* forward references */
987e8bef
SB		 31static void SetPwrLevel(struct s_comet_reg *comet);
32static void WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table);
33static void WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
50ee11fe
BB		 34
35
36void *TWV_table[12] = {
4a9fbb27 37 TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
cd1ccce1
DG		 38 TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
39 TWVShortHaul4, TWVShortHaul5,
40 /** PORT POINT - 75 Ohm not supported **/
41 TWV_E1_75Ohm,
4a9fbb27 42 TWV_E1_120Ohm
50ee11fe
BB		 43};
44
45
46static int
cd1ccce1
DG		 47lbo_tbl_lkup(int t1, int lbo) {
48 /* error switches to default */
49 if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
4a9fbb27 50 if (t1)
cd1ccce1
DG		 51 /* default T1 waveform table */
52 lbo = CFG_LBO_LH0;
4a9fbb27 53 else
cd1ccce1
DG		 54 /* default E1 waveform table */
55 lbo = CFG_LBO_E120;
4a9fbb27 56 }
cd1ccce1 57 /* make index ZERO relative */
bcf636d1 58 return lbo - 1;
50ee11fe
BB		 59}
60
987e8bef 61void init_comet(void *ci, struct s_comet_reg *comet, u_int32_t port_mode, int clockmaster,
cd1ccce1 62 u_int8_t moreParams)
50ee11fe 63{
4a9fbb27 64 u_int8_t isT1mode;
cd1ccce1
DG		 65 /* T1 default */
66 u_int8_t tix = CFG_LBO_LH0;
67 isT1mode = IS_FRAME_ANY_T1(port_mode);
68 /* T1 or E1 */
69 if (isT1mode) {
70 /* Select T1 Mode & PIO output enabled */
71 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
72 /* default T1 waveform table */
73 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
74 } else {
75 /* Select E1 Mode & PIO output enabled */
76 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
77 /* default E1 waveform table */
78 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
4a9fbb27 79 }
50ee11fe 80
4a9fbb27 81 if (moreParams & CFG_LBO_MASK)
cd1ccce1
DG		 82 /* dial-in requested waveform table */
83 tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
84 /* Tx line Intfc cfg Set for analog & no special patterns */
85 /* Transmit Line Interface Config. */
86 pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
87 /* master test Ignore Test settings for now */
88 /* making sure it's Default value */
89 pci_write_32((u_int32_t *) &comet->mtest, 0x00);
90 /* Turn on Center (CENT) and everything else off */
91 /* RJAT cfg */
92 pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
93 /* Set Jitter Attenuation to recommend T1 values */
94 if (isT1mode) {
95 /* RJAT Divider N1 Control */
96 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
97 /* RJAT Divider N2 Control */
98 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
99 } else {
100 /* RJAT Divider N1 Control */
101 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
102 /* RJAT Divider N2 Control */
103 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
4a9fbb27 104 }
50ee11fe 105
cd1ccce1
DG		 106 /* Turn on Center (CENT) and everything else off */
107 /* TJAT Config. */
108 pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
109
110 /* Do not bypass jitter attenuation and bypass elastic store */
111 /* rx opts */
112 pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
113
114 /* TJAT ctrl & TJAT divider ctrl */
115 /* Set Jitter Attenuation to recommended T1 values */
116 if (isT1mode) {
117 /* TJAT Divider N1 Control */
118 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
119 /* TJAT Divider N2 Control */
120 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
121 } else {
122 /* TJAT Divider N1 Control */
123 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
124 /* TJAT Divider N2 Control */
125 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
4a9fbb27 126 }
50ee11fe 127
cd1ccce1
DG		 128 /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
129
130 /* Select 193-bit frame format */
131 if (isT1mode) {
4a9fbb27
DG		 132 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
133 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
cd1ccce1
DG		 134 } else {
135 /* Select 256-bit frame format */
4a9fbb27
DG		 136 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
137 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
cd1ccce1
DG		 138 /* disable T1 data link receive */
139 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
140 /* disable T1 data link transmit */
141 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
4a9fbb27 142 }
50ee11fe
BB		 143
144 /* the following is a default value */
145 /* Enable 8 out of 10 validation */
cd1ccce1
DG		 146 /* t1RBOC enable(BOC:BitOriented Code) */
147 pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
6c762a42 148 if (isT1mode) {
01001398 149 /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
cd1ccce1
DG		 150 /* 6 bit down, 5 bit up (assert) */
151 pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
152 /* line loopback activate pattern */
153 pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
154 /* deactivate code pattern (i.e.001) */
155 pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
4a9fbb27 156 }
50ee11fe
BB		 157 /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */
158 /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */
159 /* 60: t1 ALMI cfg */
160 /* Configure Line Coding */
161
ae6a214b 162 switch (port_mode) {
cd1ccce1
DG		 163 /* 1 - T1 B8ZS */
164 case CFG_FRAME_SF:
165 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
166 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
167 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
168 /* 5:B8ZS */
169 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
170 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
171 break;
172 /* 2 - T1 B8ZS */
173 case CFG_FRAME_ESF:
174 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
175 /* Bit 5: T1 DataLink Enable */
176 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
177 /* 5: T1 DataLink Enable */
178 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
179 /* 4:ESF 5:ESFFA */
180 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
181 /* 2:ESF */
182 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
183 /* 4:ESF 5:B8ZS */
184 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
185 /* 4:ESF */
186 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
187 break;
188 /* 3 - HDB3 */
189 case CFG_FRAME_E1PLAIN:
190 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
191 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
192 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
193 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
194 break;
195 /* 4 - HDB3 */
196 case CFG_FRAME_E1CAS:
197 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
198 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
199 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
200 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
201 break;
202 /* 5 - HDB3 */
203 case CFG_FRAME_E1CRC:
204 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
4a9fbb27 205 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
cd1ccce1
DG		 206 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
207 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
208 break;
209 /* 6 - HDB3 */
210 case CFG_FRAME_E1CRC_CAS:
211 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
212 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
213 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
214 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
215 break;
216 /* 7 - T1 AMI */
217 case CFG_FRAME_SF_AMI:
218 /* Enable AMI Line Decoding */
219 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
220 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
221 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
222 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
223 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
224 break;
225 /* 8 - T1 AMI */
226 case CFG_FRAME_ESF_AMI:
227 /* Enable AMI Line Decoding */
228 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
229 /* 5: T1 DataLink Enable */
230 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
231 /* 5: T1 DataLink Enable */
232 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
233 /* Bit 4:ESF 5:ESFFA */
234 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
235 /* 2:ESF */
236 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
237 /* 4:ESF */
238 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
239 /* 4:ESF */
240 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
241 break;
242 /* 9 - AMI */
243 case CFG_FRAME_E1PLAIN_AMI:
244 /* Enable AMI Line Decoding */
245 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
246 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
247 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
248 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
249 break;
250 /* 10 - AMI */
251 case CFG_FRAME_E1CAS_AMI:
252 /* Enable AMI Line Decoding */
253 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
254 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
255 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
256 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
257 break;
258 /* 11 - AMI */
259 case CFG_FRAME_E1CRC_AMI:
260 /* Enable AMI Line Decoding */
261 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
262 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
263 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
264 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
265 break;
266 /* 12 - AMI */
267 case CFG_FRAME_E1CRC_CAS_AMI:
268 /* Enable AMI Line Decoding */
269 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
270 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
271 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
272 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
273 break;
274 } /* end switch */
50ee11fe
BB		 275
276 /***
277 * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
278 * CMODE=1: Clock slave mode with BRCLK as an input,
279 * DE=0: Use falling edge of BRCLK for data,
280 * FE=0: Use falling edge of BRCLK for frame,
281 * CMS=0: Use backplane freq,
282 * RATE[1:0]=0,0: T1
283 ***/
284
285
286 /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
287 /* note "rate bits can only be set once after reset" */
ae6a214b 288 if (clockmaster) {
cd1ccce1
DG		 289 /* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
290 /* rate = 1.544 Mb/s */
291 if (isT1mode)
292 /* Comet 0 Master Mode(CMODE=0) */
293 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
294 /* rate = 2.048 Mb/s */
295 else
296 /* Comet 0 Master Mode(CMODE=0) */
297 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
298
299 /* 31: BRIF frame pulse cfg 06: tx timing options */
300
301 /* Master Mode i.e.FPMODE=0 (@0x20) */
302 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
ae6a214b 303 if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
4a9fbb27 304 if (cxt1e1_log_level >= LOG_SBEBUG12)
9b38da66
SB		 305 pr_info(">> %s: clockmaster internal clock\n",
306 __func__);
cd1ccce1
DG		 307 /* internal oscillator */
308 pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
309 } else {
310 /* external clock source */
4a9fbb27 311 if (cxt1e1_log_level >= LOG_SBEBUG12)
9b38da66
SB		 312 pr_info(">> %s: clockmaster external clock\n",
313 __func__);
cd1ccce1
DG		 314 /* loop timing(external) */
315 pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
4a9fbb27 316 }
50ee11fe 317
cd1ccce1
DG		 318 } else {
319 /* slave */
4a9fbb27 320 if (isT1mode)
cd1ccce1
DG		 321 /* Slave Mode(CMODE=1, see above) */
322 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
4a9fbb27 323 else
cd1ccce1
DG		 324 /* Slave Mode(CMODE=1)*/
325 pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
326 /* Slave Mode i.e. FPMODE=1 (@0x20) */
327 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
328 if (cxt1e1_log_level >= LOG_SBEBUG12)
329 pr_info(">> %s: clockslave internal clock\n", __func__);
330 /* oscillator timing */
331 pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
4a9fbb27 332 }
50ee11fe 333
cd1ccce1
DG		 334 /* 32: BRIF parity F-bit cfg */
335 /* Totem-pole operation */
336 /* Receive Backplane Parity/F-bit */
337 pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
50ee11fe
BB		 338
339 /* dc: RLPS equalizer V ref */
340 /* Configuration */
4a9fbb27 341 if (isT1mode)
cd1ccce1
DG		 342 /* RLPS Equalizer Voltage */
343 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
4a9fbb27 344 else
cd1ccce1
DG		 345 /* RLPS Equalizer Voltage */
346 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
50ee11fe
BB		 347
348 /* Reserved bit set and SQUELCH enabled */
349 /* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */
cd1ccce1
DG		 350 /* RLPS Configuration Status */
351 pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
4a9fbb27 352 if (isT1mode)
01001398 353 /* ? */
cd1ccce1 354 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
4a9fbb27 355 else
cd1ccce1
DG		 356 /* ? */
357 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
50ee11fe
BB		 358
359
360 /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
361 /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
362 /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
363 /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
cd1ccce1
DG		 364 /*** Transmit side is always an Input, Slave Clock*/
365 /* 40: BTIF cfg 41: loop timing(external) */
366 /*BTIF frame pulse cfg */
4a9fbb27 367 if (isT1mode)
cd1ccce1
DG		 368 /* BTIF Configuration Reg. */
369 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
4a9fbb27 370 else
cd1ccce1
DG		 371 /* BTIF Configuration Reg. */
372 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
373 /* BTIF Frame Pulse Config. */
374 pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
50ee11fe
BB		 375
376 /* 0a: master diag 06: tx timing options */
377 /* if set Comet to loop back */
378
379 /* Comets set to normal */
4a9fbb27 380 pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
50ee11fe
BB		 381
382 /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */
383 /* Store is enabled. */
384
4a9fbb27 385 WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
cd1ccce1
DG		 386 if (isT1mode)
387 WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
388 else
389 WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
390 SetPwrLevel(comet);
391}
50ee11fe
BB		 392
393/*
394** Name: WrtXmtWaveform
395** Description: Formulate the Data for the Pulse Waveform Storage
396** Write register, (F2), from the sample and unit inputs.
397** Write the data to the Pulse Waveform Storage Data register.
398** Returns: Nothing
399*/
37ca35c4 400static void
987e8bef 401WrtXmtWaveform(ci_t *ci, struct s_comet_reg *comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
50ee11fe 402{
ee1803cf 403 u_int8_t WaveformAddr;
50ee11fe 404
4a9fbb27
DG		 405 WaveformAddr = (sample << 3) + (unit & 7);
406 pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
cd1ccce1
DG		 407 /* for write order preservation when Optimizing driver */
408 pci_flush_write(ci);
4a9fbb27 409 pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
50ee11fe
BB		 410}
411
412/*
413** Name: WrtXmtWaveformTbl
414** Description: Fill in the Transmit Waveform Values
415** for driving the transmitter DAC.
416** Returns: Nothing
417*/
37ca35c4 418static void
987e8bef 419WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
cd1ccce1 420 u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
50ee11fe 421{
4a9fbb27 422 u_int32_t sample, unit;
50ee11fe 423
ae6a214b 424 for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
cd1ccce1 425 for (unit = 0; unit < COMET_NUM_UNITS; unit++)
9b38da66
SB		 426 WrtXmtWaveform(ci, comet, sample, unit,
427 table[sample][unit]);
cd1ccce1 428 }
50ee11fe
BB		 429
430 /* Enable transmitter and set output amplitude */
9b38da66
SB		 431 pci_write_32((u_int32_t *) &comet->xlpg_cfg,
432 table[COMET_NUM_SAMPLES][0]);
50ee11fe
BB		 433}
434
435
436/*
437** Name: WrtXmtWaveform
438** Description: Fill in the Receive Equalizer RAM from the desired
439** table.
440** Returns: Nothing
441**
442** Remarks: Per PM4351 Device Errata, Receive Equalizer RAM Initialization
443** is coded with early setup of indirect address.
444*/
445
37ca35c4 446static void
987e8bef 447WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
50ee11fe 448{
4a9fbb27
DG		 449 u_int32_t ramaddr;
450 volatile u_int32_t value;
50ee11fe 451
cd1ccce1 452 for (ramaddr = 0; ramaddr < 256; ramaddr++) {
01001398 453 /*** the following lines are per Errata 7, 2.5 ***/
cd1ccce1
DG		 454 {
455 /* Set up for a read operation */
456 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
457 /* for write order preservation when Optimizing driver */
458 pci_flush_write(ci);
459 /* write the addr, initiate a read */
9b38da66
SB		 460 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
461 (u_int8_t) ramaddr);
cd1ccce1
DG		 462 /* for write order preservation when Optimizing driver */
463 pci_flush_write(ci);
464 /*
465 * wait 3 line rate clock cycles to ensure address bits are
466 * captured by T1/E1 clock
467 */
468
469 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
470 OS_uwait(4, "wret");
4a9fbb27 471 }
50ee11fe 472
4a9fbb27 473 value = *table++;
9b38da66
SB		 474 pci_write_32((u_int32_t *) &comet->rlps_idata3,
475 (u_int8_t) (value >> 24));
476 pci_write_32((u_int32_t *) &comet->rlps_idata2,
477 (u_int8_t) (value >> 16));
478 pci_write_32((u_int32_t *) &comet->rlps_idata1,
479 (u_int8_t) (value >> 8));
cd1ccce1
DG		 480 pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
481 /* for write order preservation when Optimizing driver */
482 pci_flush_write(ci);
483
484 /* Storing RAM address, causes RAM to be updated */
485
486 /* Set up for a write operation */
487 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
488 /* for write order preservation when optimizing driver */
489 pci_flush_write(ci);
490 /* write the addr, initiate a read */
9b38da66
SB		 491 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
492 (u_int8_t) ramaddr);
cd1ccce1
DG		 493 /* for write order preservation when optimizing driver */
494 pci_flush_write(ci);
495
496 /*
497 * wait 3 line rate clock cycles to ensure address bits are captured
498 * by T1/E1 clock
499 */
500 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
ee1803cf 501 OS_uwait(4, "wret");
4a9fbb27 502 }
50ee11fe 503
cd1ccce1
DG		 504 /* Enable Equalizer & set it to use 256 periods */
505 pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
50ee11fe
BB		 506}
507
508
509/*
510** Name: SetPwrLevel
511** Description: Implement power level setting algorithm described below
512** Returns: Nothing
513*/
514
37ca35c4 515static void
987e8bef 516SetPwrLevel(struct s_comet_reg *comet)
50ee11fe 517{
4a9fbb27 518 volatile u_int32_t temp;
50ee11fe
BB		 519
520/*
521** Algorithm to Balance the Power Distribution of Ttip Tring
522**
523** Zero register F6
524** Write 0x01 to register F4
525** Write another 0x01 to register F4
526** Read register F4
527** Remove the 0x01 bit by Anding register F4 with 0xFE
528** Write the resultant value to register F4
529** Repeat these steps for register F5
530** Write 0x01 to register F6
531*/
cd1ccce1
DG		 532 /* XLPG Fuse Data Select */
533 pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
534 /* XLPG Analog Test Positive control */
535 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
4a9fbb27 536 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
4a9fbb27
DG		 537 temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
538 pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
4a9fbb27 539 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
cd1ccce1
DG		 540 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
541 /* XLPG Analog Test Negative control */
4a9fbb27
DG		 542 temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
543 pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
cd1ccce1
DG		 544 /* XLPG */
545 pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
50ee11fe
BB		 546}
547
548
549/*
550** Name: SetCometOps
551** Description: Set up the selected Comet's clock edge drive for both
552** the transmit out the analog side and receive to the
553** backplane side.
554** Returns: Nothing
555*/
556#if 0
37ca35c4 557static void
987e8bef 558SetCometOps(struct s_comet_reg *comet)
50ee11fe 559{
4a9fbb27 560 volatile u_int8_t rd_value;
50ee11fe 561
ae6a214b 562 if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
cd1ccce1
DG		 563 /* read the BRIF Configuration */
564 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
4a9fbb27
DG		 565 rd_value &= ~0x20;
566 pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
cd1ccce1
DG		 567 /* read the BRIF Frame Pulse Configuration */
568 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
4a9fbb27
DG		 569 rd_value &= ~0x20;
570 pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
cd1ccce1
DG		 571 } else {
572 /* read the BRIF Configuration */
573 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
574 rd_value |= 0x20;
575 pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
576 /* read the BRIF Frame Pulse Configuration */
577 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
578 rd_value |= 0x20;
579 pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
4a9fbb27 580 }
50ee11fe
BB		 581}
582#endif
583
584/*** End-of-File ***/
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