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a49d2536 AC |
1 | /* |
2 | * Support for Intel Camera Imaging ISP subsystem. | |
3 | * Copyright (c) 2015, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #ifndef __SYSTEM_GLOBAL_H_INCLUDED__ | |
16 | #define __SYSTEM_GLOBAL_H_INCLUDED__ | |
17 | ||
18 | #include <hive_isp_css_defs.h> | |
19 | #include <type_support.h> | |
20 | ||
21 | /* | |
22 | * The longest allowed (uninteruptible) bus transfer, does not | |
23 | * take stalling into account | |
24 | */ | |
25 | #define HIVE_ISP_MAX_BURST_LENGTH 1024 | |
26 | ||
27 | /* | |
28 | * Maximum allowed burst length in words for the ISP DMA | |
29 | * This value is set to 2 to prevent the ISP DMA from blocking | |
30 | * the bus for too long; as the input system can only buffer | |
31 | * 2 lines on Moorefield and Cherrytrail, the input system buffers | |
32 | * may overflow if blocked for too long (BZ 2726). | |
33 | */ | |
34 | #define ISP_DMA_MAX_BURST_LENGTH 2 | |
35 | ||
36 | /* | |
37 | * Create a list of HAS and IS properties that defines the system | |
38 | * | |
39 | * The configuration assumes the following | |
40 | * - The system is hetereogeneous; Multiple cells and devices classes | |
41 | * - The cell and device instances are homogeneous, each device type | |
42 | * belongs to the same class | |
43 | * - Device instances supporting a subset of the class capabilities are | |
44 | * allowed | |
45 | * | |
46 | * We could manage different device classes through the enumerated | |
47 | * lists (C) or the use of classes (C++), but that is presently not | |
48 | * fully supported | |
49 | * | |
50 | * N.B. the 3 input formatters are of 2 different classess | |
51 | */ | |
52 | ||
53 | #define USE_INPUT_SYSTEM_VERSION_2401 | |
54 | ||
55 | #define IS_ISP_2400_SYSTEM | |
56 | /* | |
57 | * Since this file is visible everywhere and the system definition | |
58 | * macros are not, detect the separate definitions for {host, SP, ISP} | |
59 | * | |
60 | * The 2401 system has the nice property that it uses a vanilla 2400 SP | |
61 | * so the SP will believe it is a 2400 system rather than 2401... | |
62 | */ | |
63 | /* #if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) || defined(__scalar_processor_2401) */ | |
64 | #if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) | |
65 | #define IS_ISP_2401_MAMOIADA_SYSTEM | |
66 | #define HAS_ISP_2401_MAMOIADA | |
67 | #define HAS_SP_2400 | |
68 | /* #elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) || defined(__scalar_processor_2400)*/ | |
69 | #elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) | |
70 | #define IS_ISP_2400_MAMOIADA_SYSTEM | |
71 | #define HAS_ISP_2400_MAMOIADA | |
72 | #define HAS_SP_2400 | |
73 | #else | |
74 | #error "system_global.h: 2400_SYSTEM must be one of {2400, 2401 }" | |
75 | #endif | |
76 | ||
77 | #define HAS_MMU_VERSION_2 | |
78 | #define HAS_DMA_VERSION_2 | |
79 | #define HAS_GDC_VERSION_2 | |
80 | #define HAS_VAMEM_VERSION_2 | |
81 | #define HAS_HMEM_VERSION_1 | |
82 | #define HAS_BAMEM_VERSION_2 | |
83 | #define HAS_IRQ_VERSION_2 | |
84 | #define HAS_IRQ_MAP_VERSION_2 | |
85 | #define HAS_INPUT_FORMATTER_VERSION_2 | |
86 | /* 2401: HAS_INPUT_SYSTEM_VERSION_3 */ | |
87 | /* 2400: HAS_INPUT_SYSTEM_VERSION_2 */ | |
88 | #define HAS_INPUT_SYSTEM_VERSION_2 | |
89 | #define HAS_INPUT_SYSTEM_VERSION_2401 | |
90 | #define HAS_BUFFERED_SENSOR | |
91 | #define HAS_FIFO_MONITORS_VERSION_2 | |
92 | /* #define HAS_GP_REGS_VERSION_2 */ | |
93 | #define HAS_GP_DEVICE_VERSION_2 | |
94 | #define HAS_GPIO_VERSION_1 | |
95 | #define HAS_TIMED_CTRL_VERSION_1 | |
96 | #define HAS_RX_VERSION_2 | |
97 | #define HAS_NO_INPUT_FORMATTER | |
98 | /*#define HAS_NO_PACKED_RAW_PIXELS*/ | |
99 | /*#define HAS_NO_DVS_6AXIS_CONFIG_UPDATE*/ | |
100 | ||
101 | #define DMA_DDR_TO_VAMEM_WORKAROUND | |
102 | #define DMA_DDR_TO_HMEM_WORKAROUND | |
103 | ||
104 | ||
105 | /* | |
106 | * Semi global. "HRT" is accessible from SP, but | |
107 | * the HRT types do not fully apply | |
108 | */ | |
109 | #define HRT_VADDRESS_WIDTH 32 | |
110 | /* Surprise, this is a local property*/ | |
111 | /*#define HRT_ADDRESS_WIDTH 64 */ | |
112 | #define HRT_DATA_WIDTH 32 | |
113 | ||
114 | #define SIZEOF_HRT_REG (HRT_DATA_WIDTH>>3) | |
115 | #define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH/8) | |
116 | ||
117 | /* The main bus connecting all devices */ | |
118 | #define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH | |
119 | #define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES | |
120 | ||
121 | #define CSI2P_DISABLE_ISYS2401_ONLINE_MODE | |
122 | ||
123 | /* per-frame parameter handling support */ | |
124 | #define SH_CSS_ENABLE_PER_FRAME_PARAMS | |
125 | ||
126 | typedef uint32_t hrt_bus_align_t; | |
127 | ||
128 | /* | |
129 | * Enumerate the devices, device access through the API is by ID, | |
130 | * through the DLI by address. The enumerator terminators are used | |
131 | * to size the wiring arrays and as an exception value. | |
132 | */ | |
133 | typedef enum { | |
134 | DDR0_ID = 0, | |
135 | N_DDR_ID | |
136 | } ddr_ID_t; | |
137 | ||
138 | typedef enum { | |
139 | ISP0_ID = 0, | |
140 | N_ISP_ID | |
141 | } isp_ID_t; | |
142 | ||
143 | typedef enum { | |
144 | SP0_ID = 0, | |
145 | N_SP_ID | |
146 | } sp_ID_t; | |
147 | ||
148 | #if defined(IS_ISP_2401_MAMOIADA_SYSTEM) | |
149 | typedef enum { | |
150 | MMU0_ID = 0, | |
151 | MMU1_ID, | |
152 | N_MMU_ID | |
153 | } mmu_ID_t; | |
154 | #elif defined(IS_ISP_2400_MAMOIADA_SYSTEM) | |
155 | typedef enum { | |
156 | MMU0_ID = 0, | |
157 | MMU1_ID, | |
158 | N_MMU_ID | |
159 | } mmu_ID_t; | |
160 | #else | |
161 | #error "system_global.h: SYSTEM must be one of {2400, 2401}" | |
162 | #endif | |
163 | ||
164 | typedef enum { | |
165 | DMA0_ID = 0, | |
166 | N_DMA_ID | |
167 | } dma_ID_t; | |
168 | ||
169 | typedef enum { | |
170 | GDC0_ID = 0, | |
171 | GDC1_ID, | |
172 | N_GDC_ID | |
173 | } gdc_ID_t; | |
174 | ||
175 | /* this extra define is needed because we want to use it also | |
176 | in the preprocessor, and that doesn't work with enums. | |
177 | */ | |
178 | #define N_GDC_ID_CPP 2 | |
179 | ||
180 | typedef enum { | |
181 | VAMEM0_ID = 0, | |
182 | VAMEM1_ID, | |
183 | VAMEM2_ID, | |
184 | N_VAMEM_ID | |
185 | } vamem_ID_t; | |
186 | ||
187 | typedef enum { | |
188 | BAMEM0_ID = 0, | |
189 | N_BAMEM_ID | |
190 | } bamem_ID_t; | |
191 | ||
192 | typedef enum { | |
193 | HMEM0_ID = 0, | |
194 | N_HMEM_ID | |
195 | } hmem_ID_t; | |
196 | ||
197 | typedef enum { | |
198 | ISYS_IRQ0_ID = 0, /* port a */ | |
199 | ISYS_IRQ1_ID, /* port b */ | |
200 | ISYS_IRQ2_ID, /* port c */ | |
201 | N_ISYS_IRQ_ID | |
202 | } isys_irq_ID_t; | |
203 | ||
204 | typedef enum { | |
205 | IRQ0_ID = 0, /* GP IRQ block */ | |
206 | IRQ1_ID, /* Input formatter */ | |
207 | IRQ2_ID, /* input system */ | |
208 | IRQ3_ID, /* input selector */ | |
209 | N_IRQ_ID | |
210 | } irq_ID_t; | |
211 | ||
212 | typedef enum { | |
213 | FIFO_MONITOR0_ID = 0, | |
214 | N_FIFO_MONITOR_ID | |
215 | } fifo_monitor_ID_t; | |
216 | ||
217 | /* | |
218 | * Deprecated: Since all gp_reg instances are different | |
219 | * and put in the address maps of other devices we cannot | |
220 | * enumerate them as that assumes the instrances are the | |
221 | * same. | |
222 | * | |
223 | * We define a single GP_DEVICE containing all gp_regs | |
224 | * w.r.t. a single base address | |
225 | * | |
226 | typedef enum { | |
227 | GP_REGS0_ID = 0, | |
228 | N_GP_REGS_ID | |
229 | } gp_regs_ID_t; | |
230 | */ | |
231 | typedef enum { | |
232 | GP_DEVICE0_ID = 0, | |
233 | N_GP_DEVICE_ID | |
234 | } gp_device_ID_t; | |
235 | ||
236 | typedef enum { | |
237 | GP_TIMER0_ID = 0, | |
238 | GP_TIMER1_ID, | |
239 | GP_TIMER2_ID, | |
240 | GP_TIMER3_ID, | |
241 | GP_TIMER4_ID, | |
242 | GP_TIMER5_ID, | |
243 | GP_TIMER6_ID, | |
244 | GP_TIMER7_ID, | |
245 | N_GP_TIMER_ID | |
246 | } gp_timer_ID_t; | |
247 | ||
248 | typedef enum { | |
249 | GPIO0_ID = 0, | |
250 | N_GPIO_ID | |
251 | } gpio_ID_t; | |
252 | ||
253 | typedef enum { | |
254 | TIMED_CTRL0_ID = 0, | |
255 | N_TIMED_CTRL_ID | |
256 | } timed_ctrl_ID_t; | |
257 | ||
258 | typedef enum { | |
259 | INPUT_FORMATTER0_ID = 0, | |
260 | INPUT_FORMATTER1_ID, | |
261 | INPUT_FORMATTER2_ID, | |
262 | INPUT_FORMATTER3_ID, | |
263 | N_INPUT_FORMATTER_ID | |
264 | } input_formatter_ID_t; | |
265 | ||
266 | /* The IF RST is outside the IF */ | |
267 | #define INPUT_FORMATTER0_SRST_OFFSET 0x0824 | |
268 | #define INPUT_FORMATTER1_SRST_OFFSET 0x0624 | |
269 | #define INPUT_FORMATTER2_SRST_OFFSET 0x0424 | |
270 | #define INPUT_FORMATTER3_SRST_OFFSET 0x0224 | |
271 | ||
272 | #define INPUT_FORMATTER0_SRST_MASK 0x0001 | |
273 | #define INPUT_FORMATTER1_SRST_MASK 0x0002 | |
274 | #define INPUT_FORMATTER2_SRST_MASK 0x0004 | |
275 | #define INPUT_FORMATTER3_SRST_MASK 0x0008 | |
276 | ||
277 | typedef enum { | |
278 | INPUT_SYSTEM0_ID = 0, | |
279 | N_INPUT_SYSTEM_ID | |
280 | } input_system_ID_t; | |
281 | ||
282 | typedef enum { | |
283 | RX0_ID = 0, | |
284 | N_RX_ID | |
285 | } rx_ID_t; | |
286 | ||
287 | typedef enum { | |
288 | MIPI_PORT0_ID = 0, | |
289 | MIPI_PORT1_ID, | |
290 | MIPI_PORT2_ID, | |
291 | N_MIPI_PORT_ID | |
292 | } mipi_port_ID_t; | |
293 | ||
294 | #define N_RX_CHANNEL_ID 4 | |
295 | ||
296 | /* Generic port enumeration with an internal port type ID */ | |
297 | typedef enum { | |
298 | CSI_PORT0_ID = 0, | |
299 | CSI_PORT1_ID, | |
300 | CSI_PORT2_ID, | |
301 | TPG_PORT0_ID, | |
302 | PRBS_PORT0_ID, | |
303 | FIFO_PORT0_ID, | |
304 | MEMORY_PORT0_ID, | |
305 | N_INPUT_PORT_ID | |
306 | } input_port_ID_t; | |
307 | ||
308 | typedef enum { | |
309 | CAPTURE_UNIT0_ID = 0, | |
310 | CAPTURE_UNIT1_ID, | |
311 | CAPTURE_UNIT2_ID, | |
312 | ACQUISITION_UNIT0_ID, | |
313 | DMA_UNIT0_ID, | |
314 | CTRL_UNIT0_ID, | |
315 | GPREGS_UNIT0_ID, | |
316 | FIFO_UNIT0_ID, | |
317 | IRQ_UNIT0_ID, | |
318 | N_SUB_SYSTEM_ID | |
319 | } sub_system_ID_t; | |
320 | ||
321 | #define N_CAPTURE_UNIT_ID 3 | |
322 | #define N_ACQUISITION_UNIT_ID 1 | |
323 | #define N_CTRL_UNIT_ID 1 | |
324 | ||
325 | /* | |
326 | * Input-buffer Controller. | |
327 | */ | |
328 | typedef enum { | |
329 | IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */ | |
330 | IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */ | |
331 | IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */ | |
332 | N_IBUF_CTRL_ID | |
333 | } ibuf_ctrl_ID_t; | |
d929fb4e | 334 | /* end of Input-buffer Controller */ |
a49d2536 AC |
335 | |
336 | /* | |
337 | * Stream2MMIO. | |
338 | */ | |
339 | typedef enum { | |
340 | STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */ | |
341 | STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */ | |
342 | STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */ | |
343 | N_STREAM2MMIO_ID | |
344 | } stream2mmio_ID_t; | |
345 | ||
346 | typedef enum { | |
347 | /* | |
348 | * Stream2MMIO 0 has 8 SIDs that are indexed by | |
349 | * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID]. | |
350 | * | |
351 | * Stream2MMIO 1 has 4 SIDs that are indexed by | |
352 | * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID]. | |
353 | * | |
354 | * Stream2MMIO 2 has 4 SIDs that are indexed by | |
355 | * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID]. | |
356 | */ | |
357 | STREAM2MMIO_SID0_ID = 0, | |
358 | STREAM2MMIO_SID1_ID, | |
359 | STREAM2MMIO_SID2_ID, | |
360 | STREAM2MMIO_SID3_ID, | |
361 | STREAM2MMIO_SID4_ID, | |
362 | STREAM2MMIO_SID5_ID, | |
363 | STREAM2MMIO_SID6_ID, | |
364 | STREAM2MMIO_SID7_ID, | |
365 | N_STREAM2MMIO_SID_ID | |
366 | } stream2mmio_sid_ID_t; | |
d929fb4e | 367 | /* end of Stream2MMIO */ |
a49d2536 AC |
368 | |
369 | /** | |
370 | * Input System 2401: CSI-MIPI recevier. | |
371 | */ | |
372 | typedef enum { | |
373 | CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */ | |
374 | CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */ | |
375 | CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */ | |
376 | N_CSI_RX_BACKEND_ID | |
377 | } csi_rx_backend_ID_t; | |
378 | ||
379 | typedef enum { | |
380 | CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */ | |
381 | CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */ | |
382 | CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */ | |
383 | #define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID+1) | |
384 | } csi_rx_frontend_ID_t; | |
385 | ||
386 | typedef enum { | |
387 | CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */ | |
388 | CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */ | |
389 | CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */ | |
390 | CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */ | |
391 | N_CSI_RX_DLANE_ID | |
392 | } csi_rx_fe_dlane_ID_t; | |
d929fb4e | 393 | /* end of CSI-MIPI receiver */ |
a49d2536 AC |
394 | |
395 | typedef enum { | |
396 | ISYS2401_DMA0_ID = 0, | |
397 | N_ISYS2401_DMA_ID | |
398 | } isys2401_dma_ID_t; | |
399 | ||
400 | /** | |
401 | * Pixel-generator. ("system_global.h") | |
402 | */ | |
403 | typedef enum { | |
404 | PIXELGEN0_ID = 0, | |
405 | PIXELGEN1_ID, | |
406 | PIXELGEN2_ID, | |
407 | N_PIXELGEN_ID | |
408 | } pixelgen_ID_t; | |
d929fb4e | 409 | /* end of pixel-generator. ("system_global.h") */ |
a49d2536 AC |
410 | |
411 | typedef enum { | |
412 | INPUT_SYSTEM_CSI_PORT0_ID = 0, | |
413 | INPUT_SYSTEM_CSI_PORT1_ID, | |
414 | INPUT_SYSTEM_CSI_PORT2_ID, | |
415 | ||
416 | INPUT_SYSTEM_PIXELGEN_PORT0_ID, | |
417 | INPUT_SYSTEM_PIXELGEN_PORT1_ID, | |
418 | INPUT_SYSTEM_PIXELGEN_PORT2_ID, | |
419 | ||
420 | N_INPUT_SYSTEM_INPUT_PORT_ID | |
421 | } input_system_input_port_ID_t; | |
422 | ||
423 | #define N_INPUT_SYSTEM_CSI_PORT 3 | |
424 | ||
425 | typedef enum { | |
426 | ISYS2401_DMA_CHANNEL_0 = 0, | |
427 | ISYS2401_DMA_CHANNEL_1, | |
428 | ISYS2401_DMA_CHANNEL_2, | |
429 | ISYS2401_DMA_CHANNEL_3, | |
430 | ISYS2401_DMA_CHANNEL_4, | |
431 | ISYS2401_DMA_CHANNEL_5, | |
432 | ISYS2401_DMA_CHANNEL_6, | |
433 | ISYS2401_DMA_CHANNEL_7, | |
434 | ISYS2401_DMA_CHANNEL_8, | |
435 | ISYS2401_DMA_CHANNEL_9, | |
436 | ISYS2401_DMA_CHANNEL_10, | |
437 | ISYS2401_DMA_CHANNEL_11, | |
438 | N_ISYS2401_DMA_CHANNEL | |
439 | } isys2401_dma_channel; | |
440 | ||
441 | enum ia_css_isp_memories { | |
442 | IA_CSS_ISP_PMEM0 = 0, | |
443 | IA_CSS_ISP_DMEM0, | |
444 | IA_CSS_ISP_VMEM0, | |
445 | IA_CSS_ISP_VAMEM0, | |
446 | IA_CSS_ISP_VAMEM1, | |
447 | IA_CSS_ISP_VAMEM2, | |
448 | IA_CSS_ISP_HMEM0, | |
449 | IA_CSS_SP_DMEM0, | |
450 | IA_CSS_DDR, | |
451 | N_IA_CSS_MEMORIES | |
452 | }; | |
453 | #define IA_CSS_NUM_MEMORIES 9 | |
454 | /* For driver compatability */ | |
455 | #define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES | |
456 | #define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES | |
457 | ||
458 | #endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */ |