[mirror_ubuntu-artful-kernel.git] / drivers / staging / rdma / hfi1 / platform.h

/*
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2015 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * BSD LICENSE
 *
 * Copyright(c) 2015 Intel Corporation.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  - Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  - Neither the name of Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#ifndef __PLATFORM_H
#define __PLATFORM_H

#define METADATA_TABLE_FIELD_START_SHIFT		0
#define METADATA_TABLE_FIELD_START_LEN_BITS		15
#define METADATA_TABLE_FIELD_LEN_SHIFT			16
#define METADATA_TABLE_FIELD_LEN_LEN_BITS		16

/* Header structure */
#define PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT			0
#define PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS		6
#define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT		16
#define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS		12
#define PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT			28
#define PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS		4

enum platform_config_table_type_encoding {
	PLATFORM_CONFIG_TABLE_RESERVED,
	PLATFORM_CONFIG_SYSTEM_TABLE,
	PLATFORM_CONFIG_PORT_TABLE,
	PLATFORM_CONFIG_RX_PRESET_TABLE,
	PLATFORM_CONFIG_TX_PRESET_TABLE,
	PLATFORM_CONFIG_QSFP_ATTEN_TABLE,
	PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE,
	PLATFORM_CONFIG_TABLE_MAX
};

enum platform_config_system_table_fields {
	SYSTEM_TABLE_RESERVED,
	SYSTEM_TABLE_NODE_STRING,
	SYSTEM_TABLE_SYSTEM_IMAGE_GUID,
	SYSTEM_TABLE_NODE_GUID,
	SYSTEM_TABLE_REVISION,
	SYSTEM_TABLE_VENDOR_OUI,
	SYSTEM_TABLE_META_VERSION,
	SYSTEM_TABLE_DEVICE_ID,
	SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP,
	SYSTEM_TABLE_QSFP_POWER_CLASS_MAX,
	SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G,
	SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G,
	SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT,
	SYSTEM_TABLE_MAX
};

enum platform_config_port_table_fields {
	PORT_TABLE_RESERVED,
	PORT_TABLE_PORT_TYPE,
	PORT_TABLE_LOCAL_ATTEN_12G,
	PORT_TABLE_LOCAL_ATTEN_25G,
	PORT_TABLE_LINK_SPEED_SUPPORTED,
	PORT_TABLE_LINK_WIDTH_SUPPORTED,
	PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED,
	PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED,
	PORT_TABLE_VL_CAP,
	PORT_TABLE_MTU_CAP,
	PORT_TABLE_TX_LANE_ENABLE_MASK,
	PORT_TABLE_LOCAL_MAX_TIMEOUT,
	PORT_TABLE_REMOTE_ATTEN_12G,
	PORT_TABLE_REMOTE_ATTEN_25G,
	PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ,
	PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ,
	PORT_TABLE_RX_PRESET_IDX,
	PORT_TABLE_CABLE_REACH_CLASS,
	PORT_TABLE_MAX
};

enum platform_config_rx_preset_table_fields {
	RX_PRESET_TABLE_RESERVED,
	RX_PRESET_TABLE_QSFP_RX_CDR_APPLY,
	RX_PRESET_TABLE_QSFP_RX_EMP_APPLY,
	RX_PRESET_TABLE_QSFP_RX_AMP_APPLY,
	RX_PRESET_TABLE_QSFP_RX_CDR,
	RX_PRESET_TABLE_QSFP_RX_EMP,
	RX_PRESET_TABLE_QSFP_RX_AMP,
	RX_PRESET_TABLE_MAX
};

enum platform_config_tx_preset_table_fields {
	TX_PRESET_TABLE_RESERVED,
	TX_PRESET_TABLE_PRECUR,
	TX_PRESET_TABLE_ATTN,
	TX_PRESET_TABLE_POSTCUR,
	TX_PRESET_TABLE_QSFP_TX_CDR_APPLY,
	TX_PRESET_TABLE_QSFP_TX_EQ_APPLY,
	TX_PRESET_TABLE_QSFP_TX_CDR,
	TX_PRESET_TABLE_QSFP_TX_EQ,
	TX_PRESET_TABLE_MAX
};

enum platform_config_qsfp_attn_table_fields {
	QSFP_ATTEN_TABLE_RESERVED,
	QSFP_ATTEN_TABLE_TX_PRESET_IDX,
	QSFP_ATTEN_TABLE_RX_PRESET_IDX,
	QSFP_ATTEN_TABLE_MAX
};

enum platform_config_variable_settings_table_fields {
	VARIABLE_SETTINGS_TABLE_RESERVED,
	VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX,
	VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX,
	VARIABLE_SETTINGS_TABLE_MAX
};

struct platform_config {
	size_t size;
	const u8 *data;
};

struct platform_config_data {
	u32 *table;
	u32 *table_metadata;
	u32 num_table;
};

/*
 * This struct acts as a quick reference into the platform_data binary image
 * and is populated by parse_platform_config(...) depending on the specific
 * META_VERSION
 */
struct platform_config_cache {
	u8  cache_valid;
	struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX];
};

static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
	0,
	SYSTEM_TABLE_MAX,
	PORT_TABLE_MAX,
	RX_PRESET_TABLE_MAX,
	TX_PRESET_TABLE_MAX,
	QSFP_ATTEN_TABLE_MAX,
	VARIABLE_SETTINGS_TABLE_MAX
};

/* This section defines default values and encodings for the
 * fields defined for each table above
 */

/*
 *=====================================================
 *  System table encodings
 *====================================================
 */
#define PLATFORM_CONFIG_MAGIC_NUM		0x3d4f5041
#define PLATFORM_CONFIG_MAGIC_NUMBER_LEN	4

/*
 * These power classes are the same as defined in SFF 8636 spec rev 2.4
 * describing byte 129 in table 6-16, except enumerated in a different order
 */
enum platform_config_qsfp_power_class_encoding {
	QSFP_POWER_CLASS_1 = 1,
	QSFP_POWER_CLASS_2,
	QSFP_POWER_CLASS_3,
	QSFP_POWER_CLASS_4,
	QSFP_POWER_CLASS_5,
	QSFP_POWER_CLASS_6,
	QSFP_POWER_CLASS_7
};

/*
 *=====================================================
 *  Port table encodings
 *====================================================
 */
enum platform_config_port_type_encoding {
	PORT_TYPE_UNKNOWN,
	PORT_TYPE_DISCONNECTED,
	PORT_TYPE_FIXED,
	PORT_TYPE_VARIABLE,
	PORT_TYPE_QSFP,
	PORT_TYPE_MAX
};

enum platform_config_link_speed_supported_encoding {
	LINK_SPEED_SUPP_12G = 1,
	LINK_SPEED_SUPP_25G,
	LINK_SPEED_SUPP_12G_25G,
	LINK_SPEED_SUPP_MAX
};

/*
 * This is a subset (not strict) of the link downgrades
 * supported. The link downgrades supported are expected
 * to be supplied to the driver by another entity such as
 * the fabric manager
 */
enum platform_config_link_width_supported_encoding {
	LINK_WIDTH_SUPP_1X = 1,
	LINK_WIDTH_SUPP_2X,
	LINK_WIDTH_SUPP_2X_1X,
	LINK_WIDTH_SUPP_3X,
	LINK_WIDTH_SUPP_3X_1X,
	LINK_WIDTH_SUPP_3X_2X,
	LINK_WIDTH_SUPP_3X_2X_1X,
	LINK_WIDTH_SUPP_4X,
	LINK_WIDTH_SUPP_4X_1X,
	LINK_WIDTH_SUPP_4X_2X,
	LINK_WIDTH_SUPP_4X_2X_1X,
	LINK_WIDTH_SUPP_4X_3X,
	LINK_WIDTH_SUPP_4X_3X_1X,
	LINK_WIDTH_SUPP_4X_3X_2X,
	LINK_WIDTH_SUPP_4X_3X_2X_1X,
	LINK_WIDTH_SUPP_MAX
};

enum platform_config_virtual_lane_capability_encoding {
	VL_CAP_VL0 = 1,
	VL_CAP_VL0_1,
	VL_CAP_VL0_2,
	VL_CAP_VL0_3,
	VL_CAP_VL0_4,
	VL_CAP_VL0_5,
	VL_CAP_VL0_6,
	VL_CAP_VL0_7,
	VL_CAP_VL0_8,
	VL_CAP_VL0_9,
	VL_CAP_VL0_10,
	VL_CAP_VL0_11,
	VL_CAP_VL0_12,
	VL_CAP_VL0_13,
	VL_CAP_VL0_14,
	VL_CAP_MAX
};

/* Max MTU */
enum platform_config_mtu_capability_encoding {
	MTU_CAP_256   = 1,
	MTU_CAP_512   = 2,
	MTU_CAP_1024  = 3,
	MTU_CAP_2048  = 4,
	MTU_CAP_4096  = 5,
	MTU_CAP_8192  = 6,
	MTU_CAP_10240 = 7
};

enum platform_config_local_max_timeout_encoding {
	LOCAL_MAX_TIMEOUT_10_MS = 1,
	LOCAL_MAX_TIMEOUT_100_MS,
	LOCAL_MAX_TIMEOUT_1_S,
	LOCAL_MAX_TIMEOUT_10_S,
	LOCAL_MAX_TIMEOUT_100_S,
	LOCAL_MAX_TIMEOUT_1000_S
};

enum link_tuning_encoding {
	OPA_PASSIVE_TUNING,
	OPA_ACTIVE_TUNING,
	OPA_UNKNOWN_TUNING
};

/* platform.c */
void get_platform_config(struct hfi1_devdata *dd);
void free_platform_config(struct hfi1_devdata *dd);
int set_qsfp_tx(struct hfi1_pportdata *ppd, int on);
void tune_serdes(struct hfi1_pportdata *ppd);

#endif			/*__PLATFORM_H*/
Commit	Line	Data
77241056 MM	1	/*
	2	*
	3	* This file is provided under a dual BSD/GPLv2 license. When using or
	4	* redistributing this file, you may do so under either license.
	5	*
	6	* GPL LICENSE SUMMARY
	7	*
	8	* Copyright(c) 2015 Intel Corporation.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of version 2 of the GNU General Public License as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* BSD LICENSE
	20	*
	21	* Copyright(c) 2015 Intel Corporation.
	22	*
	23	* Redistribution and use in source and binary forms, with or without
	24	* modification, are permitted provided that the following conditions
	25	* are met:
	26	*
	27	* - Redistributions of source code must retain the above copyright
	28	* notice, this list of conditions and the following disclaimer.
	29	* - Redistributions in binary form must reproduce the above copyright
	30	* notice, this list of conditions and the following disclaimer in
	31	* the documentation and/or other materials provided with the
	32	* distribution.
	33	* - Neither the name of Intel Corporation nor the names of its
	34	* contributors may be used to endorse or promote products derived
	35	* from this software without specific prior written permission.
	36	*
	37	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	38	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	39	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	40	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	41	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	42	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	43	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	44	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	45	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	46	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	47	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	48	*
	49	*/
8ebd4cf1 EH	50	#ifndef __PLATFORM_H
8ebd4cf1 EH	51	#define __PLATFORM_H
77241056 MM	52
	53	#define METADATA_TABLE_FIELD_START_SHIFT 0
	54	#define METADATA_TABLE_FIELD_START_LEN_BITS 15
	55	#define METADATA_TABLE_FIELD_LEN_SHIFT 16
	56	#define METADATA_TABLE_FIELD_LEN_LEN_BITS 16
	57
	58	/* Header structure */
	59	#define PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT 0
	60	#define PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS 6
	61	#define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT 16
	62	#define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS 12
	63	#define PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT 28
	64	#define PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS 4
	65
	66	enum platform_config_table_type_encoding {
	67	PLATFORM_CONFIG_TABLE_RESERVED,
	68	PLATFORM_CONFIG_SYSTEM_TABLE,
	69	PLATFORM_CONFIG_PORT_TABLE,
	70	PLATFORM_CONFIG_RX_PRESET_TABLE,
	71	PLATFORM_CONFIG_TX_PRESET_TABLE,
	72	PLATFORM_CONFIG_QSFP_ATTEN_TABLE,
	73	PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE,
	74	PLATFORM_CONFIG_TABLE_MAX
	75	};
	76
	77	enum platform_config_system_table_fields {
	78	SYSTEM_TABLE_RESERVED,
	79	SYSTEM_TABLE_NODE_STRING,
	80	SYSTEM_TABLE_SYSTEM_IMAGE_GUID,
	81	SYSTEM_TABLE_NODE_GUID,
	82	SYSTEM_TABLE_REVISION,
	83	SYSTEM_TABLE_VENDOR_OUI,
	84	SYSTEM_TABLE_META_VERSION,
	85	SYSTEM_TABLE_DEVICE_ID,
	86	SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP,
	87	SYSTEM_TABLE_QSFP_POWER_CLASS_MAX,
	88	SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G,
	89	SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G,
	90	SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT,
	91	SYSTEM_TABLE_MAX
	92	};
	93
	94	enum platform_config_port_table_fields {
	95	PORT_TABLE_RESERVED,
	96	PORT_TABLE_PORT_TYPE,
8ebd4cf1 EH	97	PORT_TABLE_LOCAL_ATTEN_12G,
8ebd4cf1 EH	98	PORT_TABLE_LOCAL_ATTEN_25G,
77241056 MM	99	PORT_TABLE_LINK_SPEED_SUPPORTED,
77241056 MM	100	PORT_TABLE_LINK_WIDTH_SUPPORTED,
8ebd4cf1 EH	101	PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED,
8ebd4cf1 EH	102	PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED,
77241056 MM	103	PORT_TABLE_VL_CAP,
	104	PORT_TABLE_MTU_CAP,
	105	PORT_TABLE_TX_LANE_ENABLE_MASK,
	106	PORT_TABLE_LOCAL_MAX_TIMEOUT,
8ebd4cf1 EH	107	PORT_TABLE_REMOTE_ATTEN_12G,
8ebd4cf1 EH	108	PORT_TABLE_REMOTE_ATTEN_25G,
77241056 MM	109	PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ,
	110	PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ,
	111	PORT_TABLE_RX_PRESET_IDX,
	112	PORT_TABLE_CABLE_REACH_CLASS,
	113	PORT_TABLE_MAX
	114	};
	115
	116	enum platform_config_rx_preset_table_fields {
	117	RX_PRESET_TABLE_RESERVED,
	118	RX_PRESET_TABLE_QSFP_RX_CDR_APPLY,
8ebd4cf1	119	RX_PRESET_TABLE_QSFP_RX_EMP_APPLY,
77241056 MM	120	RX_PRESET_TABLE_QSFP_RX_AMP_APPLY,
77241056 MM	121	RX_PRESET_TABLE_QSFP_RX_CDR,
8ebd4cf1	122	RX_PRESET_TABLE_QSFP_RX_EMP,
77241056 MM	123	RX_PRESET_TABLE_QSFP_RX_AMP,
	124	RX_PRESET_TABLE_MAX
	125	};
	126
	127	enum platform_config_tx_preset_table_fields {
	128	TX_PRESET_TABLE_RESERVED,
	129	TX_PRESET_TABLE_PRECUR,
	130	TX_PRESET_TABLE_ATTN,
	131	TX_PRESET_TABLE_POSTCUR,
	132	TX_PRESET_TABLE_QSFP_TX_CDR_APPLY,
	133	TX_PRESET_TABLE_QSFP_TX_EQ_APPLY,
	134	TX_PRESET_TABLE_QSFP_TX_CDR,
	135	TX_PRESET_TABLE_QSFP_TX_EQ,
	136	TX_PRESET_TABLE_MAX
	137	};
	138
	139	enum platform_config_qsfp_attn_table_fields {
	140	QSFP_ATTEN_TABLE_RESERVED,
	141	QSFP_ATTEN_TABLE_TX_PRESET_IDX,
	142	QSFP_ATTEN_TABLE_RX_PRESET_IDX,
	143	QSFP_ATTEN_TABLE_MAX
	144	};
	145
	146	enum platform_config_variable_settings_table_fields {
	147	VARIABLE_SETTINGS_TABLE_RESERVED,
	148	VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX,
	149	VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX,
	150	VARIABLE_SETTINGS_TABLE_MAX
	151	};
	152
c3838b39 EH	153	struct platform_config {
	154	size_t size;
	155	const u8 *data;
	156	};
	157
77241056 MM	158	struct platform_config_data {
	159	u32 *table;
	160	u32 *table_metadata;
	161	u32 num_table;
	162	};
	163
	164	/*
	165	* This struct acts as a quick reference into the platform_data binary image
	166	* and is populated by parse_platform_config(...) depending on the specific
	167	* META_VERSION
	168	*/
	169	struct platform_config_cache {
	170	u8 cache_valid;
	171	struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX];
	172	};
	173
	174	static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
	175	0,
	176	SYSTEM_TABLE_MAX,
	177	PORT_TABLE_MAX,
	178	RX_PRESET_TABLE_MAX,
	179	TX_PRESET_TABLE_MAX,
	180	QSFP_ATTEN_TABLE_MAX,
	181	VARIABLE_SETTINGS_TABLE_MAX
	182	};
	183
	184	/* This section defines default values and encodings for the
	185	* fields defined for each table above
	186	*/
	187
8ebd4cf1 EH	188	/*
8ebd4cf1 EH	189	*=====================================================
77241056	190	* System table encodings
8ebd4cf1 EH	191	*====================================================
8ebd4cf1 EH	192	*/
77241056 MM	193	#define PLATFORM_CONFIG_MAGIC_NUM 0x3d4f5041
	194	#define PLATFORM_CONFIG_MAGIC_NUMBER_LEN 4
	195
	196	/*
	197	* These power classes are the same as defined in SFF 8636 spec rev 2.4
	198	* describing byte 129 in table 6-16, except enumerated in a different order
	199	*/
	200	enum platform_config_qsfp_power_class_encoding {
	201	QSFP_POWER_CLASS_1 = 1,
	202	QSFP_POWER_CLASS_2,
	203	QSFP_POWER_CLASS_3,
	204	QSFP_POWER_CLASS_4,
	205	QSFP_POWER_CLASS_5,
	206	QSFP_POWER_CLASS_6,
	207	QSFP_POWER_CLASS_7
	208	};
	209
8ebd4cf1 EH	210	/*
8ebd4cf1 EH	211	*=====================================================
77241056	212	* Port table encodings
8ebd4cf1 EH	213	*====================================================
8ebd4cf1 EH	214	*/
77241056	215	enum platform_config_port_type_encoding {
8ebd4cf1	216	PORT_TYPE_UNKNOWN,
77241056 MM	217	PORT_TYPE_DISCONNECTED,
	218	PORT_TYPE_FIXED,
	219	PORT_TYPE_VARIABLE,
	220	PORT_TYPE_QSFP,
	221	PORT_TYPE_MAX
	222	};
	223
	224	enum platform_config_link_speed_supported_encoding {
	225	LINK_SPEED_SUPP_12G = 1,
	226	LINK_SPEED_SUPP_25G,
	227	LINK_SPEED_SUPP_12G_25G,
	228	LINK_SPEED_SUPP_MAX
	229	};
	230
	231	/*
	232	* This is a subset (not strict) of the link downgrades
	233	* supported. The link downgrades supported are expected
	234	* to be supplied to the driver by another entity such as
	235	* the fabric manager
	236	*/
	237	enum platform_config_link_width_supported_encoding {
	238	LINK_WIDTH_SUPP_1X = 1,
	239	LINK_WIDTH_SUPP_2X,
	240	LINK_WIDTH_SUPP_2X_1X,
	241	LINK_WIDTH_SUPP_3X,
	242	LINK_WIDTH_SUPP_3X_1X,
	243	LINK_WIDTH_SUPP_3X_2X,
	244	LINK_WIDTH_SUPP_3X_2X_1X,
	245	LINK_WIDTH_SUPP_4X,
	246	LINK_WIDTH_SUPP_4X_1X,
	247	LINK_WIDTH_SUPP_4X_2X,
	248	LINK_WIDTH_SUPP_4X_2X_1X,
	249	LINK_WIDTH_SUPP_4X_3X,
	250	LINK_WIDTH_SUPP_4X_3X_1X,
	251	LINK_WIDTH_SUPP_4X_3X_2X,
	252	LINK_WIDTH_SUPP_4X_3X_2X_1X,
	253	LINK_WIDTH_SUPP_MAX
	254	};
	255
	256	enum platform_config_virtual_lane_capability_encoding {
	257	VL_CAP_VL0 = 1,
	258	VL_CAP_VL0_1,
	259	VL_CAP_VL0_2,
	260	VL_CAP_VL0_3,
	261	VL_CAP_VL0_4,
	262	VL_CAP_VL0_5,
	263	VL_CAP_VL0_6,
	264	VL_CAP_VL0_7,
	265	VL_CAP_VL0_8,
	266	VL_CAP_VL0_9,
	267	VL_CAP_VL0_10,
	268	VL_CAP_VL0_11,
	269	VL_CAP_VL0_12,
	270	VL_CAP_VL0_13,
	271	VL_CAP_VL0_14,
	272	VL_CAP_MAX
	273	};
	274
	275	/* Max MTU */
	276	enum platform_config_mtu_capability_encoding {
	277	MTU_CAP_256 = 1,
	278	MTU_CAP_512 = 2,
	279	MTU_CAP_1024 = 3,
	280	MTU_CAP_2048 = 4,
281	MTU_CAP_4096 = 5,
282	MTU_CAP_8192 = 6,
283	MTU_CAP_10240 = 7
284	};
285
286	enum platform_config_local_max_timeout_encoding {
287	LOCAL_MAX_TIMEOUT_10_MS = 1,
288	LOCAL_MAX_TIMEOUT_100_MS,
289	LOCAL_MAX_TIMEOUT_1_S,
290	LOCAL_MAX_TIMEOUT_10_S,
291	LOCAL_MAX_TIMEOUT_100_S,
292	LOCAL_MAX_TIMEOUT_1000_S
293	};
294
8ebd4cf1 EH	295	enum link_tuning_encoding {
	296	OPA_PASSIVE_TUNING,
	297	OPA_ACTIVE_TUNING,
	298	OPA_UNKNOWN_TUNING
	299	};
	300
c3838b39 EH	301	/* platform.c */
	302	void get_platform_config(struct hfi1_devdata *dd);
	303	void free_platform_config(struct hfi1_devdata *dd);
8ebd4cf1 EH	304	int set_qsfp_tx(struct hfi1_pportdata *ppd, int on);
8ebd4cf1 EH	305	void tune_serdes(struct hfi1_pportdata *ppd);
c3838b39	306
8ebd4cf1	307	#endif /__PLATFORM_H/