]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/tty/serial/msm_serial.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
msm_serial: Fix NUL byte output on UARTDM
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / msm_serial.c
CommitLineData
04896a77 1/*
99edb3d1 2 * Driver for msm7k serial device and console
04896a77
RL		 3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
ec8f29e7 6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
04896a77
RL		 7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19# define SUPPORT_SYSRQ
20#endif
21
cfdad2ab 22#include <linux/atomic.h>
04896a77
RL		 23#include <linux/hrtimer.h>
24#include <linux/module.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/irq.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/clk.h>
35#include <linux/platform_device.h>
ec8f29e7 36#include <linux/delay.h>
cfdad2ab
DB		 37#include <linux/of.h>
38#include <linux/of_device.h>
04896a77
RL		 39
40#include "msm_serial.h"
41
42struct msm_port {
43 struct uart_port uart;
44 char name[16];
45 struct clk *clk;
ec8f29e7 46 struct clk *pclk;
04896a77 47 unsigned int imr;
ec8f29e7
SM		 48 unsigned int *gsbi_base;
49 int is_uartdm;
50 unsigned int old_snap_state;
04896a77
RL		 51};
52
4a5662d6 53static inline void wait_for_xmitr(struct uart_port *port)
ec8f29e7 54{
4a5662d6
SB		 55 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
56 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
57 break;
58 udelay(1);
59 }
60 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
ec8f29e7
SM		 61}
62
04896a77
RL		 63static void msm_stop_tx(struct uart_port *port)
64{
65 struct msm_port *msm_port = UART_TO_MSM(port);
66
67 msm_port->imr &= ~UART_IMR_TXLEV;
68 msm_write(port, msm_port->imr, UART_IMR);
69}
70
71static void msm_start_tx(struct uart_port *port)
72{
73 struct msm_port *msm_port = UART_TO_MSM(port);
74
75 msm_port->imr |= UART_IMR_TXLEV;
76 msm_write(port, msm_port->imr, UART_IMR);
77}
78
79static void msm_stop_rx(struct uart_port *port)
80{
81 struct msm_port *msm_port = UART_TO_MSM(port);
82
83 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
84 msm_write(port, msm_port->imr, UART_IMR);
85}
86
87static void msm_enable_ms(struct uart_port *port)
88{
89 struct msm_port *msm_port = UART_TO_MSM(port);
90
91 msm_port->imr |= UART_IMR_DELTA_CTS;
92 msm_write(port, msm_port->imr, UART_IMR);
93}
94
ec8f29e7
SM		 95static void handle_rx_dm(struct uart_port *port, unsigned int misr)
96{
92a19f9c 97 struct tty_port *tport = &port->state->port;
ec8f29e7
SM		 98 unsigned int sr;
99 int count = 0;
100 struct msm_port *msm_port = UART_TO_MSM(port);
101
102 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
103 port->icount.overrun++;
92a19f9c 104 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
ec8f29e7
SM		 105 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
106 }
107
108 if (misr & UART_IMR_RXSTALE) {
109 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
110 msm_port->old_snap_state;
111 msm_port->old_snap_state = 0;
112 } else {
113 count = 4 * (msm_read(port, UART_RFWR));
114 msm_port->old_snap_state += count;
115 }
116
117 /* TODO: Precise error reporting */
118
119 port->icount.rx += count;
120
121 while (count > 0) {
122 unsigned int c;
123
124 sr = msm_read(port, UART_SR);
125 if ((sr & UART_SR_RX_READY) == 0) {
126 msm_port->old_snap_state -= count;
127 break;
128 }
129 c = msm_read(port, UARTDM_RF);
130 if (sr & UART_SR_RX_BREAK) {
131 port->icount.brk++;
132 if (uart_handle_break(port))
133 continue;
134 } else if (sr & UART_SR_PAR_FRAME_ERR)
135 port->icount.frame++;
136
137 /* TODO: handle sysrq */
05c7cd39 138 tty_insert_flip_string(tport, (char *)&c,
ec8f29e7
SM		 139 (count > 4) ? 4 : count);
140 count -= 4;
141 }
142
2e124b4a 143 tty_flip_buffer_push(tport);
ec8f29e7
SM		 144 if (misr & (UART_IMR_RXSTALE))
145 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
146 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
147 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
148}
149
04896a77
RL		 150static void handle_rx(struct uart_port *port)
151{
92a19f9c 152 struct tty_port *tport = &port->state->port;
04896a77
RL		 153 unsigned int sr;
154
155 /*
156 * Handle overrun. My understanding of the hardware is that overrun
157 * is not tied to the RX buffer, so we handle the case out of band.
158 */
159 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
160 port->icount.overrun++;
92a19f9c 161 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
04896a77
RL		 162 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
163 }
164
165 /* and now the main RX loop */
166 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
167 unsigned int c;
168 char flag = TTY_NORMAL;
169
170 c = msm_read(port, UART_RF);
171
172 if (sr & UART_SR_RX_BREAK) {
173 port->icount.brk++;
174 if (uart_handle_break(port))
175 continue;
176 } else if (sr & UART_SR_PAR_FRAME_ERR) {
177 port->icount.frame++;
178 } else {
179 port->icount.rx++;
180 }
181
182 /* Mask conditions we're ignorning. */
183 sr &= port->read_status_mask;
184
185 if (sr & UART_SR_RX_BREAK) {
186 flag = TTY_BREAK;
187 } else if (sr & UART_SR_PAR_FRAME_ERR) {
188 flag = TTY_FRAME;
189 }
190
191 if (!uart_handle_sysrq_char(port, c))
92a19f9c 192 tty_insert_flip_char(tport, c, flag);
04896a77
RL		 193 }
194
2e124b4a 195 tty_flip_buffer_push(tport);
04896a77
RL		 196}
197
ec8f29e7
SM		 198static void reset_dm_count(struct uart_port *port)
199{
4a5662d6 200 wait_for_xmitr(port);
ec8f29e7 201 msm_write(port, 1, UARTDM_NCF_TX);
4a5662d6 202 msm_read(port, UARTDM_NCF_TX);
ec8f29e7
SM		 203}
204
04896a77
RL		 205static void handle_tx(struct uart_port *port)
206{
ebd2c8f6 207 struct circ_buf *xmit = &port->state->xmit;
04896a77
RL		 208 struct msm_port *msm_port = UART_TO_MSM(port);
209 int sent_tx;
210
211 if (port->x_char) {
ec8f29e7
SM		 212 if (msm_port->is_uartdm)
213 reset_dm_count(port);
214
215 msm_write(port, port->x_char,
216 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
04896a77
RL		 217 port->icount.tx++;
218 port->x_char = 0;
219 }
220
ec8f29e7
SM		 221 if (msm_port->is_uartdm)
222 reset_dm_count(port);
223
04896a77
RL		 224 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
225 if (uart_circ_empty(xmit)) {
226 /* disable tx interrupts */
227 msm_port->imr &= ~UART_IMR_TXLEV;
228 msm_write(port, msm_port->imr, UART_IMR);
229 break;
230 }
ec8f29e7
SM		 231 msm_write(port, xmit->buf[xmit->tail],
232 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
04896a77 233
ec8f29e7
SM		 234 if (msm_port->is_uartdm)
235 reset_dm_count(port);
04896a77
RL		 236
237 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
238 port->icount.tx++;
239 sent_tx = 1;
240 }
241
242 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
243 uart_write_wakeup(port);
244}
245
246static void handle_delta_cts(struct uart_port *port)
247{
248 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
249 port->icount.cts++;
bdc04e31 250 wake_up_interruptible(&port->state->port.delta_msr_wait);
04896a77
RL		 251}
252
253static irqreturn_t msm_irq(int irq, void *dev_id)
254{
255 struct uart_port *port = dev_id;
256 struct msm_port *msm_port = UART_TO_MSM(port);
257 unsigned int misr;
258
259 spin_lock(&port->lock);
260 misr = msm_read(port, UART_MISR);
261 msm_write(port, 0, UART_IMR); /* disable interrupt */
262
ec8f29e7
SM		 263 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
264 if (msm_port->is_uartdm)
265 handle_rx_dm(port, misr);
266 else
267 handle_rx(port);
268 }
04896a77
RL		 269 if (misr & UART_IMR_TXLEV)
270 handle_tx(port);
271 if (misr & UART_IMR_DELTA_CTS)
272 handle_delta_cts(port);
273
274 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
275 spin_unlock(&port->lock);
276
277 return IRQ_HANDLED;
278}
279
280static unsigned int msm_tx_empty(struct uart_port *port)
281{
282 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
283}
284
285static unsigned int msm_get_mctrl(struct uart_port *port)
286{
287 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
288}
289
ec8f29e7
SM		 290
291static void msm_reset(struct uart_port *port)
04896a77 292{
ec8f29e7
SM		 293 /* reset everything */
294 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
295 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
296 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
297 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
298 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
299 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
300}
04896a77 301
ec8f29e7
SM		 302void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
303{
304 unsigned int mr;
04896a77
RL		 305 mr = msm_read(port, UART_MR1);
306
307 if (!(mctrl & TIOCM_RTS)) {
308 mr &= ~UART_MR1_RX_RDY_CTL;
309 msm_write(port, mr, UART_MR1);
310 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
311 } else {
312 mr |= UART_MR1_RX_RDY_CTL;
313 msm_write(port, mr, UART_MR1);
314 }
315}
316
317static void msm_break_ctl(struct uart_port *port, int break_ctl)
318{
319 if (break_ctl)
320 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
321 else
322 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
323}
324
44da59e4 325static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
04896a77
RL		 326{
327 unsigned int baud_code, rxstale, watermark;
ec8f29e7 328 struct msm_port *msm_port = UART_TO_MSM(port);
04896a77
RL		 329
330 switch (baud) {
331 case 300:
332 baud_code = UART_CSR_300;
333 rxstale = 1;
334 break;
335 case 600:
336 baud_code = UART_CSR_600;
337 rxstale = 1;
338 break;
339 case 1200:
340 baud_code = UART_CSR_1200;
341 rxstale = 1;
342 break;
343 case 2400:
344 baud_code = UART_CSR_2400;
345 rxstale = 1;
346 break;
347 case 4800:
348 baud_code = UART_CSR_4800;
349 rxstale = 1;
350 break;
351 case 9600:
352 baud_code = UART_CSR_9600;
353 rxstale = 2;
354 break;
355 case 14400:
356 baud_code = UART_CSR_14400;
357 rxstale = 3;
358 break;
359 case 19200:
360 baud_code = UART_CSR_19200;
361 rxstale = 4;
362 break;
363 case 28800:
364 baud_code = UART_CSR_28800;
365 rxstale = 6;
366 break;
367 case 38400:
368 baud_code = UART_CSR_38400;
369 rxstale = 8;
370 break;
371 case 57600:
372 baud_code = UART_CSR_57600;
373 rxstale = 16;
374 break;
375 case 115200:
376 default:
377 baud_code = UART_CSR_115200;
44da59e4 378 baud = 115200;
04896a77
RL		 379 rxstale = 31;
380 break;
381 }
382
ec8f29e7
SM		 383 if (msm_port->is_uartdm)
384 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
385
04896a77
RL		 386 msm_write(port, baud_code, UART_CSR);
387
388 /* RX stale watermark */
389 watermark = UART_IPR_STALE_LSB & rxstale;
390 watermark |= UART_IPR_RXSTALE_LAST;
391 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
392 msm_write(port, watermark, UART_IPR);
393
394 /* set RX watermark */
395 watermark = (port->fifosize * 3) / 4;
396 msm_write(port, watermark, UART_RFWR);
397
398 /* set TX watermark */
399 msm_write(port, 10, UART_TFWR);
44da59e4 400
ec8f29e7
SM		 401 if (msm_port->is_uartdm) {
402 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
403 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
404 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
405 }
406
44da59e4 407 return baud;
04896a77
RL		 408}
409
04896a77
RL		 410
411static void msm_init_clock(struct uart_port *port)
412{
413 struct msm_port *msm_port = UART_TO_MSM(port);
414
f98cf83d 415 clk_prepare_enable(msm_port->clk);
ec8f29e7 416 if (!IS_ERR(msm_port->pclk))
f98cf83d 417 clk_prepare_enable(msm_port->pclk);
18c79d76 418 msm_serial_set_mnd_regs(port);
04896a77
RL		 419}
420
421static int msm_startup(struct uart_port *port)
422{
423 struct msm_port *msm_port = UART_TO_MSM(port);
424 unsigned int data, rfr_level;
425 int ret;
426
427 snprintf(msm_port->name, sizeof(msm_port->name),
428 "msm_serial%d", port->line);
429
430 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
431 msm_port->name, port);
432 if (unlikely(ret))
433 return ret;
434
435 msm_init_clock(port);
436
437 if (likely(port->fifosize > 12))
438 rfr_level = port->fifosize - 12;
439 else
440 rfr_level = port->fifosize;
441
442 /* set automatic RFR level */
443 data = msm_read(port, UART_MR1);
444 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
445 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
446 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
447 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
448 msm_write(port, data, UART_MR1);
449
450 /* make sure that RXSTALE count is non-zero */
451 data = msm_read(port, UART_IPR);
452 if (unlikely(!data)) {
453 data |= UART_IPR_RXSTALE_LAST;
454 data |= UART_IPR_STALE_LSB;
455 msm_write(port, data, UART_IPR);
456 }
457
ec8f29e7
SM		 458 data = 0;
459 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
460 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
461 msm_reset(port);
462 data = UART_CR_TX_ENABLE;
463 }
464
465 data |= UART_CR_RX_ENABLE;
466 msm_write(port, data, UART_CR); /* enable TX & RX */
04896a77 467
ec8f29e7
SM		 468 /* Make sure IPR is not 0 to start with*/
469 if (msm_port->is_uartdm)
470 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
04896a77
RL		 471
472 /* turn on RX and CTS interrupts */
473 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
474 UART_IMR_CURRENT_CTS;
04896a77 475
ec8f29e7
SM		 476 if (msm_port->is_uartdm) {
477 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
478 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
479 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
480 }
481
482 msm_write(port, msm_port->imr, UART_IMR);
04896a77
RL		 483 return 0;
484}
485
486static void msm_shutdown(struct uart_port *port)
487{
488 struct msm_port *msm_port = UART_TO_MSM(port);
489
490 msm_port->imr = 0;
491 msm_write(port, 0, UART_IMR); /* disable interrupts */
492
f98cf83d 493 clk_disable_unprepare(msm_port->clk);
04896a77
RL		 494
495 free_irq(port->irq, port);
496}
497
498static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
499 struct ktermios *old)
500{
501 unsigned long flags;
502 unsigned int baud, mr;
503
504 spin_lock_irqsave(&port->lock, flags);
505
506 /* calculate and set baud rate */
507 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
44da59e4
AC		 508 baud = msm_set_baud_rate(port, baud);
509 if (tty_termios_baud_rate(termios))
510 tty_termios_encode_baud_rate(termios, baud, baud);
ec8f29e7 511
04896a77
RL		 512 /* calculate parity */
513 mr = msm_read(port, UART_MR2);
514 mr &= ~UART_MR2_PARITY_MODE;
515 if (termios->c_cflag & PARENB) {
516 if (termios->c_cflag & PARODD)
517 mr |= UART_MR2_PARITY_MODE_ODD;
518 else if (termios->c_cflag & CMSPAR)
519 mr |= UART_MR2_PARITY_MODE_SPACE;
520 else
521 mr |= UART_MR2_PARITY_MODE_EVEN;
522 }
523
524 /* calculate bits per char */
525 mr &= ~UART_MR2_BITS_PER_CHAR;
526 switch (termios->c_cflag & CSIZE) {
527 case CS5:
528 mr |= UART_MR2_BITS_PER_CHAR_5;
529 break;
530 case CS6:
531 mr |= UART_MR2_BITS_PER_CHAR_6;
532 break;
533 case CS7:
534 mr |= UART_MR2_BITS_PER_CHAR_7;
535 break;
536 case CS8:
537 default:
538 mr |= UART_MR2_BITS_PER_CHAR_8;
539 break;
540 }
541
542 /* calculate stop bits */
543 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
544 if (termios->c_cflag & CSTOPB)
545 mr |= UART_MR2_STOP_BIT_LEN_TWO;
546 else
547 mr |= UART_MR2_STOP_BIT_LEN_ONE;
548
549 /* set parity, bits per char, and stop bit */
550 msm_write(port, mr, UART_MR2);
551
552 /* calculate and set hardware flow control */
553 mr = msm_read(port, UART_MR1);
554 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
555 if (termios->c_cflag & CRTSCTS) {
556 mr |= UART_MR1_CTS_CTL;
557 mr |= UART_MR1_RX_RDY_CTL;
558 }
559 msm_write(port, mr, UART_MR1);
560
561 /* Configure status bits to ignore based on termio flags. */
562 port->read_status_mask = 0;
563 if (termios->c_iflag & INPCK)
564 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
565 if (termios->c_iflag & (BRKINT | PARMRK))
566 port->read_status_mask |= UART_SR_RX_BREAK;
567
568 uart_update_timeout(port, termios->c_cflag, baud);
569
570 spin_unlock_irqrestore(&port->lock, flags);
571}
572
573static const char *msm_type(struct uart_port *port)
574{
575 return "MSM";
576}
577
578static void msm_release_port(struct uart_port *port)
579{
580 struct platform_device *pdev = to_platform_device(port->dev);
ec8f29e7
SM		 581 struct msm_port *msm_port = UART_TO_MSM(port);
582 struct resource *uart_resource;
583 struct resource *gsbi_resource;
04896a77
RL		 584 resource_size_t size;
585
ec8f29e7
SM		 586 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
587 if (unlikely(!uart_resource))
04896a77 588 return;
ec8f29e7 589 size = resource_size(uart_resource);
04896a77
RL		 590
591 release_mem_region(port->mapbase, size);
592 iounmap(port->membase);
593 port->membase = NULL;
ec8f29e7
SM		 594
595 if (msm_port->gsbi_base) {
596 iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
597 GSBI_CONTROL);
598
886a451b
DB		 599 gsbi_resource = platform_get_resource(pdev,
600 IORESOURCE_MEM, 1);
ec8f29e7
SM		 601
602 if (unlikely(!gsbi_resource))
603 return;
604
605 size = resource_size(gsbi_resource);
606 release_mem_region(gsbi_resource->start, size);
607 iounmap(msm_port->gsbi_base);
608 msm_port->gsbi_base = NULL;
609 }
04896a77
RL		 610}
611
612static int msm_request_port(struct uart_port *port)
613{
ec8f29e7 614 struct msm_port *msm_port = UART_TO_MSM(port);
04896a77 615 struct platform_device *pdev = to_platform_device(port->dev);
ec8f29e7
SM		 616 struct resource *uart_resource;
617 struct resource *gsbi_resource;
04896a77 618 resource_size_t size;
ec8f29e7 619 int ret;
04896a77 620
886a451b 621 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ec8f29e7 622 if (unlikely(!uart_resource))
04896a77 623 return -ENXIO;
04896a77 624
ec8f29e7
SM		 625 size = resource_size(uart_resource);
626
627 if (!request_mem_region(port->mapbase, size, "msm_serial"))
04896a77
RL		 628 return -EBUSY;
629
630 port->membase = ioremap(port->mapbase, size);
631 if (!port->membase) {
ec8f29e7
SM		 632 ret = -EBUSY;
633 goto fail_release_port;
634 }
635
886a451b 636 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
ec8f29e7
SM		 637 /* Is this a GSBI-based port? */
638 if (gsbi_resource) {
639 size = resource_size(gsbi_resource);
640
641 if (!request_mem_region(gsbi_resource->start, size,
642 "msm_serial")) {
643 ret = -EBUSY;
195be84a 644 goto fail_release_port_membase;
ec8f29e7
SM		 645 }
646
647 msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
648 if (!msm_port->gsbi_base) {
649 ret = -EBUSY;
650 goto fail_release_gsbi;
651 }
04896a77
RL		 652 }
653
654 return 0;
ec8f29e7
SM		 655
656fail_release_gsbi:
657 release_mem_region(gsbi_resource->start, size);
195be84a
WY		 658fail_release_port_membase:
659 iounmap(port->membase);
ec8f29e7
SM		 660fail_release_port:
661 release_mem_region(port->mapbase, size);
662 return ret;
04896a77
RL		 663}
664
665static void msm_config_port(struct uart_port *port, int flags)
666{
ec8f29e7
SM		 667 struct msm_port *msm_port = UART_TO_MSM(port);
668 int ret;
04896a77
RL		 669 if (flags & UART_CONFIG_TYPE) {
670 port->type = PORT_MSM;
ec8f29e7
SM		 671 ret = msm_request_port(port);
672 if (ret)
673 return;
04896a77 674 }
ec8f29e7
SM		 675
676 if (msm_port->is_uartdm)
677 iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base +
678 GSBI_CONTROL);
04896a77
RL		 679}
680
681static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
682{
683 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
684 return -EINVAL;
685 if (unlikely(port->irq != ser->irq))
686 return -EINVAL;
687 return 0;
688}
689
690static void msm_power(struct uart_port *port, unsigned int state,
691 unsigned int oldstate)
692{
693 struct msm_port *msm_port = UART_TO_MSM(port);
694
695 switch (state) {
696 case 0:
f98cf83d 697 clk_prepare_enable(msm_port->clk);
ec8f29e7 698 if (!IS_ERR(msm_port->pclk))
f98cf83d 699 clk_prepare_enable(msm_port->pclk);
04896a77
RL		 700 break;
701 case 3:
f98cf83d 702 clk_disable_unprepare(msm_port->clk);
ec8f29e7 703 if (!IS_ERR(msm_port->pclk))
f98cf83d 704 clk_disable_unprepare(msm_port->pclk);
04896a77
RL		 705 break;
706 default:
707 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
708 }
709}
710
711static struct uart_ops msm_uart_pops = {
712 .tx_empty = msm_tx_empty,
713 .set_mctrl = msm_set_mctrl,
714 .get_mctrl = msm_get_mctrl,
715 .stop_tx = msm_stop_tx,
716 .start_tx = msm_start_tx,
717 .stop_rx = msm_stop_rx,
718 .enable_ms = msm_enable_ms,
719 .break_ctl = msm_break_ctl,
720 .startup = msm_startup,
721 .shutdown = msm_shutdown,
722 .set_termios = msm_set_termios,
723 .type = msm_type,
724 .release_port = msm_release_port,
725 .request_port = msm_request_port,
726 .config_port = msm_config_port,
727 .verify_port = msm_verify_port,
728 .pm = msm_power,
729};
730
731static struct msm_port msm_uart_ports[] = {
732 {
733 .uart = {
734 .iotype = UPIO_MEM,
735 .ops = &msm_uart_pops,
736 .flags = UPF_BOOT_AUTOCONF,
ec8f29e7 737 .fifosize = 64,
04896a77
RL		 738 .line = 0,
739 },
740 },
741 {
742 .uart = {
743 .iotype = UPIO_MEM,
744 .ops = &msm_uart_pops,
745 .flags = UPF_BOOT_AUTOCONF,
ec8f29e7 746 .fifosize = 64,
04896a77
RL		 747 .line = 1,
748 },
749 },
750 {
751 .uart = {
752 .iotype = UPIO_MEM,
753 .ops = &msm_uart_pops,
754 .flags = UPF_BOOT_AUTOCONF,
755 .fifosize = 64,
756 .line = 2,
757 },
758 },
759};
760
761#define UART_NR ARRAY_SIZE(msm_uart_ports)
762
763static inline struct uart_port *get_port_from_line(unsigned int line)
764{
765 return &msm_uart_ports[line].uart;
766}
767
768#ifdef CONFIG_SERIAL_MSM_CONSOLE
769
770static void msm_console_putchar(struct uart_port *port, int c)
771{
ec8f29e7
SM		 772 struct msm_port *msm_port = UART_TO_MSM(port);
773
774 if (msm_port->is_uartdm)
775 reset_dm_count(port);
776
04896a77
RL		 777 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
778 ;
ec8f29e7 779 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
04896a77
RL		 780}
781
782static void msm_console_write(struct console *co, const char *s,
783 unsigned int count)
784{
785 struct uart_port *port;
786 struct msm_port *msm_port;
787
788 BUG_ON(co->index < 0 || co->index >= UART_NR);
789
790 port = get_port_from_line(co->index);
791 msm_port = UART_TO_MSM(port);
792
793 spin_lock(&port->lock);
794 uart_console_write(port, s, count, msm_console_putchar);
795 spin_unlock(&port->lock);
796}
797
798static int __init msm_console_setup(struct console *co, char *options)
799{
800 struct uart_port *port;
ec8f29e7 801 struct msm_port *msm_port;
04896a77
RL		 802 int baud, flow, bits, parity;
803
804 if (unlikely(co->index >= UART_NR || co->index < 0))
805 return -ENXIO;
806
807 port = get_port_from_line(co->index);
ec8f29e7 808 msm_port = UART_TO_MSM(port);
04896a77
RL		 809
810 if (unlikely(!port->membase))
811 return -ENXIO;
812
04896a77
RL		 813 msm_init_clock(port);
814
815 if (options)
816 uart_parse_options(options, &baud, &parity, &bits, &flow);
817
818 bits = 8;
819 parity = 'n';
820 flow = 'n';
821 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
822 UART_MR2); /* 8N1 */
823
824 if (baud < 300 || baud > 115200)
825 baud = 115200;
826 msm_set_baud_rate(port, baud);
827
828 msm_reset(port);
829
ec8f29e7
SM		 830 if (msm_port->is_uartdm) {
831 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
832 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
833 }
834
04896a77
RL		 835 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
836
837 return uart_set_options(port, co, baud, parity, bits, flow);
838}
839
840static struct uart_driver msm_uart_driver;
841
842static struct console msm_console = {
843 .name = "ttyMSM",
844 .write = msm_console_write,
845 .device = uart_console_device,
846 .setup = msm_console_setup,
847 .flags = CON_PRINTBUFFER,
848 .index = -1,
849 .data = &msm_uart_driver,
850};
851
852#define MSM_CONSOLE (&msm_console)
853
854#else
855#define MSM_CONSOLE NULL
856#endif
857
858static struct uart_driver msm_uart_driver = {
859 .owner = THIS_MODULE,
860 .driver_name = "msm_serial",
861 .dev_name = "ttyMSM",
862 .nr = UART_NR,
863 .cons = MSM_CONSOLE,
864};
865
cfdad2ab
DB		 866static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
867
04896a77
RL		 868static int __init msm_serial_probe(struct platform_device *pdev)
869{
870 struct msm_port *msm_port;
871 struct resource *resource;
872 struct uart_port *port;
1e091751 873 int irq;
04896a77 874
cfdad2ab
DB		 875 if (pdev->id == -1)
876 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
877
04896a77
RL		 878 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
879 return -ENXIO;
880
881 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
882
883 port = get_port_from_line(pdev->id);
884 port->dev = &pdev->dev;
885 msm_port = UART_TO_MSM(port);
886
886a451b 887 if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
ec8f29e7
SM		 888 msm_port->is_uartdm = 1;
889 else
890 msm_port->is_uartdm = 0;
891
892 if (msm_port->is_uartdm) {
519b371d
SB		 893 msm_port->clk = devm_clk_get(&pdev->dev, "gsbi_uart_clk");
894 msm_port->pclk = devm_clk_get(&pdev->dev, "gsbi_pclk");
ec8f29e7 895 } else {
519b371d 896 msm_port->clk = devm_clk_get(&pdev->dev, "uart_clk");
ec8f29e7
SM		 897 msm_port->pclk = ERR_PTR(-ENOENT);
898 }
899
519b371d
SB		 900 if (IS_ERR(msm_port->clk))
901 return PTR_ERR(msm_port->clk);
902
903 if (msm_port->is_uartdm) {
904 if (IS_ERR(msm_port->pclk))
905 return PTR_ERR(msm_port->pclk);
ec8f29e7 906
7b6031a7 907 clk_set_rate(msm_port->clk, 1843200);
519b371d 908 }
ec8f29e7 909
04896a77 910 port->uartclk = clk_get_rate(msm_port->clk);
18c79d76
AD		 911 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
912
04896a77 913
886a451b 914 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
04896a77
RL		 915 if (unlikely(!resource))
916 return -ENXIO;
917 port->mapbase = resource->start;
918
1e091751
RK		 919 irq = platform_get_irq(pdev, 0);
920 if (unlikely(irq < 0))
04896a77 921 return -ENXIO;
1e091751 922 port->irq = irq;
04896a77
RL		 923
924 platform_set_drvdata(pdev, port);
925
926 return uart_add_one_port(&msm_uart_driver, port);
927}
928
ae8d8a14 929static int msm_serial_remove(struct platform_device *pdev)
04896a77 930{
519b371d 931 struct uart_port *port = platform_get_drvdata(pdev);
04896a77 932
519b371d 933 uart_remove_one_port(&msm_uart_driver, port);
04896a77
RL		 934
935 return 0;
936}
937
cfdad2ab
DB		 938static struct of_device_id msm_match_table[] = {
939 { .compatible = "qcom,msm-uart" },
940 {}
941};
942
04896a77 943static struct platform_driver msm_platform_driver = {
04896a77
RL		 944 .remove = msm_serial_remove,
945 .driver = {
946 .name = "msm_serial",
947 .owner = THIS_MODULE,
cfdad2ab 948 .of_match_table = msm_match_table,
04896a77
RL		 949 },
950};
951
952static int __init msm_serial_init(void)
953{
954 int ret;
955
956 ret = uart_register_driver(&msm_uart_driver);
957 if (unlikely(ret))
958 return ret;
959
960 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
961 if (unlikely(ret))
962 uart_unregister_driver(&msm_uart_driver);
963
964 printk(KERN_INFO "msm_serial: driver initialized\n");
965
966 return ret;
967}
968
969static void __exit msm_serial_exit(void)
970{
971#ifdef CONFIG_SERIAL_MSM_CONSOLE
972 unregister_console(&msm_console);
973#endif
974 platform_driver_unregister(&msm_platform_driver);
975 uart_unregister_driver(&msm_uart_driver);
976}
977
978module_init(msm_serial_init);
979module_exit(msm_serial_exit);
980
981MODULE_AUTHOR("Robert Love <rlove@google.com>");
982MODULE_DESCRIPTION("Driver for msm7x serial device");
983MODULE_LICENSE("GPL");
ubuntu-bionic-kernel mirror