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Commit | Line | Data |
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161e773c RW |
1 | /* |
2 | * Drivers for CSR SiRFprimaII onboard UARTs. | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | #include <linux/bitops.h> | |
5df83111 QL |
9 | struct sirfsoc_uart_param { |
10 | const char *uart_name; | |
11 | const char *port_name; | |
12 | u32 uart_nr; | |
13 | u32 register_uart_nr; | |
14 | }; | |
15 | ||
16 | struct sirfsoc_register { | |
17 | /* hardware uart specific */ | |
18 | u32 sirfsoc_line_ctrl; | |
19 | u32 sirfsoc_divisor; | |
20 | /* uart - usp common */ | |
21 | u32 sirfsoc_tx_rx_en; | |
22 | u32 sirfsoc_int_en_reg; | |
23 | u32 sirfsoc_int_st_reg; | |
24 | u32 sirfsoc_tx_dma_io_ctrl; | |
25 | u32 sirfsoc_tx_dma_io_len; | |
26 | u32 sirfsoc_tx_fifo_ctrl; | |
27 | u32 sirfsoc_tx_fifo_level_chk; | |
28 | u32 sirfsoc_tx_fifo_op; | |
29 | u32 sirfsoc_tx_fifo_status; | |
30 | u32 sirfsoc_tx_fifo_data; | |
31 | u32 sirfsoc_rx_dma_io_ctrl; | |
32 | u32 sirfsoc_rx_dma_io_len; | |
33 | u32 sirfsoc_rx_fifo_ctrl; | |
34 | u32 sirfsoc_rx_fifo_level_chk; | |
35 | u32 sirfsoc_rx_fifo_op; | |
36 | u32 sirfsoc_rx_fifo_status; | |
37 | u32 sirfsoc_rx_fifo_data; | |
38 | u32 sirfsoc_afc_ctrl; | |
39 | u32 sirfsoc_swh_dma_io; | |
40 | /* hardware usp specific */ | |
41 | u32 sirfsoc_mode1; | |
42 | u32 sirfsoc_mode2; | |
43 | u32 sirfsoc_tx_frame_ctrl; | |
44 | u32 sirfsoc_rx_frame_ctrl; | |
45 | u32 sirfsoc_async_param_reg; | |
46 | }; | |
47 | ||
48 | typedef u32 (*fifo_full_mask)(int line); | |
49 | typedef u32 (*fifo_empty_mask)(int line); | |
50 | ||
51 | struct sirfsoc_fifo_status { | |
52 | fifo_full_mask ff_full; | |
53 | fifo_empty_mask ff_empty; | |
54 | }; | |
55 | ||
56 | struct sirfsoc_int_en { | |
57 | u32 sirfsoc_rx_done_en; | |
58 | u32 sirfsoc_tx_done_en; | |
59 | u32 sirfsoc_rx_oflow_en; | |
60 | u32 sirfsoc_tx_allout_en; | |
61 | u32 sirfsoc_rx_io_dma_en; | |
62 | u32 sirfsoc_tx_io_dma_en; | |
63 | u32 sirfsoc_rxfifo_full_en; | |
64 | u32 sirfsoc_txfifo_empty_en; | |
65 | u32 sirfsoc_rxfifo_thd_en; | |
66 | u32 sirfsoc_txfifo_thd_en; | |
67 | u32 sirfsoc_frm_err_en; | |
68 | u32 sirfsoc_rxd_brk_en; | |
69 | u32 sirfsoc_rx_timeout_en; | |
70 | u32 sirfsoc_parity_err_en; | |
71 | u32 sirfsoc_cts_en; | |
72 | u32 sirfsoc_rts_en; | |
73 | }; | |
74 | ||
75 | struct sirfsoc_int_status { | |
76 | u32 sirfsoc_rx_done; | |
77 | u32 sirfsoc_tx_done; | |
78 | u32 sirfsoc_rx_oflow; | |
79 | u32 sirfsoc_tx_allout; | |
80 | u32 sirfsoc_rx_io_dma; | |
81 | u32 sirfsoc_tx_io_dma; | |
82 | u32 sirfsoc_rxfifo_full; | |
83 | u32 sirfsoc_txfifo_empty; | |
84 | u32 sirfsoc_rxfifo_thd; | |
85 | u32 sirfsoc_txfifo_thd; | |
86 | u32 sirfsoc_frm_err; | |
87 | u32 sirfsoc_rxd_brk; | |
88 | u32 sirfsoc_rx_timeout; | |
89 | u32 sirfsoc_parity_err; | |
90 | u32 sirfsoc_cts; | |
91 | u32 sirfsoc_rts; | |
92 | }; | |
93 | ||
94 | enum sirfsoc_uart_type { | |
95 | SIRF_REAL_UART, | |
96 | SIRF_USP_UART, | |
97 | }; | |
98 | ||
99 | struct sirfsoc_uart_register { | |
100 | struct sirfsoc_register uart_reg; | |
101 | struct sirfsoc_int_en uart_int_en; | |
102 | struct sirfsoc_int_status uart_int_st; | |
103 | struct sirfsoc_fifo_status fifo_status; | |
104 | struct sirfsoc_uart_param uart_param; | |
105 | enum sirfsoc_uart_type uart_type; | |
106 | }; | |
161e773c | 107 | |
5df83111 QL |
108 | u32 usp_ff_full(int line) |
109 | { | |
110 | return 0x80; | |
111 | } | |
112 | u32 usp_ff_empty(int line) | |
113 | { | |
114 | return 0x100; | |
115 | } | |
116 | u32 uart_ff_full(int line) | |
117 | { | |
118 | return (line == 1) ? (0x20) : (0x80); | |
119 | } | |
120 | u32 uart_ff_empty(int line) | |
121 | { | |
122 | return (line == 1) ? (0x40) : (0x100); | |
123 | } | |
124 | struct sirfsoc_uart_register sirfsoc_usp = { | |
125 | .uart_reg = { | |
126 | .sirfsoc_mode1 = 0x0000, | |
127 | .sirfsoc_mode2 = 0x0004, | |
128 | .sirfsoc_tx_frame_ctrl = 0x0008, | |
129 | .sirfsoc_rx_frame_ctrl = 0x000c, | |
130 | .sirfsoc_tx_rx_en = 0x0010, | |
131 | .sirfsoc_int_en_reg = 0x0014, | |
132 | .sirfsoc_int_st_reg = 0x0018, | |
133 | .sirfsoc_async_param_reg = 0x0024, | |
134 | .sirfsoc_tx_dma_io_ctrl = 0x0100, | |
135 | .sirfsoc_tx_dma_io_len = 0x0104, | |
136 | .sirfsoc_tx_fifo_ctrl = 0x0108, | |
137 | .sirfsoc_tx_fifo_level_chk = 0x010c, | |
138 | .sirfsoc_tx_fifo_op = 0x0110, | |
139 | .sirfsoc_tx_fifo_status = 0x0114, | |
140 | .sirfsoc_tx_fifo_data = 0x0118, | |
141 | .sirfsoc_rx_dma_io_ctrl = 0x0120, | |
142 | .sirfsoc_rx_dma_io_len = 0x0124, | |
143 | .sirfsoc_rx_fifo_ctrl = 0x0128, | |
144 | .sirfsoc_rx_fifo_level_chk = 0x012c, | |
145 | .sirfsoc_rx_fifo_op = 0x0130, | |
146 | .sirfsoc_rx_fifo_status = 0x0134, | |
147 | .sirfsoc_rx_fifo_data = 0x0138, | |
148 | }, | |
149 | .uart_int_en = { | |
150 | .sirfsoc_rx_done_en = BIT(0), | |
151 | .sirfsoc_tx_done_en = BIT(1), | |
152 | .sirfsoc_rx_oflow_en = BIT(2), | |
153 | .sirfsoc_tx_allout_en = BIT(3), | |
154 | .sirfsoc_rx_io_dma_en = BIT(4), | |
155 | .sirfsoc_tx_io_dma_en = BIT(5), | |
156 | .sirfsoc_rxfifo_full_en = BIT(6), | |
157 | .sirfsoc_txfifo_empty_en = BIT(7), | |
158 | .sirfsoc_rxfifo_thd_en = BIT(8), | |
159 | .sirfsoc_txfifo_thd_en = BIT(9), | |
160 | .sirfsoc_frm_err_en = BIT(10), | |
161 | .sirfsoc_rx_timeout_en = BIT(11), | |
162 | .sirfsoc_rxd_brk_en = BIT(15), | |
163 | }, | |
164 | .uart_int_st = { | |
165 | .sirfsoc_rx_done = BIT(0), | |
166 | .sirfsoc_tx_done = BIT(1), | |
167 | .sirfsoc_rx_oflow = BIT(2), | |
168 | .sirfsoc_tx_allout = BIT(3), | |
169 | .sirfsoc_rx_io_dma = BIT(4), | |
170 | .sirfsoc_tx_io_dma = BIT(5), | |
171 | .sirfsoc_rxfifo_full = BIT(6), | |
172 | .sirfsoc_txfifo_empty = BIT(7), | |
173 | .sirfsoc_rxfifo_thd = BIT(8), | |
174 | .sirfsoc_txfifo_thd = BIT(9), | |
175 | .sirfsoc_frm_err = BIT(10), | |
176 | .sirfsoc_rx_timeout = BIT(11), | |
177 | .sirfsoc_rxd_brk = BIT(15), | |
178 | }, | |
179 | .fifo_status = { | |
180 | .ff_full = usp_ff_full, | |
181 | .ff_empty = usp_ff_empty, | |
182 | }, | |
183 | .uart_param = { | |
184 | .uart_name = "ttySiRF", | |
185 | .port_name = "sirfsoc-uart", | |
186 | .uart_nr = 2, | |
187 | .register_uart_nr = 3, | |
188 | }, | |
189 | }; | |
190 | ||
191 | struct sirfsoc_uart_register sirfsoc_uart = { | |
192 | .uart_reg = { | |
193 | .sirfsoc_line_ctrl = 0x0040, | |
194 | .sirfsoc_tx_rx_en = 0x004c, | |
195 | .sirfsoc_divisor = 0x0050, | |
196 | .sirfsoc_int_en_reg = 0x0054, | |
197 | .sirfsoc_int_st_reg = 0x0058, | |
198 | .sirfsoc_tx_dma_io_ctrl = 0x0100, | |
199 | .sirfsoc_tx_dma_io_len = 0x0104, | |
200 | .sirfsoc_tx_fifo_ctrl = 0x0108, | |
201 | .sirfsoc_tx_fifo_level_chk = 0x010c, | |
202 | .sirfsoc_tx_fifo_op = 0x0110, | |
203 | .sirfsoc_tx_fifo_status = 0x0114, | |
204 | .sirfsoc_tx_fifo_data = 0x0118, | |
205 | .sirfsoc_rx_dma_io_ctrl = 0x0120, | |
206 | .sirfsoc_rx_dma_io_len = 0x0124, | |
207 | .sirfsoc_rx_fifo_ctrl = 0x0128, | |
208 | .sirfsoc_rx_fifo_level_chk = 0x012c, | |
209 | .sirfsoc_rx_fifo_op = 0x0130, | |
210 | .sirfsoc_rx_fifo_status = 0x0134, | |
211 | .sirfsoc_rx_fifo_data = 0x0138, | |
212 | .sirfsoc_afc_ctrl = 0x0140, | |
213 | .sirfsoc_swh_dma_io = 0x0148, | |
214 | }, | |
215 | .uart_int_en = { | |
216 | .sirfsoc_rx_done_en = BIT(0), | |
217 | .sirfsoc_tx_done_en = BIT(1), | |
218 | .sirfsoc_rx_oflow_en = BIT(2), | |
219 | .sirfsoc_tx_allout_en = BIT(3), | |
220 | .sirfsoc_rx_io_dma_en = BIT(4), | |
221 | .sirfsoc_tx_io_dma_en = BIT(5), | |
222 | .sirfsoc_rxfifo_full_en = BIT(6), | |
223 | .sirfsoc_txfifo_empty_en = BIT(7), | |
224 | .sirfsoc_rxfifo_thd_en = BIT(8), | |
225 | .sirfsoc_txfifo_thd_en = BIT(9), | |
226 | .sirfsoc_frm_err_en = BIT(10), | |
227 | .sirfsoc_rxd_brk_en = BIT(11), | |
228 | .sirfsoc_rx_timeout_en = BIT(12), | |
229 | .sirfsoc_parity_err_en = BIT(13), | |
230 | .sirfsoc_cts_en = BIT(14), | |
231 | .sirfsoc_rts_en = BIT(15), | |
232 | }, | |
233 | .uart_int_st = { | |
234 | .sirfsoc_rx_done = BIT(0), | |
235 | .sirfsoc_tx_done = BIT(1), | |
236 | .sirfsoc_rx_oflow = BIT(2), | |
237 | .sirfsoc_tx_allout = BIT(3), | |
238 | .sirfsoc_rx_io_dma = BIT(4), | |
239 | .sirfsoc_tx_io_dma = BIT(5), | |
240 | .sirfsoc_rxfifo_full = BIT(6), | |
241 | .sirfsoc_txfifo_empty = BIT(7), | |
242 | .sirfsoc_rxfifo_thd = BIT(8), | |
243 | .sirfsoc_txfifo_thd = BIT(9), | |
244 | .sirfsoc_frm_err = BIT(10), | |
245 | .sirfsoc_rxd_brk = BIT(11), | |
246 | .sirfsoc_rx_timeout = BIT(12), | |
247 | .sirfsoc_parity_err = BIT(13), | |
248 | .sirfsoc_cts = BIT(14), | |
249 | .sirfsoc_rts = BIT(15), | |
250 | }, | |
251 | .fifo_status = { | |
252 | .ff_full = uart_ff_full, | |
253 | .ff_empty = uart_ff_empty, | |
254 | }, | |
255 | .uart_param = { | |
256 | .uart_name = "ttySiRF", | |
257 | .port_name = "sirfsoc_uart", | |
258 | .uart_nr = 3, | |
259 | .register_uart_nr = 0, | |
260 | }, | |
261 | }; | |
262 | /* uart io ctrl */ | |
161e773c RW |
263 | #define SIRFUART_DATA_BIT_LEN_MASK 0x3 |
264 | #define SIRFUART_DATA_BIT_LEN_5 BIT(0) | |
265 | #define SIRFUART_DATA_BIT_LEN_6 1 | |
266 | #define SIRFUART_DATA_BIT_LEN_7 2 | |
267 | #define SIRFUART_DATA_BIT_LEN_8 3 | |
268 | #define SIRFUART_STOP_BIT_LEN_1 0 | |
269 | #define SIRFUART_STOP_BIT_LEN_2 BIT(2) | |
270 | #define SIRFUART_PARITY_EN BIT(3) | |
271 | #define SIRFUART_EVEN_BIT BIT(4) | |
272 | #define SIRFUART_STICK_BIT_MASK (7 << 3) | |
273 | #define SIRFUART_STICK_BIT_NONE (0 << 3) | |
274 | #define SIRFUART_STICK_BIT_EVEN BIT(3) | |
275 | #define SIRFUART_STICK_BIT_ODD (3 << 3) | |
276 | #define SIRFUART_STICK_BIT_MARK (5 << 3) | |
277 | #define SIRFUART_STICK_BIT_SPACE (7 << 3) | |
278 | #define SIRFUART_SET_BREAK BIT(6) | |
279 | #define SIRFUART_LOOP_BACK BIT(7) | |
280 | #define SIRFUART_PARITY_MASK (7 << 3) | |
281 | #define SIRFUART_DUMMY_READ BIT(16) | |
5df83111 | 282 | #define SIRFUART_AFC_CTRL_RX_THD 0x70 |
161e773c RW |
283 | #define SIRFUART_AFC_RX_EN BIT(8) |
284 | #define SIRFUART_AFC_TX_EN BIT(9) | |
5df83111 QL |
285 | #define SIRFUART_AFC_CTS_CTRL BIT(10) |
286 | #define SIRFUART_AFC_RTS_CTRL BIT(11) | |
287 | #define SIRFUART_AFC_CTS_STATUS BIT(12) | |
288 | #define SIRFUART_AFC_RTS_STATUS BIT(13) | |
161e773c | 289 | /* UART FIFO Register */ |
5df83111 QL |
290 | #define SIRFUART_FIFO_STOP 0x0 |
291 | #define SIRFUART_FIFO_RESET BIT(0) | |
292 | #define SIRFUART_FIFO_START BIT(1) | |
293 | ||
294 | #define SIRFUART_RX_EN BIT(0) | |
295 | #define SIRFUART_TX_EN BIT(1) | |
296 | ||
297 | #define SIRFUART_IO_MODE BIT(0) | |
298 | #define SIRFUART_DMA_MODE 0x0 | |
299 | ||
300 | /* Macro Specific*/ | |
301 | #define SIRFUART_INT_EN_CLR 0x0060 | |
302 | /* Baud Rate Calculation */ | |
303 | #define SIRF_MIN_SAMPLE_DIV 0xf | |
304 | #define SIRF_MAX_SAMPLE_DIV 0x3f | |
305 | #define SIRF_IOCLK_DIV_MAX 0xffff | |
306 | #define SIRF_SAMPLE_DIV_SHIFT 16 | |
307 | #define SIRF_IOCLK_DIV_MASK 0xffff | |
308 | #define SIRF_SAMPLE_DIV_MASK 0x3f0000 | |
309 | #define SIRF_BAUD_RATE_SUPPORT_NR 18 | |
310 | ||
311 | /* USP SPEC */ | |
312 | #define SIRFSOC_USP_ENDIAN_CTRL_LSBF BIT(4) | |
313 | #define SIRFSOC_USP_EN BIT(5) | |
314 | ||
315 | /* USP-UART Common */ | |
316 | #define SIRFSOC_UART_RX_TIMEOUT(br, to) (((br) * (((to) + 999) / 1000)) / 1000) | |
317 | #define SIRFUART_RECV_TIMEOUT_VALUE(x) \ | |
318 | (((x) > 0xFFFF) ? 0xFFFF : ((x) & 0xFFFF)) | |
319 | #define SIRFUART_RECV_TIMEOUT(port, x) \ | |
320 | (((port)->line > 2) ? (x & 0xFFFF) : ((x) & 0xFFFF) << 16) | |
161e773c | 321 | |
5df83111 QL |
322 | #define SIRFUART_FIFO_THD(port) ((port->line) == 1 ? 16 : 64) |
323 | #define SIRFUART_ERR_INT_STAT(port, unit_st) \ | |
324 | (uint_st->sirfsoc_rx_oflow | \ | |
325 | uint_st->sirfsoc_frm_err | \ | |
326 | uint_st->sirfsoc_rxd_brk | \ | |
327 | ((port->line > 2) ? 0 : uint_st->sirfsoc_parity_err)) | |
328 | #define SIRFUART_RX_IO_INT_EN(port, uint_en) \ | |
329 | (uint_en->sirfsoc_rx_timeout_en |\ | |
330 | uint_en->sirfsoc_rxfifo_thd_en |\ | |
331 | uint_en->sirfsoc_rxfifo_full_en |\ | |
332 | uint_en->sirfsoc_frm_err_en |\ | |
333 | uint_en->sirfsoc_rx_oflow_en |\ | |
334 | uint_en->sirfsoc_rxd_brk_en |\ | |
335 | ((port->line > 2) ? 0 : uint_en->sirfsoc_parity_err_en)) | |
336 | #define SIRFUART_RX_IO_INT_ST(uint_st) \ | |
337 | (uint_st->sirfsoc_rx_timeout |\ | |
338 | uint_st->sirfsoc_rxfifo_thd |\ | |
339 | uint_st->sirfsoc_rxfifo_full) | |
340 | #define SIRFUART_CTS_INT_ST(uint_st) (uint_st->sirfsoc_cts) | |
161e773c RW |
341 | /* Generic Definitions */ |
342 | #define SIRFSOC_UART_NAME "ttySiRF" | |
343 | #define SIRFSOC_UART_MAJOR 0 | |
344 | #define SIRFSOC_UART_MINOR 0 | |
345 | #define SIRFUART_PORT_NAME "sirfsoc-uart" | |
346 | #define SIRFUART_MAP_SIZE 0x200 | |
5425e03f | 347 | #define SIRFSOC_UART_NR 5 |
161e773c RW |
348 | #define SIRFSOC_PORT_TYPE 0xa5 |
349 | ||
350 | /* Baud Rate Calculation */ | |
351 | #define SIRF_MIN_SAMPLE_DIV 0xf | |
352 | #define SIRF_MAX_SAMPLE_DIV 0x3f | |
353 | #define SIRF_IOCLK_DIV_MAX 0xffff | |
354 | #define SIRF_SAMPLE_DIV_SHIFT 16 | |
355 | #define SIRF_IOCLK_DIV_MASK 0xffff | |
356 | #define SIRF_SAMPLE_DIV_MASK 0x3f0000 | |
357 | #define SIRF_BAUD_RATE_SUPPORT_NR 18 | |
358 | ||
359 | /* For Fast Baud Rate Calculation */ | |
360 | struct sirfsoc_baudrate_to_regv { | |
361 | unsigned int baud_rate; | |
362 | unsigned int reg_val; | |
363 | }; | |
364 | ||
365 | struct sirfsoc_uart_port { | |
366 | unsigned char hw_flow_ctrl; | |
367 | unsigned char ms_enabled; | |
368 | ||
369 | struct uart_port port; | |
ac4ce718 | 370 | struct clk *clk; |
909102db BS |
371 | /* for SiRFmarco, there are SET/CLR for UART_INT_EN */ |
372 | bool is_marco; | |
5df83111 | 373 | struct sirfsoc_uart_register *uart_reg; |
161e773c RW |
374 | }; |
375 | ||
376 | /* Hardware Flow Control */ | |
377 | #define SIRFUART_AFC_CTRL_RX_THD 0x70 | |
378 | ||
379 | /* Register Access Control */ | |
380 | #define portaddr(port, reg) ((port)->membase + (reg)) | |
381 | #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg))) | |
382 | #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) | |
383 | #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg)) | |
384 | #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) | |
385 | ||
386 | /* UART Port Mask */ | |
387 | #define SIRFUART_FIFOLEVEL_MASK(port) ((port->line == 1) ? (0x1f) : (0x7f)) | |
388 | #define SIRFUART_FIFOFULL_MASK(port) ((port->line == 1) ? (0x20) : (0x80)) | |
389 | #define SIRFUART_FIFOEMPTY_MASK(port) ((port->line == 1) ? (0x40) : (0x100)) | |
390 | ||
391 | /* I/O Mode */ | |
392 | #define SIRFSOC_UART_IO_RX_MAX_CNT 256 | |
393 | #define SIRFSOC_UART_IO_TX_REASONABLE_CNT 6 |