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Commit | Line | Data |
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8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
7ad8096e | 23 | #include <linux/mutex.h> |
5b7d70c6 BD |
24 | #include <linux/seq_file.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
c50f056c | 28 | #include <linux/of_platform.h> |
5b7d70c6 BD |
29 | |
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
b2e587db | 32 | #include <linux/usb/phy.h> |
5b7d70c6 | 33 | |
f7c0b143 | 34 | #include "core.h" |
941fcce4 | 35 | #include "hw.h" |
5b7d70c6 BD |
36 | |
37 | /* conversion functions */ | |
1f91b4cc | 38 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 39 | { |
1f91b4cc | 40 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
41 | } |
42 | ||
1f91b4cc | 43 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 44 | { |
1f91b4cc | 45 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
46 | } |
47 | ||
941fcce4 | 48 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 49 | { |
941fcce4 | 50 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
51 | } |
52 | ||
53 | static inline void __orr32(void __iomem *ptr, u32 val) | |
54 | { | |
95c8bc36 | 55 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
56 | } |
57 | ||
58 | static inline void __bic32(void __iomem *ptr, u32 val) | |
59 | { | |
95c8bc36 | 60 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
61 | } |
62 | ||
1f91b4cc | 63 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
64 | u32 ep_index, u32 dir_in) |
65 | { | |
66 | if (dir_in) | |
67 | return hsotg->eps_in[ep_index]; | |
68 | else | |
69 | return hsotg->eps_out[ep_index]; | |
70 | } | |
71 | ||
997f4f81 | 72 | /* forward declaration of functions */ |
1f91b4cc | 73 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
74 | |
75 | /** | |
76 | * using_dma - return the DMA status of the driver. | |
77 | * @hsotg: The driver state. | |
78 | * | |
79 | * Return true if we're using DMA. | |
80 | * | |
81 | * Currently, we have the DMA support code worked into everywhere | |
82 | * that needs it, but the AMBA DMA implementation in the hardware can | |
83 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
84 | * as the CDC Ethernet cannot work as they often pass packets which are | |
85 | * not 32bit aligned. | |
86 | * | |
87 | * Unfortunately the choice to use DMA or not is global to the controller | |
88 | * and seems to be only settable when the controller is being put through | |
89 | * a core reset. This means we either need to fix the gadgets to take | |
90 | * account of DMA alignment, or add bounce buffers (yuerk). | |
91 | * | |
edd74be8 | 92 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 93 | */ |
941fcce4 | 94 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 95 | { |
edd74be8 | 96 | return hsotg->g_using_dma; |
5b7d70c6 BD |
97 | } |
98 | ||
99 | /** | |
1f91b4cc | 100 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
101 | * @hsotg: The device state |
102 | * @ints: A bitmask of the interrupts to enable | |
103 | */ | |
1f91b4cc | 104 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 105 | { |
95c8bc36 | 106 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
107 | u32 new_gsintmsk; |
108 | ||
109 | new_gsintmsk = gsintmsk | ints; | |
110 | ||
111 | if (new_gsintmsk != gsintmsk) { | |
112 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 113 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
114 | } |
115 | } | |
116 | ||
117 | /** | |
1f91b4cc | 118 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
119 | * @hsotg: The device state |
120 | * @ints: A bitmask of the interrupts to enable | |
121 | */ | |
1f91b4cc | 122 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 123 | { |
95c8bc36 | 124 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
125 | u32 new_gsintmsk; |
126 | ||
127 | new_gsintmsk = gsintmsk & ~ints; | |
128 | ||
129 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 130 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
131 | } |
132 | ||
133 | /** | |
1f91b4cc | 134 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
135 | * @hsotg: The device state |
136 | * @ep: The endpoint index | |
137 | * @dir_in: True if direction is in. | |
138 | * @en: The enable value, true to enable | |
139 | * | |
140 | * Set or clear the mask for an individual endpoint's interrupt | |
141 | * request. | |
142 | */ | |
1f91b4cc | 143 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
144 | unsigned int ep, unsigned int dir_in, |
145 | unsigned int en) | |
146 | { | |
147 | unsigned long flags; | |
148 | u32 bit = 1 << ep; | |
149 | u32 daint; | |
150 | ||
151 | if (!dir_in) | |
152 | bit <<= 16; | |
153 | ||
154 | local_irq_save(flags); | |
95c8bc36 | 155 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
156 | if (en) |
157 | daint |= bit; | |
158 | else | |
159 | daint &= ~bit; | |
95c8bc36 | 160 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
161 | local_irq_restore(flags); |
162 | } | |
163 | ||
164 | /** | |
1f91b4cc | 165 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
166 | * @hsotg: The device instance. |
167 | */ | |
1f91b4cc | 168 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 169 | { |
0f002d20 BD |
170 | unsigned int ep; |
171 | unsigned int addr; | |
1703a6d3 | 172 | int timeout; |
0f002d20 BD |
173 | u32 val; |
174 | ||
7fcbc95c GH |
175 | /* Reset fifo map if not correctly cleared during previous session */ |
176 | WARN_ON(hsotg->fifo_map); | |
177 | hsotg->fifo_map = 0; | |
178 | ||
0a176279 | 179 | /* set RX/NPTX FIFO sizes */ |
95c8bc36 AS |
180 | dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); |
181 | dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
0a176279 GH |
182 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), |
183 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 184 | |
8b9bc460 LM |
185 | /* |
186 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
187 | * block have overlapping default addresses. This also ensures |
188 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
189 | * known values. |
190 | */ | |
0f002d20 BD |
191 | |
192 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 193 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 194 | |
8b9bc460 | 195 | /* |
0a176279 | 196 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
197 | * them to endpoints dynamically according to maxpacket size value of |
198 | * given endpoint. | |
8b9bc460 | 199 | */ |
0a176279 GH |
200 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
201 | if (!hsotg->g_tx_fifo_sz[ep]) | |
202 | continue; | |
0f002d20 | 203 | val = addr; |
0a176279 GH |
204 | val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT; |
205 | WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem, | |
cff9eb75 | 206 | "insufficient fifo memory"); |
0a176279 | 207 | addr += hsotg->g_tx_fifo_sz[ep]; |
0f002d20 | 208 | |
95c8bc36 | 209 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 210 | } |
1703a6d3 | 211 | |
8b9bc460 LM |
212 | /* |
213 | * according to p428 of the design guide, we need to ensure that | |
214 | * all fifos are flushed before continuing | |
215 | */ | |
1703a6d3 | 216 | |
95c8bc36 | 217 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 218 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
219 | |
220 | /* wait until the fifos are both flushed */ | |
221 | timeout = 100; | |
222 | while (1) { | |
95c8bc36 | 223 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 224 | |
47a1685f | 225 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
226 | break; |
227 | ||
228 | if (--timeout == 0) { | |
229 | dev_err(hsotg->dev, | |
230 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
231 | __func__, val); | |
48b20bcb | 232 | break; |
1703a6d3 BD |
233 | } |
234 | ||
235 | udelay(1); | |
236 | } | |
237 | ||
238 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
239 | } |
240 | ||
241 | /** | |
242 | * @ep: USB endpoint to allocate request for. | |
243 | * @flags: Allocation flags | |
244 | * | |
245 | * Allocate a new USB request structure appropriate for the specified endpoint | |
246 | */ | |
1f91b4cc | 247 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
0978f8c5 | 248 | gfp_t flags) |
5b7d70c6 | 249 | { |
1f91b4cc | 250 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 251 | |
1f91b4cc | 252 | req = kzalloc(sizeof(struct dwc2_hsotg_req), flags); |
5b7d70c6 BD |
253 | if (!req) |
254 | return NULL; | |
255 | ||
256 | INIT_LIST_HEAD(&req->queue); | |
257 | ||
5b7d70c6 BD |
258 | return &req->req; |
259 | } | |
260 | ||
261 | /** | |
262 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
263 | * @hs_ep: The endpoint to query. | |
264 | * | |
265 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
266 | * used for an Interrupt or ISO transfer. | |
267 | */ | |
1f91b4cc | 268 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
269 | { |
270 | return hs_ep->periodic; | |
271 | } | |
272 | ||
273 | /** | |
1f91b4cc | 274 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
275 | * @hsotg: The device state. |
276 | * @hs_ep: The endpoint for the request | |
277 | * @hs_req: The request being processed. | |
278 | * | |
1f91b4cc | 279 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 280 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 281 | */ |
1f91b4cc FB |
282 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
283 | struct dwc2_hsotg_ep *hs_ep, | |
284 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
285 | { |
286 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
287 | |
288 | /* ignore this if we're not moving any data */ | |
289 | if (hs_req->req.length == 0) | |
290 | return; | |
291 | ||
17d966a3 | 292 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
293 | } |
294 | ||
295 | /** | |
1f91b4cc | 296 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
297 | * @hsotg: The controller state. |
298 | * @hs_ep: The endpoint we're going to write for. | |
299 | * @hs_req: The request to write data for. | |
300 | * | |
301 | * This is called when the TxFIFO has some space in it to hold a new | |
302 | * transmission and we have something to give it. The actual setup of | |
303 | * the data size is done elsewhere, so all we have to do is to actually | |
304 | * write the data. | |
305 | * | |
306 | * The return value is zero if there is more space (or nothing was done) | |
307 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
308 | * | |
309 | * This routine is only needed for PIO | |
8b9bc460 | 310 | */ |
1f91b4cc FB |
311 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
312 | struct dwc2_hsotg_ep *hs_ep, | |
313 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
314 | { |
315 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 316 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
317 | int buf_pos = hs_req->req.actual; |
318 | int to_write = hs_ep->size_loaded; | |
319 | void *data; | |
320 | int can_write; | |
321 | int pkt_round; | |
4fca54aa | 322 | int max_transfer; |
5b7d70c6 BD |
323 | |
324 | to_write -= (buf_pos - hs_ep->last_load); | |
325 | ||
326 | /* if there's nothing to write, get out early */ | |
327 | if (to_write == 0) | |
328 | return 0; | |
329 | ||
10aebc77 | 330 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 331 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
332 | int size_left; |
333 | int size_done; | |
334 | ||
8b9bc460 LM |
335 | /* |
336 | * work out how much data was loaded so we can calculate | |
337 | * how much data is left in the fifo. | |
338 | */ | |
5b7d70c6 | 339 | |
47a1685f | 340 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 341 | |
8b9bc460 LM |
342 | /* |
343 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
344 | * previous data has been completely sent. |
345 | */ | |
346 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 347 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
348 | return -ENOSPC; |
349 | } | |
350 | ||
5b7d70c6 BD |
351 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
352 | __func__, size_left, | |
353 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
354 | ||
355 | /* how much of the data has moved */ | |
356 | size_done = hs_ep->size_loaded - size_left; | |
357 | ||
358 | /* how much data is left in the fifo */ | |
359 | can_write = hs_ep->fifo_load - size_done; | |
360 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
361 | __func__, can_write); | |
362 | ||
363 | can_write = hs_ep->fifo_size - can_write; | |
364 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
365 | __func__, can_write); | |
366 | ||
367 | if (can_write <= 0) { | |
1f91b4cc | 368 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
369 | return -ENOSPC; |
370 | } | |
10aebc77 | 371 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
95c8bc36 | 372 | can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
373 | |
374 | can_write &= 0xffff; | |
375 | can_write *= 4; | |
5b7d70c6 | 376 | } else { |
47a1685f | 377 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
378 | dev_dbg(hsotg->dev, |
379 | "%s: no queue slots available (0x%08x)\n", | |
380 | __func__, gnptxsts); | |
381 | ||
1f91b4cc | 382 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
383 | return -ENOSPC; |
384 | } | |
385 | ||
47a1685f | 386 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 387 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
388 | } |
389 | ||
4fca54aa RB |
390 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
391 | ||
392 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
393 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 394 | |
8b9bc460 LM |
395 | /* |
396 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
397 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
398 | * fragment of the end of the transfer in it. | |
399 | */ | |
811f3303 | 400 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
401 | can_write = 512; |
402 | ||
8b9bc460 LM |
403 | /* |
404 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 405 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
406 | * doing it. |
407 | */ | |
4fca54aa RB |
408 | if (to_write > max_transfer) { |
409 | to_write = max_transfer; | |
03e10e5a | 410 | |
5cb2ff0c RB |
411 | /* it's needed only when we do not use dedicated fifos */ |
412 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 413 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
414 | periodic ? GINTSTS_PTXFEMP : |
415 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
416 | } |
417 | ||
5b7d70c6 BD |
418 | /* see if we can write data */ |
419 | ||
420 | if (to_write > can_write) { | |
421 | to_write = can_write; | |
4fca54aa | 422 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 423 | |
8b9bc460 LM |
424 | /* |
425 | * Round the write down to an | |
5b7d70c6 BD |
426 | * exact number of packets. |
427 | * | |
428 | * Note, we do not currently check to see if we can ever | |
429 | * write a full packet or not to the FIFO. | |
430 | */ | |
431 | ||
432 | if (pkt_round) | |
433 | to_write -= pkt_round; | |
434 | ||
8b9bc460 LM |
435 | /* |
436 | * enable correct FIFO interrupt to alert us when there | |
437 | * is more room left. | |
438 | */ | |
5b7d70c6 | 439 | |
5cb2ff0c RB |
440 | /* it's needed only when we do not use dedicated fifos */ |
441 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 442 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
443 | periodic ? GINTSTS_PTXFEMP : |
444 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
445 | } |
446 | ||
447 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
448 | to_write, hs_req->req.length, can_write, buf_pos); | |
449 | ||
450 | if (to_write <= 0) | |
451 | return -ENOSPC; | |
452 | ||
453 | hs_req->req.actual = buf_pos + to_write; | |
454 | hs_ep->total_data += to_write; | |
455 | ||
456 | if (periodic) | |
457 | hs_ep->fifo_load += to_write; | |
458 | ||
459 | to_write = DIV_ROUND_UP(to_write, 4); | |
460 | data = hs_req->req.buf + buf_pos; | |
461 | ||
1a7ed5be | 462 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
463 | |
464 | return (to_write >= can_write) ? -ENOSPC : 0; | |
465 | } | |
466 | ||
467 | /** | |
468 | * get_ep_limit - get the maximum data legnth for this endpoint | |
469 | * @hs_ep: The endpoint | |
470 | * | |
471 | * Return the maximum data that can be queued in one go on a given endpoint | |
472 | * so that transfers that are too long can be split. | |
473 | */ | |
1f91b4cc | 474 | static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
475 | { |
476 | int index = hs_ep->index; | |
477 | unsigned maxsize; | |
478 | unsigned maxpkt; | |
479 | ||
480 | if (index != 0) { | |
47a1685f DN |
481 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
482 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 483 | } else { |
b05ca580 | 484 | maxsize = 64+64; |
66e5c643 | 485 | if (hs_ep->dir_in) |
47a1685f | 486 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 487 | else |
5b7d70c6 | 488 | maxpkt = 2; |
5b7d70c6 BD |
489 | } |
490 | ||
491 | /* we made the constant loading easier above by using +1 */ | |
492 | maxpkt--; | |
493 | maxsize--; | |
494 | ||
8b9bc460 LM |
495 | /* |
496 | * constrain by packet count if maxpkts*pktsize is greater | |
497 | * than the length register size. | |
498 | */ | |
5b7d70c6 BD |
499 | |
500 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
501 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
502 | ||
503 | return maxsize; | |
504 | } | |
505 | ||
506 | /** | |
1f91b4cc | 507 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
508 | * @hsotg: The controller state. |
509 | * @hs_ep: The endpoint to process a request for | |
510 | * @hs_req: The request to start. | |
511 | * @continuing: True if we are doing more for the current request. | |
512 | * | |
513 | * Start the given request running by setting the endpoint registers | |
514 | * appropriately, and writing any data to the FIFOs. | |
515 | */ | |
1f91b4cc FB |
516 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
517 | struct dwc2_hsotg_ep *hs_ep, | |
518 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
519 | bool continuing) |
520 | { | |
521 | struct usb_request *ureq = &hs_req->req; | |
522 | int index = hs_ep->index; | |
523 | int dir_in = hs_ep->dir_in; | |
524 | u32 epctrl_reg; | |
525 | u32 epsize_reg; | |
526 | u32 epsize; | |
527 | u32 ctrl; | |
528 | unsigned length; | |
529 | unsigned packets; | |
530 | unsigned maxreq; | |
531 | ||
532 | if (index != 0) { | |
533 | if (hs_ep->req && !continuing) { | |
534 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
535 | WARN_ON(1); | |
536 | return; | |
537 | } else if (hs_ep->req != hs_req && continuing) { | |
538 | dev_err(hsotg->dev, | |
539 | "%s: continue different req\n", __func__); | |
540 | WARN_ON(1); | |
541 | return; | |
542 | } | |
543 | } | |
544 | ||
94cb8fd6 LM |
545 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
546 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
547 | |
548 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 549 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
550 | hs_ep->dir_in ? "in" : "out"); |
551 | ||
9c39ddc6 | 552 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 553 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 554 | |
b2d4c54e | 555 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
556 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
557 | return; | |
558 | } | |
559 | ||
5b7d70c6 | 560 | length = ureq->length - ureq->actual; |
71225bee LM |
561 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
562 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
563 | |
564 | maxreq = get_ep_limit(hs_ep); | |
565 | if (length > maxreq) { | |
566 | int round = maxreq % hs_ep->ep.maxpacket; | |
567 | ||
568 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
569 | __func__, length, maxreq, round); | |
570 | ||
571 | /* round down to multiple of packets */ | |
572 | if (round) | |
573 | maxreq -= round; | |
574 | ||
575 | length = maxreq; | |
576 | } | |
577 | ||
578 | if (length) | |
579 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
580 | else | |
581 | packets = 1; /* send one packet if length is zero. */ | |
582 | ||
4fca54aa RB |
583 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
584 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
585 | return; | |
586 | } | |
587 | ||
5b7d70c6 | 588 | if (dir_in && index != 0) |
4fca54aa | 589 | if (hs_ep->isochronous) |
47a1685f | 590 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 591 | else |
47a1685f | 592 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
593 | else |
594 | epsize = 0; | |
595 | ||
f71b5e25 MYK |
596 | /* |
597 | * zero length packet should be programmed on its own and should not | |
598 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
599 | */ | |
600 | if (dir_in && ureq->zero && !continuing) { | |
601 | /* Test if zlp is actually required. */ | |
602 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
603 | !(ureq->length % hs_ep->ep.maxpacket)) | |
8a20fa45 | 604 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
605 | } |
606 | ||
47a1685f DN |
607 | epsize |= DXEPTSIZ_PKTCNT(packets); |
608 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
609 | |
610 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
611 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
612 | ||
613 | /* store the request as the current one we're doing */ | |
614 | hs_ep->req = hs_req; | |
615 | ||
616 | /* write size / packets */ | |
95c8bc36 | 617 | dwc2_writel(epsize, hsotg->regs + epsize_reg); |
5b7d70c6 | 618 | |
db1d8ba3 | 619 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
620 | unsigned int dma_reg; |
621 | ||
8b9bc460 LM |
622 | /* |
623 | * write DMA address to control register, buffer already | |
1f91b4cc | 624 | * synced by dwc2_hsotg_ep_queue(). |
8b9bc460 | 625 | */ |
5b7d70c6 | 626 | |
94cb8fd6 | 627 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
95c8bc36 | 628 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
5b7d70c6 | 629 | |
0cc4cf6f | 630 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 631 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
632 | } |
633 | ||
47a1685f DN |
634 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
635 | ctrl |= DXEPCTL_USBACTEP; | |
71225bee | 636 | |
fe0b94ab | 637 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
638 | |
639 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 640 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 641 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 642 | |
5b7d70c6 | 643 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 644 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 645 | |
8b9bc460 LM |
646 | /* |
647 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 648 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
649 | * this information. |
650 | */ | |
5b7d70c6 BD |
651 | hs_ep->size_loaded = length; |
652 | hs_ep->last_load = ureq->actual; | |
653 | ||
654 | if (dir_in && !using_dma(hsotg)) { | |
655 | /* set these anyway, we may need them for non-periodic in */ | |
656 | hs_ep->fifo_load = 0; | |
657 | ||
1f91b4cc | 658 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
659 | } |
660 | ||
8b9bc460 LM |
661 | /* |
662 | * clear the INTknTXFEmpMsk when we start request, more as a aide | |
663 | * to debugging to see what is going on. | |
664 | */ | |
5b7d70c6 | 665 | if (dir_in) |
95c8bc36 | 666 | dwc2_writel(DIEPMSK_INTKNTXFEMPMSK, |
94cb8fd6 | 667 | hsotg->regs + DIEPINT(index)); |
5b7d70c6 | 668 | |
8b9bc460 LM |
669 | /* |
670 | * Note, trying to clear the NAK here causes problems with transmit | |
671 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
672 | */ | |
5b7d70c6 BD |
673 | |
674 | /* check ep is enabled */ | |
95c8bc36 | 675 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 676 | dev_dbg(hsotg->dev, |
47a1685f | 677 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 678 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 679 | |
47a1685f | 680 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 681 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
682 | |
683 | /* enable ep interrupts */ | |
1f91b4cc | 684 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
685 | } |
686 | ||
687 | /** | |
1f91b4cc | 688 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
689 | * @hsotg: The device state. |
690 | * @hs_ep: The endpoint the request is on. | |
691 | * @req: The request being processed. | |
692 | * | |
693 | * We've been asked to queue a request, so ensure that the memory buffer | |
694 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
695 | * then ensure the buffer has been synced to memory. If our buffer has no | |
696 | * DMA memory, then we map the memory and mark our request to allow us to | |
697 | * cleanup on completion. | |
8b9bc460 | 698 | */ |
1f91b4cc FB |
699 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
700 | struct dwc2_hsotg_ep *hs_ep, | |
5b7d70c6 BD |
701 | struct usb_request *req) |
702 | { | |
1f91b4cc | 703 | struct dwc2_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 704 | int ret; |
5b7d70c6 BD |
705 | |
706 | /* if the length is zero, ignore the DMA data */ | |
707 | if (hs_req->req.length == 0) | |
708 | return 0; | |
709 | ||
e58ebcd1 FB |
710 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
711 | if (ret) | |
712 | goto dma_error; | |
5b7d70c6 BD |
713 | |
714 | return 0; | |
715 | ||
716 | dma_error: | |
717 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
718 | __func__, req->buf, req->length); | |
719 | ||
720 | return -EIO; | |
721 | } | |
722 | ||
1f91b4cc FB |
723 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
724 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
725 | { |
726 | void *req_buf = hs_req->req.buf; | |
727 | ||
728 | /* If dma is not being used or buffer is aligned */ | |
729 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
730 | return 0; | |
731 | ||
732 | WARN_ON(hs_req->saved_req_buf); | |
733 | ||
734 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
735 | hs_ep->ep.name, req_buf, hs_req->req.length); | |
736 | ||
737 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
738 | if (!hs_req->req.buf) { | |
739 | hs_req->req.buf = req_buf; | |
740 | dev_err(hsotg->dev, | |
741 | "%s: unable to allocate memory for bounce buffer\n", | |
742 | __func__); | |
743 | return -ENOMEM; | |
744 | } | |
745 | ||
746 | /* Save actual buffer */ | |
747 | hs_req->saved_req_buf = req_buf; | |
748 | ||
749 | if (hs_ep->dir_in) | |
750 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
751 | return 0; | |
752 | } | |
753 | ||
1f91b4cc FB |
754 | static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, |
755 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
756 | { |
757 | /* If dma is not being used or buffer was aligned */ | |
758 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
759 | return; | |
760 | ||
761 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
762 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
763 | ||
764 | /* Copy data from bounce buffer on successful out transfer */ | |
765 | if (!hs_ep->dir_in && !hs_req->req.status) | |
766 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
767 | hs_req->req.actual); | |
768 | ||
769 | /* Free bounce buffer */ | |
770 | kfree(hs_req->req.buf); | |
771 | ||
772 | hs_req->req.buf = hs_req->saved_req_buf; | |
773 | hs_req->saved_req_buf = NULL; | |
774 | } | |
775 | ||
1f91b4cc | 776 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
5b7d70c6 BD |
777 | gfp_t gfp_flags) |
778 | { | |
1f91b4cc FB |
779 | struct dwc2_hsotg_req *hs_req = our_req(req); |
780 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 781 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 782 | bool first; |
7d24c1b5 | 783 | int ret; |
5b7d70c6 BD |
784 | |
785 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
786 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
787 | req->zero, req->short_not_ok); | |
788 | ||
7ababa92 GH |
789 | /* Prevent new request submission when controller is suspended */ |
790 | if (hs->lx_state == DWC2_L2) { | |
791 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", | |
792 | __func__); | |
793 | return -EAGAIN; | |
794 | } | |
795 | ||
5b7d70c6 BD |
796 | /* initialise status of the request */ |
797 | INIT_LIST_HEAD(&hs_req->queue); | |
798 | req->actual = 0; | |
799 | req->status = -EINPROGRESS; | |
800 | ||
1f91b4cc | 801 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
802 | if (ret) |
803 | return ret; | |
804 | ||
5b7d70c6 BD |
805 | /* if we're using DMA, sync the buffers as necessary */ |
806 | if (using_dma(hs)) { | |
1f91b4cc | 807 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
808 | if (ret) |
809 | return ret; | |
810 | } | |
811 | ||
5b7d70c6 BD |
812 | first = list_empty(&hs_ep->queue); |
813 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
814 | ||
815 | if (first) | |
1f91b4cc | 816 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); |
5b7d70c6 | 817 | |
5b7d70c6 BD |
818 | return 0; |
819 | } | |
820 | ||
1f91b4cc | 821 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
5ad1d316 LM |
822 | gfp_t gfp_flags) |
823 | { | |
1f91b4cc | 824 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 825 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
826 | unsigned long flags = 0; |
827 | int ret = 0; | |
828 | ||
829 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 830 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
831 | spin_unlock_irqrestore(&hs->lock, flags); |
832 | ||
833 | return ret; | |
834 | } | |
835 | ||
1f91b4cc | 836 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
5b7d70c6 BD |
837 | struct usb_request *req) |
838 | { | |
1f91b4cc | 839 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
840 | |
841 | kfree(hs_req); | |
842 | } | |
843 | ||
844 | /** | |
1f91b4cc | 845 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
846 | * @ep: The endpoint the request was on. |
847 | * @req: The request completed. | |
848 | * | |
849 | * Called on completion of any requests the driver itself | |
850 | * submitted that need cleaning up. | |
851 | */ | |
1f91b4cc | 852 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
5b7d70c6 BD |
853 | struct usb_request *req) |
854 | { | |
1f91b4cc | 855 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 856 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
857 | |
858 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
859 | ||
1f91b4cc | 860 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
861 | } |
862 | ||
863 | /** | |
864 | * ep_from_windex - convert control wIndex value to endpoint | |
865 | * @hsotg: The driver state. | |
866 | * @windex: The control request wIndex field (in host order). | |
867 | * | |
868 | * Convert the given wIndex into a pointer to an driver endpoint | |
869 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 870 | */ |
1f91b4cc | 871 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
872 | u32 windex) |
873 | { | |
1f91b4cc | 874 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
875 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
876 | int idx = windex & 0x7F; | |
877 | ||
878 | if (windex >= 0x100) | |
879 | return NULL; | |
880 | ||
b3f489b2 | 881 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
882 | return NULL; |
883 | ||
c6f5c050 MYK |
884 | ep = index_to_ep(hsotg, idx, dir); |
885 | ||
5b7d70c6 BD |
886 | if (idx && ep->dir_in != dir) |
887 | return NULL; | |
888 | ||
889 | return ep; | |
890 | } | |
891 | ||
9e14d0a5 | 892 | /** |
1f91b4cc | 893 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
894 | * @hsotg: The driver state. |
895 | * @testmode: requested usb test mode | |
896 | * Enable usb Test Mode requested by the Host. | |
897 | */ | |
1f91b4cc | 898 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 899 | { |
95c8bc36 | 900 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
901 | |
902 | dctl &= ~DCTL_TSTCTL_MASK; | |
903 | switch (testmode) { | |
904 | case TEST_J: | |
905 | case TEST_K: | |
906 | case TEST_SE0_NAK: | |
907 | case TEST_PACKET: | |
908 | case TEST_FORCE_EN: | |
909 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
910 | break; | |
911 | default: | |
912 | return -EINVAL; | |
913 | } | |
95c8bc36 | 914 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
915 | return 0; |
916 | } | |
917 | ||
5b7d70c6 | 918 | /** |
1f91b4cc | 919 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
920 | * @hsotg: The device state |
921 | * @ep: Endpoint 0 | |
922 | * @buff: Buffer for request | |
923 | * @length: Length of reply. | |
924 | * | |
925 | * Create a request and queue it on the given endpoint. This is useful as | |
926 | * an internal method of sending replies to certain control requests, etc. | |
927 | */ | |
1f91b4cc FB |
928 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
929 | struct dwc2_hsotg_ep *ep, | |
5b7d70c6 BD |
930 | void *buff, |
931 | int length) | |
932 | { | |
933 | struct usb_request *req; | |
934 | int ret; | |
935 | ||
936 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
937 | ||
1f91b4cc | 938 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
939 | hsotg->ep0_reply = req; |
940 | if (!req) { | |
941 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
942 | return -ENOMEM; | |
943 | } | |
944 | ||
945 | req->buf = hsotg->ep0_buff; | |
946 | req->length = length; | |
f71b5e25 MYK |
947 | /* |
948 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
949 | * STATUS stage. | |
950 | */ | |
951 | req->zero = 0; | |
1f91b4cc | 952 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
953 | |
954 | if (length) | |
955 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 956 | |
1f91b4cc | 957 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
958 | if (ret) { |
959 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
960 | return ret; | |
961 | } | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | /** | |
1f91b4cc | 967 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
968 | * @hsotg: The device state |
969 | * @ctrl: USB control request | |
970 | */ | |
1f91b4cc | 971 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
972 | struct usb_ctrlrequest *ctrl) |
973 | { | |
1f91b4cc FB |
974 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
975 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
976 | __le16 reply; |
977 | int ret; | |
978 | ||
979 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
980 | ||
981 | if (!ep0->dir_in) { | |
982 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
983 | return -EINVAL; | |
984 | } | |
985 | ||
986 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
987 | case USB_RECIP_DEVICE: | |
988 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
989 | * bit 1 => remote wakeup */ | |
990 | break; | |
991 | ||
992 | case USB_RECIP_INTERFACE: | |
993 | /* currently, the data result should be zero */ | |
994 | reply = cpu_to_le16(0); | |
995 | break; | |
996 | ||
997 | case USB_RECIP_ENDPOINT: | |
998 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
999 | if (!ep) | |
1000 | return -ENOENT; | |
1001 | ||
1002 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1003 | break; | |
1004 | ||
1005 | default: | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1010 | return -EINVAL; | |
1011 | ||
1f91b4cc | 1012 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1013 | if (ret) { |
1014 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1015 | return ret; | |
1016 | } | |
1017 | ||
1018 | return 1; | |
1019 | } | |
1020 | ||
1f91b4cc | 1021 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value); |
5b7d70c6 | 1022 | |
9c39ddc6 AT |
1023 | /** |
1024 | * get_ep_head - return the first request on the endpoint | |
1025 | * @hs_ep: The controller endpoint to get | |
1026 | * | |
1027 | * Get the first request on the endpoint. | |
1028 | */ | |
1f91b4cc | 1029 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 AT |
1030 | { |
1031 | if (list_empty(&hs_ep->queue)) | |
1032 | return NULL; | |
1033 | ||
1f91b4cc | 1034 | return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue); |
9c39ddc6 AT |
1035 | } |
1036 | ||
5b7d70c6 | 1037 | /** |
1f91b4cc | 1038 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1039 | * @hsotg: The device state |
1040 | * @ctrl: USB control request | |
1041 | */ | |
1f91b4cc | 1042 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1043 | struct usb_ctrlrequest *ctrl) |
1044 | { | |
1f91b4cc FB |
1045 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1046 | struct dwc2_hsotg_req *hs_req; | |
9c39ddc6 | 1047 | bool restart; |
5b7d70c6 | 1048 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1049 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1050 | int ret; |
bd9ef7bf | 1051 | bool halted; |
9e14d0a5 GH |
1052 | u32 recip; |
1053 | u32 wValue; | |
1054 | u32 wIndex; | |
5b7d70c6 BD |
1055 | |
1056 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1057 | __func__, set ? "SET" : "CLEAR"); | |
1058 | ||
9e14d0a5 GH |
1059 | wValue = le16_to_cpu(ctrl->wValue); |
1060 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1061 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1062 | ||
1063 | switch (recip) { | |
1064 | case USB_RECIP_DEVICE: | |
1065 | switch (wValue) { | |
1066 | case USB_DEVICE_TEST_MODE: | |
1067 | if ((wIndex & 0xff) != 0) | |
1068 | return -EINVAL; | |
1069 | if (!set) | |
1070 | return -EINVAL; | |
1071 | ||
1072 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1073 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1074 | if (ret) { |
1075 | dev_err(hsotg->dev, | |
1076 | "%s: failed to send reply\n", __func__); | |
1077 | return ret; | |
1078 | } | |
1079 | break; | |
1080 | default: | |
1081 | return -ENOENT; | |
1082 | } | |
1083 | break; | |
1084 | ||
1085 | case USB_RECIP_ENDPOINT: | |
1086 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1087 | if (!ep) { |
1088 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1089 | __func__, wIndex); |
5b7d70c6 BD |
1090 | return -ENOENT; |
1091 | } | |
1092 | ||
9e14d0a5 | 1093 | switch (wValue) { |
5b7d70c6 | 1094 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1095 | halted = ep->halted; |
1096 | ||
1f91b4cc | 1097 | dwc2_hsotg_ep_sethalt(&ep->ep, set); |
26ab3d0c | 1098 | |
1f91b4cc | 1099 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1100 | if (ret) { |
1101 | dev_err(hsotg->dev, | |
1102 | "%s: failed to send reply\n", __func__); | |
1103 | return ret; | |
1104 | } | |
9c39ddc6 | 1105 | |
bd9ef7bf RB |
1106 | /* |
1107 | * we have to complete all requests for ep if it was | |
1108 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1109 | */ | |
1110 | ||
1111 | if (!set && halted) { | |
9c39ddc6 AT |
1112 | /* |
1113 | * If we have request in progress, | |
1114 | * then complete it | |
1115 | */ | |
1116 | if (ep->req) { | |
1117 | hs_req = ep->req; | |
1118 | ep->req = NULL; | |
1119 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1120 | if (hs_req->req.complete) { |
1121 | spin_unlock(&hsotg->lock); | |
1122 | usb_gadget_giveback_request( | |
1123 | &ep->ep, &hs_req->req); | |
1124 | spin_lock(&hsotg->lock); | |
1125 | } | |
9c39ddc6 AT |
1126 | } |
1127 | ||
1128 | /* If we have pending request, then start it */ | |
c00dd4a6 GH |
1129 | if (!ep->req) { |
1130 | restart = !list_empty(&ep->queue); | |
1131 | if (restart) { | |
1132 | hs_req = get_ep_head(ep); | |
1f91b4cc | 1133 | dwc2_hsotg_start_req(hsotg, ep, |
c00dd4a6 GH |
1134 | hs_req, false); |
1135 | } | |
9c39ddc6 AT |
1136 | } |
1137 | } | |
1138 | ||
5b7d70c6 BD |
1139 | break; |
1140 | ||
1141 | default: | |
1142 | return -ENOENT; | |
1143 | } | |
9e14d0a5 GH |
1144 | break; |
1145 | default: | |
1146 | return -ENOENT; | |
1147 | } | |
5b7d70c6 BD |
1148 | return 1; |
1149 | } | |
1150 | ||
1f91b4cc | 1151 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1152 | |
c9f721b2 | 1153 | /** |
1f91b4cc | 1154 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1155 | * @hsotg: The device state |
1156 | * | |
1157 | * Set stall for ep0 as response for setup request. | |
1158 | */ | |
1f91b4cc | 1159 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1160 | { |
1f91b4cc | 1161 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1162 | u32 reg; |
1163 | u32 ctrl; | |
1164 | ||
1165 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1166 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1167 | ||
1168 | /* | |
1169 | * DxEPCTL_Stall will be cleared by EP once it has | |
1170 | * taken effect, so no need to clear later. | |
1171 | */ | |
1172 | ||
95c8bc36 | 1173 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1174 | ctrl |= DXEPCTL_STALL; |
1175 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1176 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1177 | |
1178 | dev_dbg(hsotg->dev, | |
47a1685f | 1179 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1180 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1181 | |
1182 | /* | |
1183 | * complete won't be called, so we enqueue | |
1184 | * setup request here | |
1185 | */ | |
1f91b4cc | 1186 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1187 | } |
1188 | ||
5b7d70c6 | 1189 | /** |
1f91b4cc | 1190 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1191 | * @hsotg: The device state |
1192 | * @ctrl: The control request received | |
1193 | * | |
1194 | * The controller has received the SETUP phase of a control request, and | |
1195 | * needs to work out what to do next (and whether to pass it on to the | |
1196 | * gadget driver). | |
1197 | */ | |
1f91b4cc | 1198 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1199 | struct usb_ctrlrequest *ctrl) |
1200 | { | |
1f91b4cc | 1201 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1202 | int ret = 0; |
1203 | u32 dcfg; | |
1204 | ||
e525e743 MYK |
1205 | dev_dbg(hsotg->dev, |
1206 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1207 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1208 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1209 | |
fe0b94ab MYK |
1210 | if (ctrl->wLength == 0) { |
1211 | ep0->dir_in = 1; | |
1212 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1213 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1214 | ep0->dir_in = 1; |
fe0b94ab MYK |
1215 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1216 | } else { | |
1217 | ep0->dir_in = 0; | |
1218 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1219 | } | |
5b7d70c6 BD |
1220 | |
1221 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1222 | switch (ctrl->bRequest) { | |
1223 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1224 | hsotg->connected = 1; |
95c8bc36 | 1225 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1226 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1227 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1228 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1229 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1230 | |
1231 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1232 | ||
1f91b4cc | 1233 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1234 | return; |
1235 | ||
1236 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1237 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1238 | break; |
1239 | ||
1240 | case USB_REQ_CLEAR_FEATURE: | |
1241 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1242 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1243 | break; |
1244 | } | |
1245 | } | |
1246 | ||
1247 | /* as a fallback, try delivering it to the driver to deal with */ | |
1248 | ||
1249 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1250 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1251 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1252 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1253 | if (ret < 0) |
1254 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1255 | } | |
1256 | ||
8b9bc460 LM |
1257 | /* |
1258 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1259 | * so respond with a STALL for the status stage to indicate failure. |
1260 | */ | |
1261 | ||
c9f721b2 | 1262 | if (ret < 0) |
1f91b4cc | 1263 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1264 | } |
1265 | ||
5b7d70c6 | 1266 | /** |
1f91b4cc | 1267 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1268 | * @ep: The endpoint the request was on. |
1269 | * @req: The request completed. | |
1270 | * | |
1271 | * Called on completion of any requests the driver itself submitted for | |
1272 | * EP0 setup packets | |
1273 | */ | |
1f91b4cc | 1274 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
5b7d70c6 BD |
1275 | struct usb_request *req) |
1276 | { | |
1f91b4cc | 1277 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1278 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1279 | |
1280 | if (req->status < 0) { | |
1281 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1282 | return; | |
1283 | } | |
1284 | ||
93f599f2 | 1285 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1286 | if (req->actual == 0) |
1f91b4cc | 1287 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1288 | else |
1f91b4cc | 1289 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1290 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1291 | } |
1292 | ||
1293 | /** | |
1f91b4cc | 1294 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1295 | * @hsotg: The device state. |
1296 | * | |
1297 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1298 | * received from the host. | |
1299 | */ | |
1f91b4cc | 1300 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1301 | { |
1302 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1303 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1304 | int ret; |
1305 | ||
1306 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1307 | ||
1308 | req->zero = 0; | |
1309 | req->length = 8; | |
1310 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1311 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1312 | |
1313 | if (!list_empty(&hs_req->queue)) { | |
1314 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1315 | return; | |
1316 | } | |
1317 | ||
c6f5c050 | 1318 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1319 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1320 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1321 | |
1f91b4cc | 1322 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1323 | if (ret < 0) { |
1324 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1325 | /* |
1326 | * Don't think there's much we can do other than watch the | |
1327 | * driver fail. | |
1328 | */ | |
5b7d70c6 BD |
1329 | } |
1330 | } | |
1331 | ||
1f91b4cc FB |
1332 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1333 | struct dwc2_hsotg_ep *hs_ep) | |
fe0b94ab MYK |
1334 | { |
1335 | u32 ctrl; | |
1336 | u8 index = hs_ep->index; | |
1337 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1338 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1339 | ||
ccb34a91 MYK |
1340 | if (hs_ep->dir_in) |
1341 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
1342 | index); | |
1343 | else | |
1344 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
1345 | index); | |
fe0b94ab | 1346 | |
95c8bc36 AS |
1347 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
1348 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1349 | epsiz_reg); | |
fe0b94ab | 1350 | |
95c8bc36 | 1351 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1352 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1353 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1354 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1355 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1356 | } |
1357 | ||
5b7d70c6 | 1358 | /** |
1f91b4cc | 1359 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1360 | * @hsotg: The device state. |
1361 | * @hs_ep: The endpoint the request was on. | |
1362 | * @hs_req: The request to complete. | |
1363 | * @result: The result code (0 => Ok, otherwise errno) | |
1364 | * | |
1365 | * The given request has finished, so call the necessary completion | |
1366 | * if it has one and then look to see if we can start a new request | |
1367 | * on the endpoint. | |
1368 | * | |
1369 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1370 | */ |
1f91b4cc FB |
1371 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
1372 | struct dwc2_hsotg_ep *hs_ep, | |
1373 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
1374 | int result) |
1375 | { | |
1376 | bool restart; | |
1377 | ||
1378 | if (!hs_req) { | |
1379 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1380 | return; | |
1381 | } | |
1382 | ||
1383 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1384 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1385 | ||
8b9bc460 LM |
1386 | /* |
1387 | * only replace the status if we've not already set an error | |
1388 | * from a previous transaction | |
1389 | */ | |
5b7d70c6 BD |
1390 | |
1391 | if (hs_req->req.status == -EINPROGRESS) | |
1392 | hs_req->req.status = result; | |
1393 | ||
44583fec YL |
1394 | if (using_dma(hsotg)) |
1395 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1396 | ||
1f91b4cc | 1397 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 1398 | |
5b7d70c6 BD |
1399 | hs_ep->req = NULL; |
1400 | list_del_init(&hs_req->queue); | |
1401 | ||
8b9bc460 LM |
1402 | /* |
1403 | * call the complete request with the locks off, just in case the | |
1404 | * request tries to queue more work for this endpoint. | |
1405 | */ | |
5b7d70c6 BD |
1406 | |
1407 | if (hs_req->req.complete) { | |
22258f49 | 1408 | spin_unlock(&hsotg->lock); |
304f7e5e | 1409 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1410 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1411 | } |
1412 | ||
8b9bc460 LM |
1413 | /* |
1414 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1415 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1416 | * so be careful when doing this. |
1417 | */ | |
5b7d70c6 BD |
1418 | |
1419 | if (!hs_ep->req && result >= 0) { | |
1420 | restart = !list_empty(&hs_ep->queue); | |
1421 | if (restart) { | |
1422 | hs_req = get_ep_head(hs_ep); | |
1f91b4cc | 1423 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); |
5b7d70c6 BD |
1424 | } |
1425 | } | |
1426 | } | |
1427 | ||
5b7d70c6 | 1428 | /** |
1f91b4cc | 1429 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
1430 | * @hsotg: The device state. |
1431 | * @ep_idx: The endpoint index for the data | |
1432 | * @size: The size of data in the fifo, in bytes | |
1433 | * | |
1434 | * The FIFO status shows there is data to read from the FIFO for a given | |
1435 | * endpoint, so sort out whether we need to read the data into a request | |
1436 | * that has been made for that endpoint. | |
1437 | */ | |
1f91b4cc | 1438 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1439 | { |
1f91b4cc FB |
1440 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
1441 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1442 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1443 | int to_read; |
1444 | int max_req; | |
1445 | int read_ptr; | |
1446 | ||
22258f49 | 1447 | |
5b7d70c6 | 1448 | if (!hs_req) { |
95c8bc36 | 1449 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1450 | int ptr; |
1451 | ||
6b448af4 | 1452 | dev_dbg(hsotg->dev, |
47a1685f | 1453 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1454 | __func__, size, ep_idx, epctl); |
1455 | ||
1456 | /* dump the data from the FIFO, we've nothing we can do */ | |
1457 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 1458 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
1459 | |
1460 | return; | |
1461 | } | |
1462 | ||
5b7d70c6 BD |
1463 | to_read = size; |
1464 | read_ptr = hs_req->req.actual; | |
1465 | max_req = hs_req->req.length - read_ptr; | |
1466 | ||
a33e7136 BD |
1467 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1468 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1469 | ||
5b7d70c6 | 1470 | if (to_read > max_req) { |
8b9bc460 LM |
1471 | /* |
1472 | * more data appeared than we where willing | |
5b7d70c6 BD |
1473 | * to deal with in this request. |
1474 | */ | |
1475 | ||
1476 | /* currently we don't deal this */ | |
1477 | WARN_ON_ONCE(1); | |
1478 | } | |
1479 | ||
5b7d70c6 BD |
1480 | hs_ep->total_data += to_read; |
1481 | hs_req->req.actual += to_read; | |
1482 | to_read = DIV_ROUND_UP(to_read, 4); | |
1483 | ||
8b9bc460 LM |
1484 | /* |
1485 | * note, we might over-write the buffer end by 3 bytes depending on | |
1486 | * alignment of the data. | |
1487 | */ | |
1a7ed5be | 1488 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1489 | } |
1490 | ||
1491 | /** | |
1f91b4cc | 1492 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1493 | * @hsotg: The device instance |
fe0b94ab | 1494 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1495 | * |
1496 | * Generate a zero-length IN packet request for terminating a SETUP | |
1497 | * transaction. | |
1498 | * | |
1499 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1500 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1501 | * the TxFIFO. |
1502 | */ | |
1f91b4cc | 1503 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1504 | { |
c6f5c050 | 1505 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1506 | hsotg->eps_out[0]->dir_in = dir_in; |
1507 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1508 | |
1f91b4cc | 1509 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1510 | } |
1511 | ||
ec1f9d9f RB |
1512 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
1513 | u32 epctl_reg) | |
1514 | { | |
1515 | u32 ctrl; | |
1516 | ||
1517 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
1518 | if (ctrl & DXEPCTL_EOFRNUM) | |
1519 | ctrl |= DXEPCTL_SETEVENFR; | |
1520 | else | |
1521 | ctrl |= DXEPCTL_SETODDFR; | |
1522 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
1523 | } | |
1524 | ||
5b7d70c6 | 1525 | /** |
1f91b4cc | 1526 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
1527 | * @hsotg: The device instance |
1528 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1529 | * |
1530 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1531 | * transfer for an OUT endpoint has been completed, either by a short | |
1532 | * packet or by the finish of a transfer. | |
8b9bc460 | 1533 | */ |
1f91b4cc | 1534 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1535 | { |
95c8bc36 | 1536 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
1537 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
1538 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 1539 | struct usb_request *req = &hs_req->req; |
47a1685f | 1540 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1541 | int result = 0; |
1542 | ||
1543 | if (!hs_req) { | |
1544 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1545 | return; | |
1546 | } | |
1547 | ||
fe0b94ab MYK |
1548 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1549 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
1550 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
1551 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
1552 | return; |
1553 | } | |
1554 | ||
5b7d70c6 | 1555 | if (using_dma(hsotg)) { |
5b7d70c6 | 1556 | unsigned size_done; |
5b7d70c6 | 1557 | |
8b9bc460 LM |
1558 | /* |
1559 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1560 | * is left in the endpoint size register and then working it |
1561 | * out from the amount we loaded for the transfer. | |
1562 | * | |
1563 | * We need to do this as DMA pointers are always 32bit aligned | |
1564 | * so may overshoot/undershoot the transfer. | |
1565 | */ | |
1566 | ||
5b7d70c6 BD |
1567 | size_done = hs_ep->size_loaded - size_left; |
1568 | size_done += hs_ep->last_load; | |
1569 | ||
1570 | req->actual = size_done; | |
1571 | } | |
1572 | ||
a33e7136 BD |
1573 | /* if there is more request to do, schedule new transfer */ |
1574 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 1575 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
1576 | return; |
1577 | } | |
1578 | ||
5b7d70c6 BD |
1579 | if (req->actual < req->length && req->short_not_ok) { |
1580 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1581 | __func__, req->actual, req->length); | |
1582 | ||
8b9bc460 LM |
1583 | /* |
1584 | * todo - what should we return here? there's no one else | |
1585 | * even bothering to check the status. | |
1586 | */ | |
5b7d70c6 BD |
1587 | } |
1588 | ||
fe0b94ab MYK |
1589 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1590 | /* Move to STATUS IN */ | |
1f91b4cc | 1591 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 1592 | return; |
5b7d70c6 BD |
1593 | } |
1594 | ||
ec1f9d9f RB |
1595 | /* |
1596 | * Slave mode OUT transfers do not go through XferComplete so | |
1597 | * adjust the ISOC parity here. | |
1598 | */ | |
1599 | if (!using_dma(hsotg)) { | |
1600 | hs_ep->has_correct_parity = 1; | |
1601 | if (hs_ep->isochronous && hs_ep->interval == 1) | |
1602 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
1603 | } | |
1604 | ||
1f91b4cc | 1605 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1606 | } |
1607 | ||
1608 | /** | |
1f91b4cc | 1609 | * dwc2_hsotg_read_frameno - read current frame number |
5b7d70c6 BD |
1610 | * @hsotg: The device instance |
1611 | * | |
1612 | * Return the current frame number | |
8b9bc460 | 1613 | */ |
1f91b4cc | 1614 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1615 | { |
1616 | u32 dsts; | |
1617 | ||
95c8bc36 | 1618 | dsts = dwc2_readl(hsotg->regs + DSTS); |
94cb8fd6 LM |
1619 | dsts &= DSTS_SOFFN_MASK; |
1620 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1621 | |
1622 | return dsts; | |
1623 | } | |
1624 | ||
1625 | /** | |
1f91b4cc | 1626 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
1627 | * @hsotg: The device instance |
1628 | * | |
1629 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1630 | * that requires processing, so find out what is in there and do the | |
1631 | * appropriate read. | |
1632 | * | |
25985edc | 1633 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1634 | * chunks, so if you have x packets received on an endpoint you'll get x |
1635 | * FIFO events delivered, each with a packet's worth of data in it. | |
1636 | * | |
1637 | * When using DMA, we should not be processing events from the RXFIFO | |
1638 | * as the actual data should be sent to the memory directly and we turn | |
1639 | * on the completion interrupts to get notifications of transfer completion. | |
1640 | */ | |
1f91b4cc | 1641 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1642 | { |
95c8bc36 | 1643 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1644 | u32 epnum, status, size; |
1645 | ||
1646 | WARN_ON(using_dma(hsotg)); | |
1647 | ||
47a1685f DN |
1648 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1649 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1650 | |
47a1685f DN |
1651 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1652 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 1653 | |
d7c747c5 | 1654 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
5b7d70c6 BD |
1655 | __func__, grxstsr, size, epnum); |
1656 | ||
47a1685f DN |
1657 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1658 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1659 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1660 | break; |
1661 | ||
47a1685f | 1662 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 1663 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 1664 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
1665 | |
1666 | if (!using_dma(hsotg)) | |
1f91b4cc | 1667 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1668 | break; |
1669 | ||
47a1685f | 1670 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1671 | dev_dbg(hsotg->dev, |
1672 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1673 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1674 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 1675 | /* |
1f91b4cc | 1676 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
1677 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
1678 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1679 | */ | |
1680 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 1681 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1682 | break; |
1683 | ||
47a1685f | 1684 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 1685 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1686 | break; |
1687 | ||
47a1685f | 1688 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1689 | dev_dbg(hsotg->dev, |
1690 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1691 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1692 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1693 | |
fe0b94ab MYK |
1694 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1695 | ||
1f91b4cc | 1696 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1697 | break; |
1698 | ||
1699 | default: | |
1700 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1701 | __func__, grxstsr); | |
1702 | ||
1f91b4cc | 1703 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
1704 | break; |
1705 | } | |
1706 | } | |
1707 | ||
1708 | /** | |
1f91b4cc | 1709 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 1710 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 1711 | */ |
1f91b4cc | 1712 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
1713 | { |
1714 | switch (mps) { | |
1715 | case 64: | |
94cb8fd6 | 1716 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1717 | case 32: |
94cb8fd6 | 1718 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1719 | case 16: |
94cb8fd6 | 1720 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1721 | case 8: |
94cb8fd6 | 1722 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1723 | } |
1724 | ||
1725 | /* bad max packet size, warn and return invalid result */ | |
1726 | WARN_ON(1); | |
1727 | return (u32)-1; | |
1728 | } | |
1729 | ||
1730 | /** | |
1f91b4cc | 1731 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
1732 | * @hsotg: The driver state. |
1733 | * @ep: The index number of the endpoint | |
1734 | * @mps: The maximum packet size in bytes | |
1735 | * | |
1736 | * Configure the maximum packet size for the given endpoint, updating | |
1737 | * the hardware control registers to reflect this. | |
1738 | */ | |
1f91b4cc | 1739 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1740 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1741 | { |
1f91b4cc | 1742 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1743 | void __iomem *regs = hsotg->regs; |
1744 | u32 mpsval; | |
4fca54aa | 1745 | u32 mcval; |
5b7d70c6 BD |
1746 | u32 reg; |
1747 | ||
c6f5c050 MYK |
1748 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1749 | if (!hs_ep) | |
1750 | return; | |
1751 | ||
5b7d70c6 BD |
1752 | if (ep == 0) { |
1753 | /* EP0 is a special case */ | |
1f91b4cc | 1754 | mpsval = dwc2_hsotg_ep0_mps(mps); |
5b7d70c6 BD |
1755 | if (mpsval > 3) |
1756 | goto bad_mps; | |
e9edd199 | 1757 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1758 | hs_ep->mc = 1; |
5b7d70c6 | 1759 | } else { |
47a1685f | 1760 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1761 | if (mpsval > 1024) |
5b7d70c6 | 1762 | goto bad_mps; |
4fca54aa RB |
1763 | mcval = ((mps >> 11) & 0x3) + 1; |
1764 | hs_ep->mc = mcval; | |
1765 | if (mcval > 3) | |
1766 | goto bad_mps; | |
e9edd199 | 1767 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1768 | } |
1769 | ||
c6f5c050 | 1770 | if (dir_in) { |
95c8bc36 | 1771 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 MYK |
1772 | reg &= ~DXEPCTL_MPS_MASK; |
1773 | reg |= mpsval; | |
95c8bc36 | 1774 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 1775 | } else { |
95c8bc36 | 1776 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 1777 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1778 | reg |= mpsval; |
95c8bc36 | 1779 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1780 | } |
5b7d70c6 BD |
1781 | |
1782 | return; | |
1783 | ||
1784 | bad_mps: | |
1785 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1786 | } | |
1787 | ||
9c39ddc6 | 1788 | /** |
1f91b4cc | 1789 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
1790 | * @hsotg: The driver state |
1791 | * @idx: The index for the endpoint (0..15) | |
1792 | */ | |
1f91b4cc | 1793 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1794 | { |
1795 | int timeout; | |
1796 | int val; | |
1797 | ||
95c8bc36 AS |
1798 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
1799 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
1800 | |
1801 | /* wait until the fifo is flushed */ | |
1802 | timeout = 100; | |
1803 | ||
1804 | while (1) { | |
95c8bc36 | 1805 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1806 | |
47a1685f | 1807 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1808 | break; |
1809 | ||
1810 | if (--timeout == 0) { | |
1811 | dev_err(hsotg->dev, | |
1812 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1813 | __func__, val); | |
e0cbe595 | 1814 | break; |
9c39ddc6 AT |
1815 | } |
1816 | ||
1817 | udelay(1); | |
1818 | } | |
1819 | } | |
5b7d70c6 BD |
1820 | |
1821 | /** | |
1f91b4cc | 1822 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
1823 | * @hsotg: The driver state |
1824 | * @hs_ep: The driver endpoint to check. | |
1825 | * | |
1826 | * Check to see if there is a request that has data to send, and if so | |
1827 | * make an attempt to write data into the FIFO. | |
1828 | */ | |
1f91b4cc FB |
1829 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
1830 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1831 | { |
1f91b4cc | 1832 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 1833 | |
afcf4169 RB |
1834 | if (!hs_ep->dir_in || !hs_req) { |
1835 | /** | |
1836 | * if request is not enqueued, we disable interrupts | |
1837 | * for endpoints, excepting ep0 | |
1838 | */ | |
1839 | if (hs_ep->index != 0) | |
1f91b4cc | 1840 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
afcf4169 | 1841 | hs_ep->dir_in, 0); |
5b7d70c6 | 1842 | return 0; |
afcf4169 | 1843 | } |
5b7d70c6 BD |
1844 | |
1845 | if (hs_req->req.actual < hs_req->req.length) { | |
1846 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1847 | hs_ep->index); | |
1f91b4cc | 1848 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1849 | } |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
1854 | /** | |
1f91b4cc | 1855 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
1856 | * @hsotg: The device state. |
1857 | * @hs_ep: The endpoint that has just completed. | |
1858 | * | |
1859 | * An IN transfer has been completed, update the transfer's state and then | |
1860 | * call the relevant completion routines. | |
1861 | */ | |
1f91b4cc FB |
1862 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
1863 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1864 | { |
1f91b4cc | 1865 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 1866 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1867 | int size_left, size_done; |
1868 | ||
1869 | if (!hs_req) { | |
1870 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1871 | return; | |
1872 | } | |
1873 | ||
d3ca0259 | 1874 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1875 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1876 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
1f91b4cc | 1877 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
1878 | if (hsotg->test_mode) { |
1879 | int ret; | |
1880 | ||
1f91b4cc | 1881 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
1882 | if (ret < 0) { |
1883 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
1884 | hsotg->test_mode); | |
1f91b4cc | 1885 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
1886 | return; |
1887 | } | |
1888 | } | |
1f91b4cc | 1889 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1890 | return; |
1891 | } | |
1892 | ||
8b9bc460 LM |
1893 | /* |
1894 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1895 | * in the endpoint size register and then working it out from |
1896 | * the amount we loaded for the transfer. | |
1897 | * | |
1898 | * We do this even for DMA, as the transfer may have incremented | |
1899 | * past the end of the buffer (DMA transfers are always 32bit | |
1900 | * aligned). | |
1901 | */ | |
1902 | ||
47a1685f | 1903 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1904 | |
1905 | size_done = hs_ep->size_loaded - size_left; | |
1906 | size_done += hs_ep->last_load; | |
1907 | ||
1908 | if (hs_req->req.actual != size_done) | |
1909 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1910 | __func__, hs_req->req.actual, size_done); | |
1911 | ||
1912 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1913 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1914 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1915 | ||
5b7d70c6 BD |
1916 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
1917 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 1918 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
1919 | return; |
1920 | } | |
1921 | ||
f71b5e25 | 1922 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 1923 | if (hs_ep->send_zlp) { |
1f91b4cc | 1924 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 1925 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
1926 | /* transfer will be completed on next complete interrupt */ |
1927 | return; | |
1928 | } | |
1929 | ||
fe0b94ab MYK |
1930 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
1931 | /* Move to STATUS OUT */ | |
1f91b4cc | 1932 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
1933 | return; |
1934 | } | |
1935 | ||
1f91b4cc | 1936 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
1937 | } |
1938 | ||
1939 | /** | |
1f91b4cc | 1940 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
1941 | * @hsotg: The driver state |
1942 | * @idx: The index for the endpoint (0..15) | |
1943 | * @dir_in: Set if this is an IN endpoint | |
1944 | * | |
1945 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 1946 | */ |
1f91b4cc | 1947 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
1948 | int dir_in) |
1949 | { | |
1f91b4cc | 1950 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
1951 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
1952 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
1953 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 1954 | u32 ints; |
1479e841 | 1955 | u32 ctrl; |
5b7d70c6 | 1956 | |
95c8bc36 AS |
1957 | ints = dwc2_readl(hsotg->regs + epint_reg); |
1958 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
5b7d70c6 | 1959 | |
a3395f0d | 1960 | /* Clear endpoint interrupts */ |
95c8bc36 | 1961 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 1962 | |
c6f5c050 MYK |
1963 | if (!hs_ep) { |
1964 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
1965 | __func__, idx, dir_in ? "in" : "out"); | |
1966 | return; | |
1967 | } | |
1968 | ||
5b7d70c6 BD |
1969 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1970 | __func__, idx, dir_in ? "in" : "out", ints); | |
1971 | ||
b787d755 MYK |
1972 | /* Don't process XferCompl interrupt if it is a setup packet */ |
1973 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
1974 | ints &= ~DXEPINT_XFERCOMPL; | |
1975 | ||
47a1685f | 1976 | if (ints & DXEPINT_XFERCOMPL) { |
ec1f9d9f RB |
1977 | hs_ep->has_correct_parity = 1; |
1978 | if (hs_ep->isochronous && hs_ep->interval == 1) | |
1979 | dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg); | |
1479e841 | 1980 | |
5b7d70c6 | 1981 | dev_dbg(hsotg->dev, |
47a1685f | 1982 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
1983 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
1984 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 1985 | |
8b9bc460 LM |
1986 | /* |
1987 | * we get OutDone from the FIFO, so we only need to look | |
1988 | * at completing IN requests here | |
1989 | */ | |
5b7d70c6 | 1990 | if (dir_in) { |
1f91b4cc | 1991 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
5b7d70c6 | 1992 | |
c9a64ea8 | 1993 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 1994 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1995 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
1996 | /* |
1997 | * We're using DMA, we need to fire an OutDone here | |
1998 | * as we ignore the RXFIFO. | |
1999 | */ | |
5b7d70c6 | 2000 | |
1f91b4cc | 2001 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2002 | } |
5b7d70c6 BD |
2003 | } |
2004 | ||
47a1685f | 2005 | if (ints & DXEPINT_EPDISBLD) { |
5b7d70c6 | 2006 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 2007 | |
9c39ddc6 | 2008 | if (dir_in) { |
95c8bc36 | 2009 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); |
9c39ddc6 | 2010 | |
1f91b4cc | 2011 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); |
9c39ddc6 | 2012 | |
47a1685f DN |
2013 | if ((epctl & DXEPCTL_STALL) && |
2014 | (epctl & DXEPCTL_EPTYPE_BULK)) { | |
95c8bc36 | 2015 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9c39ddc6 | 2016 | |
47a1685f | 2017 | dctl |= DCTL_CGNPINNAK; |
95c8bc36 | 2018 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9c39ddc6 AT |
2019 | } |
2020 | } | |
2021 | } | |
2022 | ||
47a1685f | 2023 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2024 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2025 | |
47a1685f | 2026 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2027 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2028 | ||
2029 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2030 | /* |
2031 | * this is the notification we've received a | |
5b7d70c6 BD |
2032 | * setup packet. In non-DMA mode we'd get this |
2033 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2034 | * the setup here. |
2035 | */ | |
5b7d70c6 BD |
2036 | |
2037 | if (dir_in) | |
2038 | WARN_ON_ONCE(1); | |
2039 | else | |
1f91b4cc | 2040 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2041 | } |
5b7d70c6 BD |
2042 | } |
2043 | ||
47a1685f | 2044 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2045 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2046 | |
1479e841 | 2047 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2048 | /* not sure if this is important, but we'll clear it anyway */ |
47a1685f | 2049 | if (ints & DIEPMSK_INTKNTXFEMPMSK) { |
5b7d70c6 BD |
2050 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2051 | __func__, idx); | |
5b7d70c6 BD |
2052 | } |
2053 | ||
2054 | /* this probably means something bad is happening */ | |
47a1685f | 2055 | if (ints & DIEPMSK_INTKNEPMISMSK) { |
5b7d70c6 BD |
2056 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2057 | __func__, idx); | |
5b7d70c6 | 2058 | } |
10aebc77 BD |
2059 | |
2060 | /* FIFO has space or is empty (see GAHBCFG) */ | |
2061 | if (hsotg->dedicated_fifos && | |
47a1685f | 2062 | ints & DIEPMSK_TXFIFOEMPTY) { |
10aebc77 BD |
2063 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
2064 | __func__, idx); | |
70fa030f | 2065 | if (!using_dma(hsotg)) |
1f91b4cc | 2066 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 2067 | } |
5b7d70c6 | 2068 | } |
5b7d70c6 BD |
2069 | } |
2070 | ||
2071 | /** | |
1f91b4cc | 2072 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
2073 | * @hsotg: The device state. |
2074 | * | |
2075 | * Handle updating the device settings after the enumeration phase has | |
2076 | * been completed. | |
8b9bc460 | 2077 | */ |
1f91b4cc | 2078 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2079 | { |
95c8bc36 | 2080 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 2081 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 2082 | |
8b9bc460 LM |
2083 | /* |
2084 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 2085 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2086 | * we connected at. |
2087 | */ | |
5b7d70c6 BD |
2088 | |
2089 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2090 | ||
8b9bc460 LM |
2091 | /* |
2092 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2093 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2094 | * not advertise a 64byte MPS on EP0. |
2095 | */ | |
5b7d70c6 BD |
2096 | |
2097 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 2098 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
2099 | case DSTS_ENUMSPD_FS: |
2100 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 2101 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 2102 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2103 | ep_mps = 1023; |
5b7d70c6 BD |
2104 | break; |
2105 | ||
47a1685f | 2106 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 2107 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 2108 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2109 | ep_mps = 1024; |
5b7d70c6 BD |
2110 | break; |
2111 | ||
47a1685f | 2112 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 2113 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2114 | /* |
2115 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2116 | * moment, and the documentation seems to imply that it isn't |
2117 | * supported by the PHYs on some of the devices. | |
2118 | */ | |
2119 | break; | |
2120 | } | |
e538dfda MN |
2121 | dev_info(hsotg->dev, "new device is %s\n", |
2122 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2123 | |
8b9bc460 LM |
2124 | /* |
2125 | * we should now know the maximum packet size for an | |
2126 | * endpoint, so set the endpoints to a default value. | |
2127 | */ | |
5b7d70c6 BD |
2128 | |
2129 | if (ep0_mps) { | |
2130 | int i; | |
c6f5c050 | 2131 | /* Initialize ep0 for both in and out directions */ |
1f91b4cc FB |
2132 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); |
2133 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
c6f5c050 MYK |
2134 | for (i = 1; i < hsotg->num_of_eps; i++) { |
2135 | if (hsotg->eps_in[i]) | |
1f91b4cc | 2136 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); |
c6f5c050 | 2137 | if (hsotg->eps_out[i]) |
1f91b4cc | 2138 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); |
c6f5c050 | 2139 | } |
5b7d70c6 BD |
2140 | } |
2141 | ||
2142 | /* ensure after enumeration our EP0 is active */ | |
2143 | ||
1f91b4cc | 2144 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
2145 | |
2146 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2147 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2148 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2149 | } |
2150 | ||
2151 | /** | |
2152 | * kill_all_requests - remove all requests from the endpoint's queue | |
2153 | * @hsotg: The device state. | |
2154 | * @ep: The endpoint the requests may be on. | |
2155 | * @result: The result code to use. | |
5b7d70c6 BD |
2156 | * |
2157 | * Go through the requests on the given endpoint and mark them | |
2158 | * completed with the given result code. | |
2159 | */ | |
941fcce4 | 2160 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 2161 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 2162 | int result) |
5b7d70c6 | 2163 | { |
1f91b4cc | 2164 | struct dwc2_hsotg_req *req, *treq; |
b203d0a2 | 2165 | unsigned size; |
5b7d70c6 | 2166 | |
6b448af4 | 2167 | ep->req = NULL; |
5b7d70c6 | 2168 | |
6b448af4 | 2169 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 2170 | dwc2_hsotg_complete_request(hsotg, ep, req, |
5b7d70c6 | 2171 | result); |
6b448af4 | 2172 | |
b203d0a2 RB |
2173 | if (!hsotg->dedicated_fifos) |
2174 | return; | |
95c8bc36 | 2175 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; |
b203d0a2 | 2176 | if (size < ep->fifo_size) |
1f91b4cc | 2177 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
2178 | } |
2179 | ||
5b7d70c6 | 2180 | /** |
1f91b4cc | 2181 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2182 | * @hsotg: The device state. |
2183 | * | |
5e891342 LM |
2184 | * The device has been disconnected. Remove all current |
2185 | * transactions and signal the gadget driver that this | |
2186 | * has happened. | |
8b9bc460 | 2187 | */ |
1f91b4cc | 2188 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2189 | { |
2190 | unsigned ep; | |
2191 | ||
4ace06e8 MS |
2192 | if (!hsotg->connected) |
2193 | return; | |
2194 | ||
2195 | hsotg->connected = 0; | |
9e14d0a5 | 2196 | hsotg->test_mode = 0; |
c6f5c050 MYK |
2197 | |
2198 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2199 | if (hsotg->eps_in[ep]) | |
2200 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2201 | -ESHUTDOWN); | |
2202 | if (hsotg->eps_out[ep]) | |
2203 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2204 | -ESHUTDOWN); | |
2205 | } | |
5b7d70c6 BD |
2206 | |
2207 | call_gadget(hsotg, disconnect); | |
065d3931 | 2208 | hsotg->lx_state = DWC2_L3; |
5b7d70c6 BD |
2209 | } |
2210 | ||
2211 | /** | |
1f91b4cc | 2212 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
2213 | * @hsotg: The device state: |
2214 | * @periodic: True if this is a periodic FIFO interrupt | |
2215 | */ | |
1f91b4cc | 2216 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 2217 | { |
1f91b4cc | 2218 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
2219 | int epno, ret; |
2220 | ||
2221 | /* look through for any more data to transmit */ | |
b3f489b2 | 2222 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2223 | ep = index_to_ep(hsotg, epno, 1); |
2224 | ||
2225 | if (!ep) | |
2226 | continue; | |
5b7d70c6 BD |
2227 | |
2228 | if (!ep->dir_in) | |
2229 | continue; | |
2230 | ||
2231 | if ((periodic && !ep->periodic) || | |
2232 | (!periodic && ep->periodic)) | |
2233 | continue; | |
2234 | ||
1f91b4cc | 2235 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
2236 | if (ret < 0) |
2237 | break; | |
2238 | } | |
2239 | } | |
2240 | ||
5b7d70c6 | 2241 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2242 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2243 | GINTSTS_PTXFEMP | \ | |
2244 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2245 | |
8b9bc460 | 2246 | /** |
1f91b4cc | 2247 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
2248 | * @hsotg: The device state |
2249 | * | |
2250 | * Issue a soft reset to the core, and await the core finishing it. | |
2251 | */ | |
1f91b4cc | 2252 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
643cc4de | 2253 | bool is_usb_reset) |
308d734e | 2254 | { |
1ee6903b | 2255 | u32 intmsk; |
643cc4de GH |
2256 | u32 val; |
2257 | ||
5390d438 MYK |
2258 | /* Kill any ep0 requests as controller will be reinitialized */ |
2259 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
2260 | ||
643cc4de | 2261 | if (!is_usb_reset) |
241729ba | 2262 | if (dwc2_core_reset(hsotg)) |
86de4895 | 2263 | return; |
308d734e LM |
2264 | |
2265 | /* | |
2266 | * we must now enable ep0 ready for host detection and then | |
2267 | * set configuration. | |
2268 | */ | |
2269 | ||
2270 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
fa4a8d72 | 2271 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
95c8bc36 | 2272 | dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
f889f23d | 2273 | (val << GUSBCFG_USBTRDTIM_SHIFT), hsotg->regs + GUSBCFG); |
308d734e | 2274 | |
1f91b4cc | 2275 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 2276 | |
643cc4de GH |
2277 | if (!is_usb_reset) |
2278 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
308d734e | 2279 | |
95c8bc36 | 2280 | dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2281 | |
2282 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 2283 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2284 | |
2285 | /* Clear any pending interrupts */ | |
95c8bc36 | 2286 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 2287 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 2288 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
2289 | GINTSTS_USBRST | GINTSTS_RESETDET | |
2290 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
ec1f9d9f RB |
2291 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
2292 | GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b GH |
2293 | |
2294 | if (hsotg->core_params->external_id_pin_ctl <= 0) | |
2295 | intmsk |= GINTSTS_CONIDSTSCHNG; | |
2296 | ||
2297 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e LM |
2298 | |
2299 | if (using_dma(hsotg)) | |
95c8bc36 AS |
2300 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
2301 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), | |
2302 | hsotg->regs + GAHBCFG); | |
308d734e | 2303 | else |
95c8bc36 AS |
2304 | dwc2_writel(((hsotg->dedicated_fifos) ? |
2305 | (GAHBCFG_NP_TXF_EMP_LVL | | |
2306 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2307 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
308d734e LM |
2308 | |
2309 | /* | |
8acc8296 RB |
2310 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2311 | * when we have no data to transfer. Otherwise we get being flooded by | |
2312 | * interrupts. | |
308d734e LM |
2313 | */ |
2314 | ||
95c8bc36 | 2315 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 2316 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f DN |
2317 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
2318 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2319 | DIEPMSK_INTKNEPMISMSK, | |
2320 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2321 | |
2322 | /* | |
2323 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2324 | * DMA mode we may need this. | |
2325 | */ | |
95c8bc36 | 2326 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
47a1685f DN |
2327 | DIEPMSK_TIMEOUTMSK) : 0) | |
2328 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2329 | DOEPMSK_SETUPMSK, | |
2330 | hsotg->regs + DOEPMSK); | |
308d734e | 2331 | |
95c8bc36 | 2332 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2333 | |
2334 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2335 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2336 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2337 | |
2338 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 2339 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2340 | |
2341 | /* | |
2342 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2343 | * the data. In DMA mode, we get events from the FIFO but also | |
2344 | * things we cannot process, so do not use it. | |
2345 | */ | |
2346 | if (!using_dma(hsotg)) | |
1f91b4cc | 2347 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2348 | |
2349 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
2350 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
2351 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 2352 | |
643cc4de GH |
2353 | if (!is_usb_reset) { |
2354 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2355 | udelay(10); /* see openiboot */ | |
2356 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2357 | } | |
308d734e | 2358 | |
95c8bc36 | 2359 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
2360 | |
2361 | /* | |
94cb8fd6 | 2362 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2363 | * writing to the EPCTL register.. |
2364 | */ | |
2365 | ||
2366 | /* set to read 1 8byte packet */ | |
95c8bc36 | 2367 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 2368 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 2369 | |
95c8bc36 | 2370 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2371 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2372 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2373 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2374 | |
2375 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 2376 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2377 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 2378 | |
1f91b4cc | 2379 | dwc2_hsotg_enqueue_setup(hsotg); |
308d734e LM |
2380 | |
2381 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2382 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2383 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2384 | |
2385 | /* clear global NAKs */ | |
643cc4de GH |
2386 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
2387 | if (!is_usb_reset) | |
2388 | val |= DCTL_SFTDISCON; | |
2389 | __orr32(hsotg->regs + DCTL, val); | |
308d734e LM |
2390 | |
2391 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2392 | mdelay(3); | |
2393 | ||
065d3931 | 2394 | hsotg->lx_state = DWC2_L0; |
ad38dc5d MS |
2395 | } |
2396 | ||
1f91b4cc | 2397 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2398 | { |
2399 | /* set the soft-disconnect bit */ | |
2400 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2401 | } | |
ac3c81f3 | 2402 | |
1f91b4cc | 2403 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2404 | { |
308d734e | 2405 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2406 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2407 | } |
2408 | ||
5b7d70c6 | 2409 | /** |
1f91b4cc | 2410 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
2411 | * @irq: The IRQ number triggered |
2412 | * @pw: The pw value when registered the handler. | |
2413 | */ | |
1f91b4cc | 2414 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 2415 | { |
941fcce4 | 2416 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2417 | int retry_count = 8; |
2418 | u32 gintsts; | |
2419 | u32 gintmsk; | |
2420 | ||
5ad1d316 | 2421 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2422 | irq_retry: |
95c8bc36 AS |
2423 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
2424 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2425 | |
2426 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2427 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2428 | ||
2429 | gintsts &= gintmsk; | |
2430 | ||
8fc37b82 MYK |
2431 | if (gintsts & GINTSTS_RESETDET) { |
2432 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
2433 | ||
2434 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
2435 | ||
2436 | /* This event must be used only if controller is suspended */ | |
2437 | if (hsotg->lx_state == DWC2_L2) { | |
2438 | dwc2_exit_hibernation(hsotg, true); | |
2439 | hsotg->lx_state = DWC2_L0; | |
2440 | } | |
2441 | } | |
2442 | ||
2443 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
2444 | ||
2445 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); | |
2446 | u32 connected = hsotg->connected; | |
2447 | ||
2448 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
2449 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
2450 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
2451 | ||
2452 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
2453 | ||
2454 | /* Report disconnection if it is not already done. */ | |
2455 | dwc2_hsotg_disconnect(hsotg); | |
2456 | ||
2457 | if (usb_status & GOTGCTL_BSESVLD && connected) | |
2458 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
2459 | } | |
2460 | ||
47a1685f | 2461 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 2462 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 2463 | |
1f91b4cc | 2464 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
2465 | } |
2466 | ||
47a1685f | 2467 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
2468 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
2469 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 2470 | u32 daint_out, daint_in; |
5b7d70c6 BD |
2471 | int ep; |
2472 | ||
7e804650 | 2473 | daint &= daintmsk; |
47a1685f DN |
2474 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2475 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2476 | |
5b7d70c6 BD |
2477 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2478 | ||
cec87f1d MYK |
2479 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2480 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 2481 | if (daint_out & 1) |
1f91b4cc | 2482 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
2483 | } |
2484 | ||
cec87f1d MYK |
2485 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2486 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 2487 | if (daint_in & 1) |
1f91b4cc | 2488 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 2489 | } |
5b7d70c6 BD |
2490 | } |
2491 | ||
5b7d70c6 BD |
2492 | /* check both FIFOs */ |
2493 | ||
47a1685f | 2494 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2495 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2496 | ||
8b9bc460 LM |
2497 | /* |
2498 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2499 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2500 | * it needs re-enabling |
2501 | */ | |
5b7d70c6 | 2502 | |
1f91b4cc FB |
2503 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
2504 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
2505 | } |
2506 | ||
47a1685f | 2507 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2508 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2509 | ||
94cb8fd6 | 2510 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2511 | |
1f91b4cc FB |
2512 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
2513 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
2514 | } |
2515 | ||
47a1685f | 2516 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2517 | /* |
2518 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 2519 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
2520 | * set. |
2521 | */ | |
5b7d70c6 | 2522 | |
1f91b4cc | 2523 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
2524 | } |
2525 | ||
47a1685f | 2526 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2527 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 2528 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2529 | } |
2530 | ||
8b9bc460 LM |
2531 | /* |
2532 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2533 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2534 | * the occurrence. |
2535 | */ | |
5b7d70c6 | 2536 | |
47a1685f | 2537 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2538 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2539 | ||
3be99cd0 | 2540 | __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK); |
a3395f0d | 2541 | |
1f91b4cc | 2542 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2543 | } |
2544 | ||
47a1685f | 2545 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2546 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2547 | ||
3be99cd0 | 2548 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 2549 | |
1f91b4cc | 2550 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2551 | } |
2552 | ||
ec1f9d9f RB |
2553 | if (gintsts & GINTSTS_INCOMPL_SOIN) { |
2554 | u32 idx, epctl_reg; | |
2555 | struct dwc2_hsotg_ep *hs_ep; | |
2556 | ||
2557 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__); | |
2558 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { | |
2559 | hs_ep = hsotg->eps_in[idx]; | |
2560 | ||
2561 | if (!hs_ep->isochronous || hs_ep->has_correct_parity) | |
2562 | continue; | |
2563 | ||
2564 | epctl_reg = DIEPCTL(idx); | |
2565 | dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg); | |
2566 | } | |
2567 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
2568 | } | |
2569 | ||
2570 | if (gintsts & GINTSTS_INCOMPL_SOOUT) { | |
2571 | u32 idx, epctl_reg; | |
2572 | struct dwc2_hsotg_ep *hs_ep; | |
2573 | ||
2574 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
2575 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { | |
2576 | hs_ep = hsotg->eps_out[idx]; | |
2577 | ||
2578 | if (!hs_ep->isochronous || hs_ep->has_correct_parity) | |
2579 | continue; | |
2580 | ||
2581 | epctl_reg = DOEPCTL(idx); | |
2582 | dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg); | |
2583 | } | |
2584 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
2585 | } | |
2586 | ||
8b9bc460 LM |
2587 | /* |
2588 | * if we've had fifo events, we should try and go around the | |
2589 | * loop again to see if there's any point in returning yet. | |
2590 | */ | |
5b7d70c6 BD |
2591 | |
2592 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2593 | goto irq_retry; | |
2594 | ||
5ad1d316 LM |
2595 | spin_unlock(&hsotg->lock); |
2596 | ||
5b7d70c6 BD |
2597 | return IRQ_HANDLED; |
2598 | } | |
2599 | ||
2600 | /** | |
1f91b4cc | 2601 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
2602 | * @ep: The USB endpint to configure |
2603 | * @desc: The USB endpoint descriptor to configure with. | |
2604 | * | |
2605 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2606 | */ |
1f91b4cc | 2607 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
5b7d70c6 BD |
2608 | const struct usb_endpoint_descriptor *desc) |
2609 | { | |
1f91b4cc | 2610 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2611 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 2612 | unsigned long flags; |
ca4c55ad | 2613 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
2614 | u32 epctrl_reg; |
2615 | u32 epctrl; | |
2616 | u32 mps; | |
ca4c55ad MYK |
2617 | unsigned int dir_in; |
2618 | unsigned int i, val, size; | |
19c190f9 | 2619 | int ret = 0; |
5b7d70c6 BD |
2620 | |
2621 | dev_dbg(hsotg->dev, | |
2622 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2623 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2624 | desc->wMaxPacketSize, desc->bInterval); | |
2625 | ||
2626 | /* not to be called for EP0 */ | |
2627 | WARN_ON(index == 0); | |
2628 | ||
2629 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2630 | if (dir_in != hs_ep->dir_in) { | |
2631 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2632 | return -EINVAL; | |
2633 | } | |
2634 | ||
29cc8897 | 2635 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 | 2636 | |
1f91b4cc | 2637 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 2638 | |
94cb8fd6 | 2639 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 2640 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2641 | |
2642 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2643 | __func__, epctrl, epctrl_reg); | |
2644 | ||
22258f49 | 2645 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2646 | |
47a1685f DN |
2647 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2648 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2649 | |
8b9bc460 LM |
2650 | /* |
2651 | * mark the endpoint as active, otherwise the core may ignore | |
2652 | * transactions entirely for this endpoint | |
2653 | */ | |
47a1685f | 2654 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2655 | |
8b9bc460 LM |
2656 | /* |
2657 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2658 | * do something with data that we've yet got a request to process |
2659 | * since the RXFIFO will take data for an endpoint even if the | |
2660 | * size register hasn't been set. | |
2661 | */ | |
2662 | ||
47a1685f | 2663 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2664 | |
2665 | /* update the endpoint state */ | |
1f91b4cc | 2666 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
2667 | |
2668 | /* default, set to non-periodic */ | |
1479e841 | 2669 | hs_ep->isochronous = 0; |
5b7d70c6 | 2670 | hs_ep->periodic = 0; |
a18ed7b0 | 2671 | hs_ep->halted = 0; |
1479e841 | 2672 | hs_ep->interval = desc->bInterval; |
ec1f9d9f | 2673 | hs_ep->has_correct_parity = 0; |
5b7d70c6 | 2674 | |
4fca54aa RB |
2675 | if (hs_ep->interval > 1 && hs_ep->mc > 1) |
2676 | dev_err(hsotg->dev, "MC > 1 when interval is not 1\n"); | |
2677 | ||
5b7d70c6 BD |
2678 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2679 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2680 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2681 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 RB |
2682 | hs_ep->isochronous = 1; |
2683 | if (dir_in) | |
2684 | hs_ep->periodic = 1; | |
2685 | break; | |
5b7d70c6 BD |
2686 | |
2687 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2688 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2689 | break; |
2690 | ||
2691 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 2692 | if (dir_in) |
5b7d70c6 | 2693 | hs_ep->periodic = 1; |
5b7d70c6 | 2694 | |
47a1685f | 2695 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2696 | break; |
2697 | ||
2698 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2699 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2700 | break; |
2701 | } | |
2702 | ||
4556e12c MYK |
2703 | /* If fifo is already allocated for this ep */ |
2704 | if (hs_ep->fifo_index) { | |
2705 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
2706 | /* If bigger fifo is required deallocate current one */ | |
2707 | if (size > hs_ep->fifo_size) { | |
2708 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); | |
2709 | hs_ep->fifo_index = 0; | |
2710 | hs_ep->fifo_size = 0; | |
2711 | } | |
2712 | } | |
2713 | ||
8b9bc460 LM |
2714 | /* |
2715 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2716 | * a unique tx-fifo even if it is non-periodic. |
2717 | */ | |
4556e12c | 2718 | if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) { |
ca4c55ad MYK |
2719 | u32 fifo_index = 0; |
2720 | u32 fifo_size = UINT_MAX; | |
b203d0a2 | 2721 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
5f2196bd | 2722 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
2723 | if (hsotg->fifo_map & (1<<i)) |
2724 | continue; | |
95c8bc36 | 2725 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
b203d0a2 RB |
2726 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; |
2727 | if (val < size) | |
2728 | continue; | |
ca4c55ad MYK |
2729 | /* Search for smallest acceptable fifo */ |
2730 | if (val < fifo_size) { | |
2731 | fifo_size = val; | |
2732 | fifo_index = i; | |
2733 | } | |
b203d0a2 | 2734 | } |
ca4c55ad | 2735 | if (!fifo_index) { |
5f2196bd MYK |
2736 | dev_err(hsotg->dev, |
2737 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
2738 | ret = -ENOMEM; |
2739 | goto error; | |
2740 | } | |
ca4c55ad MYK |
2741 | hsotg->fifo_map |= 1 << fifo_index; |
2742 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
2743 | hs_ep->fifo_index = fifo_index; | |
2744 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 2745 | } |
10aebc77 | 2746 | |
5b7d70c6 BD |
2747 | /* for non control endpoints, set PID to D0 */ |
2748 | if (index) | |
47a1685f | 2749 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
2750 | |
2751 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2752 | __func__, epctrl); | |
2753 | ||
95c8bc36 | 2754 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 2755 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 2756 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
2757 | |
2758 | /* enable the endpoint interrupt */ | |
1f91b4cc | 2759 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 2760 | |
b585a48b | 2761 | error: |
22258f49 | 2762 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2763 | return ret; |
5b7d70c6 BD |
2764 | } |
2765 | ||
8b9bc460 | 2766 | /** |
1f91b4cc | 2767 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
2768 | * @ep: The endpoint to disable. |
2769 | */ | |
1f91b4cc | 2770 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 2771 | { |
1f91b4cc | 2772 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2773 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2774 | int dir_in = hs_ep->dir_in; |
2775 | int index = hs_ep->index; | |
2776 | unsigned long flags; | |
2777 | u32 epctrl_reg; | |
2778 | u32 ctrl; | |
2779 | ||
1e011293 | 2780 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 2781 | |
c6f5c050 | 2782 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
2783 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
2784 | return -EINVAL; | |
2785 | } | |
2786 | ||
94cb8fd6 | 2787 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2788 | |
5ad1d316 | 2789 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2790 | |
b203d0a2 RB |
2791 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
2792 | hs_ep->fifo_index = 0; | |
2793 | hs_ep->fifo_size = 0; | |
5b7d70c6 | 2794 | |
95c8bc36 | 2795 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
47a1685f DN |
2796 | ctrl &= ~DXEPCTL_EPENA; |
2797 | ctrl &= ~DXEPCTL_USBACTEP; | |
2798 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
2799 | |
2800 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 2801 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2802 | |
2803 | /* disable endpoint interrupts */ | |
1f91b4cc | 2804 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 2805 | |
1141ea01 MYK |
2806 | /* terminate all requests with shutdown */ |
2807 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
2808 | ||
22258f49 | 2809 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2810 | return 0; |
2811 | } | |
2812 | ||
2813 | /** | |
2814 | * on_list - check request is on the given endpoint | |
2815 | * @ep: The endpoint to check. | |
2816 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2817 | */ |
1f91b4cc | 2818 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 2819 | { |
1f91b4cc | 2820 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
2821 | |
2822 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2823 | if (req == test) | |
2824 | return true; | |
2825 | } | |
2826 | ||
2827 | return false; | |
2828 | } | |
2829 | ||
c524dd5f MYK |
2830 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
2831 | u32 bit, u32 timeout) | |
2832 | { | |
2833 | u32 i; | |
2834 | ||
2835 | for (i = 0; i < timeout; i++) { | |
2836 | if (dwc2_readl(hs_otg->regs + reg) & bit) | |
2837 | return 0; | |
2838 | udelay(1); | |
2839 | } | |
2840 | ||
2841 | return -ETIMEDOUT; | |
2842 | } | |
2843 | ||
2844 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, | |
2845 | struct dwc2_hsotg_ep *hs_ep) | |
2846 | { | |
2847 | u32 epctrl_reg; | |
2848 | u32 epint_reg; | |
2849 | ||
2850 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
2851 | DOEPCTL(hs_ep->index); | |
2852 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
2853 | DOEPINT(hs_ep->index); | |
2854 | ||
2855 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
2856 | hs_ep->name); | |
2857 | if (hs_ep->dir_in) { | |
2858 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); | |
2859 | /* Wait for Nak effect */ | |
2860 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
2861 | DXEPINT_INEPNAKEFF, 100)) | |
2862 | dev_warn(hsotg->dev, | |
2863 | "%s: timeout DIEPINT.NAKEFF\n", __func__); | |
2864 | } else { | |
2865 | /* Clear any pending nak effect interrupt */ | |
0676c7e7 | 2866 | dwc2_writel(GINTSTS_GOUTNAKEFF, hsotg->regs + GINTSTS); |
c524dd5f | 2867 | |
0676c7e7 | 2868 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
c524dd5f MYK |
2869 | |
2870 | /* Wait for global nak to take effect */ | |
2871 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
0676c7e7 | 2872 | GINTSTS_GOUTNAKEFF, 100)) |
c524dd5f | 2873 | dev_warn(hsotg->dev, |
0676c7e7 | 2874 | "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__); |
c524dd5f MYK |
2875 | } |
2876 | ||
2877 | /* Disable ep */ | |
2878 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); | |
2879 | ||
2880 | /* Wait for ep to be disabled */ | |
2881 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
2882 | dev_warn(hsotg->dev, | |
2883 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
2884 | ||
2885 | if (hs_ep->dir_in) { | |
2886 | if (hsotg->dedicated_fifos) { | |
2887 | dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) | | |
2888 | GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL); | |
2889 | /* Wait for fifo flush */ | |
2890 | if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, | |
2891 | GRSTCTL_TXFFLSH, 100)) | |
2892 | dev_warn(hsotg->dev, | |
2893 | "%s: timeout flushing fifos\n", | |
2894 | __func__); | |
2895 | } | |
2896 | /* TODO: Flush shared tx fifo */ | |
2897 | } else { | |
2898 | /* Remove global NAKs */ | |
0676c7e7 | 2899 | __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
c524dd5f MYK |
2900 | } |
2901 | } | |
2902 | ||
8b9bc460 | 2903 | /** |
1f91b4cc | 2904 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
2905 | * @ep: The endpoint to dequeue. |
2906 | * @req: The request to be removed from a queue. | |
2907 | */ | |
1f91b4cc | 2908 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 2909 | { |
1f91b4cc FB |
2910 | struct dwc2_hsotg_req *hs_req = our_req(req); |
2911 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2912 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
2913 | unsigned long flags; |
2914 | ||
1e011293 | 2915 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 2916 | |
22258f49 | 2917 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
2918 | |
2919 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 2920 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2921 | return -EINVAL; |
2922 | } | |
2923 | ||
c524dd5f MYK |
2924 | /* Dequeue already started request */ |
2925 | if (req == &hs_ep->req->req) | |
2926 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
2927 | ||
1f91b4cc | 2928 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 2929 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2930 | |
2931 | return 0; | |
2932 | } | |
2933 | ||
8b9bc460 | 2934 | /** |
1f91b4cc | 2935 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
2936 | * @ep: The endpoint to set halt. |
2937 | * @value: Set or unset the halt. | |
2938 | */ | |
1f91b4cc | 2939 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value) |
5b7d70c6 | 2940 | { |
1f91b4cc | 2941 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2942 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 2943 | int index = hs_ep->index; |
5b7d70c6 BD |
2944 | u32 epreg; |
2945 | u32 epctl; | |
9c39ddc6 | 2946 | u32 xfertype; |
5b7d70c6 BD |
2947 | |
2948 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2949 | ||
c9f721b2 RB |
2950 | if (index == 0) { |
2951 | if (value) | |
1f91b4cc | 2952 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
2953 | else |
2954 | dev_warn(hs->dev, | |
2955 | "%s: can't clear halt on ep0\n", __func__); | |
2956 | return 0; | |
2957 | } | |
2958 | ||
c6f5c050 MYK |
2959 | if (hs_ep->dir_in) { |
2960 | epreg = DIEPCTL(index); | |
95c8bc36 | 2961 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
2962 | |
2963 | if (value) { | |
5a350d53 | 2964 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
2965 | if (epctl & DXEPCTL_EPENA) |
2966 | epctl |= DXEPCTL_EPDIS; | |
2967 | } else { | |
2968 | epctl &= ~DXEPCTL_STALL; | |
2969 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2970 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2971 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2972 | epctl |= DXEPCTL_SETD0PID; | |
2973 | } | |
95c8bc36 | 2974 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 2975 | } else { |
5b7d70c6 | 2976 | |
c6f5c050 | 2977 | epreg = DOEPCTL(index); |
95c8bc36 | 2978 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 2979 | |
c6f5c050 MYK |
2980 | if (value) |
2981 | epctl |= DXEPCTL_STALL; | |
2982 | else { | |
2983 | epctl &= ~DXEPCTL_STALL; | |
2984 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2985 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2986 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2987 | epctl |= DXEPCTL_SETD0PID; | |
2988 | } | |
95c8bc36 | 2989 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 2990 | } |
5b7d70c6 | 2991 | |
a18ed7b0 RB |
2992 | hs_ep->halted = value; |
2993 | ||
5b7d70c6 BD |
2994 | return 0; |
2995 | } | |
2996 | ||
5ad1d316 | 2997 | /** |
1f91b4cc | 2998 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
2999 | * @ep: The endpoint to set halt. |
3000 | * @value: Set or unset the halt. | |
3001 | */ | |
1f91b4cc | 3002 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 3003 | { |
1f91b4cc | 3004 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3005 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
3006 | unsigned long flags = 0; |
3007 | int ret = 0; | |
3008 | ||
3009 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 3010 | ret = dwc2_hsotg_ep_sethalt(ep, value); |
5ad1d316 LM |
3011 | spin_unlock_irqrestore(&hs->lock, flags); |
3012 | ||
3013 | return ret; | |
3014 | } | |
3015 | ||
1f91b4cc FB |
3016 | static struct usb_ep_ops dwc2_hsotg_ep_ops = { |
3017 | .enable = dwc2_hsotg_ep_enable, | |
3018 | .disable = dwc2_hsotg_ep_disable, | |
3019 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
3020 | .free_request = dwc2_hsotg_ep_free_request, | |
3021 | .queue = dwc2_hsotg_ep_queue_lock, | |
3022 | .dequeue = dwc2_hsotg_ep_dequeue, | |
3023 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 3024 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
3025 | }; |
3026 | ||
8b9bc460 | 3027 | /** |
1f91b4cc | 3028 | * dwc2_hsotg_init - initalize the usb core |
8b9bc460 LM |
3029 | * @hsotg: The driver state |
3030 | */ | |
1f91b4cc | 3031 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 3032 | { |
fa4a8d72 | 3033 | u32 trdtim; |
b3f489b2 LM |
3034 | /* unmask subset of endpoint interrupts */ |
3035 | ||
95c8bc36 AS |
3036 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
3037 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
3038 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 3039 | |
95c8bc36 AS |
3040 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
3041 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
3042 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 3043 | |
95c8bc36 | 3044 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
3045 | |
3046 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 3047 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 3048 | |
b3f489b2 LM |
3049 | /* setup fifos */ |
3050 | ||
3051 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
3052 | dwc2_readl(hsotg->regs + GRXFSIZ), |
3053 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 3054 | |
1f91b4cc | 3055 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 LM |
3056 | |
3057 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
fa4a8d72 | 3058 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
95c8bc36 | 3059 | dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
f889f23d | 3060 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT), |
fa4a8d72 | 3061 | hsotg->regs + GUSBCFG); |
b3f489b2 | 3062 | |
f5090044 GH |
3063 | if (using_dma(hsotg)) |
3064 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
3065 | } |
3066 | ||
8b9bc460 | 3067 | /** |
1f91b4cc | 3068 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
3069 | * @gadget: The usb gadget state |
3070 | * @driver: The usb gadget driver | |
3071 | * | |
3072 | * Perform initialization to prepare udc device and driver | |
3073 | * to work. | |
3074 | */ | |
1f91b4cc | 3075 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
f65f0f10 | 3076 | struct usb_gadget_driver *driver) |
5b7d70c6 | 3077 | { |
941fcce4 | 3078 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 3079 | unsigned long flags; |
5b7d70c6 BD |
3080 | int ret; |
3081 | ||
3082 | if (!hsotg) { | |
a023da33 | 3083 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
3084 | return -ENODEV; |
3085 | } | |
3086 | ||
3087 | if (!driver) { | |
3088 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
3089 | return -EINVAL; | |
3090 | } | |
3091 | ||
7177aed4 | 3092 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 3093 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 3094 | |
f65f0f10 | 3095 | if (!driver->setup) { |
5b7d70c6 BD |
3096 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
3097 | return -EINVAL; | |
3098 | } | |
3099 | ||
3100 | WARN_ON(hsotg->driver); | |
3101 | ||
3102 | driver->driver.bus = NULL; | |
3103 | hsotg->driver = driver; | |
7d7b2292 | 3104 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
3105 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3106 | ||
09a75e85 MS |
3107 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
3108 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
3109 | if (ret) | |
3110 | goto err; | |
5b7d70c6 BD |
3111 | } |
3112 | ||
f6c01592 GH |
3113 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3114 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 3115 | |
5b9451f8 | 3116 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc FB |
3117 | dwc2_hsotg_init(hsotg); |
3118 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
dc6e69e6 | 3119 | hsotg->enabled = 0; |
5b9451f8 MS |
3120 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3121 | ||
5b7d70c6 | 3122 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 3123 | |
5b7d70c6 BD |
3124 | return 0; |
3125 | ||
3126 | err: | |
3127 | hsotg->driver = NULL; | |
5b7d70c6 BD |
3128 | return ret; |
3129 | } | |
3130 | ||
8b9bc460 | 3131 | /** |
1f91b4cc | 3132 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
3133 | * @gadget: The usb gadget state |
3134 | * @driver: The usb gadget driver | |
3135 | * | |
3136 | * Stop udc hw block and stay tunned for future transmissions | |
3137 | */ | |
1f91b4cc | 3138 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 3139 | { |
941fcce4 | 3140 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3141 | unsigned long flags = 0; |
5b7d70c6 BD |
3142 | int ep; |
3143 | ||
3144 | if (!hsotg) | |
3145 | return -ENODEV; | |
3146 | ||
5b7d70c6 | 3147 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3148 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
3149 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3150 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3151 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3152 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3153 | } |
5b7d70c6 | 3154 | |
2b19a52c LM |
3155 | spin_lock_irqsave(&hsotg->lock, flags); |
3156 | ||
32805c35 | 3157 | hsotg->driver = NULL; |
5b7d70c6 | 3158 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 3159 | hsotg->enabled = 0; |
5b7d70c6 | 3160 | |
2b19a52c LM |
3161 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3162 | ||
f6c01592 GH |
3163 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3164 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 3165 | |
09a75e85 MS |
3166 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3167 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
3168 | |
3169 | return 0; | |
3170 | } | |
5b7d70c6 | 3171 | |
8b9bc460 | 3172 | /** |
1f91b4cc | 3173 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
3174 | * @gadget: The usb gadget state |
3175 | * | |
3176 | * Read the {micro} frame number | |
3177 | */ | |
1f91b4cc | 3178 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 3179 | { |
1f91b4cc | 3180 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
3181 | } |
3182 | ||
a188b689 | 3183 | /** |
1f91b4cc | 3184 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
3185 | * @gadget: The usb gadget state |
3186 | * @is_on: Current state of the USB PHY | |
3187 | * | |
3188 | * Connect/Disconnect the USB PHY pullup | |
3189 | */ | |
1f91b4cc | 3190 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 3191 | { |
941fcce4 | 3192 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
3193 | unsigned long flags = 0; |
3194 | ||
77ba9119 GH |
3195 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
3196 | hsotg->op_state); | |
3197 | ||
3198 | /* Don't modify pullup state while in host mode */ | |
3199 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
3200 | hsotg->enabled = is_on; | |
3201 | return 0; | |
3202 | } | |
a188b689 LM |
3203 | |
3204 | spin_lock_irqsave(&hsotg->lock, flags); | |
3205 | if (is_on) { | |
dc6e69e6 | 3206 | hsotg->enabled = 1; |
1f91b4cc FB |
3207 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
3208 | dwc2_hsotg_core_connect(hsotg); | |
a188b689 | 3209 | } else { |
1f91b4cc FB |
3210 | dwc2_hsotg_core_disconnect(hsotg); |
3211 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 3212 | hsotg->enabled = 0; |
a188b689 LM |
3213 | } |
3214 | ||
3215 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3216 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3217 | ||
3218 | return 0; | |
3219 | } | |
3220 | ||
1f91b4cc | 3221 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
3222 | { |
3223 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3224 | unsigned long flags; | |
3225 | ||
3226 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3227 | spin_lock_irqsave(&hsotg->lock, flags); | |
3228 | ||
61f7223b GH |
3229 | /* |
3230 | * If controller is hibernated, it must exit from hibernation | |
3231 | * before being initialized / de-initialized | |
3232 | */ | |
3233 | if (hsotg->lx_state == DWC2_L2) | |
3234 | dwc2_exit_hibernation(hsotg, false); | |
3235 | ||
83d98223 | 3236 | if (is_active) { |
cd0e641c | 3237 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 3238 | |
1f91b4cc | 3239 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
83d98223 | 3240 | if (hsotg->enabled) |
1f91b4cc | 3241 | dwc2_hsotg_core_connect(hsotg); |
83d98223 | 3242 | } else { |
1f91b4cc FB |
3243 | dwc2_hsotg_core_disconnect(hsotg); |
3244 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
3245 | } |
3246 | ||
3247 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3248 | return 0; | |
3249 | } | |
3250 | ||
596d696a | 3251 | /** |
1f91b4cc | 3252 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
3253 | * @gadget: The usb gadget state |
3254 | * @mA: Amount of current | |
3255 | * | |
3256 | * Report how much power the device may consume to the phy. | |
3257 | */ | |
1f91b4cc | 3258 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) |
596d696a GH |
3259 | { |
3260 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3261 | ||
3262 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
3263 | return -ENOTSUPP; | |
3264 | return usb_phy_set_power(hsotg->uphy, mA); | |
3265 | } | |
3266 | ||
1f91b4cc FB |
3267 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
3268 | .get_frame = dwc2_hsotg_gadget_getframe, | |
3269 | .udc_start = dwc2_hsotg_udc_start, | |
3270 | .udc_stop = dwc2_hsotg_udc_stop, | |
3271 | .pullup = dwc2_hsotg_pullup, | |
3272 | .vbus_session = dwc2_hsotg_vbus_session, | |
3273 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
3274 | }; |
3275 | ||
3276 | /** | |
1f91b4cc | 3277 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
3278 | * @hsotg: The device state. |
3279 | * @hs_ep: The endpoint to be initialised. | |
3280 | * @epnum: The endpoint number | |
3281 | * | |
3282 | * Initialise the given endpoint (as part of the probe and device state | |
3283 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3284 | * direction information and other state that may be required. | |
3285 | */ | |
1f91b4cc FB |
3286 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
3287 | struct dwc2_hsotg_ep *hs_ep, | |
c6f5c050 MYK |
3288 | int epnum, |
3289 | bool dir_in) | |
5b7d70c6 | 3290 | { |
5b7d70c6 BD |
3291 | char *dir; |
3292 | ||
3293 | if (epnum == 0) | |
3294 | dir = ""; | |
c6f5c050 | 3295 | else if (dir_in) |
5b7d70c6 | 3296 | dir = "in"; |
c6f5c050 MYK |
3297 | else |
3298 | dir = "out"; | |
5b7d70c6 | 3299 | |
c6f5c050 | 3300 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3301 | hs_ep->index = epnum; |
3302 | ||
3303 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3304 | ||
3305 | INIT_LIST_HEAD(&hs_ep->queue); | |
3306 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3307 | ||
5b7d70c6 BD |
3308 | /* add to the list of endpoints known by the gadget driver */ |
3309 | if (epnum) | |
3310 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3311 | ||
3312 | hs_ep->parent = hsotg; | |
3313 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3314 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
1f91b4cc | 3315 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 3316 | |
2954522f RB |
3317 | if (epnum == 0) { |
3318 | hs_ep->ep.caps.type_control = true; | |
3319 | } else { | |
3320 | hs_ep->ep.caps.type_iso = true; | |
3321 | hs_ep->ep.caps.type_bulk = true; | |
3322 | hs_ep->ep.caps.type_int = true; | |
3323 | } | |
3324 | ||
3325 | if (dir_in) | |
3326 | hs_ep->ep.caps.dir_in = true; | |
3327 | else | |
3328 | hs_ep->ep.caps.dir_out = true; | |
3329 | ||
8b9bc460 LM |
3330 | /* |
3331 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3332 | * to be something valid. |
3333 | */ | |
3334 | ||
3335 | if (using_dma(hsotg)) { | |
47a1685f | 3336 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 | 3337 | if (dir_in) |
95c8bc36 | 3338 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 3339 | else |
95c8bc36 | 3340 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
3341 | } |
3342 | } | |
3343 | ||
b3f489b2 | 3344 | /** |
1f91b4cc | 3345 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
3346 | * @param: The device state |
3347 | * | |
3348 | * Read the USB core HW configuration registers | |
3349 | */ | |
1f91b4cc | 3350 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3351 | { |
c6f5c050 MYK |
3352 | u32 cfg; |
3353 | u32 ep_type; | |
3354 | u32 i; | |
3355 | ||
b3f489b2 | 3356 | /* check hardware configuration */ |
5b7d70c6 | 3357 | |
43e90349 JY |
3358 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
3359 | ||
c6f5c050 MYK |
3360 | /* Add ep0 */ |
3361 | hsotg->num_of_eps++; | |
10aebc77 | 3362 | |
1f91b4cc | 3363 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep), |
c6f5c050 MYK |
3364 | GFP_KERNEL); |
3365 | if (!hsotg->eps_in[0]) | |
3366 | return -ENOMEM; | |
1f91b4cc | 3367 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
3368 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
3369 | ||
43e90349 | 3370 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 3371 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
3372 | ep_type = cfg & 3; |
3373 | /* Direction in or both */ | |
3374 | if (!(ep_type & 2)) { | |
3375 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3376 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3377 | if (!hsotg->eps_in[i]) |
3378 | return -ENOMEM; | |
3379 | } | |
3380 | /* Direction out or both */ | |
3381 | if (!(ep_type & 1)) { | |
3382 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3383 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3384 | if (!hsotg->eps_out[i]) |
3385 | return -ENOMEM; | |
3386 | } | |
3387 | } | |
3388 | ||
43e90349 JY |
3389 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
3390 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 3391 | |
cff9eb75 MS |
3392 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3393 | hsotg->num_of_eps, | |
3394 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3395 | hsotg->fifo_mem); | |
c6f5c050 | 3396 | return 0; |
5b7d70c6 BD |
3397 | } |
3398 | ||
8b9bc460 | 3399 | /** |
1f91b4cc | 3400 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
3401 | * @param: The device state |
3402 | */ | |
1f91b4cc | 3403 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3404 | { |
83a01804 | 3405 | #ifdef DEBUG |
5b7d70c6 BD |
3406 | struct device *dev = hsotg->dev; |
3407 | void __iomem *regs = hsotg->regs; | |
3408 | u32 val; | |
3409 | int idx; | |
3410 | ||
3411 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
3412 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
3413 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 3414 | |
f889f23d | 3415 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 3416 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
3417 | |
3418 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 3419 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3420 | |
3421 | /* show periodic fifo settings */ | |
3422 | ||
364f8e93 | 3423 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 3424 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3425 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3426 | val >> FIFOSIZE_DEPTH_SHIFT, |
3427 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3428 | } |
3429 | ||
364f8e93 | 3430 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3431 | dev_info(dev, |
3432 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
3433 | dwc2_readl(regs + DIEPCTL(idx)), |
3434 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
3435 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3436 | |
95c8bc36 | 3437 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3438 | dev_info(dev, |
3439 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
3440 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
3441 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
3442 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3443 | |
3444 | } | |
3445 | ||
3446 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 3447 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 3448 | #endif |
5b7d70c6 BD |
3449 | } |
3450 | ||
edd74be8 | 3451 | #ifdef CONFIG_OF |
1f91b4cc | 3452 | static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) |
edd74be8 GH |
3453 | { |
3454 | struct device_node *np = hsotg->dev->of_node; | |
0a176279 GH |
3455 | u32 len = 0; |
3456 | u32 i = 0; | |
edd74be8 GH |
3457 | |
3458 | /* Enable dma if requested in device tree */ | |
3459 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 GH |
3460 | |
3461 | /* | |
3462 | * Register TX periodic fifo size per endpoint. | |
3463 | * EP0 is excluded since it has no fifo configuration. | |
3464 | */ | |
3465 | if (!of_find_property(np, "g-tx-fifo-size", &len)) | |
3466 | goto rx_fifo; | |
3467 | ||
3468 | len /= sizeof(u32); | |
3469 | ||
3470 | /* Read tx fifo sizes other than ep0 */ | |
3471 | if (of_property_read_u32_array(np, "g-tx-fifo-size", | |
3472 | &hsotg->g_tx_fifo_sz[1], len)) | |
3473 | goto rx_fifo; | |
3474 | ||
3475 | /* Add ep0 */ | |
3476 | len++; | |
3477 | ||
3478 | /* Make remaining TX fifos unavailable */ | |
3479 | if (len < MAX_EPS_CHANNELS) { | |
3480 | for (i = len; i < MAX_EPS_CHANNELS; i++) | |
3481 | hsotg->g_tx_fifo_sz[i] = 0; | |
3482 | } | |
3483 | ||
3484 | rx_fifo: | |
3485 | /* Register RX fifo size */ | |
3486 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3487 | ||
3488 | /* Register NPTX fifo size */ | |
3489 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3490 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3491 | } |
3492 | #else | |
1f91b4cc | 3493 | static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } |
edd74be8 GH |
3494 | #endif |
3495 | ||
8b9bc460 | 3496 | /** |
117777b2 DN |
3497 | * dwc2_gadget_init - init function for gadget |
3498 | * @dwc2: The data structure for the DWC2 driver. | |
3499 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3500 | */ |
117777b2 | 3501 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3502 | { |
117777b2 | 3503 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
3504 | int epnum; |
3505 | int ret; | |
fc9a731e | 3506 | int i; |
0a176279 | 3507 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; |
5b7d70c6 | 3508 | |
0a176279 GH |
3509 | /* Initialize to legacy fifo configuration values */ |
3510 | hsotg->g_rx_fifo_sz = 2048; | |
3511 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
3512 | memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo)); | |
3513 | /* Device tree specific probe */ | |
1f91b4cc | 3514 | dwc2_hsotg_of_probe(hsotg); |
43e90349 JY |
3515 | |
3516 | /* Check against largest possible value. */ | |
3517 | if (hsotg->g_np_g_tx_fifo_sz > | |
3518 | hsotg->hw_params.dev_nperio_tx_fifo_size) { | |
3519 | dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n", | |
3520 | hsotg->g_np_g_tx_fifo_sz, | |
3521 | hsotg->hw_params.dev_nperio_tx_fifo_size); | |
3522 | hsotg->g_np_g_tx_fifo_sz = | |
3523 | hsotg->hw_params.dev_nperio_tx_fifo_size; | |
3524 | } | |
3525 | ||
0a176279 GH |
3526 | /* Dump fifo information */ |
3527 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3528 | hsotg->g_np_g_tx_fifo_sz); | |
3529 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
3530 | for (i = 0; i < MAX_EPS_CHANNELS; i++) | |
3531 | dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i, | |
3532 | hsotg->g_tx_fifo_sz[i]); | |
5b7d70c6 | 3533 | |
d327ab5b | 3534 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 3535 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 3536 | hsotg->gadget.name = dev_name(dev); |
097ee662 GH |
3537 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
3538 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
3539 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3540 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 3541 | |
1f91b4cc | 3542 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
3543 | if (ret) { |
3544 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 3545 | return ret; |
c6f5c050 MYK |
3546 | } |
3547 | ||
3f95001d MYK |
3548 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3549 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3550 | if (!hsotg->ctrl_buff) { | |
3551 | dev_err(dev, "failed to allocate ctrl request buff\n"); | |
09a75e85 | 3552 | return -ENOMEM; |
3f95001d MYK |
3553 | } |
3554 | ||
3555 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3556 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3557 | if (!hsotg->ep0_buff) { | |
3558 | dev_err(dev, "failed to allocate ctrl reply buff\n"); | |
09a75e85 | 3559 | return -ENOMEM; |
3f95001d MYK |
3560 | } |
3561 | ||
1f91b4cc | 3562 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
db8178c3 | 3563 | dev_name(hsotg->dev), hsotg); |
eb3c56c5 | 3564 | if (ret < 0) { |
db8178c3 | 3565 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 3566 | return ret; |
eb3c56c5 MS |
3567 | } |
3568 | ||
b3f489b2 LM |
3569 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3570 | ||
3571 | if (hsotg->num_of_eps == 0) { | |
3572 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 3573 | return -EINVAL; |
b3f489b2 LM |
3574 | } |
3575 | ||
b3f489b2 LM |
3576 | /* setup endpoint information */ |
3577 | ||
3578 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3579 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3580 | |
3581 | /* allocate EP0 request */ | |
3582 | ||
1f91b4cc | 3583 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3584 | GFP_KERNEL); |
3585 | if (!hsotg->ctrl_req) { | |
3586 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 3587 | return -ENOMEM; |
b3f489b2 | 3588 | } |
5b7d70c6 BD |
3589 | |
3590 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3591 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3592 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 3593 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
c6f5c050 MYK |
3594 | epnum, 1); |
3595 | if (hsotg->eps_out[epnum]) | |
1f91b4cc | 3596 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
c6f5c050 MYK |
3597 | epnum, 0); |
3598 | } | |
5b7d70c6 | 3599 | |
117777b2 | 3600 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3601 | if (ret) |
09a75e85 | 3602 | return ret; |
0f91349b | 3603 | |
1f91b4cc | 3604 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 3605 | |
5b7d70c6 | 3606 | return 0; |
5b7d70c6 BD |
3607 | } |
3608 | ||
8b9bc460 | 3609 | /** |
1f91b4cc | 3610 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
3611 | * @pdev: The platform information for the driver |
3612 | */ | |
1f91b4cc | 3613 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3614 | { |
0f91349b | 3615 | usb_del_gadget_udc(&hsotg->gadget); |
31ee04de | 3616 | |
5b7d70c6 BD |
3617 | return 0; |
3618 | } | |
3619 | ||
1f91b4cc | 3620 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3621 | { |
b83e333a | 3622 | unsigned long flags; |
b83e333a | 3623 | |
9e779778 | 3624 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 3625 | return 0; |
9e779778 | 3626 | |
dc6e69e6 MS |
3627 | if (hsotg->driver) { |
3628 | int ep; | |
3629 | ||
b83e333a MS |
3630 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3631 | hsotg->driver->driver.name); | |
3632 | ||
dc6e69e6 MS |
3633 | spin_lock_irqsave(&hsotg->lock, flags); |
3634 | if (hsotg->enabled) | |
1f91b4cc FB |
3635 | dwc2_hsotg_core_disconnect(hsotg); |
3636 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
3637 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3638 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 3639 | |
c6f5c050 MYK |
3640 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3641 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3642 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3643 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3644 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3645 | } |
b83e333a MS |
3646 | } |
3647 | ||
09a75e85 | 3648 | return 0; |
b83e333a MS |
3649 | } |
3650 | ||
1f91b4cc | 3651 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 3652 | { |
b83e333a | 3653 | unsigned long flags; |
b83e333a | 3654 | |
9e779778 | 3655 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 3656 | return 0; |
9e779778 | 3657 | |
b83e333a MS |
3658 | if (hsotg->driver) { |
3659 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3660 | hsotg->driver->driver.name); | |
d00b4142 | 3661 | |
dc6e69e6 | 3662 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 3663 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
dc6e69e6 | 3664 | if (hsotg->enabled) |
1f91b4cc | 3665 | dwc2_hsotg_core_connect(hsotg); |
dc6e69e6 MS |
3666 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3667 | } | |
b83e333a | 3668 | |
09a75e85 | 3669 | return 0; |
b83e333a | 3670 | } |