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72246da4 FB |
1 | /** |
2 | * core.h - DesignWare USB3 DRD Core Header | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
20 | #define __DRIVERS_USB_DWC3_CORE_H | |
21 | ||
22 | #include <linux/device.h> | |
23 | #include <linux/spinlock.h> | |
d07e8819 | 24 | #include <linux/ioport.h> |
72246da4 FB |
25 | #include <linux/list.h> |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/mm.h> | |
28 | #include <linux/debugfs.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
a45c82b8 | 32 | #include <linux/usb/otg.h> |
88bc9d19 | 33 | #include <linux/ulpi/interface.h> |
72246da4 | 34 | |
57303488 KVA |
35 | #include <linux/phy/phy.h> |
36 | ||
2c4cbe6e FB |
37 | #define DWC3_MSG_MAX 500 |
38 | ||
72246da4 | 39 | /* Global constants */ |
04c03d10 | 40 | #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */ |
3ef35faf | 41 | #define DWC3_EP0_BOUNCE_SIZE 512 |
72246da4 | 42 | #define DWC3_ENDPOINTS_NUM 32 |
51249dca | 43 | #define DWC3_XHCI_RESOURCES_NUM 2 |
72246da4 | 44 | |
0ffcaf37 | 45 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
5da93478 FB |
46 | #define DWC3_EVENT_SIZE 4 /* bytes */ |
47 | #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ | |
48 | #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) | |
72246da4 FB |
49 | #define DWC3_EVENT_TYPE_MASK 0xfe |
50 | ||
51 | #define DWC3_EVENT_TYPE_DEV 0 | |
52 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
53 | #define DWC3_EVENT_TYPE_I2C 4 | |
54 | ||
55 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
56 | #define DWC3_DEVICE_EVENT_RESET 1 | |
57 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
58 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
59 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
2c61a8ef | 60 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
72246da4 FB |
61 | #define DWC3_DEVICE_EVENT_EOPF 6 |
62 | #define DWC3_DEVICE_EVENT_SOF 7 | |
63 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
64 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
65 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
66 | ||
67 | #define DWC3_GEVNTCOUNT_MASK 0xfffc | |
68 | #define DWC3_GSNPSID_MASK 0xffff0000 | |
69 | #define DWC3_GSNPSREV_MASK 0xffff | |
70 | ||
51249dca IS |
71 | /* DWC3 registers memory space boundries */ |
72 | #define DWC3_XHCI_REGS_START 0x0 | |
73 | #define DWC3_XHCI_REGS_END 0x7fff | |
74 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
75 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
76 | #define DWC3_DEVICE_REGS_START 0xc700 | |
77 | #define DWC3_DEVICE_REGS_END 0xcbff | |
78 | #define DWC3_OTG_REGS_START 0xcc00 | |
79 | #define DWC3_OTG_REGS_END 0xccff | |
80 | ||
72246da4 FB |
81 | /* Global Registers */ |
82 | #define DWC3_GSBUSCFG0 0xc100 | |
83 | #define DWC3_GSBUSCFG1 0xc104 | |
84 | #define DWC3_GTXTHRCFG 0xc108 | |
85 | #define DWC3_GRXTHRCFG 0xc10c | |
86 | #define DWC3_GCTL 0xc110 | |
87 | #define DWC3_GEVTEN 0xc114 | |
88 | #define DWC3_GSTS 0xc118 | |
89 | #define DWC3_GSNPSID 0xc120 | |
90 | #define DWC3_GGPIO 0xc124 | |
91 | #define DWC3_GUID 0xc128 | |
92 | #define DWC3_GUCTL 0xc12c | |
93 | #define DWC3_GBUSERRADDR0 0xc130 | |
94 | #define DWC3_GBUSERRADDR1 0xc134 | |
95 | #define DWC3_GPRTBIMAP0 0xc138 | |
96 | #define DWC3_GPRTBIMAP1 0xc13c | |
97 | #define DWC3_GHWPARAMS0 0xc140 | |
98 | #define DWC3_GHWPARAMS1 0xc144 | |
99 | #define DWC3_GHWPARAMS2 0xc148 | |
100 | #define DWC3_GHWPARAMS3 0xc14c | |
101 | #define DWC3_GHWPARAMS4 0xc150 | |
102 | #define DWC3_GHWPARAMS5 0xc154 | |
103 | #define DWC3_GHWPARAMS6 0xc158 | |
104 | #define DWC3_GHWPARAMS7 0xc15c | |
105 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
106 | #define DWC3_GDBGLTSSM 0xc164 | |
107 | #define DWC3_GPRTBIMAP_HS0 0xc180 | |
108 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
109 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
110 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
111 | ||
690fb371 JY |
112 | #define DWC3_VER_NUMBER 0xc1a0 |
113 | #define DWC3_VER_TYPE 0xc1a4 | |
114 | ||
72246da4 FB |
115 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) |
116 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) | |
117 | ||
118 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) | |
119 | ||
120 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) | |
121 | ||
122 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) | |
123 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) | |
124 | ||
125 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) | |
126 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) | |
127 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) | |
128 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) | |
129 | ||
130 | #define DWC3_GHWPARAMS8 0xc600 | |
db2be4e9 | 131 | #define DWC3_GFLADJ 0xc630 |
72246da4 FB |
132 | |
133 | /* Device Registers */ | |
134 | #define DWC3_DCFG 0xc700 | |
135 | #define DWC3_DCTL 0xc704 | |
136 | #define DWC3_DEVTEN 0xc708 | |
137 | #define DWC3_DSTS 0xc70c | |
138 | #define DWC3_DGCMDPAR 0xc710 | |
139 | #define DWC3_DGCMD 0xc714 | |
140 | #define DWC3_DALEPENA 0xc720 | |
141 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) | |
142 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) | |
143 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) | |
144 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) | |
145 | ||
146 | /* OTG Registers */ | |
147 | #define DWC3_OCFG 0xcc00 | |
148 | #define DWC3_OCTL 0xcc04 | |
d4436c3a GC |
149 | #define DWC3_OEVT 0xcc08 |
150 | #define DWC3_OEVTEN 0xcc0C | |
151 | #define DWC3_OSTS 0xcc10 | |
72246da4 FB |
152 | |
153 | /* Bit fields */ | |
154 | ||
155 | /* Global Configuration Register */ | |
1d046793 | 156 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
f4aadbe4 | 157 | #define DWC3_GCTL_U2RSTECN (1 << 16) |
1d046793 | 158 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
72246da4 FB |
159 | #define DWC3_GCTL_CLK_BUS (0) |
160 | #define DWC3_GCTL_CLK_PIPE (1) | |
161 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
162 | #define DWC3_GCTL_CLK_MASK (3) | |
163 | ||
0b9fe32d | 164 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
1d046793 | 165 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
72246da4 FB |
166 | #define DWC3_GCTL_PRTCAP_HOST 1 |
167 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
168 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
169 | ||
2c61a8ef | 170 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) |
183ca111 | 171 | #define DWC3_GCTL_SOFITPSYNC (1 << 10) |
2c61a8ef PZ |
172 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
173 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | |
174 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) | |
9a5b2f31 | 175 | #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) |
2c61a8ef PZ |
176 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) |
177 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) | |
72246da4 FB |
178 | |
179 | /* Global USB2 PHY Configuration Register */ | |
2c61a8ef PZ |
180 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) |
181 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) | |
f699b947 | 182 | #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) |
ec791d14 | 183 | #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) |
72246da4 | 184 | |
b5699eee HK |
185 | /* Global USB2 PHY Vendor Control Register */ |
186 | #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) | |
187 | #define DWC3_GUSB2PHYACC_BUSY (1 << 23) | |
188 | #define DWC3_GUSB2PHYACC_WRITE (1 << 22) | |
189 | #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) | |
190 | #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) | |
191 | #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) | |
192 | ||
72246da4 | 193 | /* Global USB3 PIPE Control Register */ |
2c61a8ef | 194 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) |
b5a65c40 | 195 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) |
df31f5b3 | 196 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) |
a2a1d0f5 HR |
197 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
198 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) | |
199 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) | |
41c06ffd | 200 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) |
2c61a8ef | 201 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) |
fb67afca | 202 | #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) |
14f4ac53 | 203 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) |
6b6a0c9a HR |
204 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
205 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) | |
72246da4 | 206 | |
457e84b6 | 207 | /* Global TX Fifo Size Register */ |
2c61a8ef PZ |
208 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) |
209 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) | |
457e84b6 | 210 | |
68d6a01b FB |
211 | /* Global Event Size Registers */ |
212 | #define DWC3_GEVNTSIZ_INTMASK (1 << 31) | |
213 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) | |
214 | ||
aabb7075 | 215 | /* Global HWPARAMS1 Register */ |
1d046793 | 216 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
aabb7075 FB |
217 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
218 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
2c61a8ef PZ |
219 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
220 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) | |
221 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) | |
222 | ||
0e1e5c47 PZ |
223 | /* Global HWPARAMS3 Register */ |
224 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) | |
225 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 | |
226 | #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 | |
227 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) | |
228 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 | |
229 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 | |
230 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 | |
231 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 | |
232 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) | |
233 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 | |
234 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 | |
235 | ||
2c61a8ef PZ |
236 | /* Global HWPARAMS4 Register */ |
237 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | |
238 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | |
aabb7075 | 239 | |
946bd579 HR |
240 | /* Global HWPARAMS6 Register */ |
241 | #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) | |
242 | ||
db2be4e9 NB |
243 | /* Global Frame Length Adjustment Register */ |
244 | #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) | |
245 | #define DWC3_GFLADJ_30MHZ_MASK 0x3f | |
246 | ||
72246da4 FB |
247 | /* Device Configuration Register */ |
248 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
249 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
250 | ||
251 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
252 | #define DWC3_DCFG_SUPERSPEED (4 << 0) | |
253 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
254 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) | |
255 | #define DWC3_DCFG_LOWSPEED (2 << 0) | |
256 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) | |
257 | ||
2c61a8ef PZ |
258 | #define DWC3_DCFG_LPM_CAP (1 << 22) |
259 | ||
72246da4 FB |
260 | /* Device Control Register */ |
261 | #define DWC3_DCTL_RUN_STOP (1 << 31) | |
262 | #define DWC3_DCTL_CSFTRST (1 << 30) | |
263 | #define DWC3_DCTL_LSFTRST (1 << 29) | |
264 | ||
265 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
7e39b817 | 266 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
72246da4 FB |
267 | |
268 | #define DWC3_DCTL_APPL1RES (1 << 23) | |
269 | ||
2c61a8ef PZ |
270 | /* These apply for core versions 1.87a and earlier */ |
271 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) | |
272 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
273 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
274 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
275 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
276 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
277 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
278 | ||
279 | /* These apply for core versions 1.94a and later */ | |
80caf7d2 HR |
280 | #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) |
281 | #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) | |
8db7ed15 | 282 | |
80caf7d2 HR |
283 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) |
284 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) | |
285 | #define DWC3_DCTL_CRS (1 << 17) | |
286 | #define DWC3_DCTL_CSS (1 << 16) | |
287 | ||
288 | #define DWC3_DCTL_INITU2ENA (1 << 12) | |
289 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | |
290 | #define DWC3_DCTL_INITU1ENA (1 << 10) | |
291 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | |
292 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | |
72246da4 FB |
293 | |
294 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
295 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
296 | ||
297 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
298 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
299 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
300 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
301 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
302 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
303 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
304 | ||
305 | /* Device Event Enable Register */ | |
306 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) | |
307 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) | |
308 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) | |
309 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) | |
310 | #define DWC3_DEVTEN_SOFEN (1 << 7) | |
311 | #define DWC3_DEVTEN_EOPFEN (1 << 6) | |
2c61a8ef | 312 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) |
72246da4 FB |
313 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) |
314 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) | |
315 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) | |
316 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) | |
317 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) | |
318 | ||
319 | /* Device Status Register */ | |
2c61a8ef PZ |
320 | #define DWC3_DSTS_DCNRD (1 << 29) |
321 | ||
322 | /* This applies for core versions 1.87a and earlier */ | |
72246da4 | 323 | #define DWC3_DSTS_PWRUPREQ (1 << 24) |
2c61a8ef PZ |
324 | |
325 | /* These apply for core versions 1.94a and later */ | |
326 | #define DWC3_DSTS_RSS (1 << 25) | |
327 | #define DWC3_DSTS_SSS (1 << 24) | |
328 | ||
72246da4 FB |
329 | #define DWC3_DSTS_COREIDLE (1 << 23) |
330 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) | |
331 | ||
332 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
333 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
334 | ||
335 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) | |
336 | ||
d05b8182 | 337 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
72246da4 FB |
338 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
339 | ||
340 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
341 | ||
342 | #define DWC3_DSTS_SUPERSPEED (4 << 0) | |
343 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
344 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) | |
345 | #define DWC3_DSTS_LOWSPEED (2 << 0) | |
346 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) | |
347 | ||
348 | /* Device Generic Command Register */ | |
349 | #define DWC3_DGCMD_SET_LMP 0x01 | |
350 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
351 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
2c61a8ef PZ |
352 | |
353 | /* These apply for core versions 1.94a and later */ | |
354 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 | |
355 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 | |
356 | ||
72246da4 FB |
357 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
358 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
359 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
360 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
361 | ||
459e210c | 362 | #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) |
b09bb642 | 363 | #define DWC3_DGCMD_CMDACT (1 << 10) |
2c61a8ef PZ |
364 | #define DWC3_DGCMD_CMDIOC (1 << 8) |
365 | ||
366 | /* Device Generic Command Parameter Register */ | |
367 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) | |
368 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) | |
369 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) | |
370 | #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) | |
371 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) | |
372 | #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) | |
b09bb642 | 373 | |
72246da4 FB |
374 | /* Device Endpoint Command Register */ |
375 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
1d046793 | 376 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
835fadb4 | 377 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
459e210c | 378 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) |
72246da4 FB |
379 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) |
380 | #define DWC3_DEPCMD_CMDACT (1 << 10) | |
381 | #define DWC3_DEPCMD_CMDIOC (1 << 8) | |
382 | ||
383 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
384 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
385 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
386 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
387 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
388 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
2c61a8ef | 389 | /* This applies for core versions 1.90a and earlier */ |
72246da4 | 390 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
2c61a8ef PZ |
391 | /* This applies for core versions 1.94a and later */ |
392 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) | |
72246da4 FB |
393 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
394 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
395 | ||
396 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ | |
397 | #define DWC3_DALEPENA_EP(n) (1 << n) | |
398 | ||
399 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
400 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
401 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
402 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
403 | ||
404 | /* Structures */ | |
405 | ||
f6bafc6a | 406 | struct dwc3_trb; |
72246da4 FB |
407 | |
408 | /** | |
409 | * struct dwc3_event_buffer - Software event buffer representation | |
72246da4 FB |
410 | * @buf: _THE_ buffer |
411 | * @length: size of this buffer | |
abed4118 | 412 | * @lpos: event offset |
60d04bbe | 413 | * @count: cache of last read event count register |
abed4118 | 414 | * @flags: flags related to this event buffer |
72246da4 FB |
415 | * @dma: dma_addr_t |
416 | * @dwc: pointer to DWC controller | |
417 | */ | |
418 | struct dwc3_event_buffer { | |
419 | void *buf; | |
420 | unsigned length; | |
421 | unsigned int lpos; | |
60d04bbe | 422 | unsigned int count; |
abed4118 FB |
423 | unsigned int flags; |
424 | ||
425 | #define DWC3_EVENT_PENDING BIT(0) | |
72246da4 FB |
426 | |
427 | dma_addr_t dma; | |
428 | ||
429 | struct dwc3 *dwc; | |
430 | }; | |
431 | ||
432 | #define DWC3_EP_FLAG_STALLED (1 << 0) | |
433 | #define DWC3_EP_FLAG_WEDGED (1 << 1) | |
434 | ||
435 | #define DWC3_EP_DIRECTION_TX true | |
436 | #define DWC3_EP_DIRECTION_RX false | |
437 | ||
438 | #define DWC3_TRB_NUM 32 | |
439 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) | |
440 | ||
441 | /** | |
442 | * struct dwc3_ep - device side endpoint representation | |
443 | * @endpoint: usb endpoint | |
444 | * @request_list: list of requests for this endpoint | |
445 | * @req_queued: list of requests on this ep which have TRBs setup | |
446 | * @trb_pool: array of transaction buffers | |
447 | * @trb_pool_dma: dma address of @trb_pool | |
448 | * @free_slot: next slot which is going to be used | |
449 | * @busy_slot: first slot which is owned by HW | |
450 | * @desc: usb_endpoint_descriptor pointer | |
451 | * @dwc: pointer to DWC controller | |
4cfcf876 | 452 | * @saved_state: ep state saved during hibernation |
72246da4 | 453 | * @flags: endpoint flags (wedged, stalled, ...) |
72246da4 FB |
454 | * @number: endpoint number (1 - 15) |
455 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
b4996a86 | 456 | * @resource_index: Resource transfer index |
c75f52fb | 457 | * @interval: the interval on which the ISOC transfer is started |
72246da4 FB |
458 | * @name: a human readable name e.g. ep1out-bulk |
459 | * @direction: true for TX, false for RX | |
879631aa | 460 | * @stream_capable: true when streams are enabled |
72246da4 FB |
461 | */ |
462 | struct dwc3_ep { | |
463 | struct usb_ep endpoint; | |
464 | struct list_head request_list; | |
465 | struct list_head req_queued; | |
466 | ||
f6bafc6a | 467 | struct dwc3_trb *trb_pool; |
72246da4 FB |
468 | dma_addr_t trb_pool_dma; |
469 | u32 free_slot; | |
470 | u32 busy_slot; | |
c90bfaec | 471 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
72246da4 FB |
472 | struct dwc3 *dwc; |
473 | ||
4cfcf876 | 474 | u32 saved_state; |
72246da4 FB |
475 | unsigned flags; |
476 | #define DWC3_EP_ENABLED (1 << 0) | |
477 | #define DWC3_EP_STALL (1 << 1) | |
478 | #define DWC3_EP_WEDGE (1 << 2) | |
479 | #define DWC3_EP_BUSY (1 << 4) | |
480 | #define DWC3_EP_PENDING_REQUEST (1 << 5) | |
d6d6ec7b | 481 | #define DWC3_EP_MISSED_ISOC (1 << 6) |
72246da4 | 482 | |
984f66a6 FB |
483 | /* This last one is specific to EP0 */ |
484 | #define DWC3_EP0_DIR_IN (1 << 31) | |
485 | ||
72246da4 FB |
486 | u8 number; |
487 | u8 type; | |
b4996a86 | 488 | u8 resource_index; |
72246da4 FB |
489 | u32 interval; |
490 | ||
491 | char name[20]; | |
492 | ||
493 | unsigned direction:1; | |
879631aa | 494 | unsigned stream_capable:1; |
72246da4 FB |
495 | }; |
496 | ||
497 | enum dwc3_phy { | |
498 | DWC3_PHY_UNKNOWN = 0, | |
499 | DWC3_PHY_USB3, | |
500 | DWC3_PHY_USB2, | |
501 | }; | |
502 | ||
b53c772d FB |
503 | enum dwc3_ep0_next { |
504 | DWC3_EP0_UNKNOWN = 0, | |
505 | DWC3_EP0_COMPLETE, | |
b53c772d FB |
506 | DWC3_EP0_NRDY_DATA, |
507 | DWC3_EP0_NRDY_STATUS, | |
508 | }; | |
509 | ||
72246da4 FB |
510 | enum dwc3_ep0_state { |
511 | EP0_UNCONNECTED = 0, | |
c7fcdeb2 FB |
512 | EP0_SETUP_PHASE, |
513 | EP0_DATA_PHASE, | |
514 | EP0_STATUS_PHASE, | |
72246da4 FB |
515 | }; |
516 | ||
517 | enum dwc3_link_state { | |
518 | /* In SuperSpeed */ | |
519 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
520 | DWC3_LINK_STATE_U1 = 0x01, | |
521 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
522 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
523 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
524 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
525 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
526 | DWC3_LINK_STATE_POLL = 0x07, | |
527 | DWC3_LINK_STATE_RECOV = 0x08, | |
528 | DWC3_LINK_STATE_HRESET = 0x09, | |
529 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
530 | DWC3_LINK_STATE_LPBK = 0x0b, | |
2c61a8ef PZ |
531 | DWC3_LINK_STATE_RESET = 0x0e, |
532 | DWC3_LINK_STATE_RESUME = 0x0f, | |
72246da4 FB |
533 | DWC3_LINK_STATE_MASK = 0x0f, |
534 | }; | |
535 | ||
f6bafc6a FB |
536 | /* TRB Length, PCM and Status */ |
537 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
538 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
539 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
389f2828 | 540 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
f6bafc6a FB |
541 | |
542 | #define DWC3_TRBSTS_OK 0 | |
543 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
544 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
2c61a8ef | 545 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
f6bafc6a FB |
546 | |
547 | /* TRB Control */ | |
548 | #define DWC3_TRB_CTRL_HWO (1 << 0) | |
549 | #define DWC3_TRB_CTRL_LST (1 << 1) | |
550 | #define DWC3_TRB_CTRL_CHN (1 << 2) | |
551 | #define DWC3_TRB_CTRL_CSP (1 << 3) | |
552 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) | |
553 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) | |
554 | #define DWC3_TRB_CTRL_IOC (1 << 11) | |
555 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) | |
556 | ||
557 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) | |
558 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
559 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
560 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
561 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
562 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
563 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
564 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
72246da4 FB |
565 | |
566 | /** | |
f6bafc6a | 567 | * struct dwc3_trb - transfer request block (hw format) |
72246da4 FB |
568 | * @bpl: DW0-3 |
569 | * @bph: DW4-7 | |
570 | * @size: DW8-B | |
571 | * @trl: DWC-F | |
572 | */ | |
f6bafc6a FB |
573 | struct dwc3_trb { |
574 | u32 bpl; | |
575 | u32 bph; | |
576 | u32 size; | |
577 | u32 ctrl; | |
72246da4 FB |
578 | } __packed; |
579 | ||
a3299499 FB |
580 | /** |
581 | * dwc3_hwparams - copy of HWPARAMS registers | |
582 | * @hwparams0 - GHWPARAMS0 | |
583 | * @hwparams1 - GHWPARAMS1 | |
584 | * @hwparams2 - GHWPARAMS2 | |
585 | * @hwparams3 - GHWPARAMS3 | |
586 | * @hwparams4 - GHWPARAMS4 | |
587 | * @hwparams5 - GHWPARAMS5 | |
588 | * @hwparams6 - GHWPARAMS6 | |
589 | * @hwparams7 - GHWPARAMS7 | |
590 | * @hwparams8 - GHWPARAMS8 | |
591 | */ | |
592 | struct dwc3_hwparams { | |
593 | u32 hwparams0; | |
594 | u32 hwparams1; | |
595 | u32 hwparams2; | |
596 | u32 hwparams3; | |
597 | u32 hwparams4; | |
598 | u32 hwparams5; | |
599 | u32 hwparams6; | |
600 | u32 hwparams7; | |
601 | u32 hwparams8; | |
602 | }; | |
603 | ||
0949e99b FB |
604 | /* HWPARAMS0 */ |
605 | #define DWC3_MODE(n) ((n) & 0x7) | |
606 | ||
457e84b6 FB |
607 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
608 | ||
0949e99b | 609 | /* HWPARAMS1 */ |
457e84b6 FB |
610 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
611 | ||
789451f6 FB |
612 | /* HWPARAMS3 */ |
613 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) | |
614 | #define DWC3_NUM_EPS_MASK (0x3f << 12) | |
615 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ | |
616 | (DWC3_NUM_EPS_MASK)) >> 12) | |
617 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ | |
618 | (DWC3_NUM_IN_EPS_MASK)) >> 18) | |
619 | ||
457e84b6 FB |
620 | /* HWPARAMS7 */ |
621 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
9f622b2a | 622 | |
e0ce0b0a SAS |
623 | struct dwc3_request { |
624 | struct usb_request request; | |
625 | struct list_head list; | |
626 | struct dwc3_ep *dep; | |
e5ba5ec8 | 627 | u32 start_slot; |
e0ce0b0a SAS |
628 | |
629 | u8 epnum; | |
f6bafc6a | 630 | struct dwc3_trb *trb; |
e0ce0b0a SAS |
631 | dma_addr_t trb_dma; |
632 | ||
633 | unsigned direction:1; | |
634 | unsigned mapped:1; | |
635 | unsigned queued:1; | |
636 | }; | |
637 | ||
2c61a8ef PZ |
638 | /* |
639 | * struct dwc3_scratchpad_array - hibernation scratchpad array | |
640 | * (format defined by hw) | |
641 | */ | |
642 | struct dwc3_scratchpad_array { | |
643 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; | |
644 | }; | |
645 | ||
72246da4 FB |
646 | /** |
647 | * struct dwc3 - representation of our controller | |
91db07dc FB |
648 | * @ctrl_req: usb control request which is used for ep0 |
649 | * @ep0_trb: trb which is used for the ctrl_req | |
5812b1c2 | 650 | * @ep0_bounce: bounce buffer for ep0 |
04c03d10 | 651 | * @zlp_buf: used when request->zero is set |
91db07dc FB |
652 | * @setup_buf: used while precessing STD USB requests |
653 | * @ctrl_req_addr: dma address of ctrl_req | |
654 | * @ep0_trb: dma address of ep0_trb | |
655 | * @ep0_usb_req: dummy req used while handling STD USB requests | |
5812b1c2 | 656 | * @ep0_bounce_addr: dma address of ep0_bounce |
0ffcaf37 | 657 | * @scratch_addr: dma address of scratchbuf |
72246da4 FB |
658 | * @lock: for synchronizing |
659 | * @dev: pointer to our struct device | |
d07e8819 | 660 | * @xhci: pointer to our xHCI child |
72246da4 FB |
661 | * @event_buffer_list: a list of event buffers |
662 | * @gadget: device side representation of the peripheral controller | |
663 | * @gadget_driver: pointer to the gadget driver | |
664 | * @regs: base address for our registers | |
665 | * @regs_size: address space size | |
0ffcaf37 | 666 | * @nr_scratch: number of scratch buffers |
9f622b2a | 667 | * @num_event_buffers: calculated number of event buffers |
fae2b904 | 668 | * @u1u2: only used on revisions <1.83a for workaround |
6c167fc9 | 669 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
72246da4 | 670 | * @revision: revision register contents |
a45c82b8 | 671 | * @dr_mode: requested mode of operation |
51e1e7bc FB |
672 | * @usb2_phy: pointer to USB2 PHY |
673 | * @usb3_phy: pointer to USB3 PHY | |
57303488 KVA |
674 | * @usb2_generic_phy: pointer to USB2 PHY |
675 | * @usb3_generic_phy: pointer to USB3 PHY | |
88bc9d19 | 676 | * @ulpi: pointer to ulpi interface |
7415f17c FB |
677 | * @dcfg: saved contents of DCFG register |
678 | * @gctl: saved contents of GCTL register | |
c12a0d86 | 679 | * @isoch_delay: wValue from Set Isochronous Delay request; |
865e09e7 FB |
680 | * @u2sel: parameter from Set SEL request. |
681 | * @u2pel: parameter from Set SEL request. | |
682 | * @u1sel: parameter from Set SEL request. | |
683 | * @u1pel: parameter from Set SEL request. | |
789451f6 FB |
684 | * @num_out_eps: number of out endpoints |
685 | * @num_in_eps: number of in endpoints | |
b53c772d | 686 | * @ep0_next_event: hold the next expected event |
72246da4 FB |
687 | * @ep0state: state of endpoint zero |
688 | * @link_state: link state | |
689 | * @speed: device speed (super, high, full, low) | |
690 | * @mem: points to start of memory which is used for this struct. | |
a3299499 | 691 | * @hwparams: copy of hwparams registers |
72246da4 | 692 | * @root: debugfs root folder pointer |
f2b685d5 FB |
693 | * @regset: debugfs pointer to regdump file |
694 | * @test_mode: true when we're entering a USB test mode | |
695 | * @test_mode_nr: test feature selector | |
80caf7d2 | 696 | * @lpm_nyet_threshold: LPM NYET response threshold |
460d098c | 697 | * @hird_threshold: HIRD threshold |
3e10a2ce | 698 | * @hsphy_interface: "utmi" or "ulpi" |
f2b685d5 FB |
699 | * @delayed_status: true when gadget driver asks for delayed status |
700 | * @ep0_bounced: true when we used bounce buffer | |
701 | * @ep0_expect_in: true when we expect a DATA IN transfer | |
81bc5599 | 702 | * @has_hibernation: true when dwc3 was configured with Hibernation |
80caf7d2 HR |
703 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
704 | * there's now way for software to detect this in runtime. | |
460d098c HR |
705 | * @is_utmi_l1_suspend: the core asserts output signal |
706 | * 0 - utmi_sleep_n | |
707 | * 1 - utmi_l1_suspend_n | |
946bd579 | 708 | * @is_fpga: true when we are using the FPGA board |
f2b685d5 FB |
709 | * @needs_fifo_resize: not all users might want fifo resizing, flag it |
710 | * @pullups_connected: true when Run/Stop bit is set | |
711 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. | |
712 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround | |
713 | * @start_config_issued: true when StartConfig command has been issued | |
714 | * @three_stage_setup: set if we perform a three phase setup | |
eac68e8f | 715 | * @usb3_lpm_capable: set if hadrware supports Link Power Management |
3b81221a | 716 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
9a5b2f31 | 717 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
b5a65c40 | 718 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
df31f5b3 | 719 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
a2a1d0f5 | 720 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
41c06ffd | 721 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
fb67afca | 722 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
14f4ac53 | 723 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
59acfa20 | 724 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
0effe0a3 | 725 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
ec791d14 JY |
726 | * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, |
727 | * disabling the suspend signal to the PHY. | |
6b6a0c9a HR |
728 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
729 | * @tx_de_emphasis: Tx de-emphasis value | |
730 | * 0 - -6dB de-emphasis | |
731 | * 1 - -3.5dB de-emphasis | |
732 | * 2 - No de-emphasis | |
733 | * 3 - Reserved | |
72246da4 FB |
734 | */ |
735 | struct dwc3 { | |
736 | struct usb_ctrlrequest *ctrl_req; | |
f6bafc6a | 737 | struct dwc3_trb *ep0_trb; |
5812b1c2 | 738 | void *ep0_bounce; |
04c03d10 | 739 | void *zlp_buf; |
0ffcaf37 | 740 | void *scratchbuf; |
72246da4 FB |
741 | u8 *setup_buf; |
742 | dma_addr_t ctrl_req_addr; | |
743 | dma_addr_t ep0_trb_addr; | |
5812b1c2 | 744 | dma_addr_t ep0_bounce_addr; |
0ffcaf37 | 745 | dma_addr_t scratch_addr; |
e0ce0b0a | 746 | struct dwc3_request ep0_usb_req; |
789451f6 | 747 | |
72246da4 FB |
748 | /* device lock */ |
749 | spinlock_t lock; | |
789451f6 | 750 | |
72246da4 FB |
751 | struct device *dev; |
752 | ||
d07e8819 | 753 | struct platform_device *xhci; |
51249dca | 754 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
d07e8819 | 755 | |
457d3f21 | 756 | struct dwc3_event_buffer **ev_buffs; |
72246da4 FB |
757 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
758 | ||
759 | struct usb_gadget gadget; | |
760 | struct usb_gadget_driver *gadget_driver; | |
761 | ||
51e1e7bc FB |
762 | struct usb_phy *usb2_phy; |
763 | struct usb_phy *usb3_phy; | |
764 | ||
57303488 KVA |
765 | struct phy *usb2_generic_phy; |
766 | struct phy *usb3_generic_phy; | |
767 | ||
88bc9d19 HK |
768 | struct ulpi *ulpi; |
769 | ||
72246da4 FB |
770 | void __iomem *regs; |
771 | size_t regs_size; | |
772 | ||
a45c82b8 RK |
773 | enum usb_dr_mode dr_mode; |
774 | ||
7415f17c FB |
775 | /* used for suspend/resume */ |
776 | u32 dcfg; | |
777 | u32 gctl; | |
778 | ||
0ffcaf37 | 779 | u32 nr_scratch; |
9f622b2a | 780 | u32 num_event_buffers; |
fae2b904 | 781 | u32 u1u2; |
6c167fc9 | 782 | u32 maximum_speed; |
690fb371 JY |
783 | |
784 | /* | |
785 | * All 3.1 IP version constants are greater than the 3.0 IP | |
786 | * version constants. This works for most version checks in | |
787 | * dwc3. However, in the future, this may not apply as | |
788 | * features may be developed on newer versions of the 3.0 IP | |
789 | * that are not in the 3.1 IP. | |
790 | */ | |
72246da4 FB |
791 | u32 revision; |
792 | ||
793 | #define DWC3_REVISION_173A 0x5533173a | |
794 | #define DWC3_REVISION_175A 0x5533175a | |
795 | #define DWC3_REVISION_180A 0x5533180a | |
796 | #define DWC3_REVISION_183A 0x5533183a | |
797 | #define DWC3_REVISION_185A 0x5533185a | |
2c61a8ef | 798 | #define DWC3_REVISION_187A 0x5533187a |
72246da4 FB |
799 | #define DWC3_REVISION_188A 0x5533188a |
800 | #define DWC3_REVISION_190A 0x5533190a | |
2c61a8ef | 801 | #define DWC3_REVISION_194A 0x5533194a |
1522d703 FB |
802 | #define DWC3_REVISION_200A 0x5533200a |
803 | #define DWC3_REVISION_202A 0x5533202a | |
804 | #define DWC3_REVISION_210A 0x5533210a | |
805 | #define DWC3_REVISION_220A 0x5533220a | |
7ac6a593 FB |
806 | #define DWC3_REVISION_230A 0x5533230a |
807 | #define DWC3_REVISION_240A 0x5533240a | |
808 | #define DWC3_REVISION_250A 0x5533250a | |
dbf5aaf7 FB |
809 | #define DWC3_REVISION_260A 0x5533260a |
810 | #define DWC3_REVISION_270A 0x5533270a | |
811 | #define DWC3_REVISION_280A 0x5533280a | |
72246da4 | 812 | |
690fb371 JY |
813 | /* |
814 | * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really | |
815 | * just so dwc31 revisions are always larger than dwc3. | |
816 | */ | |
817 | #define DWC3_REVISION_IS_DWC31 0x80000000 | |
818 | #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31) | |
819 | ||
b53c772d | 820 | enum dwc3_ep0_next ep0_next_event; |
72246da4 FB |
821 | enum dwc3_ep0_state ep0state; |
822 | enum dwc3_link_state link_state; | |
72246da4 | 823 | |
c12a0d86 | 824 | u16 isoch_delay; |
865e09e7 FB |
825 | u16 u2sel; |
826 | u16 u2pel; | |
827 | u8 u1sel; | |
828 | u8 u1pel; | |
829 | ||
72246da4 | 830 | u8 speed; |
865e09e7 | 831 | |
789451f6 FB |
832 | u8 num_out_eps; |
833 | u8 num_in_eps; | |
834 | ||
72246da4 FB |
835 | void *mem; |
836 | ||
a3299499 | 837 | struct dwc3_hwparams hwparams; |
72246da4 | 838 | struct dentry *root; |
d7668024 | 839 | struct debugfs_regset32 *regset; |
3b637367 GC |
840 | |
841 | u8 test_mode; | |
842 | u8 test_mode_nr; | |
80caf7d2 | 843 | u8 lpm_nyet_threshold; |
460d098c | 844 | u8 hird_threshold; |
f2b685d5 | 845 | |
3e10a2ce HK |
846 | const char *hsphy_interface; |
847 | ||
f2b685d5 FB |
848 | unsigned delayed_status:1; |
849 | unsigned ep0_bounced:1; | |
850 | unsigned ep0_expect_in:1; | |
81bc5599 | 851 | unsigned has_hibernation:1; |
80caf7d2 | 852 | unsigned has_lpm_erratum:1; |
460d098c | 853 | unsigned is_utmi_l1_suspend:1; |
946bd579 | 854 | unsigned is_fpga:1; |
f2b685d5 FB |
855 | unsigned needs_fifo_resize:1; |
856 | unsigned pullups_connected:1; | |
857 | unsigned resize_fifos:1; | |
858 | unsigned setup_packet_pending:1; | |
f2b685d5 | 859 | unsigned three_stage_setup:1; |
eac68e8f | 860 | unsigned usb3_lpm_capable:1; |
3b81221a HR |
861 | |
862 | unsigned disable_scramble_quirk:1; | |
9a5b2f31 | 863 | unsigned u2exit_lfps_quirk:1; |
b5a65c40 | 864 | unsigned u2ss_inp3_quirk:1; |
df31f5b3 | 865 | unsigned req_p1p2p3_quirk:1; |
a2a1d0f5 | 866 | unsigned del_p1p2p3_quirk:1; |
41c06ffd | 867 | unsigned del_phy_power_chg_quirk:1; |
fb67afca | 868 | unsigned lfps_filter_quirk:1; |
14f4ac53 | 869 | unsigned rx_detect_poll_quirk:1; |
59acfa20 | 870 | unsigned dis_u3_susphy_quirk:1; |
0effe0a3 | 871 | unsigned dis_u2_susphy_quirk:1; |
ec791d14 | 872 | unsigned dis_enblslpm_quirk:1; |
6b6a0c9a HR |
873 | |
874 | unsigned tx_de_emphasis_quirk:1; | |
875 | unsigned tx_de_emphasis:2; | |
72246da4 FB |
876 | }; |
877 | ||
878 | /* -------------------------------------------------------------------------- */ | |
879 | ||
72246da4 FB |
880 | /* -------------------------------------------------------------------------- */ |
881 | ||
882 | struct dwc3_event_type { | |
883 | u32 is_devspec:1; | |
1974d494 HR |
884 | u32 type:7; |
885 | u32 reserved8_31:24; | |
72246da4 FB |
886 | } __packed; |
887 | ||
888 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
889 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
890 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
891 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
892 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
893 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
894 | ||
895 | /** | |
896 | * struct dwc3_event_depvt - Device Endpoint Events | |
897 | * @one_bit: indicates this is an endpoint event (not used) | |
898 | * @endpoint_number: number of the endpoint | |
899 | * @endpoint_event: The event we have: | |
900 | * 0x00 - Reserved | |
901 | * 0x01 - XferComplete | |
902 | * 0x02 - XferInProgress | |
903 | * 0x03 - XferNotReady | |
904 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
905 | * 0x05 - Reserved | |
906 | * 0x06 - StreamEvt | |
907 | * 0x07 - EPCmdCmplt | |
908 | * @reserved11_10: Reserved, don't use. | |
909 | * @status: Indicates the status of the event. Refer to databook for | |
910 | * more information. | |
911 | * @parameters: Parameters of the current event. Refer to databook for | |
912 | * more information. | |
913 | */ | |
914 | struct dwc3_event_depevt { | |
915 | u32 one_bit:1; | |
916 | u32 endpoint_number:5; | |
917 | u32 endpoint_event:4; | |
918 | u32 reserved11_10:2; | |
919 | u32 status:4; | |
40aa41fb FB |
920 | |
921 | /* Within XferNotReady */ | |
922 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) | |
923 | ||
924 | /* Within XferComplete */ | |
1d046793 PZ |
925 | #define DEPEVT_STATUS_BUSERR (1 << 0) |
926 | #define DEPEVT_STATUS_SHORT (1 << 1) | |
927 | #define DEPEVT_STATUS_IOC (1 << 2) | |
72246da4 | 928 | #define DEPEVT_STATUS_LST (1 << 3) |
dc137f01 | 929 | |
879631aa FB |
930 | /* Stream event only */ |
931 | #define DEPEVT_STREAMEVT_FOUND 1 | |
932 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
933 | ||
dc137f01 | 934 | /* Control-only Status */ |
dc137f01 FB |
935 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
936 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
937 | ||
72246da4 FB |
938 | u32 parameters:16; |
939 | } __packed; | |
940 | ||
941 | /** | |
942 | * struct dwc3_event_devt - Device Events | |
943 | * @one_bit: indicates this is a non-endpoint event (not used) | |
944 | * @device_event: indicates it's a device event. Should read as 0x00 | |
945 | * @type: indicates the type of device event. | |
946 | * 0 - DisconnEvt | |
947 | * 1 - USBRst | |
948 | * 2 - ConnectDone | |
949 | * 3 - ULStChng | |
950 | * 4 - WkUpEvt | |
951 | * 5 - Reserved | |
952 | * 6 - EOPF | |
953 | * 7 - SOF | |
954 | * 8 - Reserved | |
955 | * 9 - ErrticErr | |
956 | * 10 - CmdCmplt | |
957 | * 11 - EvntOverflow | |
958 | * 12 - VndrDevTstRcved | |
959 | * @reserved15_12: Reserved, not used | |
960 | * @event_info: Information about this event | |
06f9b6e5 | 961 | * @reserved31_25: Reserved, not used |
72246da4 FB |
962 | */ |
963 | struct dwc3_event_devt { | |
964 | u32 one_bit:1; | |
965 | u32 device_event:7; | |
966 | u32 type:4; | |
967 | u32 reserved15_12:4; | |
06f9b6e5 HR |
968 | u32 event_info:9; |
969 | u32 reserved31_25:7; | |
72246da4 FB |
970 | } __packed; |
971 | ||
972 | /** | |
973 | * struct dwc3_event_gevt - Other Core Events | |
974 | * @one_bit: indicates this is a non-endpoint event (not used) | |
975 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
976 | * @phy_port_number: self-explanatory | |
977 | * @reserved31_12: Reserved, not used. | |
978 | */ | |
979 | struct dwc3_event_gevt { | |
980 | u32 one_bit:1; | |
981 | u32 device_event:7; | |
982 | u32 phy_port_number:4; | |
983 | u32 reserved31_12:20; | |
984 | } __packed; | |
985 | ||
986 | /** | |
987 | * union dwc3_event - representation of Event Buffer contents | |
988 | * @raw: raw 32-bit event | |
989 | * @type: the type of the event | |
990 | * @depevt: Device Endpoint Event | |
991 | * @devt: Device Event | |
992 | * @gevt: Global Event | |
993 | */ | |
994 | union dwc3_event { | |
995 | u32 raw; | |
996 | struct dwc3_event_type type; | |
997 | struct dwc3_event_depevt depevt; | |
998 | struct dwc3_event_devt devt; | |
999 | struct dwc3_event_gevt gevt; | |
1000 | }; | |
1001 | ||
61018305 FB |
1002 | /** |
1003 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command | |
1004 | * parameters | |
1005 | * @param2: third parameter | |
1006 | * @param1: second parameter | |
1007 | * @param0: first parameter | |
1008 | */ | |
1009 | struct dwc3_gadget_ep_cmd_params { | |
1010 | u32 param2; | |
1011 | u32 param1; | |
1012 | u32 param0; | |
1013 | }; | |
1014 | ||
72246da4 FB |
1015 | /* |
1016 | * DWC3 Features to be used as Driver Data | |
1017 | */ | |
1018 | ||
1019 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
1020 | #define DWC3_HAS_XHCI BIT(1) | |
1021 | #define DWC3_HAS_OTG BIT(3) | |
1022 | ||
d07e8819 | 1023 | /* prototypes */ |
3140e8cb | 1024 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
457e84b6 | 1025 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); |
3140e8cb | 1026 | |
388e5c51 | 1027 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
d07e8819 FB |
1028 | int dwc3_host_init(struct dwc3 *dwc); |
1029 | void dwc3_host_exit(struct dwc3 *dwc); | |
388e5c51 VG |
1030 | #else |
1031 | static inline int dwc3_host_init(struct dwc3 *dwc) | |
1032 | { return 0; } | |
1033 | static inline void dwc3_host_exit(struct dwc3 *dwc) | |
1034 | { } | |
1035 | #endif | |
1036 | ||
1037 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) | |
f80b45e7 FB |
1038 | int dwc3_gadget_init(struct dwc3 *dwc); |
1039 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
61018305 FB |
1040 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
1041 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); | |
1042 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); | |
1043 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, | |
1044 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); | |
3ece0ec4 | 1045 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); |
388e5c51 VG |
1046 | #else |
1047 | static inline int dwc3_gadget_init(struct dwc3 *dwc) | |
1048 | { return 0; } | |
1049 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) | |
1050 | { } | |
61018305 FB |
1051 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
1052 | { return 0; } | |
1053 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
1054 | { return 0; } | |
1055 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, | |
1056 | enum dwc3_link_state state) | |
1057 | { return 0; } | |
1058 | ||
1059 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, | |
1060 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
1061 | { return 0; } | |
1062 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, | |
1063 | int cmd, u32 param) | |
1064 | { return 0; } | |
388e5c51 | 1065 | #endif |
f80b45e7 | 1066 | |
7415f17c FB |
1067 | /* power management interface */ |
1068 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) | |
7415f17c FB |
1069 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
1070 | int dwc3_gadget_resume(struct dwc3 *dwc); | |
1071 | #else | |
7415f17c FB |
1072 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
1073 | { | |
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) | |
1078 | { | |
1079 | return 0; | |
1080 | } | |
1081 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ | |
1082 | ||
88bc9d19 HK |
1083 | #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) |
1084 | int dwc3_ulpi_init(struct dwc3 *dwc); | |
1085 | void dwc3_ulpi_exit(struct dwc3 *dwc); | |
1086 | #else | |
1087 | static inline int dwc3_ulpi_init(struct dwc3 *dwc) | |
1088 | { return 0; } | |
1089 | static inline void dwc3_ulpi_exit(struct dwc3 *dwc) | |
1090 | { } | |
1091 | #endif | |
1092 | ||
72246da4 | 1093 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |