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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
5 | * All rights reserved. | |
6 | * | |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions, and the following disclaimer, | |
15 | * without modification. | |
16 | * 2. Redistributions in binary form must reproduce the above copyright | |
17 | * notice, this list of conditions and the following disclaimer in the | |
18 | * documentation and/or other materials provided with the distribution. | |
19 | * 3. The names of the above-listed copyright holders may not be used | |
20 | * to endorse or promote products derived from this software without | |
21 | * specific prior written permission. | |
22 | * | |
23 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
24 | * GNU General Public License ("GPL") version 2, as published by the Free | |
25 | * Software Foundation. | |
26 | * | |
27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
28 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
29 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
30 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
31 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
32 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
33 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
34 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
35 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
36 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
37 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
38 | */ | |
39 | ||
40 | #include <linux/kernel.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/platform_device.h> | |
44 | #include <linux/pm_runtime.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/io.h> | |
47 | #include <linux/list.h> | |
48 | #include <linux/dma-mapping.h> | |
49 | ||
50 | #include <linux/usb/ch9.h> | |
51 | #include <linux/usb/gadget.h> | |
52 | ||
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
57 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
58 | const struct dwc3_event_depevt *event); | |
59 | ||
60 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) | |
61 | { | |
62 | switch (state) { | |
63 | case EP0_UNCONNECTED: | |
64 | return "Unconnected"; | |
65 | case EP0_IDLE: | |
66 | return "Idle"; | |
67 | case EP0_IN_DATA_PHASE: | |
68 | return "IN Data Phase"; | |
69 | case EP0_OUT_DATA_PHASE: | |
70 | return "OUT Data Phase"; | |
71 | case EP0_IN_WAIT_GADGET: | |
72 | return "IN Wait Gadget"; | |
73 | case EP0_OUT_WAIT_GADGET: | |
74 | return "OUT Wait Gadget"; | |
75 | case EP0_IN_WAIT_NRDY: | |
76 | return "IN Wait NRDY"; | |
77 | case EP0_OUT_WAIT_NRDY: | |
78 | return "OUT Wait NRDY"; | |
79 | case EP0_IN_STATUS_PHASE: | |
80 | return "IN Status Phase"; | |
81 | case EP0_OUT_STATUS_PHASE: | |
82 | return "OUT Status Phase"; | |
83 | case EP0_STALL: | |
84 | return "Stall"; | |
85 | default: | |
86 | return "UNKNOWN"; | |
87 | } | |
88 | } | |
89 | ||
90 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
91 | u32 len) | |
92 | { | |
93 | struct dwc3_gadget_ep_cmd_params params; | |
94 | struct dwc3_trb_hw *trb_hw; | |
95 | struct dwc3_trb trb; | |
96 | struct dwc3_ep *dep; | |
97 | ||
98 | int ret; | |
99 | ||
100 | dep = dwc->eps[epnum]; | |
101 | ||
102 | trb_hw = dwc->ep0_trb; | |
103 | memset(&trb, 0, sizeof(trb)); | |
104 | ||
105 | switch (dwc->ep0state) { | |
106 | case EP0_IDLE: | |
107 | trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP; | |
108 | break; | |
109 | ||
110 | case EP0_IN_WAIT_NRDY: | |
111 | case EP0_OUT_WAIT_NRDY: | |
112 | case EP0_IN_STATUS_PHASE: | |
113 | case EP0_OUT_STATUS_PHASE: | |
114 | if (dwc->three_stage_setup) | |
115 | trb.trbctl = DWC3_TRBCTL_CONTROL_STATUS3; | |
116 | else | |
117 | trb.trbctl = DWC3_TRBCTL_CONTROL_STATUS2; | |
118 | ||
119 | if (dwc->ep0state == EP0_IN_WAIT_NRDY) | |
120 | dwc->ep0state = EP0_IN_STATUS_PHASE; | |
121 | else if (dwc->ep0state == EP0_OUT_WAIT_NRDY) | |
122 | dwc->ep0state = EP0_OUT_STATUS_PHASE; | |
123 | break; | |
124 | ||
125 | case EP0_IN_WAIT_GADGET: | |
126 | dwc->ep0state = EP0_IN_WAIT_NRDY; | |
127 | return 0; | |
128 | break; | |
129 | ||
130 | case EP0_OUT_WAIT_GADGET: | |
131 | dwc->ep0state = EP0_OUT_WAIT_NRDY; | |
132 | return 0; | |
133 | ||
134 | break; | |
135 | ||
136 | case EP0_IN_DATA_PHASE: | |
137 | case EP0_OUT_DATA_PHASE: | |
138 | trb.trbctl = DWC3_TRBCTL_CONTROL_DATA; | |
139 | break; | |
140 | ||
141 | default: | |
142 | dev_err(dwc->dev, "%s() can't in state %d\n", __func__, | |
143 | dwc->ep0state); | |
144 | return -EINVAL; | |
145 | } | |
146 | ||
147 | trb.bplh = buf_dma; | |
148 | trb.length = len; | |
149 | ||
150 | trb.hwo = 1; | |
151 | trb.lst = 1; | |
152 | trb.ioc = 1; | |
153 | trb.isp_imi = 1; | |
154 | ||
155 | dwc3_trb_to_hw(&trb, trb_hw); | |
156 | ||
157 | memset(¶ms, 0, sizeof(params)); | |
158 | params.param0.depstrtxfer.transfer_desc_addr_high = | |
159 | upper_32_bits(dwc->ep0_trb_addr); | |
160 | params.param1.depstrtxfer.transfer_desc_addr_low = | |
161 | lower_32_bits(dwc->ep0_trb_addr); | |
162 | ||
163 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
164 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
165 | if (ret < 0) { | |
166 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
167 | return ret; | |
168 | } | |
169 | ||
170 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, | |
171 | dep->number); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
177 | struct dwc3_request *req) | |
178 | { | |
179 | struct dwc3 *dwc = dep->dwc; | |
180 | int ret; | |
181 | ||
182 | req->request.actual = 0; | |
183 | req->request.status = -EINPROGRESS; | |
184 | req->direction = dep->direction; | |
185 | req->epnum = dep->number; | |
186 | ||
187 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 FB |
188 | if (req->request.length == 0) { |
189 | ret = dwc3_ep0_start_trans(dwc, dep->number, | |
190 | dwc->ctrl_req_addr, 0); | |
191 | } else if ((req->request.length % dep->endpoint.maxpacket) | |
192 | && (dep->number == 0)) { | |
193 | dwc->ep0_bounced = true; | |
194 | ||
195 | WARN_ON(req->request.length > dep->endpoint.maxpacket); | |
196 | ||
197 | /* | |
198 | * REVISIT in case request length is bigger than EP0 | |
199 | * wMaxPacketSize, we will need two chained TRBs to handle | |
200 | * the transfer. | |
201 | */ | |
202 | ret = dwc3_ep0_start_trans(dwc, dep->number, | |
203 | dwc->ep0_bounce_addr, dep->endpoint.maxpacket); | |
204 | } else { | |
205 | dwc3_map_buffer_to_dma(req); | |
206 | ||
207 | ret = dwc3_ep0_start_trans(dwc, dep->number, | |
208 | req->request.dma, req->request.length); | |
209 | } | |
72246da4 | 210 | |
72246da4 FB |
211 | if (ret < 0) { |
212 | list_del(&req->list); | |
213 | dwc3_unmap_buffer_from_dma(req); | |
214 | } | |
215 | ||
216 | return ret; | |
217 | } | |
218 | ||
219 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
220 | gfp_t gfp_flags) | |
221 | { | |
222 | struct dwc3_request *req = to_dwc3_request(request); | |
223 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
224 | struct dwc3 *dwc = dep->dwc; | |
225 | ||
226 | unsigned long flags; | |
227 | ||
228 | int ret; | |
229 | ||
230 | switch (dwc->ep0state) { | |
231 | case EP0_IN_DATA_PHASE: | |
232 | case EP0_IN_WAIT_GADGET: | |
233 | case EP0_IN_WAIT_NRDY: | |
234 | case EP0_IN_STATUS_PHASE: | |
235 | dep = dwc->eps[1]; | |
236 | break; | |
237 | ||
238 | case EP0_OUT_DATA_PHASE: | |
239 | case EP0_OUT_WAIT_GADGET: | |
240 | case EP0_OUT_WAIT_NRDY: | |
241 | case EP0_OUT_STATUS_PHASE: | |
242 | dep = dwc->eps[0]; | |
243 | break; | |
244 | default: | |
245 | return -EINVAL; | |
246 | } | |
247 | ||
248 | spin_lock_irqsave(&dwc->lock, flags); | |
249 | if (!dep->desc) { | |
250 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", | |
251 | request, dep->name); | |
252 | ret = -ESHUTDOWN; | |
253 | goto out; | |
254 | } | |
255 | ||
256 | /* we share one TRB for ep0/1 */ | |
257 | if (!list_empty(&dwc->eps[0]->request_list) || | |
258 | !list_empty(&dwc->eps[1]->request_list) || | |
259 | dwc->ep0_status_pending) { | |
260 | ret = -EBUSY; | |
261 | goto out; | |
262 | } | |
263 | ||
264 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
265 | request, dep->name, request->length, | |
266 | dwc3_ep0_state_string(dwc->ep0state)); | |
267 | ||
268 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
269 | ||
270 | out: | |
271 | spin_unlock_irqrestore(&dwc->lock, flags); | |
272 | ||
273 | return ret; | |
274 | } | |
275 | ||
276 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
277 | { | |
278 | /* stall is always issued on EP0 */ | |
279 | __dwc3_gadget_ep_set_halt(dwc->eps[0], 1); | |
280 | dwc->eps[0]->flags &= ~DWC3_EP_STALL; | |
281 | dwc->ep0state = EP0_IDLE; | |
282 | dwc3_ep0_out_start(dwc); | |
283 | } | |
284 | ||
285 | void dwc3_ep0_out_start(struct dwc3 *dwc) | |
286 | { | |
287 | struct dwc3_ep *dep; | |
288 | int ret; | |
289 | ||
290 | dep = dwc->eps[0]; | |
291 | ||
292 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8); | |
293 | WARN_ON(ret < 0); | |
294 | } | |
295 | ||
296 | /* | |
297 | * Send a zero length packet for the status phase of the control transfer | |
298 | */ | |
299 | static void dwc3_ep0_do_setup_status(struct dwc3 *dwc, | |
300 | const struct dwc3_event_depevt *event) | |
301 | { | |
302 | struct dwc3_ep *dep; | |
303 | int ret; | |
304 | u32 epnum; | |
305 | ||
306 | epnum = event->endpoint_number; | |
307 | dep = dwc->eps[epnum]; | |
308 | ||
309 | if (epnum) | |
310 | dwc->ep0state = EP0_IN_STATUS_PHASE; | |
311 | else | |
312 | dwc->ep0state = EP0_OUT_STATUS_PHASE; | |
313 | ||
314 | /* | |
315 | * Not sure Why I need a buffer for a zero transfer. Maybe the | |
316 | * HW reacts strange on a NULL pointer | |
317 | */ | |
318 | ret = dwc3_ep0_start_trans(dwc, epnum, dwc->ctrl_req_addr, 0); | |
319 | if (ret) { | |
320 | dev_dbg(dwc->dev, "failed to start transfer, stalling\n"); | |
321 | dwc3_ep0_stall_and_restart(dwc); | |
322 | } | |
323 | } | |
324 | ||
325 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) | |
326 | { | |
327 | struct dwc3_ep *dep; | |
328 | u32 windex = le16_to_cpu(wIndex_le); | |
329 | u32 epnum; | |
330 | ||
331 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
332 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
333 | epnum |= 1; | |
334 | ||
335 | dep = dwc->eps[epnum]; | |
336 | if (dep->flags & DWC3_EP_ENABLED) | |
337 | return dep; | |
338 | ||
339 | return NULL; | |
340 | } | |
341 | ||
342 | static void dwc3_ep0_send_status_response(struct dwc3 *dwc) | |
343 | { | |
344 | u32 epnum; | |
345 | ||
346 | if (dwc->ep0state == EP0_IN_DATA_PHASE) | |
347 | epnum = 1; | |
348 | else | |
349 | epnum = 0; | |
350 | ||
351 | dwc3_ep0_start_trans(dwc, epnum, dwc->ctrl_req_addr, | |
352 | dwc->ep0_usb_req.length); | |
353 | dwc->ep0_status_pending = 1; | |
354 | } | |
355 | ||
356 | /* | |
357 | * ch 9.4.5 | |
358 | */ | |
359 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
360 | { | |
361 | struct dwc3_ep *dep; | |
362 | u32 recip; | |
363 | u16 usb_status = 0; | |
364 | __le16 *response_pkt; | |
365 | ||
366 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
367 | switch (recip) { | |
368 | case USB_RECIP_DEVICE: | |
369 | /* | |
370 | * We are self-powered. U1/U2/LTM will be set later | |
371 | * once we handle this states. RemoteWakeup is 0 on SS | |
372 | */ | |
373 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
374 | break; | |
375 | ||
376 | case USB_RECIP_INTERFACE: | |
377 | /* | |
378 | * Function Remote Wake Capable D0 | |
379 | * Function Remote Wakeup D1 | |
380 | */ | |
381 | break; | |
382 | ||
383 | case USB_RECIP_ENDPOINT: | |
384 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
385 | if (!dep) | |
386 | return -EINVAL; | |
387 | ||
388 | if (dep->flags & DWC3_EP_STALL) | |
389 | usb_status = 1 << USB_ENDPOINT_HALT; | |
390 | break; | |
391 | default: | |
392 | return -EINVAL; | |
393 | }; | |
394 | ||
395 | response_pkt = (__le16 *) dwc->setup_buf; | |
396 | *response_pkt = cpu_to_le16(usb_status); | |
397 | dwc->ep0_usb_req.length = sizeof(*response_pkt); | |
398 | dwc3_ep0_send_status_response(dwc); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
404 | struct usb_ctrlrequest *ctrl, int set) | |
405 | { | |
406 | struct dwc3_ep *dep; | |
407 | u32 recip; | |
408 | u32 wValue; | |
409 | u32 wIndex; | |
410 | u32 reg; | |
411 | int ret; | |
412 | u32 mode; | |
413 | ||
414 | wValue = le16_to_cpu(ctrl->wValue); | |
415 | wIndex = le16_to_cpu(ctrl->wIndex); | |
416 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
417 | switch (recip) { | |
418 | case USB_RECIP_DEVICE: | |
419 | ||
420 | /* | |
421 | * 9.4.1 says only only for SS, in AddressState only for | |
422 | * default control pipe | |
423 | */ | |
424 | switch (wValue) { | |
425 | case USB_DEVICE_U1_ENABLE: | |
426 | case USB_DEVICE_U2_ENABLE: | |
427 | case USB_DEVICE_LTM_ENABLE: | |
428 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) | |
429 | return -EINVAL; | |
430 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
431 | return -EINVAL; | |
432 | } | |
433 | ||
434 | /* XXX add U[12] & LTM */ | |
435 | switch (wValue) { | |
436 | case USB_DEVICE_REMOTE_WAKEUP: | |
437 | break; | |
438 | case USB_DEVICE_U1_ENABLE: | |
439 | break; | |
440 | case USB_DEVICE_U2_ENABLE: | |
441 | break; | |
442 | case USB_DEVICE_LTM_ENABLE: | |
443 | break; | |
444 | ||
445 | case USB_DEVICE_TEST_MODE: | |
446 | if ((wIndex & 0xff) != 0) | |
447 | return -EINVAL; | |
448 | if (!set) | |
449 | return -EINVAL; | |
450 | ||
451 | mode = wIndex >> 8; | |
452 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
453 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
454 | ||
455 | switch (mode) { | |
456 | case TEST_J: | |
457 | case TEST_K: | |
458 | case TEST_SE0_NAK: | |
459 | case TEST_PACKET: | |
460 | case TEST_FORCE_EN: | |
461 | reg |= mode << 1; | |
462 | break; | |
463 | default: | |
464 | return -EINVAL; | |
465 | } | |
466 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
467 | break; | |
468 | default: | |
469 | return -EINVAL; | |
470 | } | |
471 | break; | |
472 | ||
473 | case USB_RECIP_INTERFACE: | |
474 | switch (wValue) { | |
475 | case USB_INTRF_FUNC_SUSPEND: | |
476 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
477 | /* XXX enable Low power suspend */ | |
478 | ; | |
479 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
480 | /* XXX enable remote wakeup */ | |
481 | ; | |
482 | break; | |
483 | default: | |
484 | return -EINVAL; | |
485 | } | |
486 | break; | |
487 | ||
488 | case USB_RECIP_ENDPOINT: | |
489 | switch (wValue) { | |
490 | case USB_ENDPOINT_HALT: | |
491 | ||
492 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
493 | if (!dep) | |
494 | return -EINVAL; | |
495 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
496 | if (ret) | |
497 | return -EINVAL; | |
498 | break; | |
499 | default: | |
500 | return -EINVAL; | |
501 | } | |
502 | break; | |
503 | ||
504 | default: | |
505 | return -EINVAL; | |
506 | }; | |
507 | ||
508 | dwc->ep0state = EP0_IN_WAIT_NRDY; | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
513 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
514 | { | |
515 | int ret = 0; | |
516 | u32 addr; | |
517 | u32 reg; | |
518 | ||
519 | addr = le16_to_cpu(ctrl->wValue); | |
520 | if (addr > 127) | |
521 | return -EINVAL; | |
522 | ||
523 | switch (dwc->dev_state) { | |
524 | case DWC3_DEFAULT_STATE: | |
525 | case DWC3_ADDRESS_STATE: | |
526 | /* | |
527 | * Not sure if we should program DevAddr now or later | |
528 | */ | |
529 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
530 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
531 | reg |= DWC3_DCFG_DEVADDR(addr); | |
532 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
533 | ||
534 | if (addr) | |
535 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
536 | else | |
537 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
538 | break; | |
539 | ||
540 | case DWC3_CONFIGURED_STATE: | |
541 | ret = -EINVAL; | |
542 | break; | |
543 | } | |
544 | dwc->ep0state = EP0_IN_WAIT_NRDY; | |
545 | return ret; | |
546 | } | |
547 | ||
548 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
549 | { | |
550 | int ret; | |
551 | ||
552 | spin_unlock(&dwc->lock); | |
553 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
554 | spin_lock(&dwc->lock); | |
555 | return ret; | |
556 | } | |
557 | ||
558 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
559 | { | |
560 | u32 cfg; | |
561 | int ret; | |
562 | ||
563 | cfg = le16_to_cpu(ctrl->wValue); | |
564 | ||
565 | switch (dwc->dev_state) { | |
566 | case DWC3_DEFAULT_STATE: | |
567 | return -EINVAL; | |
568 | break; | |
569 | ||
570 | case DWC3_ADDRESS_STATE: | |
571 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
572 | /* if the cfg matches and the cfg is non zero */ | |
573 | if (!ret && cfg) | |
574 | dwc->dev_state = DWC3_CONFIGURED_STATE; | |
575 | break; | |
576 | ||
577 | case DWC3_CONFIGURED_STATE: | |
578 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
579 | if (!cfg) | |
580 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
581 | break; | |
582 | } | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
587 | { | |
588 | int ret; | |
589 | ||
590 | switch (ctrl->bRequest) { | |
591 | case USB_REQ_GET_STATUS: | |
592 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
593 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
594 | break; | |
595 | case USB_REQ_CLEAR_FEATURE: | |
596 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
597 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
598 | break; | |
599 | case USB_REQ_SET_FEATURE: | |
600 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
601 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
602 | break; | |
603 | case USB_REQ_SET_ADDRESS: | |
604 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
605 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
606 | break; | |
607 | case USB_REQ_SET_CONFIGURATION: | |
608 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
609 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
610 | break; | |
611 | default: | |
612 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
613 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
614 | break; | |
615 | }; | |
616 | ||
617 | return ret; | |
618 | } | |
619 | ||
620 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
621 | const struct dwc3_event_depevt *event) | |
622 | { | |
623 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
624 | int ret; | |
625 | u32 len; | |
626 | ||
627 | if (!dwc->gadget_driver) | |
628 | goto err; | |
629 | ||
630 | len = le16_to_cpu(ctrl->wLength); | |
631 | if (!len) { | |
632 | dwc->ep0state = EP0_IN_WAIT_GADGET; | |
633 | dwc->three_stage_setup = 0; | |
634 | } else { | |
635 | dwc->three_stage_setup = 1; | |
636 | if (ctrl->bRequestType & USB_DIR_IN) | |
637 | dwc->ep0state = EP0_IN_DATA_PHASE; | |
638 | else | |
639 | dwc->ep0state = EP0_OUT_DATA_PHASE; | |
640 | } | |
641 | ||
642 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
643 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
644 | else | |
645 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
646 | ||
647 | if (ret >= 0) | |
648 | return; | |
649 | ||
650 | err: | |
651 | dwc3_ep0_stall_and_restart(dwc); | |
652 | } | |
653 | ||
654 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
655 | const struct dwc3_event_depevt *event) | |
656 | { | |
657 | struct dwc3_request *r = NULL; | |
658 | struct usb_request *ur; | |
659 | struct dwc3_trb trb; | |
660 | struct dwc3_ep *dep; | |
c611ccb4 | 661 | u32 transferred; |
72246da4 FB |
662 | u8 epnum; |
663 | ||
664 | epnum = event->endpoint_number; | |
665 | dep = dwc->eps[epnum]; | |
666 | ||
667 | if (!dwc->ep0_status_pending) { | |
668 | r = next_request(&dep->request_list); | |
669 | ur = &r->request; | |
670 | } else { | |
671 | ur = &dwc->ep0_usb_req; | |
672 | dwc->ep0_status_pending = 0; | |
673 | } | |
674 | ||
675 | dwc3_trb_to_nat(dwc->ep0_trb, &trb); | |
676 | ||
a6829706 FB |
677 | if (dwc->ep0_bounced) { |
678 | struct dwc3_ep *ep0 = dwc->eps[0]; | |
679 | ||
680 | transferred = min(ur->length, dep->endpoint.maxpacket - trb.length); | |
681 | memcpy(ur->buf, dwc->ep0_bounce, transferred); | |
682 | dwc->ep0_bounced = false; | |
683 | } else { | |
684 | transferred = ur->length - trb.length; | |
685 | ur->actual += transferred; | |
686 | } | |
72246da4 FB |
687 | |
688 | if ((epnum & 1) && ur->actual < ur->length) { | |
689 | /* for some reason we did not get everything out */ | |
690 | ||
691 | dwc3_ep0_stall_and_restart(dwc); | |
692 | dwc3_gadget_giveback(dep, r, -ECONNRESET); | |
693 | } else { | |
694 | /* | |
695 | * handle the case where we have to send a zero packet. This | |
696 | * seems to be case when req.length > maxpacket. Could it be? | |
697 | */ | |
698 | /* The transfer is complete, wait for HOST */ | |
699 | if (epnum & 1) | |
700 | dwc->ep0state = EP0_IN_WAIT_NRDY; | |
701 | else | |
702 | dwc->ep0state = EP0_OUT_WAIT_NRDY; | |
703 | ||
704 | if (r) | |
705 | dwc3_gadget_giveback(dep, r, 0); | |
706 | } | |
707 | } | |
708 | ||
709 | static void dwc3_ep0_complete_req(struct dwc3 *dwc, | |
710 | const struct dwc3_event_depevt *event) | |
711 | { | |
712 | struct dwc3_request *r; | |
713 | struct dwc3_ep *dep; | |
714 | u8 epnum; | |
715 | ||
716 | epnum = event->endpoint_number; | |
717 | dep = dwc->eps[epnum]; | |
718 | ||
719 | if (!list_empty(&dep->request_list)) { | |
720 | r = next_request(&dep->request_list); | |
721 | ||
722 | dwc3_gadget_giveback(dep, r, 0); | |
723 | } | |
724 | ||
725 | dwc->ep0state = EP0_IDLE; | |
726 | dwc3_ep0_out_start(dwc); | |
727 | } | |
728 | ||
729 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
730 | const struct dwc3_event_depevt *event) | |
731 | { | |
732 | switch (dwc->ep0state) { | |
733 | case EP0_IDLE: | |
734 | dwc3_ep0_inspect_setup(dwc, event); | |
735 | break; | |
736 | ||
737 | case EP0_IN_DATA_PHASE: | |
738 | case EP0_OUT_DATA_PHASE: | |
739 | dwc3_ep0_complete_data(dwc, event); | |
740 | break; | |
741 | ||
742 | case EP0_IN_STATUS_PHASE: | |
743 | case EP0_OUT_STATUS_PHASE: | |
744 | dwc3_ep0_complete_req(dwc, event); | |
745 | break; | |
746 | ||
747 | case EP0_IN_WAIT_NRDY: | |
748 | case EP0_OUT_WAIT_NRDY: | |
749 | case EP0_IN_WAIT_GADGET: | |
750 | case EP0_OUT_WAIT_GADGET: | |
751 | case EP0_UNCONNECTED: | |
752 | case EP0_STALL: | |
753 | break; | |
754 | } | |
755 | } | |
756 | ||
757 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, | |
758 | const struct dwc3_event_depevt *event) | |
759 | { | |
760 | switch (dwc->ep0state) { | |
761 | case EP0_IN_WAIT_GADGET: | |
762 | dwc->ep0state = EP0_IN_WAIT_NRDY; | |
763 | break; | |
764 | case EP0_OUT_WAIT_GADGET: | |
765 | dwc->ep0state = EP0_OUT_WAIT_NRDY; | |
766 | break; | |
767 | ||
768 | case EP0_IN_WAIT_NRDY: | |
769 | case EP0_OUT_WAIT_NRDY: | |
770 | dwc3_ep0_do_setup_status(dwc, event); | |
771 | break; | |
772 | ||
773 | case EP0_IDLE: | |
774 | case EP0_IN_STATUS_PHASE: | |
775 | case EP0_OUT_STATUS_PHASE: | |
776 | case EP0_IN_DATA_PHASE: | |
777 | case EP0_OUT_DATA_PHASE: | |
778 | case EP0_UNCONNECTED: | |
779 | case EP0_STALL: | |
780 | break; | |
781 | } | |
782 | } | |
783 | ||
784 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
785 | const const struct dwc3_event_depevt *event) | |
786 | { | |
787 | u8 epnum = event->endpoint_number; | |
788 | ||
789 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
790 | dwc3_ep_event_string(event->endpoint_event), | |
791 | epnum, (epnum & 1) ? "in" : "out", | |
792 | dwc3_ep0_state_string(dwc->ep0state)); | |
793 | ||
794 | switch (event->endpoint_event) { | |
795 | case DWC3_DEPEVT_XFERCOMPLETE: | |
796 | dwc3_ep0_xfer_complete(dwc, event); | |
797 | break; | |
798 | ||
799 | case DWC3_DEPEVT_XFERNOTREADY: | |
800 | dwc3_ep0_xfernotready(dwc, event); | |
801 | break; | |
802 | ||
803 | case DWC3_DEPEVT_XFERINPROGRESS: | |
804 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
805 | case DWC3_DEPEVT_STREAMEVT: | |
806 | case DWC3_DEPEVT_EPCMDCMPLT: | |
807 | break; | |
808 | } | |
809 | } |