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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/platform_device.h> | |
43 | #include <linux/pm_runtime.h> | |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/io.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | ||
49 | #include <linux/usb/ch9.h> | |
50 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 51 | #include <linux/usb/composite.h> |
72246da4 FB |
52 | |
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
5bdb1dcc SAS |
57 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum); |
58 | ||
72246da4 FB |
59 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) |
60 | { | |
61 | switch (state) { | |
62 | case EP0_UNCONNECTED: | |
63 | return "Unconnected"; | |
c7fcdeb2 FB |
64 | case EP0_SETUP_PHASE: |
65 | return "Setup Phase"; | |
66 | case EP0_DATA_PHASE: | |
67 | return "Data Phase"; | |
68 | case EP0_STATUS_PHASE: | |
69 | return "Status Phase"; | |
72246da4 FB |
70 | default: |
71 | return "UNKNOWN"; | |
72 | } | |
73 | } | |
74 | ||
75 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 76 | u32 len, u32 type) |
72246da4 FB |
77 | { |
78 | struct dwc3_gadget_ep_cmd_params params; | |
f6bafc6a | 79 | struct dwc3_trb *trb; |
72246da4 FB |
80 | struct dwc3_ep *dep; |
81 | ||
82 | int ret; | |
83 | ||
84 | dep = dwc->eps[epnum]; | |
c7fcdeb2 FB |
85 | if (dep->flags & DWC3_EP_BUSY) { |
86 | dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); | |
87 | return 0; | |
88 | } | |
72246da4 | 89 | |
f6bafc6a | 90 | trb = dwc->ep0_trb; |
72246da4 | 91 | |
f6bafc6a FB |
92 | trb->bpl = lower_32_bits(buf_dma); |
93 | trb->bph = upper_32_bits(buf_dma); | |
94 | trb->size = len; | |
95 | trb->ctrl = type; | |
72246da4 | 96 | |
f6bafc6a FB |
97 | trb->ctrl |= (DWC3_TRB_CTRL_HWO |
98 | | DWC3_TRB_CTRL_LST | |
99 | | DWC3_TRB_CTRL_IOC | |
100 | | DWC3_TRB_CTRL_ISP_IMI); | |
72246da4 FB |
101 | |
102 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
103 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
104 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 FB |
105 | |
106 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
107 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
108 | if (ret < 0) { | |
109 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
110 | return ret; | |
111 | } | |
112 | ||
c7fcdeb2 | 113 | dep->flags |= DWC3_EP_BUSY; |
72246da4 FB |
114 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, |
115 | dep->number); | |
116 | ||
1ddcb218 FB |
117 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
118 | ||
72246da4 FB |
119 | return 0; |
120 | } | |
121 | ||
122 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
123 | struct dwc3_request *req) | |
124 | { | |
5bdb1dcc | 125 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 126 | int ret = 0; |
72246da4 FB |
127 | |
128 | req->request.actual = 0; | |
129 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
130 | req->epnum = dep->number; |
131 | ||
132 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 133 | |
c7fcdeb2 FB |
134 | /* |
135 | * Gadget driver might not be quick enough to queue a request | |
136 | * before we get a Transfer Not Ready event on this endpoint. | |
137 | * | |
138 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
139 | * flag is set, it's telling us that as soon as Gadget queues the | |
140 | * required request, we should kick the transfer here because the | |
141 | * IRQ we were waiting for is long gone. | |
142 | */ | |
143 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 144 | unsigned direction; |
c7fcdeb2 FB |
145 | |
146 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
147 | ||
68d8a781 FB |
148 | if (dwc->ep0state != EP0_DATA_PHASE) { |
149 | dev_WARN(dwc->dev, "Unexpected pending request\n"); | |
c7fcdeb2 FB |
150 | return 0; |
151 | } | |
72246da4 | 152 | |
c7fcdeb2 | 153 | ret = dwc3_ep0_start_trans(dwc, direction, |
68d8a781 FB |
154 | req->request.dma, req->request.length, |
155 | DWC3_TRBCTL_CONTROL_DATA); | |
c7fcdeb2 FB |
156 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
157 | DWC3_EP0_DIR_IN); | |
68d3e668 | 158 | } else if (dwc->delayed_status) { |
5bdb1dcc | 159 | dwc->delayed_status = false; |
68d3e668 FB |
160 | |
161 | if (dwc->ep0state == EP0_STATUS_PHASE) | |
162 | dwc3_ep0_do_control_status(dwc, 1); | |
163 | else | |
164 | dev_dbg(dwc->dev, "too early for delayed status\n"); | |
72246da4 FB |
165 | } |
166 | ||
167 | return ret; | |
168 | } | |
169 | ||
170 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
171 | gfp_t gfp_flags) | |
172 | { | |
173 | struct dwc3_request *req = to_dwc3_request(request); | |
174 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
175 | struct dwc3 *dwc = dep->dwc; | |
176 | ||
177 | unsigned long flags; | |
178 | ||
179 | int ret; | |
180 | ||
72246da4 FB |
181 | spin_lock_irqsave(&dwc->lock, flags); |
182 | if (!dep->desc) { | |
183 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", | |
184 | request, dep->name); | |
185 | ret = -ESHUTDOWN; | |
186 | goto out; | |
187 | } | |
188 | ||
189 | /* we share one TRB for ep0/1 */ | |
c2da2ff0 | 190 | if (!list_empty(&dep->request_list)) { |
72246da4 FB |
191 | ret = -EBUSY; |
192 | goto out; | |
193 | } | |
194 | ||
195 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
196 | request, dep->name, request->length, | |
197 | dwc3_ep0_state_string(dwc->ep0state)); | |
198 | ||
199 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
200 | ||
201 | out: | |
202 | spin_unlock_irqrestore(&dwc->lock, flags); | |
203 | ||
204 | return ret; | |
205 | } | |
206 | ||
207 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
208 | { | |
d742220b FB |
209 | struct dwc3_ep *dep = dwc->eps[0]; |
210 | ||
72246da4 | 211 | /* stall is always issued on EP0 */ |
c2da2ff0 SAS |
212 | __dwc3_gadget_ep_set_halt(dep, 1); |
213 | dep->flags = DWC3_EP_ENABLED; | |
5bdb1dcc | 214 | dwc->delayed_status = false; |
d742220b FB |
215 | |
216 | if (!list_empty(&dep->request_list)) { | |
217 | struct dwc3_request *req; | |
218 | ||
219 | req = next_request(&dep->request_list); | |
220 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
221 | } | |
222 | ||
c7fcdeb2 | 223 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
224 | dwc3_ep0_out_start(dwc); |
225 | } | |
226 | ||
227 | void dwc3_ep0_out_start(struct dwc3 *dwc) | |
228 | { | |
72246da4 FB |
229 | int ret; |
230 | ||
c7fcdeb2 FB |
231 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
232 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
233 | WARN_ON(ret < 0); |
234 | } | |
235 | ||
72246da4 FB |
236 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
237 | { | |
238 | struct dwc3_ep *dep; | |
239 | u32 windex = le16_to_cpu(wIndex_le); | |
240 | u32 epnum; | |
241 | ||
242 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
243 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
244 | epnum |= 1; | |
245 | ||
246 | dep = dwc->eps[epnum]; | |
247 | if (dep->flags & DWC3_EP_ENABLED) | |
248 | return dep; | |
249 | ||
250 | return NULL; | |
251 | } | |
252 | ||
8ee6270c | 253 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 254 | { |
72246da4 | 255 | } |
72246da4 FB |
256 | /* |
257 | * ch 9.4.5 | |
258 | */ | |
25b8ff68 FB |
259 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
260 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
261 | { |
262 | struct dwc3_ep *dep; | |
263 | u32 recip; | |
e6a3b5e2 | 264 | u32 reg; |
72246da4 FB |
265 | u16 usb_status = 0; |
266 | __le16 *response_pkt; | |
267 | ||
268 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
269 | switch (recip) { | |
270 | case USB_RECIP_DEVICE: | |
271 | /* | |
e6a3b5e2 | 272 | * LTM will be set once we know how to set this in HW. |
72246da4 FB |
273 | */ |
274 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
e6a3b5e2 SAS |
275 | |
276 | if (dwc->speed == DWC3_DSTS_SUPERSPEED) { | |
277 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
278 | if (reg & DWC3_DCTL_INITU1ENA) | |
279 | usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; | |
280 | if (reg & DWC3_DCTL_INITU2ENA) | |
281 | usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; | |
282 | } | |
283 | ||
72246da4 FB |
284 | break; |
285 | ||
286 | case USB_RECIP_INTERFACE: | |
287 | /* | |
288 | * Function Remote Wake Capable D0 | |
289 | * Function Remote Wakeup D1 | |
290 | */ | |
291 | break; | |
292 | ||
293 | case USB_RECIP_ENDPOINT: | |
294 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
295 | if (!dep) | |
25b8ff68 | 296 | return -EINVAL; |
72246da4 FB |
297 | |
298 | if (dep->flags & DWC3_EP_STALL) | |
299 | usb_status = 1 << USB_ENDPOINT_HALT; | |
300 | break; | |
301 | default: | |
302 | return -EINVAL; | |
303 | }; | |
304 | ||
305 | response_pkt = (__le16 *) dwc->setup_buf; | |
306 | *response_pkt = cpu_to_le16(usb_status); | |
e2617796 FB |
307 | |
308 | dep = dwc->eps[0]; | |
309 | dwc->ep0_usb_req.dep = dep; | |
e0ce0b0a | 310 | dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
0fc9a1be | 311 | dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
e0ce0b0a | 312 | dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; |
e2617796 FB |
313 | |
314 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
72246da4 FB |
315 | } |
316 | ||
317 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
318 | struct usb_ctrlrequest *ctrl, int set) | |
319 | { | |
320 | struct dwc3_ep *dep; | |
321 | u32 recip; | |
322 | u32 wValue; | |
323 | u32 wIndex; | |
e6a3b5e2 | 324 | u32 reg; |
72246da4 | 325 | int ret; |
72246da4 FB |
326 | |
327 | wValue = le16_to_cpu(ctrl->wValue); | |
328 | wIndex = le16_to_cpu(ctrl->wIndex); | |
329 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
330 | switch (recip) { | |
331 | case USB_RECIP_DEVICE: | |
332 | ||
e6a3b5e2 SAS |
333 | switch (wValue) { |
334 | case USB_DEVICE_REMOTE_WAKEUP: | |
335 | break; | |
72246da4 FB |
336 | /* |
337 | * 9.4.1 says only only for SS, in AddressState only for | |
338 | * default control pipe | |
339 | */ | |
72246da4 | 340 | case USB_DEVICE_U1_ENABLE: |
72246da4 FB |
341 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) |
342 | return -EINVAL; | |
343 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
344 | return -EINVAL; | |
72246da4 | 345 | |
e6a3b5e2 SAS |
346 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
347 | if (set) | |
348 | reg |= DWC3_DCTL_INITU1ENA; | |
349 | else | |
350 | reg &= ~DWC3_DCTL_INITU1ENA; | |
351 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 352 | break; |
e6a3b5e2 | 353 | |
72246da4 | 354 | case USB_DEVICE_U2_ENABLE: |
e6a3b5e2 SAS |
355 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) |
356 | return -EINVAL; | |
357 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
358 | return -EINVAL; | |
359 | ||
360 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
361 | if (set) | |
362 | reg |= DWC3_DCTL_INITU2ENA; | |
363 | else | |
364 | reg &= ~DWC3_DCTL_INITU2ENA; | |
365 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 366 | break; |
e6a3b5e2 | 367 | |
72246da4 | 368 | case USB_DEVICE_LTM_ENABLE: |
e6a3b5e2 | 369 | return -EINVAL; |
72246da4 FB |
370 | break; |
371 | ||
372 | case USB_DEVICE_TEST_MODE: | |
373 | if ((wIndex & 0xff) != 0) | |
374 | return -EINVAL; | |
375 | if (!set) | |
376 | return -EINVAL; | |
377 | ||
3b637367 GC |
378 | dwc->test_mode_nr = wIndex >> 8; |
379 | dwc->test_mode = true; | |
72246da4 FB |
380 | } |
381 | break; | |
382 | ||
383 | case USB_RECIP_INTERFACE: | |
384 | switch (wValue) { | |
385 | case USB_INTRF_FUNC_SUSPEND: | |
386 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
387 | /* XXX enable Low power suspend */ | |
388 | ; | |
389 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
390 | /* XXX enable remote wakeup */ | |
391 | ; | |
392 | break; | |
393 | default: | |
394 | return -EINVAL; | |
395 | } | |
396 | break; | |
397 | ||
398 | case USB_RECIP_ENDPOINT: | |
399 | switch (wValue) { | |
400 | case USB_ENDPOINT_HALT: | |
1d046793 | 401 | dep = dwc3_wIndex_to_dep(dwc, wIndex); |
72246da4 FB |
402 | if (!dep) |
403 | return -EINVAL; | |
404 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
405 | if (ret) | |
406 | return -EINVAL; | |
407 | break; | |
408 | default: | |
409 | return -EINVAL; | |
410 | } | |
411 | break; | |
412 | ||
413 | default: | |
414 | return -EINVAL; | |
415 | }; | |
416 | ||
72246da4 FB |
417 | return 0; |
418 | } | |
419 | ||
420 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
421 | { | |
72246da4 FB |
422 | u32 addr; |
423 | u32 reg; | |
424 | ||
425 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 FB |
426 | if (addr > 127) { |
427 | dev_dbg(dwc->dev, "invalid device address %d\n", addr); | |
72246da4 | 428 | return -EINVAL; |
f96a6ec1 FB |
429 | } |
430 | ||
431 | if (dwc->dev_state == DWC3_CONFIGURED_STATE) { | |
432 | dev_dbg(dwc->dev, "trying to set address when configured\n"); | |
433 | return -EINVAL; | |
434 | } | |
72246da4 | 435 | |
2646021e FB |
436 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
437 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
438 | reg |= DWC3_DCFG_DEVADDR(addr); | |
439 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 440 | |
2646021e FB |
441 | if (addr) |
442 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
443 | else | |
444 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
c7fcdeb2 | 445 | |
2646021e | 446 | return 0; |
72246da4 FB |
447 | } |
448 | ||
449 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
450 | { | |
451 | int ret; | |
452 | ||
453 | spin_unlock(&dwc->lock); | |
454 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
455 | spin_lock(&dwc->lock); | |
456 | return ret; | |
457 | } | |
458 | ||
459 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
460 | { | |
461 | u32 cfg; | |
462 | int ret; | |
463 | ||
b23c8439 | 464 | dwc->start_config_issued = false; |
72246da4 FB |
465 | cfg = le16_to_cpu(ctrl->wValue); |
466 | ||
467 | switch (dwc->dev_state) { | |
468 | case DWC3_DEFAULT_STATE: | |
469 | return -EINVAL; | |
470 | break; | |
471 | ||
472 | case DWC3_ADDRESS_STATE: | |
473 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
474 | /* if the cfg matches and the cfg is non zero */ | |
457e84b6 | 475 | if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
72246da4 | 476 | dwc->dev_state = DWC3_CONFIGURED_STATE; |
457e84b6 FB |
477 | dwc->resize_fifos = true; |
478 | dev_dbg(dwc->dev, "resize fifos flag SET\n"); | |
479 | } | |
72246da4 FB |
480 | break; |
481 | ||
482 | case DWC3_CONFIGURED_STATE: | |
483 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
484 | if (!cfg) | |
485 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
486 | break; | |
5bdb1dcc SAS |
487 | default: |
488 | ret = -EINVAL; | |
72246da4 | 489 | } |
5bdb1dcc | 490 | return ret; |
72246da4 FB |
491 | } |
492 | ||
493 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
494 | { | |
495 | int ret; | |
496 | ||
497 | switch (ctrl->bRequest) { | |
498 | case USB_REQ_GET_STATUS: | |
499 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
500 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
501 | break; | |
502 | case USB_REQ_CLEAR_FEATURE: | |
503 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
504 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
505 | break; | |
506 | case USB_REQ_SET_FEATURE: | |
507 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
508 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
509 | break; | |
510 | case USB_REQ_SET_ADDRESS: | |
511 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
512 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
513 | break; | |
514 | case USB_REQ_SET_CONFIGURATION: | |
515 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
516 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
517 | break; | |
518 | default: | |
519 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
520 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
521 | break; | |
522 | }; | |
523 | ||
524 | return ret; | |
525 | } | |
526 | ||
527 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
528 | const struct dwc3_event_depevt *event) | |
529 | { | |
530 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
531 | int ret; | |
532 | u32 len; | |
533 | ||
534 | if (!dwc->gadget_driver) | |
535 | goto err; | |
536 | ||
537 | len = le16_to_cpu(ctrl->wLength); | |
1ddcb218 | 538 | if (!len) { |
d95b09b9 FB |
539 | dwc->three_stage_setup = false; |
540 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
541 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
542 | } else { | |
d95b09b9 FB |
543 | dwc->three_stage_setup = true; |
544 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
545 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
546 | } | |
72246da4 FB |
547 | |
548 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
549 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
550 | else | |
551 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
552 | ||
5bdb1dcc SAS |
553 | if (ret == USB_GADGET_DELAYED_STATUS) |
554 | dwc->delayed_status = true; | |
555 | ||
72246da4 FB |
556 | if (ret >= 0) |
557 | return; | |
558 | ||
559 | err: | |
560 | dwc3_ep0_stall_and_restart(dwc); | |
561 | } | |
562 | ||
563 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
564 | const struct dwc3_event_depevt *event) | |
565 | { | |
566 | struct dwc3_request *r = NULL; | |
567 | struct usb_request *ur; | |
f6bafc6a | 568 | struct dwc3_trb *trb; |
c2da2ff0 | 569 | struct dwc3_ep *ep0; |
c611ccb4 | 570 | u32 transferred; |
f6bafc6a | 571 | u32 length; |
72246da4 FB |
572 | u8 epnum; |
573 | ||
574 | epnum = event->endpoint_number; | |
c2da2ff0 | 575 | ep0 = dwc->eps[0]; |
72246da4 | 576 | |
1ddcb218 FB |
577 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
578 | ||
c2da2ff0 | 579 | r = next_request(&ep0->request_list); |
8ee6270c | 580 | ur = &r->request; |
72246da4 | 581 | |
f6bafc6a FB |
582 | trb = dwc->ep0_trb; |
583 | length = trb->size & DWC3_TRB_SIZE_MASK; | |
72246da4 | 584 | |
a6829706 | 585 | if (dwc->ep0_bounced) { |
c7fcdeb2 | 586 | transferred = min_t(u32, ur->length, |
f6bafc6a | 587 | ep0->endpoint.maxpacket - length); |
a6829706 FB |
588 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
589 | dwc->ep0_bounced = false; | |
590 | } else { | |
f6bafc6a | 591 | transferred = ur->length - length; |
a6829706 FB |
592 | ur->actual += transferred; |
593 | } | |
72246da4 FB |
594 | |
595 | if ((epnum & 1) && ur->actual < ur->length) { | |
596 | /* for some reason we did not get everything out */ | |
597 | ||
598 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
599 | } else { |
600 | /* | |
601 | * handle the case where we have to send a zero packet. This | |
602 | * seems to be case when req.length > maxpacket. Could it be? | |
603 | */ | |
72246da4 | 604 | if (r) |
c2da2ff0 | 605 | dwc3_gadget_giveback(ep0, r, 0); |
72246da4 FB |
606 | } |
607 | } | |
608 | ||
609 | static void dwc3_ep0_complete_req(struct dwc3 *dwc, | |
610 | const struct dwc3_event_depevt *event) | |
611 | { | |
612 | struct dwc3_request *r; | |
613 | struct dwc3_ep *dep; | |
72246da4 | 614 | |
c7fcdeb2 | 615 | dep = dwc->eps[0]; |
72246da4 FB |
616 | |
617 | if (!list_empty(&dep->request_list)) { | |
618 | r = next_request(&dep->request_list); | |
619 | ||
620 | dwc3_gadget_giveback(dep, r, 0); | |
621 | } | |
622 | ||
3b637367 GC |
623 | if (dwc->test_mode) { |
624 | int ret; | |
625 | ||
626 | ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); | |
627 | if (ret < 0) { | |
628 | dev_dbg(dwc->dev, "Invalid Test #%d\n", | |
629 | dwc->test_mode_nr); | |
630 | dwc3_ep0_stall_and_restart(dwc); | |
631 | } | |
632 | } | |
633 | ||
c7fcdeb2 | 634 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
635 | dwc3_ep0_out_start(dwc); |
636 | } | |
637 | ||
638 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
639 | const struct dwc3_event_depevt *event) | |
640 | { | |
c7fcdeb2 FB |
641 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
642 | ||
643 | dep->flags &= ~DWC3_EP_BUSY; | |
c2df85ca | 644 | dep->res_trans_idx = 0; |
df62df56 | 645 | dwc->setup_packet_pending = false; |
c7fcdeb2 | 646 | |
72246da4 | 647 | switch (dwc->ep0state) { |
c7fcdeb2 FB |
648 | case EP0_SETUP_PHASE: |
649 | dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); | |
72246da4 FB |
650 | dwc3_ep0_inspect_setup(dwc, event); |
651 | break; | |
652 | ||
c7fcdeb2 FB |
653 | case EP0_DATA_PHASE: |
654 | dev_vdbg(dwc->dev, "Data Phase\n"); | |
72246da4 FB |
655 | dwc3_ep0_complete_data(dwc, event); |
656 | break; | |
657 | ||
c7fcdeb2 FB |
658 | case EP0_STATUS_PHASE: |
659 | dev_vdbg(dwc->dev, "Status Phase\n"); | |
72246da4 FB |
660 | dwc3_ep0_complete_req(dwc, event); |
661 | break; | |
c7fcdeb2 FB |
662 | default: |
663 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
664 | } | |
665 | } | |
72246da4 | 666 | |
c7fcdeb2 FB |
667 | static void dwc3_ep0_do_control_setup(struct dwc3 *dwc, |
668 | const struct dwc3_event_depevt *event) | |
669 | { | |
c7fcdeb2 FB |
670 | dwc3_ep0_out_start(dwc); |
671 | } | |
672 | ||
673 | static void dwc3_ep0_do_control_data(struct dwc3 *dwc, | |
674 | const struct dwc3_event_depevt *event) | |
675 | { | |
676 | struct dwc3_ep *dep; | |
677 | struct dwc3_request *req; | |
678 | int ret; | |
679 | ||
680 | dep = dwc->eps[0]; | |
c7fcdeb2 FB |
681 | |
682 | if (list_empty(&dep->request_list)) { | |
683 | dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n"); | |
684 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
685 | ||
686 | if (event->endpoint_number) | |
687 | dep->flags |= DWC3_EP0_DIR_IN; | |
688 | return; | |
72246da4 | 689 | } |
c7fcdeb2 FB |
690 | |
691 | req = next_request(&dep->request_list); | |
692 | req->direction = !!event->endpoint_number; | |
693 | ||
c7fcdeb2 FB |
694 | if (req->request.length == 0) { |
695 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
696 | dwc->ctrl_req_addr, 0, | |
697 | DWC3_TRBCTL_CONTROL_DATA); | |
698 | } else if ((req->request.length % dep->endpoint.maxpacket) | |
699 | && (event->endpoint_number == 0)) { | |
0fc9a1be FB |
700 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
701 | event->endpoint_number); | |
702 | if (ret) { | |
703 | dev_dbg(dwc->dev, "failed to map request\n"); | |
704 | return; | |
705 | } | |
c7fcdeb2 FB |
706 | |
707 | WARN_ON(req->request.length > dep->endpoint.maxpacket); | |
708 | ||
709 | dwc->ep0_bounced = true; | |
710 | ||
711 | /* | |
712 | * REVISIT in case request length is bigger than EP0 | |
713 | * wMaxPacketSize, we will need two chained TRBs to handle | |
714 | * the transfer. | |
715 | */ | |
716 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
717 | dwc->ep0_bounce_addr, dep->endpoint.maxpacket, | |
718 | DWC3_TRBCTL_CONTROL_DATA); | |
719 | } else { | |
0fc9a1be FB |
720 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
721 | event->endpoint_number); | |
722 | if (ret) { | |
723 | dev_dbg(dwc->dev, "failed to map request\n"); | |
724 | return; | |
725 | } | |
c7fcdeb2 FB |
726 | |
727 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
728 | req->request.dma, req->request.length, | |
729 | DWC3_TRBCTL_CONTROL_DATA); | |
730 | } | |
731 | ||
732 | WARN_ON(ret < 0); | |
72246da4 FB |
733 | } |
734 | ||
f0f2b2a2 | 735 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 736 | { |
f0f2b2a2 | 737 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 738 | u32 type; |
72246da4 | 739 | |
c7fcdeb2 FB |
740 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
741 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
742 | ||
f0f2b2a2 | 743 | return dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 | 744 | dwc->ctrl_req_addr, 0, type); |
f0f2b2a2 | 745 | } |
c7fcdeb2 | 746 | |
f0f2b2a2 SAS |
747 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum) |
748 | { | |
749 | struct dwc3_ep *dep = dwc->eps[epnum]; | |
750 | ||
457e84b6 FB |
751 | if (dwc->resize_fifos) { |
752 | dev_dbg(dwc->dev, "starting to resize fifos\n"); | |
753 | dwc3_gadget_resize_tx_fifos(dwc); | |
754 | dwc->resize_fifos = 0; | |
755 | } | |
756 | ||
f0f2b2a2 | 757 | WARN_ON(dwc3_ep0_start_control_status(dep)); |
c7fcdeb2 FB |
758 | } |
759 | ||
760 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, | |
761 | const struct dwc3_event_depevt *event) | |
762 | { | |
df62df56 FB |
763 | dwc->setup_packet_pending = true; |
764 | ||
9cc9bcd5 FB |
765 | /* |
766 | * This part is very tricky: If we has just handled | |
767 | * XferNotReady(Setup) and we're now expecting a | |
768 | * XferComplete but, instead, we receive another | |
769 | * XferNotReady(Setup), we should STALL and restart | |
770 | * the state machine. | |
771 | * | |
772 | * In all other cases, we just continue waiting | |
773 | * for the XferComplete event. | |
774 | * | |
775 | * We are a little bit unsafe here because we're | |
776 | * not trying to ensure that last event was, indeed, | |
777 | * XferNotReady(Setup). | |
778 | * | |
779 | * Still, we don't expect any condition where that | |
780 | * should happen and, even if it does, it would be | |
781 | * another error condition. | |
782 | */ | |
783 | if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) { | |
784 | switch (event->status) { | |
785 | case DEPEVT_STATUS_CONTROL_SETUP: | |
786 | dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n"); | |
787 | dwc3_ep0_stall_and_restart(dwc); | |
788 | break; | |
789 | case DEPEVT_STATUS_CONTROL_DATA: | |
790 | /* FALLTHROUGH */ | |
791 | case DEPEVT_STATUS_CONTROL_STATUS: | |
792 | /* FALLTHROUGH */ | |
793 | default: | |
794 | dev_vdbg(dwc->dev, "waiting for XferComplete\n"); | |
795 | } | |
796 | ||
797 | return; | |
798 | } | |
799 | ||
c7fcdeb2 FB |
800 | switch (event->status) { |
801 | case DEPEVT_STATUS_CONTROL_SETUP: | |
802 | dev_vdbg(dwc->dev, "Control Setup\n"); | |
f0f2b2a2 SAS |
803 | |
804 | dwc->ep0state = EP0_SETUP_PHASE; | |
805 | ||
c7fcdeb2 FB |
806 | dwc3_ep0_do_control_setup(dwc, event); |
807 | break; | |
1ddcb218 | 808 | |
c7fcdeb2 FB |
809 | case DEPEVT_STATUS_CONTROL_DATA: |
810 | dev_vdbg(dwc->dev, "Control Data\n"); | |
1ddcb218 | 811 | |
f0f2b2a2 SAS |
812 | dwc->ep0state = EP0_DATA_PHASE; |
813 | ||
1ddcb218 FB |
814 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) { |
815 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
816 | dwc->ep0_next_event, |
817 | DWC3_EP0_NRDY_DATA); | |
1ddcb218 FB |
818 | |
819 | dwc3_ep0_stall_and_restart(dwc); | |
820 | return; | |
821 | } | |
822 | ||
55f3fba6 FB |
823 | /* |
824 | * One of the possible error cases is when Host _does_ | |
825 | * request for Data Phase, but it does so on the wrong | |
826 | * direction. | |
827 | * | |
828 | * Here, we already know ep0_next_event is DATA (see above), | |
829 | * so we only need to check for direction. | |
830 | */ | |
831 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
832 | dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); | |
833 | dwc3_ep0_stall_and_restart(dwc); | |
834 | return; | |
835 | } | |
836 | ||
c7fcdeb2 FB |
837 | dwc3_ep0_do_control_data(dwc, event); |
838 | break; | |
1ddcb218 | 839 | |
c7fcdeb2 FB |
840 | case DEPEVT_STATUS_CONTROL_STATUS: |
841 | dev_vdbg(dwc->dev, "Control Status\n"); | |
1ddcb218 | 842 | |
f0f2b2a2 SAS |
843 | dwc->ep0state = EP0_STATUS_PHASE; |
844 | ||
1ddcb218 FB |
845 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) { |
846 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
847 | dwc->ep0_next_event, |
848 | DWC3_EP0_NRDY_STATUS); | |
1ddcb218 FB |
849 | |
850 | dwc3_ep0_stall_and_restart(dwc); | |
851 | return; | |
852 | } | |
5bdb1dcc SAS |
853 | |
854 | if (dwc->delayed_status) { | |
855 | WARN_ON_ONCE(event->endpoint_number != 1); | |
856 | dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); | |
857 | return; | |
858 | } | |
859 | ||
f0f2b2a2 | 860 | dwc3_ep0_do_control_status(dwc, event->endpoint_number); |
72246da4 FB |
861 | } |
862 | } | |
863 | ||
864 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 865 | const struct dwc3_event_depevt *event) |
72246da4 FB |
866 | { |
867 | u8 epnum = event->endpoint_number; | |
868 | ||
869 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
870 | dwc3_ep_event_string(event->endpoint_event), | |
b147f357 | 871 | epnum >> 1, (epnum & 1) ? "in" : "out", |
72246da4 FB |
872 | dwc3_ep0_state_string(dwc->ep0state)); |
873 | ||
874 | switch (event->endpoint_event) { | |
875 | case DWC3_DEPEVT_XFERCOMPLETE: | |
876 | dwc3_ep0_xfer_complete(dwc, event); | |
877 | break; | |
878 | ||
879 | case DWC3_DEPEVT_XFERNOTREADY: | |
880 | dwc3_ep0_xfernotready(dwc, event); | |
881 | break; | |
882 | ||
883 | case DWC3_DEPEVT_XFERINPROGRESS: | |
884 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
885 | case DWC3_DEPEVT_STREAMEVT: | |
886 | case DWC3_DEPEVT_EPCMDCMPLT: | |
887 | break; | |
888 | } | |
889 | } |