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UBUNTU: Ubuntu-4.10.0-37.41
[mirror_ubuntu-zesty-kernel.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
1eb92ec9 174 unsigned int unmap_after_complete = false;
72246da4 175
737f1ae2 176 req->started = false;
72246da4 177 list_del(&req->list);
eeb720fb 178 req->trb = NULL;
e62c5bc5 179 req->remaining = 0;
72246da4
FB		 180
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
183
1eb92ec9
JD		 184 /*
185 * NOTICE we don't want to unmap before calling ->complete() if we're
186 * dealing with a bounced ep0 request. If we unmap it here, we would end
187 * up overwritting the contents of req->buf and this could confuse the
188 * gadget driver.
189 */
190 if (dwc->ep0_bounced && dep->number <= 1) {
0416e494 191 dwc->ep0_bounced = false;
1eb92ec9
JD		 192 unmap_after_complete = true;
193 } else {
194 usb_gadget_unmap_request_by_dev(dwc->sysdev,
195 &req->request, req->direction);
196 }
72246da4 197
2c4cbe6e 198 trace_dwc3_gadget_giveback(req);
72246da4
FB		 199
200 spin_unlock(&dwc->lock);
304f7e5e 201 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 202 spin_lock(&dwc->lock);
fc8bb91b 203
1eb92ec9
JD		 204 if (unmap_after_complete)
205 usb_gadget_unmap_request_by_dev(dwc->sysdev,
206 &req->request, req->direction);
207
fc8bb91b
FB		 208 if (dep->number > 1)
209 pm_runtime_put(dwc->dev);
72246da4
FB		 210}
211
3ece0ec4 212int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 213{
214 u32 timeout = 500;
71f7e702 215 int status = 0;
0fe886cd 216 int ret = 0;
b09bb642
FB		 217 u32 reg;
218
219 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
220 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
221
222 do {
223 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
224 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 225 status = DWC3_DGCMD_STATUS(reg);
226 if (status)
0fe886cd
FB		 227 ret = -EINVAL;
228 break;
b09bb642 229 }
e3aee486 230 } while (--timeout);
0fe886cd
FB		 231
232 if (!timeout) {
0fe886cd 233 ret = -ETIMEDOUT;
71f7e702 234 status = -ETIMEDOUT;
0fe886cd
FB		 235 }
236
71f7e702
FB		 237 trace_dwc3_gadget_generic_cmd(cmd, param, status);
238
0fe886cd 239 return ret;
b09bb642
FB		 240}
241
c36d8e94
FB		 242static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
243
2cd4718d
FB		 244int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
245 struct dwc3_gadget_ep_cmd_params *params)
72246da4 246{
8897a761 247 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 248 struct dwc3 *dwc = dep->dwc;
61d58242 249 u32 timeout = 500;
72246da4
FB		 250 u32 reg;
251
0933df15 252 int cmd_status = 0;
2b0f11df 253 int susphy = false;
c0ca324d 254 int ret = -EINVAL;
72246da4 255
2b0f11df
FB		 256 /*
257 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
258 * we're issuing an endpoint command, we must check if
259 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
260 *
261 * We will also set SUSPHY bit to what it was before returning as stated
262 * by the same section on Synopsys databook.
263 */
ab2a92e7
FB		 264 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
265 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
266 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
267 susphy = true;
268 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
269 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
270 }
2b0f11df
FB		 271 }
272
5999914f 273 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 274 int needs_wakeup;
275
276 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
277 dwc->link_state == DWC3_LINK_STATE_U2 ||
278 dwc->link_state == DWC3_LINK_STATE_U3);
279
280 if (unlikely(needs_wakeup)) {
281 ret = __dwc3_gadget_wakeup(dwc);
282 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
283 ret);
284 }
285 }
286
2eb88016
FB		 287 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
288 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
289 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 290
8897a761
FB		 291 /*
292 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
293 * not relying on XferNotReady, we can make use of a special "No
294 * Response Update Transfer" command where we should clear both CmdAct
295 * and CmdIOC bits.
296 *
297 * With this, we don't need to wait for command completion and can
298 * straight away issue further commands to the endpoint.
299 *
300 * NOTICE: We're making an assumption that control endpoints will never
301 * make use of Update Transfer command. This is a safe assumption
302 * because we can never have more than one request at a time with
303 * Control Endpoints. If anybody changes that assumption, this chunk
304 * needs to be updated accordingly.
305 */
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
307 !usb_endpoint_xfer_isoc(desc))
308 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
309 else
310 cmd |= DWC3_DEPCMD_CMDACT;
311
312 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 313 do {
2eb88016 314 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 315 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 316 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 317
7b9cc7a2
KL		 318 switch (cmd_status) {
319 case 0:
320 ret = 0;
321 break;
322 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 323 ret = -EINVAL;
c0ca324d 324 break;
7b9cc7a2
KL		 325 case DEPEVT_TRANSFER_BUS_EXPIRY:
326 /*
327 * SW issues START TRANSFER command to
328 * isochronous ep with future frame interval. If
329 * future interval time has already passed when
330 * core receives the command, it will respond
331 * with an error status of 'Bus Expiry'.
332 *
333 * Instead of always returning -EINVAL, let's
334 * give a hint to the gadget driver that this is
335 * the case by returning -EAGAIN.
336 */
7b9cc7a2
KL		 337 ret = -EAGAIN;
338 break;
339 default:
340 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
341 }
342
c0ca324d 343 break;
72246da4 344 }
f6bb225b 345 } while (--timeout);
72246da4 346
f6bb225b 347 if (timeout == 0) {
f6bb225b 348 ret = -ETIMEDOUT;
0933df15 349 cmd_status = -ETIMEDOUT;
f6bb225b 350 }
c0ca324d 351
0933df15
FB		 352 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
353
6cb2e4e3
FB		 354 if (ret == 0) {
355 switch (DWC3_DEPCMD_CMD(cmd)) {
356 case DWC3_DEPCMD_STARTTRANSFER:
357 dep->flags |= DWC3_EP_TRANSFER_STARTED;
358 break;
359 case DWC3_DEPCMD_ENDTRANSFER:
360 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
361 break;
362 default:
363 /* nothing */
364 break;
365 }
366 }
367
2b0f11df
FB		 368 if (unlikely(susphy)) {
369 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
370 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
371 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
372 }
373
c0ca324d 374 return ret;
72246da4
FB		 375}
376
50c763f8
JY		 377static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380 struct dwc3_gadget_ep_cmd_params params;
381 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
382
383 /*
384 * As of core revision 2.60a the recommended programming model
385 * is to set the ClearPendIN bit when issuing a Clear Stall EP
386 * command for IN endpoints. This is to prevent an issue where
387 * some (non-compliant) hosts may not send ACK TPs for pending
388 * IN transfers due to a mishandled error condition. Synopsys
389 * STAR 9000614252.
390 */
5e6c88d2
LB		 391 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
392 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 393 cmd |= DWC3_DEPCMD_CLEARPENDIN;
394
395 memset(&params, 0, sizeof(params));
396
2cd4718d 397 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 398}
399
72246da4 400static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 401 struct dwc3_trb *trb)
72246da4 402{
c439ef87 403 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 404
405 return dep->trb_pool_dma + offset;
406}
407
408static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
409{
410 struct dwc3 *dwc = dep->dwc;
411
412 if (dep->trb_pool)
413 return 0;
414
d64ff406 415 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 416 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
417 &dep->trb_pool_dma, GFP_KERNEL);
418 if (!dep->trb_pool) {
419 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
420 dep->name);
421 return -ENOMEM;
422 }
423
424 return 0;
425}
426
427static void dwc3_free_trb_pool(struct dwc3_ep *dep)
428{
429 struct dwc3 *dwc = dep->dwc;
430
d64ff406 431 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 432 dep->trb_pool, dep->trb_pool_dma);
433
434 dep->trb_pool = NULL;
435 dep->trb_pool_dma = 0;
436}
437
c4509601
JY		 438static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
439
440/**
441 * dwc3_gadget_start_config - Configure EP resources
442 * @dwc: pointer to our controller context structure
443 * @dep: endpoint that is being enabled
444 *
445 * The assignment of transfer resources cannot perfectly follow the
446 * data book due to the fact that the controller driver does not have
447 * all knowledge of the configuration in advance. It is given this
448 * information piecemeal by the composite gadget framework after every
449 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
450 * programming model in this scenario can cause errors. For two
451 * reasons:
452 *
453 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
454 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
455 * multiple interfaces.
456 *
457 * 2) The databook does not mention doing more DEPXFERCFG for new
458 * endpoint on alt setting (8.1.6).
459 *
460 * The following simplified method is used instead:
461 *
462 * All hardware endpoints can be assigned a transfer resource and this
463 * setting will stay persistent until either a core reset or
464 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
465 * do DEPXFERCFG for every hardware endpoint as well. We are
466 * guaranteed that there are as many transfer resources as endpoints.
467 *
468 * This function is called for each endpoint when it is being enabled
469 * but is triggered only when called for EP0-out, which always happens
470 * first, and which should only happen in one of the above conditions.
471 */
72246da4
FB		 472static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
473{
474 struct dwc3_gadget_ep_cmd_params params;
475 u32 cmd;
c4509601
JY		 476 int i;
477 int ret;
478
479 if (dep->number)
480 return 0;
72246da4
FB		 481
482 memset(&params, 0x00, sizeof(params));
c4509601 483 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 484
2cd4718d 485 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 486 if (ret)
487 return ret;
488
489 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
490 struct dwc3_ep *dep = dwc->eps[i];
72246da4 491
c4509601
JY		 492 if (!dep)
493 continue;
494
495 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
496 if (ret)
497 return ret;
72246da4
FB		 498 }
499
500 return 0;
501}
502
503static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 504 bool modify, bool restore)
72246da4 505{
39ebb05c
JY		 506 const struct usb_ss_ep_comp_descriptor *comp_desc;
507 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 508 struct dwc3_gadget_ep_cmd_params params;
509
21e64bf2
FB		 510 if (dev_WARN_ONCE(dwc->dev, modify && restore,
511 "Can't modify and restore\n"))
512 return -EINVAL;
513
39ebb05c
JY		 514 comp_desc = dep->endpoint.comp_desc;
515 desc = dep->endpoint.desc;
516
72246da4
FB		 517 memset(&params, 0x00, sizeof(params));
518
dc1c70a7 519 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 520 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
521
522 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 523 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 524 u32 burst = dep->endpoint.maxburst;
676e3497 525 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 526 }
72246da4 527
21e64bf2
FB		 528 if (modify) {
529 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
530 } else if (restore) {
265b70a7
PZ		 531 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
532 params.param2 |= dep->saved_state;
21e64bf2
FB		 533 } else {
534 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 535 }
536
4bc48c97
FB		 537 if (usb_endpoint_xfer_control(desc))
538 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 539
540 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
541 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 542
18b7ede5 543 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 544 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
545 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 546 dep->stream_capable = true;
547 }
548
0b93a4c8 549 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 550 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 551
552 /*
553 * We are doing 1:1 mapping for endpoints, meaning
554 * Physical Endpoints 2 maps to Logical Endpoint 2 and
555 * so on. We consider the direction bit as part of the physical
556 * endpoint number. So USB endpoint 0x81 is 0x03.
557 */
dc1c70a7 558 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 559
560 /*
561 * We must use the lower 16 TX FIFOs even though
562 * HW might have more
563 */
564 if (dep->direction)
dc1c70a7 565 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 566
567 if (desc->bInterval) {
dc1c70a7 568 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 569 dep->interval = 1 << (desc->bInterval - 1);
570 }
571
2cd4718d 572 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 573}
574
575static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
576{
577 struct dwc3_gadget_ep_cmd_params params;
578
579 memset(&params, 0x00, sizeof(params));
580
dc1c70a7 581 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 582
2cd4718d
FB		 583 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
584 &params);
72246da4
FB		 585}
586
587/**
588 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
589 * @dep: endpoint to be initialized
590 * @desc: USB Endpoint Descriptor
591 *
592 * Caller should take care of locking
593 */
594static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 595 bool modify, bool restore)
72246da4 596{
39ebb05c 597 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 598 struct dwc3 *dwc = dep->dwc;
39ebb05c 599
72246da4 600 u32 reg;
b09e99ee 601 int ret;
72246da4
FB		 602
603 if (!(dep->flags & DWC3_EP_ENABLED)) {
604 ret = dwc3_gadget_start_config(dwc, dep);
605 if (ret)
606 return ret;
607 }
608
39ebb05c 609 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 610 if (ret)
611 return ret;
612
613 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 614 struct dwc3_trb *trb_st_hw;
615 struct dwc3_trb *trb_link;
72246da4 616
72246da4
FB		 617 dep->type = usb_endpoint_type(desc);
618 dep->flags |= DWC3_EP_ENABLED;
76a638f8 619 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 620
621 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
622 reg |= DWC3_DALEPENA_EP(dep->number);
623 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
624
76a638f8
BW		 625 init_waitqueue_head(&dep->wait_end_transfer);
626
36b68aae 627 if (usb_endpoint_xfer_control(desc))
2870e501 628 goto out;
72246da4 629
0d25744a
JY		 630 /* Initialize the TRB ring */
631 dep->trb_dequeue = 0;
632 dep->trb_enqueue = 0;
633 memset(dep->trb_pool, 0,
634 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
635
36b68aae 636 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 637 trb_st_hw = &dep->trb_pool[0];
638
f6bafc6a 639 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 640 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
641 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
642 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
643 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 644 }
645
a97ea994
FB		 646 /*
647 * Issue StartTransfer here with no-op TRB so we can always rely on No
648 * Response Update Transfer command.
649 */
650 if (usb_endpoint_xfer_bulk(desc)) {
651 struct dwc3_gadget_ep_cmd_params params;
652 struct dwc3_trb *trb;
653 dma_addr_t trb_dma;
654 u32 cmd;
655
656 memset(&params, 0, sizeof(params));
657 trb = &dep->trb_pool[0];
658 trb_dma = dwc3_trb_dma_offset(dep, trb);
659
660 params.param0 = upper_32_bits(trb_dma);
661 params.param1 = lower_32_bits(trb_dma);
662
663 cmd = DWC3_DEPCMD_STARTTRANSFER;
664
665 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
666 if (ret < 0)
667 return ret;
668
669 dep->flags |= DWC3_EP_BUSY;
670
671 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
672 WARN_ON_ONCE(!dep->resource_index);
673 }
674
2870e501
FB		 675
676out:
677 trace_dwc3_gadget_ep_enable(dep);
678
72246da4
FB		 679 return 0;
680}
681
b992e681 682static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 683static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 684{
685 struct dwc3_request *req;
686
0e146028 687 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 688
0e146028
FB		 689 /* - giveback all requests to gadget driver */
690 while (!list_empty(&dep->started_list)) {
691 req = next_request(&dep->started_list);
1591633e 692
0e146028 693 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 694 }
695
aa3342c8
FB		 696 while (!list_empty(&dep->pending_list)) {
697 req = next_request(&dep->pending_list);
72246da4 698
624407f9 699 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 700 }
72246da4
FB		 701}
702
703/**
704 * __dwc3_gadget_ep_disable - Disables a HW endpoint
705 * @dep: the endpoint to disable
706 *
624407f9
SAS		 707 * This function also removes requests which are currently processed ny the
708 * hardware and those which are not yet scheduled.
709 * Caller should take care of locking.
72246da4 710 */
72246da4
FB		 711static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
712{
713 struct dwc3 *dwc = dep->dwc;
714 u32 reg;
715
2870e501 716 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 717
624407f9 718 dwc3_remove_requests(dwc, dep);
72246da4 719
687ef981
FB		 720 /* make sure HW endpoint isn't stalled */
721 if (dep->flags & DWC3_EP_STALL)
7a608559 722 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 723
72246da4
FB		 724 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
725 reg &= ~DWC3_DALEPENA_EP(dep->number);
726 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
727
879631aa 728 dep->stream_capable = false;
72246da4 729 dep->type = 0;
76a638f8 730 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 731
39ebb05c
JY		 732 /* Clear out the ep descriptors for non-ep0 */
733 if (dep->number > 1) {
734 dep->endpoint.comp_desc = NULL;
735 dep->endpoint.desc = NULL;
736 }
737
72246da4
FB		 738 return 0;
739}
740
741/* -------------------------------------------------------------------------- */
742
743static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
744 const struct usb_endpoint_descriptor *desc)
745{
746 return -EINVAL;
747}
748
749static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
750{
751 return -EINVAL;
752}
753
754/* -------------------------------------------------------------------------- */
755
756static int dwc3_gadget_ep_enable(struct usb_ep *ep,
757 const struct usb_endpoint_descriptor *desc)
758{
759 struct dwc3_ep *dep;
760 struct dwc3 *dwc;
761 unsigned long flags;
762 int ret;
763
764 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
765 pr_debug("dwc3: invalid parameters\n");
766 return -EINVAL;
767 }
768
769 if (!desc->wMaxPacketSize) {
770 pr_debug("dwc3: missing wMaxPacketSize\n");
771 return -EINVAL;
772 }
773
774 dep = to_dwc3_ep(ep);
775 dwc = dep->dwc;
776
95ca961c
FB		 777 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
778 "%s is already enabled\n",
779 dep->name))
c6f83f38 780 return 0;
c6f83f38 781
72246da4 782 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 783 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 784 spin_unlock_irqrestore(&dwc->lock, flags);
785
786 return ret;
787}
788
789static int dwc3_gadget_ep_disable(struct usb_ep *ep)
790{
791 struct dwc3_ep *dep;
792 struct dwc3 *dwc;
793 unsigned long flags;
794 int ret;
795
796 if (!ep) {
797 pr_debug("dwc3: invalid parameters\n");
798 return -EINVAL;
799 }
800
801 dep = to_dwc3_ep(ep);
802 dwc = dep->dwc;
803
95ca961c
FB		 804 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
805 "%s is already disabled\n",
806 dep->name))
72246da4 807 return 0;
72246da4 808
72246da4
FB		 809 spin_lock_irqsave(&dwc->lock, flags);
810 ret = __dwc3_gadget_ep_disable(dep);
811 spin_unlock_irqrestore(&dwc->lock, flags);
812
813 return ret;
814}
815
816static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
817 gfp_t gfp_flags)
818{
819 struct dwc3_request *req;
820 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 821
822 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 823 if (!req)
72246da4 824 return NULL;
72246da4
FB		 825
826 req->epnum = dep->number;
827 req->dep = dep;
72246da4 828
68d34c8a
FB		 829 dep->allocated_requests++;
830
2c4cbe6e
FB		 831 trace_dwc3_alloc_request(req);
832
72246da4
FB		 833 return &req->request;
834}
835
836static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
837 struct usb_request *request)
838{
839 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 840 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 841
68d34c8a 842 dep->allocated_requests--;
2c4cbe6e 843 trace_dwc3_free_request(req);
72246da4
FB		 844 kfree(req);
845}
846
2c78c029
FB		 847static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
848
c71fc37c
FB		 849/**
850 * dwc3_prepare_one_trb - setup one TRB from one request
851 * @dep: endpoint for which this request is prepared
852 * @req: dwc3_request pointer
853 */
68e823e2 854static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 855 struct dwc3_request *req, dma_addr_t dma,
4bc48c97 856 unsigned length, unsigned chain, unsigned node)
c71fc37c 857{
f6bafc6a 858 struct dwc3_trb *trb;
6b9018d4
FB		 859 struct dwc3 *dwc = dep->dwc;
860 struct usb_gadget *gadget = &dwc->gadget;
861 enum usb_device_speed speed = gadget->speed;
c71fc37c 862
4faf7550 863 trb = &dep->trb_pool[dep->trb_enqueue];
c71fc37c 864
eeb720fb 865 if (!req->trb) {
aa3342c8 866 dwc3_gadget_move_started_request(req);
f6bafc6a
FB		 867 req->trb = trb;
868 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
a9c3ca5f 869 dep->queued_requests++;
eeb720fb 870 }
c71fc37c 871
ef966b9d 872 dwc3_ep_inc_enq(dep);
e5ba5ec8 873
f6bafc6a
FB		 874 trb->size = DWC3_TRB_SIZE_LENGTH(length);
875 trb->bpl = lower_32_bits(dma);
876 trb->bph = upper_32_bits(dma);
c71fc37c 877
16e78db7 878 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 879 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 880 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 881 break;
882
883 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 884 if (!node) {
e5ba5ec8 885 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 886
887 if (speed == USB_SPEED_HIGH) {
888 struct usb_ep *ep = &dep->endpoint;
889 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
890 }
891 } else {
e5ba5ec8 892 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 893 }
ca4d44ea
FB		 894
895 /* always enable Interrupt on Missed ISOC */
896 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 897 break;
898
899 case USB_ENDPOINT_XFER_BULK:
900 case USB_ENDPOINT_XFER_INT:
f6bafc6a 901 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 902 break;
903 default:
904 /*
905 * This is only possible with faulty memory because we
906 * checked it already :)
907 */
0a695d4c
FB		 908 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
909 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 910 }
911
ca4d44ea 912 /* always enable Continue on Short Packet */
c9508c8c 913 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 914 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 915
c9508c8c
FB		 916 if (req->request.short_not_ok)
917 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
918 }
919
2c78c029
FB		 920 if ((!req->request.no_interrupt && !chain) ||
921 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 922 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 923
e5ba5ec8
PA		 924 if (chain)
925 trb->ctrl |= DWC3_TRB_CTRL_CHN;
926
16e78db7 927 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 928 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 929
f6bafc6a 930 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 931
932 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 933}
934
361572b5
JY		 935/**
936 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
937 * @dep: The endpoint with the TRB ring
938 * @index: The index of the current TRB in the ring
939 *
940 * Returns the TRB prior to the one pointed to by the index. If the
941 * index is 0, we will wrap backwards, skip the link TRB, and return
942 * the one just before that.
943 */
944static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
945{
45438a0c 946 u8 tmp = index;
361572b5 947
45438a0c
FB		 948 if (!tmp)
949 tmp = DWC3_TRB_NUM - 1;
361572b5 950
45438a0c 951 return &dep->trb_pool[tmp - 1];
361572b5
JY		 952}
953
c4233573
FB		 954static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
955{
956 struct dwc3_trb *tmp;
f2694a93 957 struct dwc3 *dwc = dep->dwc;
32db3d94 958 u8 trbs_left;
c4233573
FB		 959
960 /*
961 * If enqueue & dequeue are equal than it is either full or empty.
962 *
963 * One way to know for sure is if the TRB right before us has HWO bit
964 * set or not. If it has, then we're definitely full and can't fit any
965 * more transfers in our ring.
966 */
967 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 968 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
f2694a93
JD		 969 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
970 "%s No TRBS left\n", dep->name))
361572b5 971 return 0;
c4233573
FB		 972
973 return DWC3_TRB_NUM - 1;
974 }
975
9d7aba77 976 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 977 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 978
9d7aba77
JY		 979 if (dep->trb_dequeue < dep->trb_enqueue)
980 trbs_left--;
981
32db3d94 982 return trbs_left;
c4233573
FB		 983}
984
5ee85d89 985static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 986 struct dwc3_request *req)
5ee85d89 987{
1f512119 988 struct scatterlist *sg = req->sg;
5ee85d89 989 struct scatterlist *s;
5ee85d89
FB		 990 unsigned int length;
991 dma_addr_t dma;
992 int i;
993
1f512119 994 for_each_sg(sg, s, req->num_pending_sgs, i) {
5ee85d89
FB		 995 unsigned chain = true;
996
997 length = sg_dma_len(s);
998 dma = sg_dma_address(s);
999
4bc48c97 1000 if (sg_is_last(s))
5ee85d89
FB		 1001 chain = false;
1002
1003 dwc3_prepare_one_trb(dep, req, dma, length,
4bc48c97 1004 chain, i);
5ee85d89 1005
7ae7df49 1006 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1007 break;
1008 }
1009}
1010
1011static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1012 struct dwc3_request *req)
5ee85d89 1013{
5ee85d89
FB		 1014 unsigned int length;
1015 dma_addr_t dma;
1016
1017 dma = req->request.dma;
1018 length = req->request.length;
1019
5ee85d89 1020 dwc3_prepare_one_trb(dep, req, dma, length,
4bc48c97 1021 false, 0);
5ee85d89
FB		 1022}
1023
72246da4
FB		 1024/*
1025 * dwc3_prepare_trbs - setup TRBs from requests
1026 * @dep: endpoint for which requests are being prepared
72246da4 1027 *
1d046793
PZ		 1028 * The function goes through the requests list and sets up TRBs for the
1029 * transfers. The function returns once there are no more TRBs available or
1030 * it runs out of requests.
72246da4 1031 */
c4233573 1032static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1033{
68e823e2 1034 struct dwc3_request *req, *n;
72246da4
FB		 1035
1036 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1037
7ae7df49 1038 if (!dwc3_calc_trbs_left(dep))
89bc856e 1039 return;
72246da4 1040
d86c5a67
FB		 1041 /*
1042 * We can get in a situation where there's a request in the started list
1043 * but there weren't enough TRBs to fully kick it in the first time
1044 * around, so it has been waiting for more TRBs to be freed up.
1045 *
1046 * In that case, we should check if we have a request with pending_sgs
1047 * in the started list and prepare TRBs for that request first,
1048 * otherwise we will prepare TRBs completely out of order and that will
1049 * break things.
1050 */
1051 list_for_each_entry(req, &dep->started_list, list) {
1052 if (req->num_pending_sgs > 0)
1053 dwc3_prepare_one_trb_sg(dep, req);
1054
1055 if (!dwc3_calc_trbs_left(dep))
1056 return;
1057 }
1058
aa3342c8 1059 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1f512119 1060 if (req->num_pending_sgs > 0)
7ae7df49 1061 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1062 else
7ae7df49 1063 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1064
7ae7df49 1065 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1066 return;
72246da4 1067 }
72246da4
FB		 1068}
1069
4fae2e3e 1070static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1071{
1072 struct dwc3_gadget_ep_cmd_params params;
1073 struct dwc3_request *req;
4fae2e3e 1074 int starting;
72246da4
FB		 1075 int ret;
1076 u32 cmd;
1077
4fae2e3e 1078 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1079
4fae2e3e
FB		 1080 dwc3_prepare_trbs(dep);
1081 req = next_request(&dep->started_list);
72246da4
FB		 1082 if (!req) {
1083 dep->flags |= DWC3_EP_PENDING_REQUEST;
1084 return 0;
1085 }
1086
1087 memset(&params, 0, sizeof(params));
72246da4 1088
4fae2e3e 1089 if (starting) {
1877d6c9
PA		 1090 params.param0 = upper_32_bits(req->trb_dma);
1091 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1092 cmd = DWC3_DEPCMD_STARTTRANSFER |
1093 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1094 } else {
b6b1c6db
FB		 1095 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1096 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1097 }
72246da4 1098
2cd4718d 1099 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1100 if (ret < 0) {
72246da4
FB		 1101 /*
1102 * FIXME we need to iterate over the list of requests
1103 * here and stop, unmap, free and del each of the linked
1d046793 1104 * requests instead of what we do now.
72246da4 1105 */
ce3fc8b3
JD		 1106 if (req->trb)
1107 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1108 dep->queued_requests--;
15b8d933 1109 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1110 return ret;
1111 }
1112
1113 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1114
4fae2e3e 1115 if (starting) {
2eb88016 1116 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1117 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1118 }
25b8ff68 1119
72246da4
FB		 1120 return 0;
1121}
1122
6cb2e4e3
FB		 1123static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1124{
1125 u32 reg;
1126
1127 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1128 return DWC3_DSTS_SOFFN(reg);
1129}
1130
d6d6ec7b
PA		 1131static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1132 struct dwc3_ep *dep, u32 cur_uf)
1133{
1134 u32 uf;
1135
aa3342c8 1136 if (list_empty(&dep->pending_list)) {
5eb30ced 1137 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1138 dep->name);
f4a53c55 1139 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1140 return;
1141 }
1142
1143 /* 4 micro frames in the future */
1144 uf = cur_uf + dep->interval * 4;
1145
4fae2e3e 1146 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1147}
1148
1149static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1150 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1151{
1152 u32 cur_uf, mask;
1153
1154 mask = ~(dep->interval - 1);
1155 cur_uf = event->parameters & mask;
1156
1157 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1158}
1159
72246da4
FB		 1160static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1161{
0fc9a1be
FB		 1162 struct dwc3 *dwc = dep->dwc;
1163 int ret;
1164
bb423984 1165 if (!dep->endpoint.desc) {
5eb30ced
FB		 1166 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1167 dep->name);
bb423984
FB		 1168 return -ESHUTDOWN;
1169 }
1170
1171 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1172 &req->request, req->dep->name)) {
5eb30ced
FB		 1173 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1174 dep->name, &req->request, req->dep->name);
bb423984
FB		 1175 return -EINVAL;
1176 }
1177
fc8bb91b
FB		 1178 pm_runtime_get(dwc->dev);
1179
72246da4
FB		 1180 req->request.actual = 0;
1181 req->request.status = -EINPROGRESS;
1182 req->direction = dep->direction;
1183 req->epnum = dep->number;
1184
fe84f522
FB		 1185 trace_dwc3_ep_queue(req);
1186
d64ff406
AB		 1187 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1188 dep->direction);
0fc9a1be
FB		 1189 if (ret)
1190 return ret;
1191
1f512119
FB		 1192 req->sg = req->request.sg;
1193 req->num_pending_sgs = req->request.num_mapped_sgs;
89185916 1194
aa3342c8 1195 list_add_tail(&req->list, &dep->pending_list);
72246da4 1196
d889c23c
FB		 1197 /*
1198 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1199 * wait for a XferNotReady event so we will know what's the current
1200 * (micro-)frame number.
1201 *
1202 * Without this trick, we are very, very likely gonna get Bus Expiry
1203 * errors which will force us issue EndTransfer command.
1204 */
1205 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1206 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1207 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1208 dwc3_stop_active_transfer(dwc, dep->number, true);
1209 dep->flags = DWC3_EP_ENABLED;
1210 } else {
1211 u32 cur_uf;
1212
1213 cur_uf = __dwc3_gadget_get_frame(dwc);
1214 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1215 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1216 }
08a36b54
FB		 1217 }
1218 return 0;
a0925324 1219 }
72246da4 1220
594e121f
FB		 1221 if (!dwc3_calc_trbs_left(dep))
1222 return 0;
b997ada5 1223
08a36b54 1224 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817
FB		 1225 if (ret == -EBUSY)
1226 ret = 0;
1227
1228 return ret;
72246da4
FB		 1229}
1230
04c03d10
FB		 1231static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1232 struct usb_request *request)
1233{
1234 dwc3_gadget_ep_free_request(ep, request);
1235}
1236
1237static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1238{
1239 struct dwc3_request *req;
1240 struct usb_request *request;
1241 struct usb_ep *ep = &dep->endpoint;
1242
04c03d10
FB		 1243 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1244 if (!request)
1245 return -ENOMEM;
1246
1247 request->length = 0;
1248 request->buf = dwc->zlp_buf;
1249 request->complete = __dwc3_gadget_ep_zlp_complete;
1250
1251 req = to_dwc3_request(request);
1252
1253 return __dwc3_gadget_ep_queue(dep, req);
1254}
1255
72246da4
FB		 1256static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1257 gfp_t gfp_flags)
1258{
1259 struct dwc3_request *req = to_dwc3_request(request);
1260 struct dwc3_ep *dep = to_dwc3_ep(ep);
1261 struct dwc3 *dwc = dep->dwc;
1262
1263 unsigned long flags;
1264
1265 int ret;
1266
fdee4eba 1267 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1268 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1269
1270 /*
1271 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1272 * setting request->zero, instead of doing magic, we will just queue an
1273 * extra usb_request ourselves so that it gets handled the same way as
1274 * any other request.
1275 */
d9261898
JY		 1276 if (ret == 0 && request->zero && request->length &&
1277 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1278 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1279
72246da4
FB		 1280 spin_unlock_irqrestore(&dwc->lock, flags);
1281
1282 return ret;
1283}
1284
1285static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1286 struct usb_request *request)
1287{
1288 struct dwc3_request *req = to_dwc3_request(request);
1289 struct dwc3_request *r = NULL;
1290
1291 struct dwc3_ep *dep = to_dwc3_ep(ep);
1292 struct dwc3 *dwc = dep->dwc;
1293
1294 unsigned long flags;
1295 int ret = 0;
1296
2c4cbe6e
FB		 1297 trace_dwc3_ep_dequeue(req);
1298
72246da4
FB		 1299 spin_lock_irqsave(&dwc->lock, flags);
1300
aa3342c8 1301 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1302 if (r == req)
1303 break;
1304 }
1305
1306 if (r != req) {
aa3342c8 1307 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1308 if (r == req)
1309 break;
1310 }
1311 if (r == req) {
1312 /* wait until it is processed */
b992e681 1313 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1314 goto out1;
72246da4
FB		 1315 }
1316 dev_err(dwc->dev, "request %p was not queued to %s\n",
1317 request, ep->name);
1318 ret = -EINVAL;
1319 goto out0;
1320 }
1321
e8d4e8be 1322out1:
72246da4
FB		 1323 /* giveback the request */
1324 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1325
1326out0:
1327 spin_unlock_irqrestore(&dwc->lock, flags);
1328
1329 return ret;
1330}
1331
7a608559 1332int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1333{
1334 struct dwc3_gadget_ep_cmd_params params;
1335 struct dwc3 *dwc = dep->dwc;
1336 int ret;
1337
5ad02fb8
FB		 1338 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1339 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1340 return -EINVAL;
1341 }
1342
72246da4
FB		 1343 memset(&params, 0x00, sizeof(params));
1344
1345 if (value) {
69450c4d
FB		 1346 struct dwc3_trb *trb;
1347
1348 unsigned transfer_in_flight;
1349 unsigned started;
1350
1a28cfe3
FB		 1351 if (dep->flags & DWC3_EP_STALL)
1352 return 0;
1353
69450c4d
FB		 1354 if (dep->number > 1)
1355 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1356 else
1357 trb = &dwc->ep0_trb[dep->trb_enqueue];
1358
1359 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1360 started = !list_empty(&dep->started_list);
1361
1362 if (!protocol && ((dep->direction && transfer_in_flight) ||
1363 (!dep->direction && started))) {
7a608559
FB		 1364 return -EAGAIN;
1365 }
1366
2cd4718d
FB		 1367 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1368 &params);
72246da4 1369 if (ret)
3f89204b 1370 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1371 dep->name);
1372 else
1373 dep->flags |= DWC3_EP_STALL;
1374 } else {
1a28cfe3
FB		 1375 if (!(dep->flags & DWC3_EP_STALL))
1376 return 0;
2cd4718d 1377
50c763f8 1378 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1379 if (ret)
3f89204b 1380 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1381 dep->name);
1382 else
a535d81c 1383 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1384 }
5275455a 1385
72246da4
FB		 1386 return ret;
1387}
1388
1389static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1390{
1391 struct dwc3_ep *dep = to_dwc3_ep(ep);
1392 struct dwc3 *dwc = dep->dwc;
1393
1394 unsigned long flags;
1395
1396 int ret;
1397
1398 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1399 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1400 spin_unlock_irqrestore(&dwc->lock, flags);
1401
1402 return ret;
1403}
1404
1405static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1406{
1407 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1408 struct dwc3 *dwc = dep->dwc;
1409 unsigned long flags;
95aa4e8d 1410 int ret;
72246da4 1411
249a4569 1412 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1413 dep->flags |= DWC3_EP_WEDGE;
1414
08f0d966 1415 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1416 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1417 else
7a608559 1418 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1419 spin_unlock_irqrestore(&dwc->lock, flags);
1420
1421 return ret;
72246da4
FB		 1422}
1423
1424/* -------------------------------------------------------------------------- */
1425
1426static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1427 .bLength = USB_DT_ENDPOINT_SIZE,
1428 .bDescriptorType = USB_DT_ENDPOINT,
1429 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1430};
1431
1432static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1433 .enable = dwc3_gadget_ep0_enable,
1434 .disable = dwc3_gadget_ep0_disable,
1435 .alloc_request = dwc3_gadget_ep_alloc_request,
1436 .free_request = dwc3_gadget_ep_free_request,
1437 .queue = dwc3_gadget_ep0_queue,
1438 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1439 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1440 .set_wedge = dwc3_gadget_ep_set_wedge,
1441};
1442
1443static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1444 .enable = dwc3_gadget_ep_enable,
1445 .disable = dwc3_gadget_ep_disable,
1446 .alloc_request = dwc3_gadget_ep_alloc_request,
1447 .free_request = dwc3_gadget_ep_free_request,
1448 .queue = dwc3_gadget_ep_queue,
1449 .dequeue = dwc3_gadget_ep_dequeue,
1450 .set_halt = dwc3_gadget_ep_set_halt,
1451 .set_wedge = dwc3_gadget_ep_set_wedge,
1452};
1453
1454/* -------------------------------------------------------------------------- */
1455
1456static int dwc3_gadget_get_frame(struct usb_gadget *g)
1457{
1458 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1459
6cb2e4e3 1460 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1461}
1462
218ef7b6 1463static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1464{
d6011f6f 1465 int retries;
72246da4 1466
218ef7b6 1467 int ret;
72246da4
FB		 1468 u32 reg;
1469
72246da4
FB		 1470 u8 link_state;
1471 u8 speed;
1472
72246da4
FB		 1473 /*
1474 * According to the Databook Remote wakeup request should
1475 * be issued only when the device is in early suspend state.
1476 *
1477 * We can check that via USB Link State bits in DSTS register.
1478 */
1479 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1480
1481 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1482 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1483 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1484 return 0;
72246da4
FB		 1485
1486 link_state = DWC3_DSTS_USBLNKST(reg);
1487
1488 switch (link_state) {
1489 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1490 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1491 break;
1492 default:
218ef7b6 1493 return -EINVAL;
72246da4
FB		 1494 }
1495
8598bde7
FB		 1496 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1497 if (ret < 0) {
1498 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1499 return ret;
8598bde7 1500 }
72246da4 1501
802fde98
PZ		 1502 /* Recent versions do this automatically */
1503 if (dwc->revision < DWC3_REVISION_194A) {
1504 /* write zeroes to Link Change Request */
fcc023c7 1505 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1506 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1507 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1508 }
72246da4 1509
1d046793 1510 /* poll until Link State changes to ON */
d6011f6f 1511 retries = 20000;
72246da4 1512
d6011f6f 1513 while (retries--) {
72246da4
FB		 1514 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1515
1516 /* in HS, means ON */
1517 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1518 break;
1519 }
1520
1521 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1522 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1523 return -EINVAL;
72246da4
FB		 1524 }
1525
218ef7b6
FB		 1526 return 0;
1527}
1528
1529static int dwc3_gadget_wakeup(struct usb_gadget *g)
1530{
1531 struct dwc3 *dwc = gadget_to_dwc(g);
1532 unsigned long flags;
1533 int ret;
1534
1535 spin_lock_irqsave(&dwc->lock, flags);
1536 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1537 spin_unlock_irqrestore(&dwc->lock, flags);
1538
1539 return ret;
1540}
1541
1542static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1543 int is_selfpowered)
1544{
1545 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1546 unsigned long flags;
72246da4 1547
249a4569 1548 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1549 g->is_selfpowered = !!is_selfpowered;
249a4569 1550 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1551
1552 return 0;
1553}
1554
7b2a0368 1555static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1556{
1557 u32 reg;
61d58242 1558 u32 timeout = 500;
72246da4 1559
fc8bb91b
FB		 1560 if (pm_runtime_suspended(dwc->dev))
1561 return 0;
1562
72246da4 1563 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1564 if (is_on) {
802fde98
PZ		 1565 if (dwc->revision <= DWC3_REVISION_187A) {
1566 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1567 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1568 }
1569
1570 if (dwc->revision >= DWC3_REVISION_194A)
1571 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1572 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1573
1574 if (dwc->has_hibernation)
1575 reg |= DWC3_DCTL_KEEP_CONNECT;
1576
9fcb3bd8 1577 dwc->pullups_connected = true;
8db7ed15 1578 } else {
72246da4 1579 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1580
1581 if (dwc->has_hibernation && !suspend)
1582 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1583
9fcb3bd8 1584 dwc->pullups_connected = false;
8db7ed15 1585 }
72246da4
FB		 1586
1587 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1588
1589 do {
1590 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1591 reg &= DWC3_DSTS_DEVCTRLHLT;
1592 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1593
1594 if (!timeout)
1595 return -ETIMEDOUT;
72246da4 1596
6f17f74b 1597 return 0;
72246da4
FB		 1598}
1599
1600static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1601{
1602 struct dwc3 *dwc = gadget_to_dwc(g);
1603 unsigned long flags;
6f17f74b 1604 int ret;
72246da4
FB		 1605
1606 is_on = !!is_on;
1607
bb014736
BW		 1608 /*
1609 * Per databook, when we want to stop the gadget, if a control transfer
1610 * is still in process, complete it and get the core into setup phase.
1611 */
1612 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1613 reinit_completion(&dwc->ep0_in_setup);
1614
1615 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1616 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1617 if (ret == 0) {
1618 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1619 return -ETIMEDOUT;
1620 }
1621 }
1622
72246da4 1623 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1624 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1625 spin_unlock_irqrestore(&dwc->lock, flags);
1626
6f17f74b 1627 return ret;
72246da4
FB		 1628}
1629
8698e2ac
FB		 1630static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1631{
1632 u32 reg;
1633
1634 /* Enable all but Start and End of Frame IRQs */
1635 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1636 DWC3_DEVTEN_EVNTOVERFLOWEN |
1637 DWC3_DEVTEN_CMDCMPLTEN |
1638 DWC3_DEVTEN_ERRTICERREN |
1639 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1640 DWC3_DEVTEN_CONNECTDONEEN |
1641 DWC3_DEVTEN_USBRSTEN |
1642 DWC3_DEVTEN_DISCONNEVTEN);
1643
799e9dc8
FB		 1644 if (dwc->revision < DWC3_REVISION_250A)
1645 reg |= DWC3_DEVTEN_ULSTCNGEN;
1646
8698e2ac
FB		 1647 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1648}
1649
1650static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1651{
1652 /* mask all interrupts */
1653 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1654}
1655
1656static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1657static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1658
4e99472b
FB		 1659/**
1660 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1661 * dwc: pointer to our context structure
1662 *
1663 * The following looks like complex but it's actually very simple. In order to
1664 * calculate the number of packets we can burst at once on OUT transfers, we're
1665 * gonna use RxFIFO size.
1666 *
1667 * To calculate RxFIFO size we need two numbers:
1668 * MDWIDTH = size, in bits, of the internal memory bus
1669 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1670 *
1671 * Given these two numbers, the formula is simple:
1672 *
1673 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1674 *
1675 * 24 bytes is for 3x SETUP packets
1676 * 16 bytes is a clock domain crossing tolerance
1677 *
1678 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1679 */
1680static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1681{
1682 u32 ram2_depth;
1683 u32 mdwidth;
1684 u32 nump;
1685 u32 reg;
1686
1687 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1688 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1689
1690 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1691 nump = min_t(u32, nump, 16);
1692
1693 /* update NumP */
1694 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1695 reg &= ~DWC3_DCFG_NUMP_MASK;
1696 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1697 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1698}
1699
d7be2952 1700static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1701{
72246da4 1702 struct dwc3_ep *dep;
72246da4
FB		 1703 int ret = 0;
1704 u32 reg;
1705
cf40b86b
JY		 1706 /*
1707 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1708 * the core supports IMOD, disable it.
1709 */
1710 if (dwc->imod_interval) {
1711 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1712 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1713 } else if (dwc3_has_imod(dwc)) {
1714 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1715 }
1716
72246da4
FB		 1717 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1718 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1719
1720 /**
1721 * WORKAROUND: DWC3 revision < 2.20a have an issue
1722 * which would cause metastability state on Run/Stop
1723 * bit if we try to force the IP to USB2-only mode.
1724 *
1725 * Because of that, we cannot configure the IP to any
1726 * speed other than the SuperSpeed
1727 *
1728 * Refers to:
1729 *
1730 * STAR#9000525659: Clock Domain Crossing on DCTL in
1731 * USB 2.0 Mode
1732 */
f7e846f0 1733 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1734 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1735 } else {
1736 switch (dwc->maximum_speed) {
1737 case USB_SPEED_LOW:
2da9ad76 1738 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1739 break;
1740 case USB_SPEED_FULL:
9418ee15 1741 reg |= DWC3_DCFG_FULLSPEED;
f7e846f0
FB		 1742 break;
1743 case USB_SPEED_HIGH:
2da9ad76 1744 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1745 break;
7580862b 1746 case USB_SPEED_SUPER_PLUS:
2da9ad76 1747 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1748 break;
f7e846f0 1749 default:
77966eb8
JY		 1750 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1751 dwc->maximum_speed);
1752 /* fall through */
1753 case USB_SPEED_SUPER:
1754 reg |= DWC3_DCFG_SUPERSPEED;
1755 break;
f7e846f0
FB		 1756 }
1757 }
72246da4
FB		 1758 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1759
2a58f9c1
FB		 1760 /*
1761 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1762 * field instead of letting dwc3 itself calculate that automatically.
1763 *
1764 * This way, we maximize the chances that we'll be able to get several
1765 * bursts of data without going through any sort of endpoint throttling.
1766 */
1767 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1768 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1769 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1770
4e99472b
FB		 1771 dwc3_gadget_setup_nump(dwc);
1772
72246da4
FB		 1773 /* Start with SuperSpeed Default */
1774 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1775
1776 dep = dwc->eps[0];
39ebb05c 1777 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1778 if (ret) {
1779 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1780 goto err0;
72246da4
FB		 1781 }
1782
1783 dep = dwc->eps[1];
39ebb05c 1784 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1785 if (ret) {
1786 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1787 goto err1;
72246da4
FB		 1788 }
1789
1790 /* begin to receive SETUP packets */
c7fcdeb2 1791 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1792 dwc3_ep0_out_start(dwc);
1793
8698e2ac
FB		 1794 dwc3_gadget_enable_irq(dwc);
1795
72246da4
FB		 1796 return 0;
1797
b0d7ffd4 1798err1:
d7be2952 1799 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1800
1801err0:
72246da4
FB		 1802 return ret;
1803}
1804
d7be2952
FB		 1805static int dwc3_gadget_start(struct usb_gadget *g,
1806 struct usb_gadget_driver *driver)
72246da4
FB		 1807{
1808 struct dwc3 *dwc = gadget_to_dwc(g);
1809 unsigned long flags;
d7be2952 1810 int ret = 0;
8698e2ac 1811 int irq;
72246da4 1812
9522def4 1813 irq = dwc->irq_gadget;
d7be2952
FB		 1814 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1815 IRQF_SHARED, "dwc3", dwc->ev_buf);
1816 if (ret) {
1817 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1818 irq, ret);
1819 goto err0;
1820 }
1821
72246da4 1822 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1823 if (dwc->gadget_driver) {
1824 dev_err(dwc->dev, "%s is already bound to %s\n",
1825 dwc->gadget.name,
1826 dwc->gadget_driver->driver.name);
1827 ret = -EBUSY;
1828 goto err1;
1829 }
1830
1831 dwc->gadget_driver = driver;
1832
fc8bb91b
FB		 1833 if (pm_runtime_active(dwc->dev))
1834 __dwc3_gadget_start(dwc);
1835
d7be2952
FB		 1836 spin_unlock_irqrestore(&dwc->lock, flags);
1837
1838 return 0;
1839
1840err1:
1841 spin_unlock_irqrestore(&dwc->lock, flags);
1842 free_irq(irq, dwc);
1843
1844err0:
1845 return ret;
1846}
72246da4 1847
d7be2952
FB		 1848static void __dwc3_gadget_stop(struct dwc3 *dwc)
1849{
8698e2ac 1850 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1851 __dwc3_gadget_ep_disable(dwc->eps[0]);
1852 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1853}
72246da4 1854
d7be2952
FB		 1855static int dwc3_gadget_stop(struct usb_gadget *g)
1856{
1857 struct dwc3 *dwc = gadget_to_dwc(g);
1858 unsigned long flags;
76a638f8 1859 int epnum;
72246da4 1860
d7be2952 1861 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1862
1863 if (pm_runtime_suspended(dwc->dev))
1864 goto out;
1865
d7be2952 1866 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1867
1868 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1869 struct dwc3_ep *dep = dwc->eps[epnum];
1870
1871 if (!dep)
1872 continue;
1873
1874 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1875 continue;
1876
1877 wait_event_lock_irq(dep->wait_end_transfer,
1878 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1879 dwc->lock);
1880 }
1881
1882out:
d7be2952 1883 dwc->gadget_driver = NULL;
72246da4
FB		 1884 spin_unlock_irqrestore(&dwc->lock, flags);
1885
3f308d17 1886 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1887
72246da4
FB		 1888 return 0;
1889}
802fde98 1890
72246da4
FB		 1891static const struct usb_gadget_ops dwc3_gadget_ops = {
1892 .get_frame = dwc3_gadget_get_frame,
1893 .wakeup = dwc3_gadget_wakeup,
1894 .set_selfpowered = dwc3_gadget_set_selfpowered,
1895 .pullup = dwc3_gadget_pullup,
1896 .udc_start = dwc3_gadget_start,
1897 .udc_stop = dwc3_gadget_stop,
1898};
1899
1900/* -------------------------------------------------------------------------- */
1901
6a1e3ef4
FB		 1902static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1903 u8 num, u32 direction)
72246da4
FB		 1904{
1905 struct dwc3_ep *dep;
6a1e3ef4 1906 u8 i;
72246da4 1907
6a1e3ef4 1908 for (i = 0; i < num; i++) {
d07fa665 1909 u8 epnum = (i << 1) | (direction ? 1 : 0);
72246da4 1910
72246da4 1911 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1912 if (!dep)
72246da4 1913 return -ENOMEM;
72246da4
FB		 1914
1915 dep->dwc = dwc;
1916 dep->number = epnum;
9aa62ae4 1917 dep->direction = !!direction;
2eb88016 1918 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 1919 dwc->eps[epnum] = dep;
1920
1921 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1922 (epnum & 1) ? "in" : "out");
6a1e3ef4 1923
72246da4 1924 dep->endpoint.name = dep->name;
39ebb05c
JY		 1925
1926 if (!(dep->number > 1)) {
1927 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
1928 dep->endpoint.comp_desc = NULL;
1929 }
1930
74674cbf 1931 spin_lock_init(&dep->lock);
72246da4
FB		 1932
1933 if (epnum == 0 || epnum == 1) {
e117e742 1934 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1935 dep->endpoint.maxburst = 1;
72246da4
FB		 1936 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1937 if (!epnum)
1938 dwc->gadget.ep0 = &dep->endpoint;
1939 } else {
1940 int ret;
1941
e117e742 1942 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1943 dep->endpoint.max_streams = 15;
72246da4
FB		 1944 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1945 list_add_tail(&dep->endpoint.ep_list,
1946 &dwc->gadget.ep_list);
1947
1948 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1949 if (ret)
72246da4 1950 return ret;
72246da4 1951 }
25b8ff68 1952
a474d3b7
RB		 1953 if (epnum == 0 || epnum == 1) {
1954 dep->endpoint.caps.type_control = true;
1955 } else {
1956 dep->endpoint.caps.type_iso = true;
1957 dep->endpoint.caps.type_bulk = true;
1958 dep->endpoint.caps.type_int = true;
1959 }
1960
1961 dep->endpoint.caps.dir_in = !!direction;
1962 dep->endpoint.caps.dir_out = !direction;
1963
aa3342c8
FB		 1964 INIT_LIST_HEAD(&dep->pending_list);
1965 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 1966 }
1967
1968 return 0;
1969}
1970
6a1e3ef4
FB		 1971static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1972{
1973 int ret;
1974
1975 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1976
1977 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1978 if (ret < 0) {
5eb30ced 1979 dev_err(dwc->dev, "failed to initialize OUT endpoints\n");
6a1e3ef4
FB		 1980 return ret;
1981 }
1982
1983 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1984 if (ret < 0) {
5eb30ced 1985 dev_err(dwc->dev, "failed to initialize IN endpoints\n");
6a1e3ef4
FB		 1986 return ret;
1987 }
1988
1989 return 0;
1990}
1991
72246da4
FB		 1992static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1993{
1994 struct dwc3_ep *dep;
1995 u8 epnum;
1996
1997 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1998 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1999 if (!dep)
2000 continue;
5bf8fae3
GC		 2001 /*
2002 * Physical endpoints 0 and 1 are special; they form the
2003 * bi-directional USB endpoint 0.
2004 *
2005 * For those two physical endpoints, we don't allocate a TRB
2006 * pool nor do we add them the endpoints list. Due to that, we
2007 * shouldn't do these two operations otherwise we would end up
2008 * with all sorts of bugs when removing dwc3.ko.
2009 */
2010 if (epnum != 0 && epnum != 1) {
2011 dwc3_free_trb_pool(dep);
72246da4 2012 list_del(&dep->endpoint.ep_list);
5bf8fae3 2013 }
72246da4
FB		 2014
2015 kfree(dep);
2016 }
2017}
2018
72246da4 2019/* -------------------------------------------------------------------------- */
e5caff68 2020
e5ba5ec8
PA		 2021static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2022 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2023 const struct dwc3_event_depevt *event, int status,
2024 int chain)
72246da4 2025{
72246da4
FB		 2026 unsigned int count;
2027 unsigned int s_pkt = 0;
d6d6ec7b 2028 unsigned int trb_status;
72246da4 2029
dc55c67e 2030 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2031
2032 if (req->trb == trb)
2033 dep->queued_requests--;
2034
2c4cbe6e
FB		 2035 trace_dwc3_complete_trb(dep, trb);
2036
e5b36ae2
FB		 2037 /*
2038 * If we're in the middle of series of chained TRBs and we
2039 * receive a short transfer along the way, DWC3 will skip
2040 * through all TRBs including the last TRB in the chain (the
2041 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2042 * bit and SW has to do it manually.
2043 *
2044 * We're going to do that here to avoid problems of HW trying
2045 * to use bogus TRBs for transfers.
2046 */
2047 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2048 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2049
e5ba5ec8 2050 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
a0ad85ae 2051 return 1;
e5b36ae2 2052
e5ba5ec8 2053 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2054 req->remaining += count;
e5ba5ec8
PA		 2055
2056 if (dep->direction) {
2057 if (count) {
2058 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2059 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2060 /*
2061 * If missed isoc occurred and there is
2062 * no request queued then issue END
2063 * TRANSFER, so that core generates
2064 * next xfernotready and we will issue
2065 * a fresh START TRANSFER.
2066 * If there are still queued request
2067 * then wait, do not issue either END
2068 * or UPDATE TRANSFER, just attach next
aa3342c8 2069 * request in pending_list during
e5ba5ec8
PA		 2070 * giveback.If any future queued request
2071 * is successfully transferred then we
2072 * will issue UPDATE TRANSFER for all
aa3342c8 2073 * request in the pending_list.
e5ba5ec8
PA		 2074 */
2075 dep->flags |= DWC3_EP_MISSED_ISOC;
2076 } else {
2077 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2078 dep->name);
2079 status = -ECONNRESET;
2080 }
2081 } else {
2082 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2083 }
2084 } else {
2085 if (count && (event->status & DEPEVT_STATUS_SHORT))
2086 s_pkt = 1;
2087 }
2088
7c705dfe 2089 if (s_pkt && !chain)
e5ba5ec8 2090 return 1;
f99f53f2 2091
e5ba5ec8
PA		 2092 if ((event->status & DEPEVT_STATUS_IOC) &&
2093 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2094 return 1;
f99f53f2 2095
e5ba5ec8
PA		 2096 return 0;
2097}
2098
2099static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2100 const struct dwc3_event_depevt *event, int status)
2101{
31162af4 2102 struct dwc3_request *req, *n;
e5ba5ec8 2103 struct dwc3_trb *trb;
d6e10bf2 2104 bool ioc = false;
e62c5bc5 2105 int ret = 0;
e5ba5ec8 2106
31162af4 2107 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2108 unsigned length;
e5b36ae2
FB		 2109 int chain;
2110
1f512119
FB		 2111 length = req->request.length;
2112 chain = req->num_pending_sgs > 0;
31162af4 2113 if (chain) {
1f512119 2114 struct scatterlist *sg = req->sg;
31162af4 2115 struct scatterlist *s;
1f512119 2116 unsigned int pending = req->num_pending_sgs;
31162af4 2117 unsigned int i;
c7de5734 2118
1f512119 2119 for_each_sg(sg, s, pending, i) {
31162af4 2120 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2121
7282c4ef
FB		 2122 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2123 break;
2124
1f512119
FB		 2125 req->sg = sg_next(s);
2126 req->num_pending_sgs--;
2127
31162af4
FB		 2128 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2129 event, status, chain);
1f512119
FB		 2130 if (ret)
2131 break;
31162af4
FB		 2132 }
2133 } else {
737f1ae2 2134 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2135 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2136 event, status, chain);
31162af4 2137 }
d115d705 2138
e62c5bc5 2139 req->request.actual = length - req->remaining;
1f512119 2140
ff377ae4 2141 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2142 return __dwc3_gadget_kick_transfer(dep, 0);
2143
d115d705 2144 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2145
d6e10bf2
AB		 2146 if (ret) {
2147 if ((event->status & DEPEVT_STATUS_IOC) &&
2148 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2149 ioc = true;
72246da4 2150 break;
d6e10bf2 2151 }
31162af4 2152 }
72246da4 2153
4cb42217
FB		 2154 /*
2155 * Our endpoint might get disabled by another thread during
2156 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2157 * early on so DWC3_EP_BUSY flag gets cleared
2158 */
2159 if (!dep->endpoint.desc)
2160 return 1;
2161
cdc359dd 2162 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2163 list_empty(&dep->started_list)) {
2164 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2165 /*
2166 * If there is no entry in request list then do
2167 * not issue END TRANSFER now. Just set PENDING
2168 * flag, so that END TRANSFER is issued when an
2169 * entry is added into request list.
2170 */
2171 dep->flags = DWC3_EP_PENDING_REQUEST;
2172 } else {
b992e681 2173 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2174 dep->flags = DWC3_EP_ENABLED;
2175 }
7efea86c
PA		 2176 return 1;
2177 }
2178
d6e10bf2
AB		 2179 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2180 return 0;
2181
72246da4
FB		 2182 return 1;
2183}
2184
2185static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2186 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2187{
2188 unsigned status = 0;
2189 int clean_busy;
e18b7975
FB		 2190 u32 is_xfer_complete;
2191
2192 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2193
2194 if (event->status & DEPEVT_STATUS_BUSERR)
2195 status = -ECONNRESET;
2196
1d046793 2197 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2198 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2199 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2200 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2201
2202 /*
2203 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2204 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2205 */
2206 if (dwc->revision < DWC3_REVISION_183A) {
2207 u32 reg;
2208 int i;
2209
2210 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2211 dep = dwc->eps[i];
fae2b904
FB		 2212
2213 if (!(dep->flags & DWC3_EP_ENABLED))
2214 continue;
2215
aa3342c8 2216 if (!list_empty(&dep->started_list))
fae2b904
FB		 2217 return;
2218 }
2219
2220 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2221 reg |= dwc->u1u2;
2222 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2223
2224 dwc->u1u2 = 0;
2225 }
8a1a9c9e 2226
4cb42217
FB		 2227 /*
2228 * Our endpoint might get disabled by another thread during
2229 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2230 * early on so DWC3_EP_BUSY flag gets cleared
2231 */
2232 if (!dep->endpoint.desc)
2233 return;
2234
e6e709b7 2235 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2236 int ret;
2237
4fae2e3e 2238 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2239 if (!ret || ret == -EBUSY)
2240 return;
2241 }
72246da4
FB		 2242}
2243
72246da4
FB		 2244static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2245 const struct dwc3_event_depevt *event)
2246{
2247 struct dwc3_ep *dep;
2248 u8 epnum = event->endpoint_number;
76a638f8 2249 u8 cmd;
72246da4
FB		 2250
2251 dep = dwc->eps[epnum];
2252
d7fd41c6
JD		 2253 if (!(dep->flags & DWC3_EP_ENABLED)) {
2254 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2255 return;
2256
2257 /* Handle only EPCMDCMPLT when EP disabled */
2258 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2259 return;
2260 }
3336abb5 2261
72246da4
FB		 2262 if (epnum == 0 || epnum == 1) {
2263 dwc3_ep0_interrupt(dwc, event);
2264 return;
2265 }
2266
2267 switch (event->endpoint_event) {
2268 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2269 dep->resource_index = 0;
c2df85ca 2270
16e78db7 2271 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2272 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2273 return;
2274 }
2275
029d97ff 2276 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2277 break;
2278 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2279 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2280 break;
2281 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2282 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2283 dwc3_gadget_start_isoc(dwc, dep, event);
2284 } else {
2285 int ret;
2286
4fae2e3e 2287 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2288 if (!ret || ret == -EBUSY)
2289 return;
72246da4
FB		 2290 }
2291
879631aa
FB		 2292 break;
2293 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2294 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2295 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2296 dep->name);
2297 return;
2298 }
72246da4 2299 break;
72246da4 2300 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2301 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2302
2303 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2304 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2305 wake_up(&dep->wait_end_transfer);
2306 }
2307 break;
2308 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2309 break;
2310 }
2311}
2312
2313static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2314{
2315 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2316 spin_unlock(&dwc->lock);
2317 dwc->gadget_driver->disconnect(&dwc->gadget);
2318 spin_lock(&dwc->lock);
2319 }
2320}
2321
bc5ba2e0
FB		 2322static void dwc3_suspend_gadget(struct dwc3 *dwc)
2323{
73a30bfc 2324 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2325 spin_unlock(&dwc->lock);
2326 dwc->gadget_driver->suspend(&dwc->gadget);
2327 spin_lock(&dwc->lock);
2328 }
2329}
2330
2331static void dwc3_resume_gadget(struct dwc3 *dwc)
2332{
73a30bfc 2333 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2334 spin_unlock(&dwc->lock);
2335 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2336 spin_lock(&dwc->lock);
8e74475b
FB		 2337 }
2338}
2339
2340static void dwc3_reset_gadget(struct dwc3 *dwc)
2341{
2342 if (!dwc->gadget_driver)
2343 return;
2344
2345 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2346 spin_unlock(&dwc->lock);
2347 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2348 spin_lock(&dwc->lock);
2349 }
2350}
2351
b992e681 2352static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2353{
2354 struct dwc3_ep *dep;
2355 struct dwc3_gadget_ep_cmd_params params;
2356 u32 cmd;
2357 int ret;
2358
2359 dep = dwc->eps[epnum];
2360
76a638f8
BW		 2361 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2362 !dep->resource_index)
3daf74d7
PA		 2363 return;
2364
57911504
PA		 2365 /*
2366 * NOTICE: We are violating what the Databook says about the
2367 * EndTransfer command. Ideally we would _always_ wait for the
2368 * EndTransfer Command Completion IRQ, but that's causing too
2369 * much trouble synchronizing between us and gadget driver.
2370 *
2371 * We have discussed this with the IP Provider and it was
2372 * suggested to giveback all requests here, but give HW some
2373 * extra time to synchronize with the interconnect. We're using
dc93b41a 2374 * an arbitrary 100us delay for that.
57911504
PA		 2375 *
2376 * Note also that a similar handling was tested by Synopsys
2377 * (thanks a lot Paul) and nothing bad has come out of it.
2378 * In short, what we're doing is:
2379 *
2380 * - Issue EndTransfer WITH CMDIOC bit set
2381 * - Wait 100us
06281d46
JY		 2382 *
2383 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2384 * supports a mode to work around the above limitation. The
2385 * software can poll the CMDACT bit in the DEPCMD register
2386 * after issuing a EndTransfer command. This mode is enabled
2387 * by writing GUCTL2[14]. This polling is already done in the
2388 * dwc3_send_gadget_ep_cmd() function so if the mode is
2389 * enabled, the EndTransfer command will have completed upon
2390 * returning from this function and we don't need to delay for
2391 * 100us.
2392 *
2393 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2394 */
2395
3daf74d7 2396 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2397 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2398 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2399 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2400 memset(&params, 0, sizeof(params));
2cd4718d 2401 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2402 WARN_ON_ONCE(ret);
b4996a86 2403 dep->resource_index = 0;
041d81f4 2404 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2405
76a638f8
BW		 2406 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2407 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2408 udelay(100);
76a638f8 2409 }
72246da4
FB		 2410}
2411
72246da4
FB		 2412static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2413{
2414 u32 epnum;
2415
2416 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2417 struct dwc3_ep *dep;
72246da4
FB		 2418 int ret;
2419
2420 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2421 if (!dep)
2422 continue;
72246da4
FB		 2423
2424 if (!(dep->flags & DWC3_EP_STALL))
2425 continue;
2426
2427 dep->flags &= ~DWC3_EP_STALL;
2428
50c763f8 2429 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2430 WARN_ON_ONCE(ret);
2431 }
2432}
2433
2434static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2435{
c4430a26
FB		 2436 int reg;
2437
72246da4
FB		 2438 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2439 reg &= ~DWC3_DCTL_INITU1ENA;
2440 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2441
2442 reg &= ~DWC3_DCTL_INITU2ENA;
2443 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2444
72246da4
FB		 2445 dwc3_disconnect_gadget(dwc);
2446
2447 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2448 dwc->setup_packet_pending = false;
06a374ed 2449 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2450
2451 dwc->connected = false;
72246da4
FB		 2452}
2453
72246da4
FB		 2454static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2455{
2456 u32 reg;
2457
fc8bb91b
FB		 2458 dwc->connected = true;
2459
df62df56
FB		 2460 /*
2461 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2462 * would cause a missing Disconnect Event if there's a
2463 * pending Setup Packet in the FIFO.
2464 *
2465 * There's no suggested workaround on the official Bug
2466 * report, which states that "unless the driver/application
2467 * is doing any special handling of a disconnect event,
2468 * there is no functional issue".
2469 *
2470 * Unfortunately, it turns out that we _do_ some special
2471 * handling of a disconnect event, namely complete all
2472 * pending transfers, notify gadget driver of the
2473 * disconnection, and so on.
2474 *
2475 * Our suggested workaround is to follow the Disconnect
2476 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2477 * flag. Such flag gets set whenever we have a SETUP_PENDING
2478 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2479 * same endpoint.
2480 *
2481 * Refers to:
2482 *
2483 * STAR#9000466709: RTL: Device : Disconnect event not
2484 * generated if setup packet pending in FIFO
2485 */
2486 if (dwc->revision < DWC3_REVISION_188A) {
2487 if (dwc->setup_packet_pending)
2488 dwc3_gadget_disconnect_interrupt(dwc);
2489 }
2490
8e74475b 2491 dwc3_reset_gadget(dwc);
72246da4
FB		 2492
2493 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2494 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2495 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2496 dwc->test_mode = false;
72246da4
FB		 2497 dwc3_clear_stall_all_ep(dwc);
2498
2499 /* Reset device address to zero */
2500 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2501 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2502 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2503}
2504
72246da4
FB		 2505static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2506{
72246da4
FB		 2507 struct dwc3_ep *dep;
2508 int ret;
2509 u32 reg;
2510 u8 speed;
2511
72246da4
FB		 2512 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2513 speed = reg & DWC3_DSTS_CONNECTSPD;
2514 dwc->speed = speed;
2515
5fb6fdaf
JY		 2516 /*
2517 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2518 * each time on Connect Done.
2519 *
2520 * Currently we always use the reset value. If any platform
2521 * wants to set this to a different value, we need to add a
2522 * setting and update GCTL.RAMCLKSEL here.
2523 */
72246da4
FB		 2524
2525 switch (speed) {
2da9ad76 2526 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2527 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2528 dwc->gadget.ep0->maxpacket = 512;
2529 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2530 break;
2da9ad76 2531 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2532 /*
2533 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2534 * would cause a missing USB3 Reset event.
2535 *
2536 * In such situations, we should force a USB3 Reset
2537 * event by calling our dwc3_gadget_reset_interrupt()
2538 * routine.
2539 *
2540 * Refers to:
2541 *
2542 * STAR#9000483510: RTL: SS : USB3 reset event may
2543 * not be generated always when the link enters poll
2544 */
2545 if (dwc->revision < DWC3_REVISION_190A)
2546 dwc3_gadget_reset_interrupt(dwc);
2547
72246da4
FB		 2548 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2549 dwc->gadget.ep0->maxpacket = 512;
2550 dwc->gadget.speed = USB_SPEED_SUPER;
2551 break;
2da9ad76 2552 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2553 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2554 dwc->gadget.ep0->maxpacket = 64;
2555 dwc->gadget.speed = USB_SPEED_HIGH;
2556 break;
9418ee15 2557 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2558 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2559 dwc->gadget.ep0->maxpacket = 64;
2560 dwc->gadget.speed = USB_SPEED_FULL;
2561 break;
2da9ad76 2562 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2563 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2564 dwc->gadget.ep0->maxpacket = 8;
2565 dwc->gadget.speed = USB_SPEED_LOW;
2566 break;
2567 }
2568
2b758350
PA		 2569 /* Enable USB2 LPM Capability */
2570
ee5cd41c 2571 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2572 (speed != DWC3_DSTS_SUPERSPEED) &&
2573 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2574 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2575 reg |= DWC3_DCFG_LPM_CAP;
2576 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2577
2578 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2579 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2580
460d098c 2581 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2582
80caf7d2
HR		 2583 /*
2584 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2585 * DCFG.LPMCap is set, core responses with an ACK and the
2586 * BESL value in the LPM token is less than or equal to LPM
2587 * NYET threshold.
2588 */
2589 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2590 && dwc->has_lpm_erratum,
9165dabb 2591 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2592
2593 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2594 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2595
356363bf
FB		 2596 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2597 } else {
2598 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2599 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2600 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2601 }
2602
72246da4 2603 dep = dwc->eps[0];
39ebb05c 2604 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2605 if (ret) {
2606 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2607 return;
2608 }
2609
2610 dep = dwc->eps[1];
39ebb05c 2611 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2612 if (ret) {
2613 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2614 return;
2615 }
2616
2617 /*
2618 * Configure PHY via GUSB3PIPECTLn if required.
2619 *
2620 * Update GTXFIFOSIZn
2621 *
2622 * In both cases reset values should be sufficient.
2623 */
2624}
2625
2626static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2627{
72246da4
FB		 2628 /*
2629 * TODO take core out of low power mode when that's
2630 * implemented.
2631 */
2632
ad14d4e0
JL		 2633 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2634 spin_unlock(&dwc->lock);
2635 dwc->gadget_driver->resume(&dwc->gadget);
2636 spin_lock(&dwc->lock);
2637 }
72246da4
FB		 2638}
2639
2640static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2641 unsigned int evtinfo)
2642{
fae2b904 2643 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2644 unsigned int pwropt;
2645
2646 /*
2647 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2648 * Hibernation mode enabled which would show up when device detects
2649 * host-initiated U3 exit.
2650 *
2651 * In that case, device will generate a Link State Change Interrupt
2652 * from U3 to RESUME which is only necessary if Hibernation is
2653 * configured in.
2654 *
2655 * There are no functional changes due to such spurious event and we
2656 * just need to ignore it.
2657 *
2658 * Refers to:
2659 *
2660 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2661 * operational mode
2662 */
2663 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2664 if ((dwc->revision < DWC3_REVISION_250A) &&
2665 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2666 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2667 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2668 return;
2669 }
2670 }
fae2b904
FB		 2671
2672 /*
2673 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2674 * on the link partner, the USB session might do multiple entry/exit
2675 * of low power states before a transfer takes place.
2676 *
2677 * Due to this problem, we might experience lower throughput. The
2678 * suggested workaround is to disable DCTL[12:9] bits if we're
2679 * transitioning from U1/U2 to U0 and enable those bits again
2680 * after a transfer completes and there are no pending transfers
2681 * on any of the enabled endpoints.
2682 *
2683 * This is the first half of that workaround.
2684 *
2685 * Refers to:
2686 *
2687 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2688 * core send LGO_Ux entering U0
2689 */
2690 if (dwc->revision < DWC3_REVISION_183A) {
2691 if (next == DWC3_LINK_STATE_U0) {
2692 u32 u1u2;
2693 u32 reg;
2694
2695 switch (dwc->link_state) {
2696 case DWC3_LINK_STATE_U1:
2697 case DWC3_LINK_STATE_U2:
2698 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2699 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2700 | DWC3_DCTL_ACCEPTU2ENA
2701 | DWC3_DCTL_INITU1ENA
2702 | DWC3_DCTL_ACCEPTU1ENA);
2703
2704 if (!dwc->u1u2)
2705 dwc->u1u2 = reg & u1u2;
2706
2707 reg &= ~u1u2;
2708
2709 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2710 break;
2711 default:
2712 /* do nothing */
2713 break;
2714 }
2715 }
2716 }
2717
bc5ba2e0
FB		 2718 switch (next) {
2719 case DWC3_LINK_STATE_U1:
2720 if (dwc->speed == USB_SPEED_SUPER)
2721 dwc3_suspend_gadget(dwc);
2722 break;
2723 case DWC3_LINK_STATE_U2:
2724 case DWC3_LINK_STATE_U3:
2725 dwc3_suspend_gadget(dwc);
2726 break;
2727 case DWC3_LINK_STATE_RESUME:
2728 dwc3_resume_gadget(dwc);
2729 break;
2730 default:
2731 /* do nothing */
2732 break;
2733 }
2734
e57ebc1d 2735 dwc->link_state = next;
72246da4
FB		 2736}
2737
72704f87
BW		 2738static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2739 unsigned int evtinfo)
2740{
2741 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2742
2743 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2744 dwc3_suspend_gadget(dwc);
2745
2746 dwc->link_state = next;
2747}
2748
e1dadd3b
FB		 2749static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2750 unsigned int evtinfo)
2751{
2752 unsigned int is_ss = evtinfo & BIT(4);
2753
2754 /**
2755 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2756 * have a known issue which can cause USB CV TD.9.23 to fail
2757 * randomly.
2758 *
2759 * Because of this issue, core could generate bogus hibernation
2760 * events which SW needs to ignore.
2761 *
2762 * Refers to:
2763 *
2764 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2765 * Device Fallback from SuperSpeed
2766 */
2767 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2768 return;
2769
2770 /* enter hibernation here */
2771}
2772
72246da4
FB		 2773static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2774 const struct dwc3_event_devt *event)
2775{
2776 switch (event->type) {
2777 case DWC3_DEVICE_EVENT_DISCONNECT:
2778 dwc3_gadget_disconnect_interrupt(dwc);
2779 break;
2780 case DWC3_DEVICE_EVENT_RESET:
2781 dwc3_gadget_reset_interrupt(dwc);
2782 break;
2783 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2784 dwc3_gadget_conndone_interrupt(dwc);
2785 break;
2786 case DWC3_DEVICE_EVENT_WAKEUP:
2787 dwc3_gadget_wakeup_interrupt(dwc);
2788 break;
e1dadd3b
FB		 2789 case DWC3_DEVICE_EVENT_HIBER_REQ:
2790 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2791 "unexpected hibernation event\n"))
2792 break;
2793
2794 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2795 break;
72246da4
FB		 2796 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2797 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2798 break;
2799 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2800 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2801 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2802 /*
2803 * Ignore suspend event until the gadget enters into
2804 * USB_STATE_CONFIGURED state.
2805 */
2806 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2807 dwc3_gadget_suspend_interrupt(dwc,
2808 event->event_info);
2809 }
72246da4
FB		 2810 break;
2811 case DWC3_DEVICE_EVENT_SOF:
72246da4 2812 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2813 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2814 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2815 break;
2816 default:
e9f2aa87 2817 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2818 }
2819}
2820
2821static void dwc3_process_event_entry(struct dwc3 *dwc,
2822 const union dwc3_event *event)
2823{
43c96be1 2824 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2825
72246da4
FB		 2826 /* Endpoint IRQ, handle it and return early */
2827 if (event->type.is_devspec == 0) {
2828 /* depevt */
2829 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2830 }
2831
2832 switch (event->type.type) {
2833 case DWC3_EVENT_TYPE_DEV:
2834 dwc3_gadget_interrupt(dwc, &event->devt);
2835 break;
2836 /* REVISIT what to do with Carkit and I2C events ? */
2837 default:
2838 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2839 }
2840}
2841
dea520a4 2842static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2843{
dea520a4 2844 struct dwc3 *dwc = evt->dwc;
b15a762f 2845 irqreturn_t ret = IRQ_NONE;
f42f2447 2846 int left;
e8adfc30 2847 u32 reg;
b15a762f 2848
f42f2447 2849 left = evt->count;
b15a762f 2850
f42f2447
FB		 2851 if (!(evt->flags & DWC3_EVENT_PENDING))
2852 return IRQ_NONE;
b15a762f 2853
f42f2447
FB		 2854 while (left > 0) {
2855 union dwc3_event event;
b15a762f 2856
ebbb2d59 2857 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 2858
f42f2447 2859 dwc3_process_event_entry(dwc, &event);
b15a762f 2860
f42f2447
FB		 2861 /*
2862 * FIXME we wrap around correctly to the next entry as
2863 * almost all entries are 4 bytes in size. There is one
2864 * entry which has 12 bytes which is a regular entry
2865 * followed by 8 bytes data. ATM I don't know how
2866 * things are organized if we get next to the a
2867 * boundary so I worry about that once we try to handle
2868 * that.
2869 */
caefe6c7 2870 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 2871 left -= 4;
f42f2447 2872 }
b15a762f 2873
f42f2447
FB		 2874 evt->count = 0;
2875 evt->flags &= ~DWC3_EVENT_PENDING;
2876 ret = IRQ_HANDLED;
b15a762f 2877
f42f2447 2878 /* Unmask interrupt */
660e9bde 2879 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2880 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2881 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2882
cf40b86b
JY		 2883 if (dwc->imod_interval) {
2884 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2885 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2886 }
2887
f42f2447
FB		 2888 return ret;
2889}
e8adfc30 2890
dea520a4 2891static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 2892{
dea520a4
FB		 2893 struct dwc3_event_buffer *evt = _evt;
2894 struct dwc3 *dwc = evt->dwc;
e5f68b4a 2895 unsigned long flags;
f42f2447 2896 irqreturn_t ret = IRQ_NONE;
f42f2447 2897
e5f68b4a 2898 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 2899 ret = dwc3_process_event_buf(evt);
e5f68b4a 2900 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2901
2902 return ret;
2903}
2904
dea520a4 2905static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 2906{
dea520a4 2907 struct dwc3 *dwc = evt->dwc;
ebbb2d59 2908 u32 amount;
72246da4 2909 u32 count;
e8adfc30 2910 u32 reg;
72246da4 2911
fc8bb91b
FB		 2912 if (pm_runtime_suspended(dwc->dev)) {
2913 pm_runtime_get(dwc->dev);
2914 disable_irq_nosync(dwc->irq_gadget);
2915 dwc->pending_events = true;
2916 return IRQ_HANDLED;
2917 }
2918
660e9bde 2919 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 2920 count &= DWC3_GEVNTCOUNT_MASK;
2921 if (!count)
2922 return IRQ_NONE;
2923
b15a762f
FB		 2924 evt->count = count;
2925 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2926
e8adfc30 2927 /* Mask interrupt */
660e9bde 2928 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 2929 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 2930 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 2931
ebbb2d59
JY		 2932 amount = min(count, evt->length - evt->lpos);
2933 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
2934
2935 if (amount < count)
2936 memcpy(evt->cache, evt->buf, count - amount);
2937
65aca320
JY		 2938 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2939
b15a762f 2940 return IRQ_WAKE_THREAD;
72246da4
FB		 2941}
2942
dea520a4 2943static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 2944{
dea520a4 2945 struct dwc3_event_buffer *evt = _evt;
72246da4 2946
dea520a4 2947 return dwc3_check_event_buf(evt);
72246da4
FB		 2948}
2949
6db3812e
FB		 2950static int dwc3_gadget_get_irq(struct dwc3 *dwc)
2951{
2952 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
2953 int irq;
2954
2955 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
2956 if (irq > 0)
2957 goto out;
2958
2959 if (irq == -EPROBE_DEFER)
2960 goto out;
2961
2962 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
2963 if (irq > 0)
2964 goto out;
2965
2966 if (irq == -EPROBE_DEFER)
2967 goto out;
2968
2969 irq = platform_get_irq(dwc3_pdev, 0);
2970 if (irq > 0)
2971 goto out;
2972
2973 if (irq != -EPROBE_DEFER)
2974 dev_err(dwc->dev, "missing peripheral IRQ\n");
2975
2976 if (!irq)
2977 irq = -EINVAL;
2978
2979out:
2980 return irq;
2981}
2982
72246da4
FB		 2983/**
2984 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2985 * @dwc: pointer to our controller context structure
72246da4
FB		 2986 *
2987 * Returns 0 on success otherwise negative errno.
2988 */
41ac7b3a 2989int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2990{
6db3812e
FB		 2991 int ret;
2992 int irq;
9522def4 2993
6db3812e
FB		 2994 irq = dwc3_gadget_get_irq(dwc);
2995 if (irq < 0) {
2996 ret = irq;
2997 goto err0;
9522def4
RQ		 2998 }
2999
3000 dwc->irq_gadget = irq;
72246da4 3001
d64ff406 3002 dwc->ctrl_req = dma_alloc_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4
FB		 3003 &dwc->ctrl_req_addr, GFP_KERNEL);
3004 if (!dwc->ctrl_req) {
3005 dev_err(dwc->dev, "failed to allocate ctrl request\n");
3006 ret = -ENOMEM;
3007 goto err0;
3008 }
3009
d64ff406
AB		 3010 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3011 sizeof(*dwc->ep0_trb) * 2,
3012 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 3013 if (!dwc->ep0_trb) {
3014 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3015 ret = -ENOMEM;
3016 goto err1;
3017 }
3018
3ef35faf 3019 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 3020 if (!dwc->setup_buf) {
72246da4
FB		 3021 ret = -ENOMEM;
3022 goto err2;
3023 }
3024
d64ff406 3025 dwc->ep0_bounce = dma_alloc_coherent(dwc->sysdev,
3ef35faf
FB		 3026 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3027 GFP_KERNEL);
5812b1c2
FB		 3028 if (!dwc->ep0_bounce) {
3029 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3030 ret = -ENOMEM;
3031 goto err3;
3032 }
3033
04c03d10
FB		 3034 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3035 if (!dwc->zlp_buf) {
3036 ret = -ENOMEM;
3037 goto err4;
3038 }
3039
bb014736
BW		 3040 init_completion(&dwc->ep0_in_setup);
3041
72246da4 3042 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3043 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3044 dwc->gadget.sg_supported = true;
72246da4 3045 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3046 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3047
b9e51b2b
BM		 3048 /*
3049 * FIXME We might be setting max_speed to <SUPER, however versions
3050 * <2.20a of dwc3 have an issue with metastability (documented
3051 * elsewhere in this driver) which tells us we can't set max speed to
3052 * anything lower than SUPER.
3053 *
3054 * Because gadget.max_speed is only used by composite.c and function
3055 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3056 * to happen so we avoid sending SuperSpeed Capability descriptor
3057 * together with our BOS descriptor as that could confuse host into
3058 * thinking we can handle super speed.
3059 *
3060 * Note that, in fact, we won't even support GetBOS requests when speed
3061 * is less than super speed because we don't have means, yet, to tell
3062 * composite.c that we are USB 2.0 + LPM ECN.
3063 */
3064 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3065 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3066 dwc->revision);
3067
3068 dwc->gadget.max_speed = dwc->maximum_speed;
3069
a4b9d94b
DC		 3070 /*
3071 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3072 * on ep out.
3073 */
3074 dwc->gadget.quirk_ep_out_aligned_size = true;
3075
72246da4
FB		 3076 /*
3077 * REVISIT: Here we should clear all pending IRQs to be
3078 * sure we're starting from a well known location.
3079 */
3080
3081 ret = dwc3_gadget_init_endpoints(dwc);
3082 if (ret)
04c03d10 3083 goto err5;
72246da4 3084
72246da4
FB		 3085 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3086 if (ret) {
3087 dev_err(dwc->dev, "failed to register udc\n");
04c03d10 3088 goto err5;
72246da4
FB		 3089 }
3090
3091 return 0;
3092
04c03d10
FB		 3093err5:
3094 kfree(dwc->zlp_buf);
3095
5812b1c2 3096err4:
e1f80467 3097 dwc3_gadget_free_endpoints(dwc);
d64ff406 3098 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3099 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3100
72246da4 3101err3:
0fc9a1be 3102 kfree(dwc->setup_buf);
72246da4
FB		 3103
3104err2:
d64ff406 3105 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3106 dwc->ep0_trb, dwc->ep0_trb_addr);
3107
3108err1:
d64ff406 3109 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4
FB		 3110 dwc->ctrl_req, dwc->ctrl_req_addr);
3111
3112err0:
3113 return ret;
3114}
3115
7415f17c
FB		 3116/* -------------------------------------------------------------------------- */
3117
72246da4
FB		 3118void dwc3_gadget_exit(struct dwc3 *dwc)
3119{
72246da4 3120 usb_del_gadget_udc(&dwc->gadget);
72246da4 3121
72246da4
FB		 3122 dwc3_gadget_free_endpoints(dwc);
3123
d64ff406 3124 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3125 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3126
0fc9a1be 3127 kfree(dwc->setup_buf);
04c03d10 3128 kfree(dwc->zlp_buf);
72246da4 3129
d64ff406 3130 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3131 dwc->ep0_trb, dwc->ep0_trb_addr);
3132
d64ff406 3133 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4 3134 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 3135}
7415f17c 3136
0b0231aa 3137int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3138{
9f8a67b6
FB		 3139 int ret;
3140
9772b47a
RQ		 3141 if (!dwc->gadget_driver)
3142 return 0;
3143
9f8a67b6
FB		 3144 ret = dwc3_gadget_run_stop(dwc, false, false);
3145 if (ret < 0)
3146 return ret;
7415f17c 3147
9f8a67b6
FB		 3148 dwc3_disconnect_gadget(dwc);
3149 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3150
3151 return 0;
3152}
3153
3154int dwc3_gadget_resume(struct dwc3 *dwc)
3155{
7415f17c
FB		 3156 int ret;
3157
9772b47a
RQ		 3158 if (!dwc->gadget_driver)
3159 return 0;
3160
9f8a67b6
FB		 3161 ret = __dwc3_gadget_start(dwc);
3162 if (ret < 0)
7415f17c
FB		 3163 goto err0;
3164
9f8a67b6
FB		 3165 ret = dwc3_gadget_run_stop(dwc, true, false);
3166 if (ret < 0)
7415f17c
FB		 3167 goto err1;
3168
7415f17c
FB		 3169 return 0;
3170
3171err1:
9f8a67b6 3172 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3173
3174err0:
3175 return ret;
3176}
fc8bb91b
FB		 3177
3178void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3179{
3180 if (dwc->pending_events) {
3181 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3182 dwc->pending_events = false;
3183 enable_irq(dwc->irq_gadget);
3184 }
3185}
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