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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
17230acd | 16 | * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
17 | * |
18 | * Intel documents this fairly well, and as far as I know there | |
19 | * are no royalties or anything like that, but even so there are | |
20 | * people who decided that they want to do the same thing in a | |
21 | * completely different way. | |
22 | * | |
1da177e4 LT |
23 | */ |
24 | ||
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/ioport.h> | |
1da177e4 | 31 | #include <linux/slab.h> |
1da177e4 LT |
32 | #include <linux/errno.h> |
33 | #include <linux/unistd.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/pm.h> | |
38 | #include <linux/dmapool.h> | |
39 | #include <linux/dma-mapping.h> | |
40 | #include <linux/usb.h> | |
27729aad | 41 | #include <linux/usb/hcd.h> |
1da177e4 | 42 | #include <linux/bitops.h> |
b62df451 | 43 | #include <linux/dmi.h> |
1da177e4 | 44 | |
7c0f6ba6 | 45 | #include <linux/uaccess.h> |
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/irq.h> | |
1da177e4 | 48 | |
1da177e4 LT |
49 | #include "uhci-hcd.h" |
50 | ||
51 | /* | |
52 | * Version Information | |
53 | */ | |
85ee7a1d JP |
54 | #define DRIVER_AUTHOR \ |
55 | "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \ | |
56 | "Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \ | |
57 | "Roman Weissgaerber, Alan Stern" | |
1da177e4 LT |
58 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" |
59 | ||
5f8364b7 | 60 | /* for flakey hardware, ignore overcurrent indicators */ |
90ab5ee9 | 61 | static bool ignore_oc; |
5f8364b7 AS |
62 | module_param(ignore_oc, bool, S_IRUGO); |
63 | MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications"); | |
64 | ||
1da177e4 LT |
65 | /* |
66 | * debug = 0, no debugging messages | |
687f5f34 AS |
67 | * debug = 1, dump failed URBs except for stalls |
68 | * debug = 2, dump all failed URBs (including stalls) | |
837cbb07 | 69 | * show all queues in /sys/kernel/debug/uhci/[pci_addr] |
687f5f34 | 70 | * debug = 3, show all TDs in URBs when dumping |
1da177e4 | 71 | */ |
1c20163d | 72 | #ifdef CONFIG_DYNAMIC_DEBUG |
cadb3756 | 73 | |
1da177e4 | 74 | static int debug = 1; |
1da177e4 LT |
75 | module_param(debug, int, S_IRUGO | S_IWUSR); |
76 | MODULE_PARM_DESC(debug, "Debug level"); | |
cadb3756 | 77 | static char *errbuf; |
8d402e1a AS |
78 | |
79 | #else | |
cadb3756 ON |
80 | |
81 | #define debug 0 | |
82 | #define errbuf NULL | |
83 | ||
8d402e1a AS |
84 | #endif |
85 | ||
cadb3756 | 86 | |
1da177e4 LT |
87 | #define ERRBUF_LEN (32 * 1024) |
88 | ||
e18b890b | 89 | static struct kmem_cache *uhci_up_cachep; /* urb_priv */ |
1da177e4 | 90 | |
6c1b445c AS |
91 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); |
92 | static void wakeup_rh(struct uhci_hcd *uhci); | |
1da177e4 | 93 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci); |
1da177e4 | 94 | |
f3fe239b AS |
95 | /* |
96 | * Calculate the link pointer DMA value for the first Skeleton QH in a frame. | |
97 | */ | |
51e2f62f | 98 | static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) |
f3fe239b AS |
99 | { |
100 | int skelnum; | |
101 | ||
102 | /* | |
103 | * The interrupt queues will be interleaved as evenly as possible. | |
104 | * There's not much to be done about period-1 interrupts; they have | |
105 | * to occur in every frame. But we can schedule period-2 interrupts | |
106 | * in odd-numbered frames, period-4 interrupts in frames congruent | |
107 | * to 2 (mod 4), and so on. This way each frame only has two | |
108 | * interrupt QHs, which will help spread out bandwidth utilization. | |
109 | * | |
110 | * ffs (Find First bit Set) does exactly what we need: | |
17230acd AS |
111 | * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8], |
112 | * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc. | |
f3fe239b | 113 | * ffs >= 7 => not on any high-period queue, so use |
17230acd | 114 | * period-1 QH = skelqh[9]. |
f3fe239b AS |
115 | * Add in UHCI_NUMFRAMES to insure at least one bit is set. |
116 | */ | |
117 | skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); | |
118 | if (skelnum <= 1) | |
119 | skelnum = 9; | |
51e2f62f | 120 | return LINK_TO_QH(uhci, uhci->skelqh[skelnum]); |
f3fe239b AS |
121 | } |
122 | ||
1da177e4 LT |
123 | #include "uhci-debug.c" |
124 | #include "uhci-q.c" | |
1f09df8b | 125 | #include "uhci-hub.c" |
1da177e4 | 126 | |
a8bed8b6 | 127 | /* |
bb200f6e | 128 | * Finish up a host controller reset and update the recorded state. |
a8bed8b6 | 129 | */ |
bb200f6e | 130 | static void finish_reset(struct uhci_hcd *uhci) |
1da177e4 | 131 | { |
c074b416 AS |
132 | int port; |
133 | ||
c074b416 AS |
134 | /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect |
135 | * bits in the port status and control registers. | |
136 | * We have to clear them by hand. | |
137 | */ | |
138 | for (port = 0; port < uhci->rh_numports; ++port) | |
9faa091a | 139 | uhci_writew(uhci, 0, USBPORTSC1 + (port * 2)); |
c074b416 | 140 | |
8e326406 | 141 | uhci->port_c_suspend = uhci->resuming_ports = 0; |
c8f4fe43 | 142 | uhci->rh_state = UHCI_RH_RESET; |
a8bed8b6 | 143 | uhci->is_stopped = UHCI_IS_STOPPED; |
541c7d43 | 144 | clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
1da177e4 LT |
145 | } |
146 | ||
4daaa87c AS |
147 | /* |
148 | * Last rites for a defunct/nonfunctional controller | |
02597d2d | 149 | * or one we don't want to use any more. |
4daaa87c | 150 | */ |
e323de46 | 151 | static void uhci_hc_died(struct uhci_hcd *uhci) |
4daaa87c | 152 | { |
e323de46 | 153 | uhci_get_current_frame_number(uhci); |
e7652e1e | 154 | uhci->reset_hc(uhci); |
bb200f6e | 155 | finish_reset(uhci); |
e323de46 AS |
156 | uhci->dead = 1; |
157 | ||
158 | /* The current frame may already be partway finished */ | |
159 | ++uhci->frame_number; | |
4daaa87c AS |
160 | } |
161 | ||
a8bed8b6 | 162 | /* |
be3cbc5f DB |
163 | * Initialize a controller that was newly discovered or has lost power |
164 | * or otherwise been reset while it was suspended. In none of these cases | |
165 | * can we be sure of its previous state. | |
a8bed8b6 AS |
166 | */ |
167 | static void check_and_reset_hc(struct uhci_hcd *uhci) | |
168 | { | |
e7652e1e | 169 | if (uhci->check_and_reset_hc(uhci)) |
bb200f6e | 170 | finish_reset(uhci); |
a8bed8b6 AS |
171 | } |
172 | ||
d3219d1c JA |
173 | #if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC) |
174 | /* | |
175 | * The two functions below are generic reset functions that are used on systems | |
176 | * that do not have keyboard and mouse legacy support. We assume that we are | |
177 | * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined. | |
178 | */ | |
179 | ||
180 | /* | |
181 | * Make sure the controller is completely inactive, unable to | |
182 | * generate interrupts or do DMA. | |
183 | */ | |
184 | static void uhci_generic_reset_hc(struct uhci_hcd *uhci) | |
185 | { | |
186 | /* Reset the HC - this will force us to get a | |
187 | * new notification of any already connected | |
188 | * ports due to the virtual disconnect that it | |
189 | * implies. | |
190 | */ | |
191 | uhci_writew(uhci, USBCMD_HCRESET, USBCMD); | |
192 | mb(); | |
193 | udelay(5); | |
194 | if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET) | |
195 | dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n"); | |
196 | ||
197 | /* Just to be safe, disable interrupt requests and | |
198 | * make sure the controller is stopped. | |
199 | */ | |
200 | uhci_writew(uhci, 0, USBINTR); | |
201 | uhci_writew(uhci, 0, USBCMD); | |
202 | } | |
203 | ||
204 | /* | |
205 | * Initialize a controller that was newly discovered or has just been | |
206 | * resumed. In either case we can't be sure of its previous state. | |
207 | * | |
208 | * Returns: 1 if the controller was reset, 0 otherwise. | |
209 | */ | |
210 | static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci) | |
211 | { | |
212 | unsigned int cmd, intr; | |
213 | ||
214 | /* | |
215 | * When restarting a suspended controller, we expect all the | |
216 | * settings to be the same as we left them: | |
217 | * | |
218 | * Controller is stopped and configured with EGSM set; | |
219 | * No interrupts enabled except possibly Resume Detect. | |
220 | * | |
221 | * If any of these conditions are violated we do a complete reset. | |
222 | */ | |
223 | ||
224 | cmd = uhci_readw(uhci, USBCMD); | |
225 | if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) { | |
226 | dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n", | |
227 | __func__, cmd); | |
228 | goto reset_needed; | |
229 | } | |
230 | ||
231 | intr = uhci_readw(uhci, USBINTR); | |
232 | if (intr & (~USBINTR_RESUME)) { | |
233 | dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n", | |
234 | __func__, intr); | |
235 | goto reset_needed; | |
236 | } | |
237 | return 0; | |
238 | ||
239 | reset_needed: | |
240 | dev_dbg(uhci_dev(uhci), "Performing full reset\n"); | |
241 | uhci_generic_reset_hc(uhci); | |
242 | return 1; | |
243 | } | |
244 | #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ | |
245 | ||
a8bed8b6 AS |
246 | /* |
247 | * Store the basic register settings needed by the controller. | |
248 | */ | |
249 | static void configure_hc(struct uhci_hcd *uhci) | |
250 | { | |
251 | /* Set the frame length to the default: 1 ms exactly */ | |
9faa091a | 252 | uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF); |
a8bed8b6 AS |
253 | |
254 | /* Store the frame list base address */ | |
9faa091a | 255 | uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD); |
a8bed8b6 AS |
256 | |
257 | /* Set the current frame number */ | |
9faa091a JA |
258 | uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER, |
259 | USBFRNUM); | |
0d436b42 | 260 | |
e7652e1e JA |
261 | /* perform any arch/bus specific configuration */ |
262 | if (uhci->configure_hc) | |
263 | uhci->configure_hc(uhci); | |
a8bed8b6 AS |
264 | } |
265 | ||
c8f4fe43 | 266 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) |
1da177e4 | 267 | { |
5f8364b7 AS |
268 | /* If we have to ignore overcurrent events then almost by definition |
269 | * we can't depend on resume-detect interrupts. */ | |
270 | if (ignore_oc) | |
271 | return 1; | |
272 | ||
e7652e1e JA |
273 | return uhci->resume_detect_interrupts_are_broken ? |
274 | uhci->resume_detect_interrupts_are_broken(uhci) : 0; | |
c8f4fe43 AS |
275 | } |
276 | ||
d8f12ab5 | 277 | static int global_suspend_mode_is_broken(struct uhci_hcd *uhci) |
b62df451 | 278 | { |
e7652e1e JA |
279 | return uhci->global_suspend_mode_is_broken ? |
280 | uhci->global_suspend_mode_is_broken(uhci) : 0; | |
b62df451 AS |
281 | } |
282 | ||
a8bed8b6 | 283 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) |
c8f4fe43 AS |
284 | __releases(uhci->lock) |
285 | __acquires(uhci->lock) | |
286 | { | |
287 | int auto_stop; | |
d8f12ab5 | 288 | int int_enable, egsm_enable, wakeup_enable; |
58a97ffe | 289 | struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub; |
c8f4fe43 AS |
290 | |
291 | auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); | |
58a97ffe | 292 | dev_dbg(&rhdev->dev, "%s%s\n", __func__, |
c8f4fe43 AS |
293 | (auto_stop ? " (auto-stop)" : "")); |
294 | ||
d8f12ab5 AS |
295 | /* Start off by assuming Resume-Detect interrupts and EGSM work |
296 | * and that remote wakeups should be enabled. | |
c8f4fe43 | 297 | */ |
b62df451 | 298 | egsm_enable = USBCMD_EGSM; |
1f09df8b | 299 | int_enable = USBINTR_RESUME; |
d8f12ab5 AS |
300 | wakeup_enable = 1; |
301 | ||
5c12e785 AS |
302 | /* |
303 | * In auto-stop mode, we must be able to detect new connections. | |
304 | * The user can force us to poll by disabling remote wakeup; | |
305 | * otherwise we will use the EGSM/RD mechanism. | |
d8f12ab5 AS |
306 | */ |
307 | if (auto_stop) { | |
308 | if (!device_may_wakeup(&rhdev->dev)) | |
5c12e785 AS |
309 | egsm_enable = int_enable = 0; |
310 | } | |
d8f12ab5 | 311 | |
58a97ffe | 312 | #ifdef CONFIG_PM |
5c12e785 AS |
313 | /* |
314 | * In bus-suspend mode, we use the wakeup setting specified | |
315 | * for the root hub. | |
316 | */ | |
317 | else { | |
d8f12ab5 AS |
318 | if (!rhdev->do_remote_wakeup) |
319 | wakeup_enable = 0; | |
d8f12ab5 | 320 | } |
5c12e785 | 321 | #endif |
d8f12ab5 | 322 | |
5c12e785 AS |
323 | /* |
324 | * UHCI doesn't distinguish between wakeup requests from downstream | |
325 | * devices and local connect/disconnect events. There's no way to | |
326 | * enable one without the other; both are controlled by EGSM. Thus | |
327 | * if wakeups are disallowed then EGSM must be turned off -- in which | |
328 | * case remote wakeup requests from downstream during system sleep | |
329 | * will be lost. | |
330 | * | |
331 | * In addition, if EGSM is broken then we can't use it. Likewise, | |
332 | * if Resume-Detect interrupts are broken then we can't use them. | |
d8f12ab5 | 333 | * |
5c12e785 AS |
334 | * Finally, neither EGSM nor RD is useful by itself. Without EGSM, |
335 | * the RD status bit will never get set. Without RD, the controller | |
336 | * won't generate interrupts to tell the system about wakeup events. | |
d8f12ab5 | 337 | */ |
5c12e785 AS |
338 | if (!wakeup_enable || global_suspend_mode_is_broken(uhci) || |
339 | resume_detect_interrupts_are_broken(uhci)) | |
340 | egsm_enable = int_enable = 0; | |
b62df451 | 341 | |
5c12e785 | 342 | uhci->RD_enable = !!int_enable; |
9faa091a JA |
343 | uhci_writew(uhci, int_enable, USBINTR); |
344 | uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD); | |
a8bed8b6 | 345 | mb(); |
c8f4fe43 AS |
346 | udelay(5); |
347 | ||
348 | /* If we're auto-stopping then no devices have been attached | |
349 | * for a while, so there shouldn't be any active URBs and the | |
350 | * controller should stop after a few microseconds. Otherwise | |
351 | * we will give the controller one frame to stop. | |
352 | */ | |
9faa091a | 353 | if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) { |
c8f4fe43 AS |
354 | uhci->rh_state = UHCI_RH_SUSPENDING; |
355 | spin_unlock_irq(&uhci->lock); | |
356 | msleep(1); | |
357 | spin_lock_irq(&uhci->lock); | |
e323de46 | 358 | if (uhci->dead) |
4daaa87c | 359 | return; |
c8f4fe43 | 360 | } |
9faa091a | 361 | if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) |
58a97ffe | 362 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); |
1da177e4 | 363 | |
1da177e4 | 364 | uhci_get_current_frame_number(uhci); |
c8f4fe43 AS |
365 | |
366 | uhci->rh_state = new_state; | |
1da177e4 | 367 | uhci->is_stopped = UHCI_IS_STOPPED; |
d8f12ab5 | 368 | |
5c12e785 AS |
369 | /* |
370 | * If remote wakeup is enabled but either EGSM or RD interrupts | |
371 | * doesn't work, then we won't get an interrupt when a wakeup event | |
372 | * occurs. Thus the suspended root hub needs to be polled. | |
d8f12ab5 | 373 | */ |
5c12e785 | 374 | if (wakeup_enable && (!int_enable || !egsm_enable)) |
541c7d43 AS |
375 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
376 | else | |
377 | clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); | |
1da177e4 | 378 | |
7d12e780 | 379 | uhci_scan_schedule(uhci); |
84afddd7 | 380 | uhci_fsbr_off(uhci); |
1da177e4 LT |
381 | } |
382 | ||
a8bed8b6 AS |
383 | static void start_rh(struct uhci_hcd *uhci) |
384 | { | |
a8bed8b6 | 385 | uhci->is_stopped = 0; |
a8bed8b6 AS |
386 | |
387 | /* Mark it configured and running with a 64-byte max packet. | |
388 | * All interrupts are enabled, even though RESUME won't do anything. | |
389 | */ | |
9faa091a JA |
390 | uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD); |
391 | uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME | | |
392 | USBINTR_IOC | USBINTR_SP, USBINTR); | |
a8bed8b6 | 393 | mb(); |
6c1b445c | 394 | uhci->rh_state = UHCI_RH_RUNNING; |
541c7d43 | 395 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
a8bed8b6 AS |
396 | } |
397 | ||
398 | static void wakeup_rh(struct uhci_hcd *uhci) | |
c8f4fe43 AS |
399 | __releases(uhci->lock) |
400 | __acquires(uhci->lock) | |
1da177e4 | 401 | { |
be3cbc5f | 402 | dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, |
441b62c1 | 403 | "%s%s\n", __func__, |
c8f4fe43 AS |
404 | uhci->rh_state == UHCI_RH_AUTO_STOPPED ? |
405 | " (auto-start)" : ""); | |
1da177e4 | 406 | |
c8f4fe43 AS |
407 | /* If we are auto-stopped then no devices are attached so there's |
408 | * no need for wakeup signals. Otherwise we send Global Resume | |
409 | * for 20 ms. | |
410 | */ | |
411 | if (uhci->rh_state == UHCI_RH_SUSPENDED) { | |
d8f12ab5 AS |
412 | unsigned egsm; |
413 | ||
414 | /* Keep EGSM on if it was set before */ | |
9faa091a | 415 | egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM; |
c8f4fe43 | 416 | uhci->rh_state = UHCI_RH_RESUMING; |
9faa091a | 417 | uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD); |
c8f4fe43 AS |
418 | spin_unlock_irq(&uhci->lock); |
419 | msleep(20); | |
420 | spin_lock_irq(&uhci->lock); | |
e323de46 | 421 | if (uhci->dead) |
4daaa87c | 422 | return; |
1da177e4 | 423 | |
c8f4fe43 | 424 | /* End Global Resume and wait for EOP to be sent */ |
9faa091a | 425 | uhci_writew(uhci, USBCMD_CF, USBCMD); |
a8bed8b6 | 426 | mb(); |
c8f4fe43 | 427 | udelay(4); |
9faa091a | 428 | if (uhci_readw(uhci, USBCMD) & USBCMD_FGR) |
c8f4fe43 AS |
429 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); |
430 | } | |
1da177e4 | 431 | |
a8bed8b6 | 432 | start_rh(uhci); |
c8f4fe43 | 433 | |
6c1b445c AS |
434 | /* Restart root hub polling */ |
435 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); | |
1da177e4 LT |
436 | } |
437 | ||
7d12e780 | 438 | static irqreturn_t uhci_irq(struct usb_hcd *hcd) |
014e73c9 AS |
439 | { |
440 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
014e73c9 | 441 | unsigned short status; |
1da177e4 LT |
442 | |
443 | /* | |
014e73c9 AS |
444 | * Read the interrupt status, and write it back to clear the |
445 | * interrupt cause. Contrary to the UHCI specification, the | |
446 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | |
1da177e4 | 447 | */ |
9faa091a | 448 | status = uhci_readw(uhci, USBSTS); |
014e73c9 AS |
449 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
450 | return IRQ_NONE; | |
9faa091a | 451 | uhci_writew(uhci, status, USBSTS); /* Clear it */ |
014e73c9 | 452 | |
0f815a0a AS |
453 | spin_lock(&uhci->lock); |
454 | if (unlikely(!uhci->is_initialized)) /* not yet configured */ | |
455 | goto done; | |
456 | ||
014e73c9 AS |
457 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { |
458 | if (status & USBSTS_HSE) | |
3171fcab CG |
459 | dev_err(uhci_dev(uhci), |
460 | "host system error, PCI problems?\n"); | |
014e73c9 | 461 | if (status & USBSTS_HCPE) |
3171fcab CG |
462 | dev_err(uhci_dev(uhci), |
463 | "host controller process error, something bad happened!\n"); | |
4daaa87c | 464 | if (status & USBSTS_HCH) { |
4daaa87c AS |
465 | if (uhci->rh_state >= UHCI_RH_RUNNING) { |
466 | dev_err(uhci_dev(uhci), | |
3171fcab | 467 | "host controller halted, very bad!\n"); |
8d402e1a AS |
468 | if (debug > 1 && errbuf) { |
469 | /* Print the schedule for debugging */ | |
13996ca7 CG |
470 | uhci_sprint_schedule(uhci, errbuf, |
471 | ERRBUF_LEN - EXTRA_SPACE); | |
8d402e1a AS |
472 | lprintk(errbuf); |
473 | } | |
e323de46 | 474 | uhci_hc_died(uhci); |
7d670a2e | 475 | usb_hc_died(hcd); |
1f09df8b AS |
476 | |
477 | /* Force a callback in case there are | |
478 | * pending unlinks */ | |
479 | mod_timer(&hcd->rh_timer, jiffies); | |
4daaa87c | 480 | } |
1da177e4 | 481 | } |
1da177e4 LT |
482 | } |
483 | ||
0f815a0a AS |
484 | if (status & USBSTS_RD) { |
485 | spin_unlock(&uhci->lock); | |
6c1b445c | 486 | usb_hcd_poll_rh_status(hcd); |
0f815a0a | 487 | } else { |
7d12e780 | 488 | uhci_scan_schedule(uhci); |
0f815a0a | 489 | done: |
442258e2 | 490 | spin_unlock(&uhci->lock); |
1f09df8b | 491 | } |
1da177e4 | 492 | |
014e73c9 AS |
493 | return IRQ_HANDLED; |
494 | } | |
1da177e4 | 495 | |
014e73c9 AS |
496 | /* |
497 | * Store the current frame number in uhci->frame_number if the controller | |
06125beb | 498 | * is running. Expand from 11 bits (of which we use only 10) to a |
c4334726 AS |
499 | * full-sized integer. |
500 | * | |
501 | * Like many other parts of the driver, this code relies on being polled | |
502 | * more than once per second as long as the controller is running. | |
014e73c9 AS |
503 | */ |
504 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |
505 | { | |
c4334726 AS |
506 | if (!uhci->is_stopped) { |
507 | unsigned delta; | |
508 | ||
9faa091a | 509 | delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) & |
c4334726 AS |
510 | (UHCI_NUMFRAMES - 1); |
511 | uhci->frame_number += delta; | |
512 | } | |
1da177e4 LT |
513 | } |
514 | ||
515 | /* | |
516 | * De-allocate all resources | |
517 | */ | |
518 | static void release_uhci(struct uhci_hcd *uhci) | |
519 | { | |
520 | int i; | |
521 | ||
8d402e1a | 522 | |
cadb3756 ON |
523 | spin_lock_irq(&uhci->lock); |
524 | uhci->is_initialized = 0; | |
525 | spin_unlock_irq(&uhci->lock); | |
526 | ||
527 | debugfs_remove(uhci->dentry); | |
8d402e1a | 528 | |
1da177e4 | 529 | for (i = 0; i < UHCI_NUM_SKELQH; i++) |
8b4cd421 | 530 | uhci_free_qh(uhci, uhci->skelqh[i]); |
1da177e4 | 531 | |
8b4cd421 | 532 | uhci_free_td(uhci, uhci->term_td); |
1da177e4 | 533 | |
8b4cd421 | 534 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 | 535 | |
8b4cd421 | 536 | dma_pool_destroy(uhci->td_pool); |
1da177e4 | 537 | |
a1d59ce8 AS |
538 | kfree(uhci->frame_cpu); |
539 | ||
540 | dma_free_coherent(uhci_dev(uhci), | |
541 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
542 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 LT |
543 | } |
544 | ||
1da177e4 LT |
545 | /* |
546 | * Allocate a frame list, and then setup the skeleton | |
547 | * | |
548 | * The hardware doesn't really know any difference | |
549 | * in the queues, but the order does matter for the | |
17230acd AS |
550 | * protocols higher up. The order in which the queues |
551 | * are encountered by the hardware is: | |
1da177e4 | 552 | * |
17230acd | 553 | * - All isochronous events are handled before any |
1da177e4 LT |
554 | * of the queues. We don't do that here, because |
555 | * we'll create the actual TD entries on demand. | |
17230acd AS |
556 | * - The first queue is the high-period interrupt queue. |
557 | * - The second queue is the period-1 interrupt and async | |
558 | * (low-speed control, full-speed control, then bulk) queue. | |
559 | * - The third queue is the terminating bandwidth reclamation queue, | |
560 | * which contains no members, loops back to itself, and is present | |
561 | * only when FSBR is on and there are no full-speed control or bulk QHs. | |
1da177e4 LT |
562 | */ |
563 | static int uhci_start(struct usb_hcd *hcd) | |
564 | { | |
565 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
566 | int retval = -EBUSY; | |
c074b416 | 567 | int i; |
b409214c | 568 | struct dentry __maybe_unused *dentry; |
1da177e4 | 569 | |
6c1b445c | 570 | hcd->uses_new_polling = 1; |
2851784f SAS |
571 | /* Accept arbitrarily long scatter-gather lists */ |
572 | if (!(hcd->driver->flags & HCD_LOCAL_MEM)) | |
573 | hcd->self.sg_tablesize = ~0; | |
1da177e4 | 574 | |
1da177e4 | 575 | spin_lock_init(&uhci->lock); |
c5e3b741 AS |
576 | setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout, |
577 | (unsigned long) uhci); | |
dccf4a48 | 578 | INIT_LIST_HEAD(&uhci->idle_qh_list); |
1da177e4 LT |
579 | init_waitqueue_head(&uhci->waitqh); |
580 | ||
b409214c AS |
581 | #ifdef UHCI_DEBUG_OPS |
582 | dentry = debugfs_create_file(hcd->self.bus_name, | |
583 | S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, | |
584 | uhci, &uhci_debug_operations); | |
585 | if (!dentry) { | |
586 | dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n"); | |
587 | return -ENOMEM; | |
8d402e1a | 588 | } |
b409214c AS |
589 | uhci->dentry = dentry; |
590 | #endif | |
8d402e1a | 591 | |
a1d59ce8 AS |
592 | uhci->frame = dma_alloc_coherent(uhci_dev(uhci), |
593 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
f589b3e0 | 594 | &uhci->frame_dma_handle, GFP_KERNEL); |
a1d59ce8 | 595 | if (!uhci->frame) { |
3171fcab CG |
596 | dev_err(uhci_dev(uhci), |
597 | "unable to allocate consistent memory for frame list\n"); | |
a1d59ce8 | 598 | goto err_alloc_frame; |
1da177e4 | 599 | } |
a1d59ce8 | 600 | memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame)); |
1da177e4 | 601 | |
a1d59ce8 AS |
602 | uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), |
603 | GFP_KERNEL); | |
314e6725 | 604 | if (!uhci->frame_cpu) |
a1d59ce8 | 605 | goto err_alloc_frame_cpu; |
1da177e4 LT |
606 | |
607 | uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), | |
608 | sizeof(struct uhci_td), 16, 0); | |
609 | if (!uhci->td_pool) { | |
610 | dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); | |
611 | goto err_create_td_pool; | |
612 | } | |
613 | ||
614 | uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), | |
615 | sizeof(struct uhci_qh), 16, 0); | |
616 | if (!uhci->qh_pool) { | |
617 | dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); | |
618 | goto err_create_qh_pool; | |
619 | } | |
620 | ||
2532178a | 621 | uhci->term_td = uhci_alloc_td(uhci); |
1da177e4 LT |
622 | if (!uhci->term_td) { |
623 | dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); | |
624 | goto err_alloc_term_td; | |
625 | } | |
626 | ||
627 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { | |
dccf4a48 | 628 | uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); |
1da177e4 LT |
629 | if (!uhci->skelqh[i]) { |
630 | dev_err(uhci_dev(uhci), "unable to allocate QH\n"); | |
631 | goto err_alloc_skelqh; | |
632 | } | |
633 | } | |
634 | ||
635 | /* | |
17230acd | 636 | * 8 Interrupt queues; link all higher int queues to int1 = async |
1da177e4 | 637 | */ |
17230acd | 638 | for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) |
51e2f62f JA |
639 | uhci->skelqh[i]->link = LINK_TO_QH(uhci, uhci->skel_async_qh); |
640 | uhci->skel_async_qh->link = UHCI_PTR_TERM(uhci); | |
641 | uhci->skel_term_qh->link = LINK_TO_QH(uhci, uhci->skel_term_qh); | |
1da177e4 LT |
642 | |
643 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | |
51e2f62f | 644 | uhci_fill_td(uhci, uhci->term_td, 0, uhci_explen(0) | |
17230acd | 645 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); |
51e2f62f | 646 | uhci->term_td->link = UHCI_PTR_TERM(uhci); |
17230acd | 647 | uhci->skel_async_qh->element = uhci->skel_term_qh->element = |
51e2f62f | 648 | LINK_TO_TD(uhci, uhci->term_td); |
1da177e4 LT |
649 | |
650 | /* | |
651 | * Fill the frame list: make all entries point to the proper | |
652 | * interrupt queue. | |
1da177e4 LT |
653 | */ |
654 | for (i = 0; i < UHCI_NUMFRAMES; i++) { | |
1da177e4 LT |
655 | |
656 | /* Only place we don't use the frame list routines */ | |
f3fe239b | 657 | uhci->frame[i] = uhci_frame_skel_link(uhci, i); |
1da177e4 LT |
658 | } |
659 | ||
660 | /* | |
661 | * Some architectures require a full mb() to enforce completion of | |
a8bed8b6 | 662 | * the memory writes above before the I/O transfers in configure_hc(). |
1da177e4 LT |
663 | */ |
664 | mb(); | |
a8bed8b6 | 665 | |
0f815a0a | 666 | spin_lock_irq(&uhci->lock); |
a8bed8b6 | 667 | configure_hc(uhci); |
8d402e1a | 668 | uhci->is_initialized = 1; |
a8bed8b6 | 669 | start_rh(uhci); |
ba297edd | 670 | spin_unlock_irq(&uhci->lock); |
1da177e4 LT |
671 | return 0; |
672 | ||
673 | /* | |
674 | * error exits: | |
675 | */ | |
1da177e4 | 676 | err_alloc_skelqh: |
8b4cd421 AS |
677 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { |
678 | if (uhci->skelqh[i]) | |
1da177e4 | 679 | uhci_free_qh(uhci, uhci->skelqh[i]); |
8b4cd421 | 680 | } |
1da177e4 LT |
681 | |
682 | uhci_free_td(uhci, uhci->term_td); | |
1da177e4 LT |
683 | |
684 | err_alloc_term_td: | |
1da177e4 | 685 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 LT |
686 | |
687 | err_create_qh_pool: | |
688 | dma_pool_destroy(uhci->td_pool); | |
1da177e4 LT |
689 | |
690 | err_create_td_pool: | |
a1d59ce8 AS |
691 | kfree(uhci->frame_cpu); |
692 | ||
693 | err_alloc_frame_cpu: | |
694 | dma_free_coherent(uhci_dev(uhci), | |
695 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
696 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 | 697 | |
a1d59ce8 | 698 | err_alloc_frame: |
1da177e4 | 699 | debugfs_remove(uhci->dentry); |
1da177e4 | 700 | |
1da177e4 LT |
701 | return retval; |
702 | } | |
703 | ||
704 | static void uhci_stop(struct usb_hcd *hcd) | |
705 | { | |
706 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
707 | ||
1da177e4 | 708 | spin_lock_irq(&uhci->lock); |
541c7d43 | 709 | if (HCD_HW_ACCESSIBLE(hcd) && !uhci->dead) |
e323de46 | 710 | uhci_hc_died(uhci); |
7d12e780 | 711 | uhci_scan_schedule(uhci); |
1da177e4 | 712 | spin_unlock_irq(&uhci->lock); |
d23356da | 713 | synchronize_irq(hcd->irq); |
6c1b445c | 714 | |
c5e3b741 | 715 | del_timer_sync(&uhci->fsbr_timer); |
1da177e4 LT |
716 | release_uhci(uhci); |
717 | } | |
718 | ||
719 | #ifdef CONFIG_PM | |
a8bed8b6 AS |
720 | static int uhci_rh_suspend(struct usb_hcd *hcd) |
721 | { | |
722 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
be3cbc5f | 723 | int rc = 0; |
a8bed8b6 AS |
724 | |
725 | spin_lock_irq(&uhci->lock); | |
541c7d43 | 726 | if (!HCD_HW_ACCESSIBLE(hcd)) |
be3cbc5f | 727 | rc = -ESHUTDOWN; |
cec3a53c AS |
728 | else if (uhci->dead) |
729 | ; /* Dead controllers tell no tales */ | |
730 | ||
731 | /* Once the controller is stopped, port resumes that are already | |
732 | * in progress won't complete. Hence if remote wakeup is enabled | |
733 | * for the root hub and any ports are in the middle of a resume or | |
734 | * remote wakeup, we must fail the suspend. | |
735 | */ | |
736 | else if (hcd->self.root_hub->do_remote_wakeup && | |
737 | uhci->resuming_ports) { | |
3171fcab CG |
738 | dev_dbg(uhci_dev(uhci), |
739 | "suspend failed because a port is resuming\n"); | |
cec3a53c AS |
740 | rc = -EBUSY; |
741 | } else | |
4daaa87c | 742 | suspend_rh(uhci, UHCI_RH_SUSPENDED); |
a8bed8b6 | 743 | spin_unlock_irq(&uhci->lock); |
be3cbc5f | 744 | return rc; |
a8bed8b6 AS |
745 | } |
746 | ||
747 | static int uhci_rh_resume(struct usb_hcd *hcd) | |
748 | { | |
749 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 750 | int rc = 0; |
a8bed8b6 AS |
751 | |
752 | spin_lock_irq(&uhci->lock); | |
541c7d43 | 753 | if (!HCD_HW_ACCESSIBLE(hcd)) |
be3cbc5f | 754 | rc = -ESHUTDOWN; |
cfa59dab | 755 | else if (!uhci->dead) |
4daaa87c | 756 | wakeup_rh(uhci); |
a8bed8b6 | 757 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 758 | return rc; |
a8bed8b6 AS |
759 | } |
760 | ||
1da177e4 LT |
761 | #endif |
762 | ||
dccf4a48 | 763 | /* Wait until a particular device/endpoint's QH is idle, and free it */ |
1da177e4 | 764 | static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, |
dccf4a48 | 765 | struct usb_host_endpoint *hep) |
1da177e4 LT |
766 | { |
767 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
dccf4a48 AS |
768 | struct uhci_qh *qh; |
769 | ||
770 | spin_lock_irq(&uhci->lock); | |
771 | qh = (struct uhci_qh *) hep->hcpriv; | |
772 | if (qh == NULL) | |
773 | goto done; | |
1da177e4 | 774 | |
dccf4a48 AS |
775 | while (qh->state != QH_STATE_IDLE) { |
776 | ++uhci->num_waiting; | |
777 | spin_unlock_irq(&uhci->lock); | |
778 | wait_event_interruptible(uhci->waitqh, | |
779 | qh->state == QH_STATE_IDLE); | |
780 | spin_lock_irq(&uhci->lock); | |
781 | --uhci->num_waiting; | |
782 | } | |
783 | ||
784 | uhci_free_qh(uhci, qh); | |
785 | done: | |
786 | spin_unlock_irq(&uhci->lock); | |
1da177e4 LT |
787 | } |
788 | ||
789 | static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |
790 | { | |
791 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c4334726 AS |
792 | unsigned frame_number; |
793 | unsigned delta; | |
1da177e4 LT |
794 | |
795 | /* Minimize latency by avoiding the spinlock */ | |
c4334726 AS |
796 | frame_number = uhci->frame_number; |
797 | barrier(); | |
9faa091a | 798 | delta = (uhci_readw(uhci, USBFRNUM) - frame_number) & |
c4334726 AS |
799 | (UHCI_NUMFRAMES - 1); |
800 | return frame_number + delta; | |
1da177e4 LT |
801 | } |
802 | ||
c31a65f8 JA |
803 | /* Determines number of ports on controller */ |
804 | static int uhci_count_ports(struct usb_hcd *hcd) | |
805 | { | |
806 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
807 | unsigned io_size = (unsigned) hcd->rsrc_len; | |
808 | int port; | |
1da177e4 | 809 | |
c31a65f8 JA |
810 | /* The UHCI spec says devices must have 2 ports, and goes on to say |
811 | * they may have more but gives no way to determine how many there | |
812 | * are. However according to the UHCI spec, Bit 7 of the port | |
813 | * status and control register is always set to 1. So we try to | |
814 | * use this to our advantage. Another common failure mode when | |
815 | * a nonexistent register is addressed is to return all ones, so | |
816 | * we test for that also. | |
817 | */ | |
818 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | |
819 | unsigned int portstatus; | |
1da177e4 | 820 | |
9faa091a | 821 | portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2)); |
c31a65f8 JA |
822 | if (!(portstatus & 0x0080) || portstatus == 0xffff) |
823 | break; | |
824 | } | |
825 | if (debug) | |
826 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | |
1da177e4 | 827 | |
c31a65f8 JA |
828 | /* Anything greater than 7 is weird so we'll ignore it. */ |
829 | if (port > UHCI_RH_MAXCHILD) { | |
3171fcab CG |
830 | dev_info(uhci_dev(uhci), |
831 | "port count misdetected? forcing to 2 ports\n"); | |
c31a65f8 JA |
832 | port = 2; |
833 | } | |
1da177e4 | 834 | |
c31a65f8 JA |
835 | return port; |
836 | } | |
1da177e4 | 837 | |
c31a65f8 | 838 | static const char hcd_name[] = "uhci_hcd"; |
1da177e4 | 839 | |
3db7739c | 840 | #ifdef CONFIG_PCI |
c31a65f8 | 841 | #include "uhci-pci.c" |
3db7739c JA |
842 | #define PCI_DRIVER uhci_pci_driver |
843 | #endif | |
1da177e4 | 844 | |
3db7739c JA |
845 | #ifdef CONFIG_SPARC_LEON |
846 | #include "uhci-grlib.c" | |
847 | #define PLATFORM_DRIVER uhci_grlib_driver | |
848 | #endif | |
1da177e4 | 849 | |
100d4597 TP |
850 | #ifdef CONFIG_USB_UHCI_PLATFORM |
851 | #include "uhci-platform.c" | |
852 | #define PLATFORM_DRIVER uhci_platform_driver | |
853 | #endif | |
854 | ||
3db7739c JA |
855 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) |
856 | #error "missing bus glue for uhci-hcd" | |
abb30641 | 857 | #endif |
1da177e4 | 858 | |
1da177e4 LT |
859 | static int __init uhci_hcd_init(void) |
860 | { | |
861 | int retval = -ENOMEM; | |
862 | ||
1da177e4 LT |
863 | if (usb_disabled()) |
864 | return -ENODEV; | |
865 | ||
2b70f073 AS |
866 | printk(KERN_INFO "uhci_hcd: " DRIVER_DESC "%s\n", |
867 | ignore_oc ? ", overcurrent ignored" : ""); | |
9beeee65 | 868 | set_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
2b70f073 | 869 | |
1c20163d | 870 | #ifdef CONFIG_DYNAMIC_DEBUG |
cadb3756 ON |
871 | errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); |
872 | if (!errbuf) | |
873 | goto errbuf_failed; | |
874 | uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root); | |
875 | if (!uhci_debugfs_root) | |
876 | goto debug_failed; | |
877 | #endif | |
1da177e4 | 878 | |
1da177e4 | 879 | uhci_up_cachep = kmem_cache_create("uhci_urb_priv", |
20c2df83 | 880 | sizeof(struct urb_priv), 0, 0, NULL); |
1da177e4 LT |
881 | if (!uhci_up_cachep) |
882 | goto up_failed; | |
883 | ||
3db7739c JA |
884 | #ifdef PLATFORM_DRIVER |
885 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
886 | if (retval < 0) | |
887 | goto clean0; | |
888 | #endif | |
889 | ||
890 | #ifdef PCI_DRIVER | |
891 | retval = pci_register_driver(&PCI_DRIVER); | |
892 | if (retval < 0) | |
893 | goto clean1; | |
894 | #endif | |
1da177e4 LT |
895 | |
896 | return 0; | |
897 | ||
3db7739c JA |
898 | #ifdef PCI_DRIVER |
899 | clean1: | |
900 | #endif | |
901 | #ifdef PLATFORM_DRIVER | |
902 | platform_driver_unregister(&PLATFORM_DRIVER); | |
903 | clean0: | |
904 | #endif | |
1a1d92c1 | 905 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 LT |
906 | |
907 | up_failed: | |
cadb3756 | 908 | #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) |
1da177e4 LT |
909 | debugfs_remove(uhci_debugfs_root); |
910 | ||
911 | debug_failed: | |
1bc3c9e1 | 912 | kfree(errbuf); |
1da177e4 LT |
913 | |
914 | errbuf_failed: | |
cadb3756 | 915 | #endif |
1da177e4 | 916 | |
9beeee65 | 917 | clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
1da177e4 LT |
918 | return retval; |
919 | } | |
920 | ||
921 | static void __exit uhci_hcd_cleanup(void) | |
922 | { | |
3db7739c JA |
923 | #ifdef PLATFORM_DRIVER |
924 | platform_driver_unregister(&PLATFORM_DRIVER); | |
925 | #endif | |
926 | #ifdef PCI_DRIVER | |
927 | pci_unregister_driver(&PCI_DRIVER); | |
928 | #endif | |
1a1d92c1 | 929 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 | 930 | debugfs_remove(uhci_debugfs_root); |
1c20163d | 931 | #ifdef CONFIG_DYNAMIC_DEBUG |
1bc3c9e1 | 932 | kfree(errbuf); |
cadb3756 | 933 | #endif |
9beeee65 | 934 | clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
1da177e4 LT |
935 | } |
936 | ||
937 | module_init(uhci_hcd_init); | |
938 | module_exit(uhci_hcd_cleanup); | |
939 | ||
940 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
941 | MODULE_DESCRIPTION(DRIVER_DESC); | |
942 | MODULE_LICENSE("GPL"); |