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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 SS |
69 | #include "xhci.h" |
70 | ||
be88fe4f AX |
71 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, |
72 | struct xhci_virt_device *virt_dev, | |
73 | struct xhci_event_cmd *event); | |
74 | ||
7f84eef0 SS |
75 | /* |
76 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
77 | * address of the TRB. | |
78 | */ | |
23e3be11 | 79 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
80 | union xhci_trb *trb) |
81 | { | |
6071d836 | 82 | unsigned long segment_offset; |
7f84eef0 | 83 | |
6071d836 | 84 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 85 | return 0; |
6071d836 SS |
86 | /* offset in TRBs */ |
87 | segment_offset = trb - seg->trbs; | |
88 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 89 | return 0; |
6071d836 | 90 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
91 | } |
92 | ||
93 | /* Does this link TRB point to the first segment in a ring, | |
94 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
95 | */ | |
96 | static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
97 | struct xhci_segment *seg, union xhci_trb *trb) | |
98 | { | |
99 | if (ring == xhci->event_ring) | |
100 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
101 | (seg->next == xhci->event_ring->first_seg); | |
102 | else | |
103 | return trb->link.control & LINK_TOGGLE; | |
104 | } | |
105 | ||
106 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
107 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
108 | * event seg? | |
109 | */ | |
110 | static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
111 | struct xhci_segment *seg, union xhci_trb *trb) | |
112 | { | |
113 | if (ring == xhci->event_ring) | |
114 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
115 | else | |
116 | return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK); | |
117 | } | |
118 | ||
6c12db90 JY |
119 | static inline int enqueue_is_link_trb(struct xhci_ring *ring) |
120 | { | |
121 | struct xhci_link_trb *link = &ring->enqueue->link; | |
122 | return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)); | |
123 | } | |
124 | ||
ae636747 SS |
125 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
126 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
127 | * effect the ring dequeue or enqueue pointers. | |
128 | */ | |
129 | static void next_trb(struct xhci_hcd *xhci, | |
130 | struct xhci_ring *ring, | |
131 | struct xhci_segment **seg, | |
132 | union xhci_trb **trb) | |
133 | { | |
134 | if (last_trb(xhci, ring, *seg, *trb)) { | |
135 | *seg = (*seg)->next; | |
136 | *trb = ((*seg)->trbs); | |
137 | } else { | |
a1669b2c | 138 | (*trb)++; |
ae636747 SS |
139 | } |
140 | } | |
141 | ||
7f84eef0 SS |
142 | /* |
143 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
144 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
145 | */ | |
146 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) | |
147 | { | |
148 | union xhci_trb *next = ++(ring->dequeue); | |
66e49d87 | 149 | unsigned long long addr; |
7f84eef0 SS |
150 | |
151 | ring->deq_updates++; | |
152 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
153 | * the end of an event ring segment (which doesn't have link TRBS) | |
154 | */ | |
155 | while (last_trb(xhci, ring, ring->deq_seg, next)) { | |
156 | if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) { | |
157 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
158 | if (!in_interrupt()) | |
700e2052 GKH |
159 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
160 | ring, | |
7f84eef0 SS |
161 | (unsigned int) ring->cycle_state); |
162 | } | |
163 | ring->deq_seg = ring->deq_seg->next; | |
164 | ring->dequeue = ring->deq_seg->trbs; | |
165 | next = ring->dequeue; | |
166 | } | |
66e49d87 SS |
167 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
168 | if (ring == xhci->event_ring) | |
169 | xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); | |
170 | else if (ring == xhci->cmd_ring) | |
171 | xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); | |
172 | else | |
173 | xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
174 | } |
175 | ||
176 | /* | |
177 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
178 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
179 | * | |
180 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
181 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
182 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
183 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
184 | * | |
185 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
186 | * set, but other sections talk about dealing with the chain bit set. This was |
187 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
188 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
189 | * |
190 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
191 | * prepare_transfer()? | |
7f84eef0 | 192 | */ |
6cc30d85 SS |
193 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
194 | bool consumer, bool more_trbs_coming) | |
7f84eef0 SS |
195 | { |
196 | u32 chain; | |
197 | union xhci_trb *next; | |
66e49d87 | 198 | unsigned long long addr; |
7f84eef0 SS |
199 | |
200 | chain = ring->enqueue->generic.field[3] & TRB_CHAIN; | |
201 | next = ++(ring->enqueue); | |
202 | ||
203 | ring->enq_updates++; | |
204 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
205 | * the end of an event ring segment (which doesn't have link TRBS) | |
206 | */ | |
207 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
208 | if (!consumer) { | |
209 | if (ring != xhci->event_ring) { | |
6cc30d85 SS |
210 | /* |
211 | * If the caller doesn't plan on enqueueing more | |
212 | * TDs before ringing the doorbell, then we | |
213 | * don't want to give the link TRB to the | |
214 | * hardware just yet. We'll give the link TRB | |
215 | * back in prepare_ring() just before we enqueue | |
216 | * the TD at the top of the ring. | |
217 | */ | |
218 | if (!chain && !more_trbs_coming) | |
6c12db90 | 219 | break; |
6cc30d85 SS |
220 | |
221 | /* If we're not dealing with 0.95 hardware, | |
222 | * carry over the chain bit of the previous TRB | |
223 | * (which may mean the chain bit is cleared). | |
224 | */ | |
225 | if (!xhci_link_trb_quirk(xhci)) { | |
226 | next->link.control &= ~TRB_CHAIN; | |
227 | next->link.control |= chain; | |
b0567b3f | 228 | } |
6cc30d85 SS |
229 | /* Give this link TRB to the hardware */ |
230 | wmb(); | |
231 | next->link.control ^= TRB_CYCLE; | |
7f84eef0 SS |
232 | } |
233 | /* Toggle the cycle bit after the last ring segment. */ | |
234 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
235 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
236 | if (!in_interrupt()) | |
700e2052 GKH |
237 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
238 | ring, | |
7f84eef0 SS |
239 | (unsigned int) ring->cycle_state); |
240 | } | |
241 | } | |
242 | ring->enq_seg = ring->enq_seg->next; | |
243 | ring->enqueue = ring->enq_seg->trbs; | |
244 | next = ring->enqueue; | |
245 | } | |
66e49d87 SS |
246 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
247 | if (ring == xhci->event_ring) | |
248 | xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); | |
249 | else if (ring == xhci->cmd_ring) | |
250 | xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); | |
251 | else | |
252 | xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
253 | } |
254 | ||
255 | /* | |
256 | * Check to see if there's room to enqueue num_trbs on the ring. See rules | |
257 | * above. | |
258 | * FIXME: this would be simpler and faster if we just kept track of the number | |
259 | * of free TRBs in a ring. | |
260 | */ | |
261 | static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
262 | unsigned int num_trbs) | |
263 | { | |
264 | int i; | |
265 | union xhci_trb *enq = ring->enqueue; | |
266 | struct xhci_segment *enq_seg = ring->enq_seg; | |
44ebd037 SS |
267 | struct xhci_segment *cur_seg; |
268 | unsigned int left_on_ring; | |
7f84eef0 | 269 | |
6c12db90 JY |
270 | /* If we are currently pointing to a link TRB, advance the |
271 | * enqueue pointer before checking for space */ | |
272 | while (last_trb(xhci, ring, enq_seg, enq)) { | |
273 | enq_seg = enq_seg->next; | |
274 | enq = enq_seg->trbs; | |
275 | } | |
276 | ||
7f84eef0 | 277 | /* Check if ring is empty */ |
44ebd037 SS |
278 | if (enq == ring->dequeue) { |
279 | /* Can't use link trbs */ | |
280 | left_on_ring = TRBS_PER_SEGMENT - 1; | |
281 | for (cur_seg = enq_seg->next; cur_seg != enq_seg; | |
282 | cur_seg = cur_seg->next) | |
283 | left_on_ring += TRBS_PER_SEGMENT - 1; | |
284 | ||
285 | /* Always need one TRB free in the ring. */ | |
286 | left_on_ring -= 1; | |
287 | if (num_trbs > left_on_ring) { | |
288 | xhci_warn(xhci, "Not enough room on ring; " | |
289 | "need %u TRBs, %u TRBs left\n", | |
290 | num_trbs, left_on_ring); | |
291 | return 0; | |
292 | } | |
7f84eef0 | 293 | return 1; |
44ebd037 | 294 | } |
7f84eef0 SS |
295 | /* Make sure there's an extra empty TRB available */ |
296 | for (i = 0; i <= num_trbs; ++i) { | |
297 | if (enq == ring->dequeue) | |
298 | return 0; | |
299 | enq++; | |
300 | while (last_trb(xhci, ring, enq_seg, enq)) { | |
301 | enq_seg = enq_seg->next; | |
302 | enq = enq_seg->trbs; | |
303 | } | |
304 | } | |
305 | return 1; | |
306 | } | |
307 | ||
7f84eef0 | 308 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 309 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 310 | { |
7f84eef0 | 311 | xhci_dbg(xhci, "// Ding dong!\n"); |
50d64676 | 312 | xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 SS |
313 | /* Flush PCI posted writes */ |
314 | xhci_readl(xhci, &xhci->dba->doorbell[0]); | |
315 | } | |
316 | ||
be88fe4f | 317 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 318 | unsigned int slot_id, |
e9df17eb SS |
319 | unsigned int ep_index, |
320 | unsigned int stream_id) | |
ae636747 | 321 | { |
ae636747 | 322 | __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
323 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
324 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 325 | |
ae636747 | 326 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 327 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
328 | * We don't want to restart any stream rings if there's a set dequeue |
329 | * pointer command pending because the device can choose to start any | |
330 | * stream once the endpoint is on the HW schedule. | |
331 | * FIXME - check all the stream rings for pending cancellations. | |
ae636747 | 332 | */ |
50d64676 MW |
333 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
334 | (ep_state & EP_HALTED)) | |
335 | return; | |
336 | xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr); | |
337 | /* The CPU has better things to do at this point than wait for a | |
338 | * write-posting flush. It'll get there soon enough. | |
339 | */ | |
ae636747 SS |
340 | } |
341 | ||
e9df17eb SS |
342 | /* Ring the doorbell for any rings with pending URBs */ |
343 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
344 | unsigned int slot_id, | |
345 | unsigned int ep_index) | |
346 | { | |
347 | unsigned int stream_id; | |
348 | struct xhci_virt_ep *ep; | |
349 | ||
350 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
351 | ||
352 | /* A ring has pending URBs if its TD list is not empty */ | |
353 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
354 | if (!(list_empty(&ep->ring->td_list))) | |
be88fe4f | 355 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
356 | return; |
357 | } | |
358 | ||
359 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
360 | stream_id++) { | |
361 | struct xhci_stream_info *stream_info = ep->stream_info; | |
362 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
363 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
364 | stream_id); | |
e9df17eb SS |
365 | } |
366 | } | |
367 | ||
ae636747 SS |
368 | /* |
369 | * Find the segment that trb is in. Start searching in start_seg. | |
370 | * If we must move past a segment that has a link TRB with a toggle cycle state | |
371 | * bit set, then we will toggle the value pointed at by cycle_state. | |
372 | */ | |
373 | static struct xhci_segment *find_trb_seg( | |
374 | struct xhci_segment *start_seg, | |
375 | union xhci_trb *trb, int *cycle_state) | |
376 | { | |
377 | struct xhci_segment *cur_seg = start_seg; | |
378 | struct xhci_generic_trb *generic_trb; | |
379 | ||
380 | while (cur_seg->trbs > trb || | |
381 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | |
382 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | |
54b5acf3 AX |
383 | if ((generic_trb->field[3] & TRB_TYPE_BITMASK) == |
384 | TRB_TYPE(TRB_LINK) && | |
ae636747 SS |
385 | (generic_trb->field[3] & LINK_TOGGLE)) |
386 | *cycle_state = ~(*cycle_state) & 0x1; | |
387 | cur_seg = cur_seg->next; | |
388 | if (cur_seg == start_seg) | |
389 | /* Looped over the entire list. Oops! */ | |
326b4810 | 390 | return NULL; |
ae636747 SS |
391 | } |
392 | return cur_seg; | |
393 | } | |
394 | ||
021bff91 SS |
395 | |
396 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
397 | unsigned int slot_id, unsigned int ep_index, | |
398 | unsigned int stream_id) | |
399 | { | |
400 | struct xhci_virt_ep *ep; | |
401 | ||
402 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
403 | /* Common case: no streams */ | |
404 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
405 | return ep->ring; | |
406 | ||
407 | if (stream_id == 0) { | |
408 | xhci_warn(xhci, | |
409 | "WARN: Slot ID %u, ep index %u has streams, " | |
410 | "but URB has no stream ID.\n", | |
411 | slot_id, ep_index); | |
412 | return NULL; | |
413 | } | |
414 | ||
415 | if (stream_id < ep->stream_info->num_streams) | |
416 | return ep->stream_info->stream_rings[stream_id]; | |
417 | ||
418 | xhci_warn(xhci, | |
419 | "WARN: Slot ID %u, ep index %u has " | |
420 | "stream IDs 1 to %u allocated, " | |
421 | "but stream ID %u is requested.\n", | |
422 | slot_id, ep_index, | |
423 | ep->stream_info->num_streams - 1, | |
424 | stream_id); | |
425 | return NULL; | |
426 | } | |
427 | ||
428 | /* Get the right ring for the given URB. | |
429 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
430 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
431 | */ | |
432 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
433 | struct urb *urb) | |
434 | { | |
435 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, | |
436 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); | |
437 | } | |
438 | ||
ae636747 SS |
439 | /* |
440 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
441 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
442 | * dequeue pointer, and new consumer cycle state in state. | |
443 | * Update our internal representation of the ring's dequeue pointer. | |
444 | * | |
445 | * We do this in three jumps: | |
446 | * - First we update our new ring state to be the same as when the xHC stopped. | |
447 | * - Then we traverse the ring to find the segment that contains | |
448 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
449 | * any link TRBs with the toggle cycle bit set. | |
450 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
451 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
452 | */ | |
c92bcfa7 | 453 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 454 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
455 | unsigned int stream_id, struct xhci_td *cur_td, |
456 | struct xhci_dequeue_state *state) | |
ae636747 SS |
457 | { |
458 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
e9df17eb | 459 | struct xhci_ring *ep_ring; |
ae636747 | 460 | struct xhci_generic_trb *trb; |
d115b048 | 461 | struct xhci_ep_ctx *ep_ctx; |
c92bcfa7 | 462 | dma_addr_t addr; |
ae636747 | 463 | |
e9df17eb SS |
464 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
465 | ep_index, stream_id); | |
466 | if (!ep_ring) { | |
467 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
468 | "for invalid stream ID %u.\n", | |
469 | stream_id); | |
470 | return; | |
471 | } | |
ae636747 | 472 | state->new_cycle_state = 0; |
c92bcfa7 | 473 | xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); |
ae636747 | 474 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
63a0d9ab | 475 | dev->eps[ep_index].stopped_trb, |
ae636747 SS |
476 | &state->new_cycle_state); |
477 | if (!state->new_deq_seg) | |
478 | BUG(); | |
479 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ | |
c92bcfa7 | 480 | xhci_dbg(xhci, "Finding endpoint context\n"); |
d115b048 JY |
481 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
482 | state->new_cycle_state = 0x1 & ep_ctx->deq; | |
ae636747 SS |
483 | |
484 | state->new_deq_ptr = cur_td->last_trb; | |
c92bcfa7 | 485 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
ae636747 SS |
486 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
487 | state->new_deq_ptr, | |
488 | &state->new_cycle_state); | |
489 | if (!state->new_deq_seg) | |
490 | BUG(); | |
491 | ||
492 | trb = &state->new_deq_ptr->generic; | |
54b5acf3 | 493 | if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) && |
ae636747 SS |
494 | (trb->field[3] & LINK_TOGGLE)) |
495 | state->new_cycle_state = ~(state->new_cycle_state) & 0x1; | |
496 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); | |
497 | ||
498 | /* Don't update the ring cycle state for the producer (us). */ | |
c92bcfa7 SS |
499 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
500 | state->new_deq_seg); | |
501 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
502 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", | |
503 | (unsigned long long) addr); | |
504 | xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n"); | |
ae636747 SS |
505 | ep_ring->dequeue = state->new_deq_ptr; |
506 | ep_ring->deq_seg = state->new_deq_seg; | |
507 | } | |
508 | ||
23e3be11 | 509 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
ae636747 SS |
510 | struct xhci_td *cur_td) |
511 | { | |
512 | struct xhci_segment *cur_seg; | |
513 | union xhci_trb *cur_trb; | |
514 | ||
515 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
516 | true; | |
517 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
518 | if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) == | |
519 | TRB_TYPE(TRB_LINK)) { | |
520 | /* Unchain any chained Link TRBs, but | |
521 | * leave the pointers intact. | |
522 | */ | |
523 | cur_trb->generic.field[3] &= ~TRB_CHAIN; | |
524 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); | |
700e2052 GKH |
525 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
526 | "in seg %p (0x%llx dma)\n", | |
527 | cur_trb, | |
23e3be11 | 528 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
529 | cur_seg, |
530 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
531 | } else { |
532 | cur_trb->generic.field[0] = 0; | |
533 | cur_trb->generic.field[1] = 0; | |
534 | cur_trb->generic.field[2] = 0; | |
535 | /* Preserve only the cycle bit of this TRB */ | |
536 | cur_trb->generic.field[3] &= TRB_CYCLE; | |
537 | cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP); | |
700e2052 GKH |
538 | xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " |
539 | "in seg %p (0x%llx dma)\n", | |
540 | cur_trb, | |
23e3be11 | 541 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
542 | cur_seg, |
543 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
544 | } |
545 | if (cur_trb == cur_td->last_trb) | |
546 | break; | |
547 | } | |
548 | } | |
549 | ||
550 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
551 | unsigned int ep_index, unsigned int stream_id, |
552 | struct xhci_segment *deq_seg, | |
ae636747 SS |
553 | union xhci_trb *deq_ptr, u32 cycle_state); |
554 | ||
c92bcfa7 | 555 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
63a0d9ab | 556 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb | 557 | unsigned int stream_id, |
63a0d9ab | 558 | struct xhci_dequeue_state *deq_state) |
c92bcfa7 | 559 | { |
63a0d9ab SS |
560 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
561 | ||
c92bcfa7 SS |
562 | xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " |
563 | "new deq ptr = %p (0x%llx dma), new cycle = %u\n", | |
564 | deq_state->new_deq_seg, | |
565 | (unsigned long long)deq_state->new_deq_seg->dma, | |
566 | deq_state->new_deq_ptr, | |
567 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
568 | deq_state->new_cycle_state); | |
e9df17eb | 569 | queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, |
c92bcfa7 SS |
570 | deq_state->new_deq_seg, |
571 | deq_state->new_deq_ptr, | |
572 | (u32) deq_state->new_cycle_state); | |
573 | /* Stop the TD queueing code from ringing the doorbell until | |
574 | * this command completes. The HC won't set the dequeue pointer | |
575 | * if the ring is running, and ringing the doorbell starts the | |
576 | * ring running. | |
577 | */ | |
63a0d9ab | 578 | ep->ep_state |= SET_DEQ_PENDING; |
c92bcfa7 SS |
579 | } |
580 | ||
6f5165cf SS |
581 | static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
582 | struct xhci_virt_ep *ep) | |
583 | { | |
584 | ep->ep_state &= ~EP_HALT_PENDING; | |
585 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
586 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
587 | * (since we didn't successfully stop the watchdog timer). | |
588 | */ | |
589 | if (del_timer(&ep->stop_cmd_timer)) | |
590 | ep->stop_cmds_pending--; | |
591 | } | |
592 | ||
593 | /* Must be called with xhci->lock held in interrupt context */ | |
594 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
595 | struct xhci_td *cur_td, int status, char *adjective) | |
596 | { | |
597 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
8e51adcc AX |
598 | struct urb *urb; |
599 | struct urb_priv *urb_priv; | |
6f5165cf | 600 | |
8e51adcc AX |
601 | urb = cur_td->urb; |
602 | urb_priv = urb->hcpriv; | |
603 | urb_priv->td_cnt++; | |
6f5165cf | 604 | |
8e51adcc AX |
605 | /* Only giveback urb when this is the last td in urb */ |
606 | if (urb_priv->td_cnt == urb_priv->length) { | |
607 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
608 | xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb); | |
609 | ||
610 | spin_unlock(&xhci->lock); | |
611 | usb_hcd_giveback_urb(hcd, urb, status); | |
612 | xhci_urb_free_priv(xhci, urb_priv); | |
613 | spin_lock(&xhci->lock); | |
614 | xhci_dbg(xhci, "%s URB given back\n", adjective); | |
615 | } | |
6f5165cf SS |
616 | } |
617 | ||
ae636747 SS |
618 | /* |
619 | * When we get a command completion for a Stop Endpoint Command, we need to | |
620 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
621 | * | |
622 | * 1. If the HW was in the middle of processing the TD that needs to be | |
623 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
624 | * in the TD with a Set Dequeue Pointer Command. | |
625 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
626 | * bit cleared) so that the HW will skip over them. | |
627 | */ | |
628 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, | |
be88fe4f | 629 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 SS |
630 | { |
631 | unsigned int slot_id; | |
632 | unsigned int ep_index; | |
be88fe4f | 633 | struct xhci_virt_device *virt_dev; |
ae636747 | 634 | struct xhci_ring *ep_ring; |
63a0d9ab | 635 | struct xhci_virt_ep *ep; |
ae636747 | 636 | struct list_head *entry; |
326b4810 | 637 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
638 | struct xhci_td *last_unlinked_td; |
639 | ||
c92bcfa7 | 640 | struct xhci_dequeue_state deq_state; |
ae636747 | 641 | |
be88fe4f AX |
642 | if (unlikely(TRB_TO_SUSPEND_PORT( |
643 | xhci->cmd_ring->dequeue->generic.field[3]))) { | |
644 | slot_id = TRB_TO_SLOT_ID( | |
645 | xhci->cmd_ring->dequeue->generic.field[3]); | |
646 | virt_dev = xhci->devs[slot_id]; | |
647 | if (virt_dev) | |
648 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, | |
649 | event); | |
650 | else | |
651 | xhci_warn(xhci, "Stop endpoint command " | |
652 | "completion for disabled slot %u\n", | |
653 | slot_id); | |
654 | return; | |
655 | } | |
656 | ||
ae636747 SS |
657 | memset(&deq_state, 0, sizeof(deq_state)); |
658 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
659 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
63a0d9ab | 660 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 661 | |
678539cf | 662 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 663 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
e9df17eb | 664 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 665 | return; |
678539cf | 666 | } |
ae636747 SS |
667 | |
668 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
669 | * We have the xHCI lock, so nothing can modify this list until we drop | |
670 | * it. We're also in the event handler, so we can't get re-interrupted | |
671 | * if another Stop Endpoint command completes | |
672 | */ | |
63a0d9ab | 673 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 674 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
700e2052 GKH |
675 | xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n", |
676 | cur_td->first_trb, | |
23e3be11 | 677 | (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb)); |
e9df17eb SS |
678 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
679 | if (!ep_ring) { | |
680 | /* This shouldn't happen unless a driver is mucking | |
681 | * with the stream ID after submission. This will | |
682 | * leave the TD on the hardware ring, and the hardware | |
683 | * will try to execute it, and may access a buffer | |
684 | * that has already been freed. In the best case, the | |
685 | * hardware will execute it, and the event handler will | |
686 | * ignore the completion event for that TD, since it was | |
687 | * removed from the td_list for that endpoint. In | |
688 | * short, don't muck with the stream ID after | |
689 | * submission. | |
690 | */ | |
691 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
692 | "has invalid stream ID %u.\n", | |
693 | cur_td->urb, | |
694 | cur_td->urb->stream_id); | |
695 | goto remove_finished_td; | |
696 | } | |
ae636747 SS |
697 | /* |
698 | * If we stopped on the TD we need to cancel, then we have to | |
699 | * move the xHC endpoint ring dequeue pointer past this TD. | |
700 | */ | |
63a0d9ab | 701 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
702 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
703 | cur_td->urb->stream_id, | |
704 | cur_td, &deq_state); | |
ae636747 SS |
705 | else |
706 | td_to_noop(xhci, ep_ring, cur_td); | |
e9df17eb | 707 | remove_finished_td: |
ae636747 SS |
708 | /* |
709 | * The event handler won't see a completion for this TD anymore, | |
710 | * so remove it from the endpoint ring's TD list. Keep it in | |
711 | * the cancelled TD list for URB completion later. | |
712 | */ | |
713 | list_del(&cur_td->td_list); | |
ae636747 SS |
714 | } |
715 | last_unlinked_td = cur_td; | |
6f5165cf | 716 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
717 | |
718 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
719 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
63a0d9ab | 720 | xhci_queue_new_dequeue_state(xhci, |
e9df17eb SS |
721 | slot_id, ep_index, |
722 | ep->stopped_td->urb->stream_id, | |
723 | &deq_state); | |
ac9d8fe7 | 724 | xhci_ring_cmd_db(xhci); |
ae636747 | 725 | } else { |
e9df17eb SS |
726 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
727 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 728 | } |
1624ae1c SS |
729 | ep->stopped_td = NULL; |
730 | ep->stopped_trb = NULL; | |
ae636747 SS |
731 | |
732 | /* | |
733 | * Drop the lock and complete the URBs in the cancelled TD list. | |
734 | * New TDs to be cancelled might be added to the end of the list before | |
735 | * we can complete all the URBs for the TDs we already unlinked. | |
736 | * So stop when we've completed the URB for the last TD we unlinked. | |
737 | */ | |
738 | do { | |
63a0d9ab | 739 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 SS |
740 | struct xhci_td, cancelled_td_list); |
741 | list_del(&cur_td->cancelled_td_list); | |
742 | ||
743 | /* Clean up the cancelled URB */ | |
ae636747 SS |
744 | /* Doesn't matter what we pass for status, since the core will |
745 | * just overwrite it (because the URB has been unlinked). | |
746 | */ | |
6f5165cf | 747 | xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); |
ae636747 | 748 | |
6f5165cf SS |
749 | /* Stop processing the cancelled list if the watchdog timer is |
750 | * running. | |
751 | */ | |
752 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
753 | return; | |
ae636747 SS |
754 | } while (cur_td != last_unlinked_td); |
755 | ||
756 | /* Return to the event handler with xhci->lock re-acquired */ | |
757 | } | |
758 | ||
6f5165cf SS |
759 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
760 | * In this case, we assume the host controller is broken or dying or dead. The | |
761 | * host may still be completing some other events, so we have to be careful to | |
762 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
763 | * through xhci->state. | |
764 | * | |
765 | * The timer may also fire if the host takes a very long time to respond to the | |
766 | * command, and the stop endpoint command completion handler cannot delete the | |
767 | * timer before the timer function is called. Another endpoint cancellation may | |
768 | * sneak in before the timer function can grab the lock, and that may queue | |
769 | * another stop endpoint command and add the timer back. So we cannot use a | |
770 | * simple flag to say whether there is a pending stop endpoint command for a | |
771 | * particular endpoint. | |
772 | * | |
773 | * Instead we use a combination of that flag and a counter for the number of | |
774 | * pending stop endpoint commands. If the timer is the tail end of the last | |
775 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
776 | * the host is dying. | |
777 | */ | |
778 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
779 | { | |
780 | struct xhci_hcd *xhci; | |
781 | struct xhci_virt_ep *ep; | |
782 | struct xhci_virt_ep *temp_ep; | |
783 | struct xhci_ring *ring; | |
784 | struct xhci_td *cur_td; | |
785 | int ret, i, j; | |
786 | ||
787 | ep = (struct xhci_virt_ep *) arg; | |
788 | xhci = ep->xhci; | |
789 | ||
790 | spin_lock(&xhci->lock); | |
791 | ||
792 | ep->stop_cmds_pending--; | |
793 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
794 | xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " | |
795 | "xHCI as DYING, exiting.\n"); | |
796 | spin_unlock(&xhci->lock); | |
797 | return; | |
798 | } | |
799 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
800 | xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " | |
801 | "exiting.\n"); | |
802 | spin_unlock(&xhci->lock); | |
803 | return; | |
804 | } | |
805 | ||
806 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
807 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
808 | /* Oops, HC is dead or dying or at least not responding to the stop | |
809 | * endpoint command. | |
810 | */ | |
811 | xhci->xhc_state |= XHCI_STATE_DYING; | |
812 | /* Disable interrupts from the host controller and start halting it */ | |
813 | xhci_quiesce(xhci); | |
814 | spin_unlock(&xhci->lock); | |
815 | ||
816 | ret = xhci_halt(xhci); | |
817 | ||
818 | spin_lock(&xhci->lock); | |
819 | if (ret < 0) { | |
820 | /* This is bad; the host is not responding to commands and it's | |
821 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 822 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
823 | * disconnect all device drivers under this host. Those |
824 | * disconnect() methods will wait for all URBs to be unlinked, | |
825 | * so we must complete them. | |
826 | */ | |
827 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
828 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
829 | /* We could turn all TDs on the rings to no-ops. This won't | |
830 | * help if the host has cached part of the ring, and is slow if | |
831 | * we want to preserve the cycle bit. Skip it and hope the host | |
832 | * doesn't touch the memory. | |
833 | */ | |
834 | } | |
835 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
836 | if (!xhci->devs[i]) | |
837 | continue; | |
838 | for (j = 0; j < 31; j++) { | |
839 | temp_ep = &xhci->devs[i]->eps[j]; | |
840 | ring = temp_ep->ring; | |
841 | if (!ring) | |
842 | continue; | |
843 | xhci_dbg(xhci, "Killing URBs for slot ID %u, " | |
844 | "ep index %u\n", i, j); | |
845 | while (!list_empty(&ring->td_list)) { | |
846 | cur_td = list_first_entry(&ring->td_list, | |
847 | struct xhci_td, | |
848 | td_list); | |
849 | list_del(&cur_td->td_list); | |
850 | if (!list_empty(&cur_td->cancelled_td_list)) | |
851 | list_del(&cur_td->cancelled_td_list); | |
852 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
853 | -ESHUTDOWN, "killed"); | |
854 | } | |
855 | while (!list_empty(&temp_ep->cancelled_td_list)) { | |
856 | cur_td = list_first_entry( | |
857 | &temp_ep->cancelled_td_list, | |
858 | struct xhci_td, | |
859 | cancelled_td_list); | |
860 | list_del(&cur_td->cancelled_td_list); | |
861 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
862 | -ESHUTDOWN, "killed"); | |
863 | } | |
864 | } | |
865 | } | |
866 | spin_unlock(&xhci->lock); | |
6f5165cf SS |
867 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); |
868 | usb_hc_died(xhci_to_hcd(xhci)); | |
869 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
870 | } | |
871 | ||
ae636747 SS |
872 | /* |
873 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
874 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
875 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
876 | * endpoint doorbell to restart the ring, but only if there aren't more | |
877 | * cancellations pending. | |
878 | */ | |
879 | static void handle_set_deq_completion(struct xhci_hcd *xhci, | |
880 | struct xhci_event_cmd *event, | |
881 | union xhci_trb *trb) | |
882 | { | |
883 | unsigned int slot_id; | |
884 | unsigned int ep_index; | |
e9df17eb | 885 | unsigned int stream_id; |
ae636747 SS |
886 | struct xhci_ring *ep_ring; |
887 | struct xhci_virt_device *dev; | |
d115b048 JY |
888 | struct xhci_ep_ctx *ep_ctx; |
889 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 SS |
890 | |
891 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
892 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
e9df17eb | 893 | stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]); |
ae636747 | 894 | dev = xhci->devs[slot_id]; |
e9df17eb SS |
895 | |
896 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
897 | if (!ep_ring) { | |
898 | xhci_warn(xhci, "WARN Set TR deq ptr command for " | |
899 | "freed stream ID %u\n", | |
900 | stream_id); | |
901 | /* XXX: Harmless??? */ | |
902 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; | |
903 | return; | |
904 | } | |
905 | ||
d115b048 JY |
906 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
907 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 SS |
908 | |
909 | if (GET_COMP_CODE(event->status) != COMP_SUCCESS) { | |
910 | unsigned int ep_state; | |
911 | unsigned int slot_state; | |
912 | ||
913 | switch (GET_COMP_CODE(event->status)) { | |
914 | case COMP_TRB_ERR: | |
915 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " | |
916 | "of stream ID configuration\n"); | |
917 | break; | |
918 | case COMP_CTX_STATE: | |
919 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " | |
920 | "to incorrect slot or ep state.\n"); | |
d115b048 | 921 | ep_state = ep_ctx->ep_info; |
ae636747 | 922 | ep_state &= EP_STATE_MASK; |
d115b048 | 923 | slot_state = slot_ctx->dev_state; |
ae636747 SS |
924 | slot_state = GET_SLOT_STATE(slot_state); |
925 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", | |
926 | slot_state, ep_state); | |
927 | break; | |
928 | case COMP_EBADSLT: | |
929 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " | |
930 | "slot %u was not enabled.\n", slot_id); | |
931 | break; | |
932 | default: | |
933 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " | |
934 | "completion code of %u.\n", | |
935 | GET_COMP_CODE(event->status)); | |
936 | break; | |
937 | } | |
938 | /* OK what do we do now? The endpoint state is hosed, and we | |
939 | * should never get to this point if the synchronization between | |
940 | * queueing, and endpoint state are correct. This might happen | |
941 | * if the device gets disconnected after we've finished | |
942 | * cancelling URBs, which might not be an error... | |
943 | */ | |
944 | } else { | |
8e595a5d | 945 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
d115b048 | 946 | ep_ctx->deq); |
ae636747 SS |
947 | } |
948 | ||
63a0d9ab | 949 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
e9df17eb SS |
950 | /* Restart any rings with pending URBs */ |
951 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
952 | } |
953 | ||
a1587d97 SS |
954 | static void handle_reset_ep_completion(struct xhci_hcd *xhci, |
955 | struct xhci_event_cmd *event, | |
956 | union xhci_trb *trb) | |
957 | { | |
958 | int slot_id; | |
959 | unsigned int ep_index; | |
960 | ||
961 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
962 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
963 | /* This command will only fail if the endpoint wasn't halted, | |
964 | * but we don't care. | |
965 | */ | |
966 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", | |
967 | (unsigned int) GET_COMP_CODE(event->status)); | |
968 | ||
ac9d8fe7 SS |
969 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
970 | * command complete before the endpoint can be used. Queue that here | |
971 | * because the HW can't handle two commands being queued in a row. | |
972 | */ | |
973 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
974 | xhci_dbg(xhci, "Queueing configure endpoint command\n"); | |
975 | xhci_queue_configure_endpoint(xhci, | |
913a8a34 SS |
976 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
977 | false); | |
ac9d8fe7 SS |
978 | xhci_ring_cmd_db(xhci); |
979 | } else { | |
e9df17eb | 980 | /* Clear our internal halted state and restart the ring(s) */ |
63a0d9ab | 981 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
e9df17eb | 982 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ac9d8fe7 | 983 | } |
a1587d97 | 984 | } |
ae636747 | 985 | |
a50c8aa9 SS |
986 | /* Check to see if a command in the device's command queue matches this one. |
987 | * Signal the completion or free the command, and return 1. Return 0 if the | |
988 | * completed command isn't at the head of the command list. | |
989 | */ | |
990 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
991 | struct xhci_virt_device *virt_dev, | |
992 | struct xhci_event_cmd *event) | |
993 | { | |
994 | struct xhci_command *command; | |
995 | ||
996 | if (list_empty(&virt_dev->cmd_list)) | |
997 | return 0; | |
998 | ||
999 | command = list_entry(virt_dev->cmd_list.next, | |
1000 | struct xhci_command, cmd_list); | |
1001 | if (xhci->cmd_ring->dequeue != command->command_trb) | |
1002 | return 0; | |
1003 | ||
1004 | command->status = | |
1005 | GET_COMP_CODE(event->status); | |
1006 | list_del(&command->cmd_list); | |
1007 | if (command->completion) | |
1008 | complete(command->completion); | |
1009 | else | |
1010 | xhci_free_command(xhci, command); | |
1011 | return 1; | |
1012 | } | |
1013 | ||
7f84eef0 SS |
1014 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1015 | struct xhci_event_cmd *event) | |
1016 | { | |
3ffbba95 | 1017 | int slot_id = TRB_TO_SLOT_ID(event->flags); |
7f84eef0 SS |
1018 | u64 cmd_dma; |
1019 | dma_addr_t cmd_dequeue_dma; | |
ac9d8fe7 | 1020 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 1021 | struct xhci_virt_device *virt_dev; |
ac9d8fe7 SS |
1022 | unsigned int ep_index; |
1023 | struct xhci_ring *ep_ring; | |
1024 | unsigned int ep_state; | |
7f84eef0 | 1025 | |
8e595a5d | 1026 | cmd_dma = event->cmd_trb; |
23e3be11 | 1027 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
7f84eef0 SS |
1028 | xhci->cmd_ring->dequeue); |
1029 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ | |
1030 | if (cmd_dequeue_dma == 0) { | |
1031 | xhci->error_bitmask |= 1 << 4; | |
1032 | return; | |
1033 | } | |
1034 | /* Does the DMA address match our internal dequeue pointer address? */ | |
1035 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
1036 | xhci->error_bitmask |= 1 << 5; | |
1037 | return; | |
1038 | } | |
1039 | switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) { | |
3ffbba95 SS |
1040 | case TRB_TYPE(TRB_ENABLE_SLOT): |
1041 | if (GET_COMP_CODE(event->status) == COMP_SUCCESS) | |
1042 | xhci->slot_id = slot_id; | |
1043 | else | |
1044 | xhci->slot_id = 0; | |
1045 | complete(&xhci->addr_dev); | |
1046 | break; | |
1047 | case TRB_TYPE(TRB_DISABLE_SLOT): | |
1048 | if (xhci->devs[slot_id]) | |
1049 | xhci_free_virt_device(xhci, slot_id); | |
1050 | break; | |
f94e0186 | 1051 | case TRB_TYPE(TRB_CONFIG_EP): |
913a8a34 | 1052 | virt_dev = xhci->devs[slot_id]; |
a50c8aa9 | 1053 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
913a8a34 | 1054 | break; |
ac9d8fe7 SS |
1055 | /* |
1056 | * Configure endpoint commands can come from the USB core | |
1057 | * configuration or alt setting changes, or because the HW | |
1058 | * needed an extra configure endpoint command after a reset | |
8df75f42 SS |
1059 | * endpoint command or streams were being configured. |
1060 | * If the command was for a halted endpoint, the xHCI driver | |
1061 | * is not waiting on the configure endpoint command. | |
ac9d8fe7 SS |
1062 | */ |
1063 | ctrl_ctx = xhci_get_input_control_ctx(xhci, | |
913a8a34 | 1064 | virt_dev->in_ctx); |
ac9d8fe7 SS |
1065 | /* Input ctx add_flags are the endpoint index plus one */ |
1066 | ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1; | |
06df5729 | 1067 | /* A usb_set_interface() call directly after clearing a halted |
e9df17eb SS |
1068 | * condition may race on this quirky hardware. Not worth |
1069 | * worrying about, since this is prototype hardware. Not sure | |
1070 | * if this will work for streams, but streams support was | |
1071 | * untested on this prototype. | |
06df5729 | 1072 | */ |
ac9d8fe7 | 1073 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
06df5729 SS |
1074 | ep_index != (unsigned int) -1 && |
1075 | ctrl_ctx->add_flags - SLOT_FLAG == | |
1076 | ctrl_ctx->drop_flags) { | |
1077 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
1078 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
1079 | if (!(ep_state & EP_HALTED)) | |
1080 | goto bandwidth_change; | |
1081 | xhci_dbg(xhci, "Completed config ep cmd - " | |
1082 | "last ep index = %d, state = %d\n", | |
1083 | ep_index, ep_state); | |
e9df17eb | 1084 | /* Clear internal halted state and restart ring(s) */ |
63a0d9ab | 1085 | xhci->devs[slot_id]->eps[ep_index].ep_state &= |
ac9d8fe7 | 1086 | ~EP_HALTED; |
e9df17eb | 1087 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
06df5729 | 1088 | break; |
ac9d8fe7 | 1089 | } |
06df5729 SS |
1090 | bandwidth_change: |
1091 | xhci_dbg(xhci, "Completed config ep cmd\n"); | |
1092 | xhci->devs[slot_id]->cmd_status = | |
1093 | GET_COMP_CODE(event->status); | |
1094 | complete(&xhci->devs[slot_id]->cmd_completion); | |
f94e0186 | 1095 | break; |
2d3f1fac | 1096 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
ac1c1b7f SS |
1097 | virt_dev = xhci->devs[slot_id]; |
1098 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
1099 | break; | |
2d3f1fac SS |
1100 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); |
1101 | complete(&xhci->devs[slot_id]->cmd_completion); | |
1102 | break; | |
3ffbba95 SS |
1103 | case TRB_TYPE(TRB_ADDR_DEV): |
1104 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); | |
1105 | complete(&xhci->addr_dev); | |
1106 | break; | |
ae636747 | 1107 | case TRB_TYPE(TRB_STOP_RING): |
be88fe4f | 1108 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event); |
ae636747 SS |
1109 | break; |
1110 | case TRB_TYPE(TRB_SET_DEQ): | |
1111 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); | |
1112 | break; | |
7f84eef0 | 1113 | case TRB_TYPE(TRB_CMD_NOOP): |
7f84eef0 | 1114 | break; |
a1587d97 SS |
1115 | case TRB_TYPE(TRB_RESET_EP): |
1116 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); | |
1117 | break; | |
2a8f82c4 SS |
1118 | case TRB_TYPE(TRB_RESET_DEV): |
1119 | xhci_dbg(xhci, "Completed reset device command.\n"); | |
1120 | slot_id = TRB_TO_SLOT_ID( | |
1121 | xhci->cmd_ring->dequeue->generic.field[3]); | |
1122 | virt_dev = xhci->devs[slot_id]; | |
1123 | if (virt_dev) | |
1124 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); | |
1125 | else | |
1126 | xhci_warn(xhci, "Reset device command completion " | |
1127 | "for disabled slot %u\n", slot_id); | |
1128 | break; | |
0238634d SS |
1129 | case TRB_TYPE(TRB_NEC_GET_FW): |
1130 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1131 | xhci->error_bitmask |= 1 << 6; | |
1132 | break; | |
1133 | } | |
1134 | xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", | |
1135 | NEC_FW_MAJOR(event->status), | |
1136 | NEC_FW_MINOR(event->status)); | |
1137 | break; | |
7f84eef0 SS |
1138 | default: |
1139 | /* Skip over unknown commands on the event ring */ | |
1140 | xhci->error_bitmask |= 1 << 6; | |
1141 | break; | |
1142 | } | |
1143 | inc_deq(xhci, xhci->cmd_ring, false); | |
1144 | } | |
1145 | ||
0238634d SS |
1146 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1147 | union xhci_trb *event) | |
1148 | { | |
1149 | u32 trb_type; | |
1150 | ||
1151 | trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]); | |
1152 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); | |
1153 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1154 | handle_cmd_completion(xhci, &event->event_cmd); | |
1155 | } | |
1156 | ||
0f2a7930 SS |
1157 | static void handle_port_status(struct xhci_hcd *xhci, |
1158 | union xhci_trb *event) | |
1159 | { | |
56192531 | 1160 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
0f2a7930 | 1161 | u32 port_id; |
56192531 AX |
1162 | u32 temp, temp1; |
1163 | u32 __iomem *addr; | |
518e848e | 1164 | int max_ports; |
56192531 | 1165 | int slot_id; |
0f2a7930 SS |
1166 | |
1167 | /* Port status change events always have a successful completion code */ | |
1168 | if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) { | |
1169 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); | |
1170 | xhci->error_bitmask |= 1 << 8; | |
1171 | } | |
0f2a7930 SS |
1172 | port_id = GET_PORT_ID(event->generic.field[0]); |
1173 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); | |
1174 | ||
518e848e SS |
1175 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1176 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 AX |
1177 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
1178 | goto cleanup; | |
1179 | } | |
1180 | ||
1181 | addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS * (port_id - 1); | |
1182 | temp = xhci_readl(xhci, addr); | |
7111ebc9 | 1183 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1184 | xhci_dbg(xhci, "resume root hub\n"); |
1185 | usb_hcd_resume_root_hub(hcd); | |
1186 | } | |
1187 | ||
1188 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { | |
1189 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1190 | ||
1191 | temp1 = xhci_readl(xhci, &xhci->op_regs->command); | |
1192 | if (!(temp1 & CMD_RUN)) { | |
1193 | xhci_warn(xhci, "xHC is not running.\n"); | |
1194 | goto cleanup; | |
1195 | } | |
1196 | ||
1197 | if (DEV_SUPERSPEED(temp)) { | |
1198 | xhci_dbg(xhci, "resume SS port %d\n", port_id); | |
1199 | temp = xhci_port_state_to_neutral(temp); | |
1200 | temp &= ~PORT_PLS_MASK; | |
1201 | temp |= PORT_LINK_STROBE | XDEV_U0; | |
1202 | xhci_writel(xhci, temp, addr); | |
1203 | slot_id = xhci_find_slot_id_by_port(xhci, port_id); | |
1204 | if (!slot_id) { | |
1205 | xhci_dbg(xhci, "slot_id is zero\n"); | |
1206 | goto cleanup; | |
1207 | } | |
1208 | xhci_ring_device(xhci, slot_id); | |
1209 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); | |
1210 | /* Clear PORT_PLC */ | |
1211 | temp = xhci_readl(xhci, addr); | |
1212 | temp = xhci_port_state_to_neutral(temp); | |
1213 | temp |= PORT_PLC; | |
1214 | xhci_writel(xhci, temp, addr); | |
1215 | } else { | |
1216 | xhci_dbg(xhci, "resume HS port %d\n", port_id); | |
1217 | xhci->resume_done[port_id - 1] = jiffies + | |
1218 | msecs_to_jiffies(20); | |
1219 | mod_timer(&hcd->rh_timer, | |
1220 | xhci->resume_done[port_id - 1]); | |
1221 | /* Do the rest in GetPortStatus */ | |
1222 | } | |
1223 | } | |
1224 | ||
1225 | cleanup: | |
0f2a7930 SS |
1226 | /* Update event ring dequeue pointer before dropping the lock */ |
1227 | inc_deq(xhci, xhci->event_ring, true); | |
0f2a7930 SS |
1228 | |
1229 | spin_unlock(&xhci->lock); | |
1230 | /* Pass this up to the core */ | |
1231 | usb_hcd_poll_rh_status(xhci_to_hcd(xhci)); | |
1232 | spin_lock(&xhci->lock); | |
1233 | } | |
1234 | ||
d0e96f5a SS |
1235 | /* |
1236 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1237 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1238 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1239 | * returns 0. | |
1240 | */ | |
6648f29d | 1241 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
1242 | union xhci_trb *start_trb, |
1243 | union xhci_trb *end_trb, | |
1244 | dma_addr_t suspect_dma) | |
1245 | { | |
1246 | dma_addr_t start_dma; | |
1247 | dma_addr_t end_seg_dma; | |
1248 | dma_addr_t end_trb_dma; | |
1249 | struct xhci_segment *cur_seg; | |
1250 | ||
23e3be11 | 1251 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1252 | cur_seg = start_seg; |
1253 | ||
1254 | do { | |
2fa88daa | 1255 | if (start_dma == 0) |
326b4810 | 1256 | return NULL; |
ae636747 | 1257 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1258 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1259 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1260 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1261 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1262 | |
1263 | if (end_trb_dma > 0) { | |
1264 | /* The end TRB is in this segment, so suspect should be here */ | |
1265 | if (start_dma <= end_trb_dma) { | |
1266 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1267 | return cur_seg; | |
1268 | } else { | |
1269 | /* Case for one segment with | |
1270 | * a TD wrapped around to the top | |
1271 | */ | |
1272 | if ((suspect_dma >= start_dma && | |
1273 | suspect_dma <= end_seg_dma) || | |
1274 | (suspect_dma >= cur_seg->dma && | |
1275 | suspect_dma <= end_trb_dma)) | |
1276 | return cur_seg; | |
1277 | } | |
326b4810 | 1278 | return NULL; |
d0e96f5a SS |
1279 | } else { |
1280 | /* Might still be somewhere in this segment */ | |
1281 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1282 | return cur_seg; | |
1283 | } | |
1284 | cur_seg = cur_seg->next; | |
23e3be11 | 1285 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1286 | } while (cur_seg != start_seg); |
d0e96f5a | 1287 | |
326b4810 | 1288 | return NULL; |
d0e96f5a SS |
1289 | } |
1290 | ||
bcef3fd5 SS |
1291 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1292 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1293 | unsigned int stream_id, |
bcef3fd5 SS |
1294 | struct xhci_td *td, union xhci_trb *event_trb) |
1295 | { | |
1296 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1297 | ep->ep_state |= EP_HALTED; | |
1298 | ep->stopped_td = td; | |
1299 | ep->stopped_trb = event_trb; | |
e9df17eb | 1300 | ep->stopped_stream = stream_id; |
1624ae1c | 1301 | |
bcef3fd5 SS |
1302 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
1303 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); | |
1624ae1c SS |
1304 | |
1305 | ep->stopped_td = NULL; | |
1306 | ep->stopped_trb = NULL; | |
5e5cf6fc | 1307 | ep->stopped_stream = 0; |
1624ae1c | 1308 | |
bcef3fd5 SS |
1309 | xhci_ring_cmd_db(xhci); |
1310 | } | |
1311 | ||
1312 | /* Check if an error has halted the endpoint ring. The class driver will | |
1313 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1314 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1315 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1316 | * Ring Dequeue Pointer command manually. | |
1317 | */ | |
1318 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1319 | struct xhci_ep_ctx *ep_ctx, | |
1320 | unsigned int trb_comp_code) | |
1321 | { | |
1322 | /* TRB completion codes that may require a manual halt cleanup */ | |
1323 | if (trb_comp_code == COMP_TX_ERR || | |
1324 | trb_comp_code == COMP_BABBLE || | |
1325 | trb_comp_code == COMP_SPLIT_ERR) | |
1326 | /* The 0.96 spec says a babbling control endpoint | |
1327 | * is not halted. The 0.96 spec says it is. Some HW | |
1328 | * claims to be 0.95 compliant, but it halts the control | |
1329 | * endpoint anyway. Check if a babble halted the | |
1330 | * endpoint. | |
1331 | */ | |
1332 | if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED) | |
1333 | return 1; | |
1334 | ||
1335 | return 0; | |
1336 | } | |
1337 | ||
b45b5069 SS |
1338 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1339 | { | |
1340 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1341 | /* Vendor defined "informational" completion code, | |
1342 | * treat as not-an-error. | |
1343 | */ | |
1344 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1345 | trb_comp_code); | |
1346 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1347 | return 1; | |
1348 | } | |
1349 | return 0; | |
1350 | } | |
1351 | ||
4422da61 AX |
1352 | /* |
1353 | * Finish the td processing, remove the td from td list; | |
1354 | * Return 1 if the urb can be given back. | |
1355 | */ | |
1356 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1357 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1358 | struct xhci_virt_ep *ep, int *status, bool skip) | |
1359 | { | |
1360 | struct xhci_virt_device *xdev; | |
1361 | struct xhci_ring *ep_ring; | |
1362 | unsigned int slot_id; | |
1363 | int ep_index; | |
1364 | struct urb *urb = NULL; | |
1365 | struct xhci_ep_ctx *ep_ctx; | |
1366 | int ret = 0; | |
8e51adcc | 1367 | struct urb_priv *urb_priv; |
4422da61 AX |
1368 | u32 trb_comp_code; |
1369 | ||
1370 | slot_id = TRB_TO_SLOT_ID(event->flags); | |
1371 | xdev = xhci->devs[slot_id]; | |
1372 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | |
1373 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | |
1374 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
1375 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | |
1376 | ||
1377 | if (skip) | |
1378 | goto td_cleanup; | |
1379 | ||
1380 | if (trb_comp_code == COMP_STOP_INVAL || | |
1381 | trb_comp_code == COMP_STOP) { | |
1382 | /* The Endpoint Stop Command completion will take care of any | |
1383 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1384 | * the ring dequeue pointer or take this TD off any lists yet. | |
1385 | */ | |
1386 | ep->stopped_td = td; | |
1387 | ep->stopped_trb = event_trb; | |
1388 | return 0; | |
1389 | } else { | |
1390 | if (trb_comp_code == COMP_STALL) { | |
1391 | /* The transfer is completed from the driver's | |
1392 | * perspective, but we need to issue a set dequeue | |
1393 | * command for this stalled endpoint to move the dequeue | |
1394 | * pointer past the TD. We can't do that here because | |
1395 | * the halt condition must be cleared first. Let the | |
1396 | * USB class driver clear the stall later. | |
1397 | */ | |
1398 | ep->stopped_td = td; | |
1399 | ep->stopped_trb = event_trb; | |
1400 | ep->stopped_stream = ep_ring->stream_id; | |
1401 | } else if (xhci_requires_manual_halt_cleanup(xhci, | |
1402 | ep_ctx, trb_comp_code)) { | |
1403 | /* Other types of errors halt the endpoint, but the | |
1404 | * class driver doesn't call usb_reset_endpoint() unless | |
1405 | * the error is -EPIPE. Clear the halted status in the | |
1406 | * xHCI hardware manually. | |
1407 | */ | |
1408 | xhci_cleanup_halted_endpoint(xhci, | |
1409 | slot_id, ep_index, ep_ring->stream_id, | |
1410 | td, event_trb); | |
1411 | } else { | |
1412 | /* Update ring dequeue pointer */ | |
1413 | while (ep_ring->dequeue != td->last_trb) | |
1414 | inc_deq(xhci, ep_ring, false); | |
1415 | inc_deq(xhci, ep_ring, false); | |
1416 | } | |
1417 | ||
1418 | td_cleanup: | |
1419 | /* Clean up the endpoint's TD list */ | |
1420 | urb = td->urb; | |
8e51adcc | 1421 | urb_priv = urb->hcpriv; |
4422da61 AX |
1422 | |
1423 | /* Do one last check of the actual transfer length. | |
1424 | * If the host controller said we transferred more data than | |
1425 | * the buffer length, urb->actual_length will be a very big | |
1426 | * number (since it's unsigned). Play it safe and say we didn't | |
1427 | * transfer anything. | |
1428 | */ | |
1429 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1430 | xhci_warn(xhci, "URB transfer length is wrong, " | |
1431 | "xHC issue? req. len = %u, " | |
1432 | "act. len = %u\n", | |
1433 | urb->transfer_buffer_length, | |
1434 | urb->actual_length); | |
1435 | urb->actual_length = 0; | |
1436 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1437 | *status = -EREMOTEIO; | |
1438 | else | |
1439 | *status = 0; | |
1440 | } | |
1441 | list_del(&td->td_list); | |
1442 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1443 | if (!list_empty(&td->cancelled_td_list)) | |
1444 | list_del(&td->cancelled_td_list); | |
1445 | ||
8e51adcc AX |
1446 | urb_priv->td_cnt++; |
1447 | /* Giveback the urb when all the tds are completed */ | |
1448 | if (urb_priv->td_cnt == urb_priv->length) | |
1449 | ret = 1; | |
4422da61 AX |
1450 | } |
1451 | ||
1452 | return ret; | |
1453 | } | |
1454 | ||
8af56be1 AX |
1455 | /* |
1456 | * Process control tds, update urb status and actual_length. | |
1457 | */ | |
1458 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1459 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1460 | struct xhci_virt_ep *ep, int *status) | |
1461 | { | |
1462 | struct xhci_virt_device *xdev; | |
1463 | struct xhci_ring *ep_ring; | |
1464 | unsigned int slot_id; | |
1465 | int ep_index; | |
1466 | struct xhci_ep_ctx *ep_ctx; | |
1467 | u32 trb_comp_code; | |
1468 | ||
1469 | slot_id = TRB_TO_SLOT_ID(event->flags); | |
1470 | xdev = xhci->devs[slot_id]; | |
1471 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | |
1472 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | |
1473 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
1474 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | |
1475 | ||
1476 | xhci_debug_trb(xhci, xhci->event_ring->dequeue); | |
1477 | switch (trb_comp_code) { | |
1478 | case COMP_SUCCESS: | |
1479 | if (event_trb == ep_ring->dequeue) { | |
1480 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " | |
1481 | "without IOC set??\n"); | |
1482 | *status = -ESHUTDOWN; | |
1483 | } else if (event_trb != td->last_trb) { | |
1484 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " | |
1485 | "without IOC set??\n"); | |
1486 | *status = -ESHUTDOWN; | |
1487 | } else { | |
1488 | xhci_dbg(xhci, "Successful control transfer!\n"); | |
1489 | *status = 0; | |
1490 | } | |
1491 | break; | |
1492 | case COMP_SHORT_TX: | |
1493 | xhci_warn(xhci, "WARN: short transfer on control ep\n"); | |
1494 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1495 | *status = -EREMOTEIO; | |
1496 | else | |
1497 | *status = 0; | |
1498 | break; | |
1499 | default: | |
1500 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
1501 | ep_ctx, trb_comp_code)) | |
1502 | break; | |
1503 | xhci_dbg(xhci, "TRB error code %u, " | |
1504 | "halted endpoint index = %u\n", | |
1505 | trb_comp_code, ep_index); | |
1506 | /* else fall through */ | |
1507 | case COMP_STALL: | |
1508 | /* Did we transfer part of the data (middle) phase? */ | |
1509 | if (event_trb != ep_ring->dequeue && | |
1510 | event_trb != td->last_trb) | |
1511 | td->urb->actual_length = | |
1512 | td->urb->transfer_buffer_length | |
1513 | - TRB_LEN(event->transfer_len); | |
1514 | else | |
1515 | td->urb->actual_length = 0; | |
1516 | ||
1517 | xhci_cleanup_halted_endpoint(xhci, | |
1518 | slot_id, ep_index, 0, td, event_trb); | |
1519 | return finish_td(xhci, td, event_trb, event, ep, status, true); | |
1520 | } | |
1521 | /* | |
1522 | * Did we transfer any data, despite the errors that might have | |
1523 | * happened? I.e. did we get past the setup stage? | |
1524 | */ | |
1525 | if (event_trb != ep_ring->dequeue) { | |
1526 | /* The event was for the status stage */ | |
1527 | if (event_trb == td->last_trb) { | |
1528 | if (td->urb->actual_length != 0) { | |
1529 | /* Don't overwrite a previously set error code | |
1530 | */ | |
1531 | if ((*status == -EINPROGRESS || *status == 0) && | |
1532 | (td->urb->transfer_flags | |
1533 | & URB_SHORT_NOT_OK)) | |
1534 | /* Did we already see a short data | |
1535 | * stage? */ | |
1536 | *status = -EREMOTEIO; | |
1537 | } else { | |
1538 | td->urb->actual_length = | |
1539 | td->urb->transfer_buffer_length; | |
1540 | } | |
1541 | } else { | |
1542 | /* Maybe the event was for the data stage? */ | |
1543 | if (trb_comp_code != COMP_STOP_INVAL) { | |
1544 | /* We didn't stop on a link TRB in the middle */ | |
1545 | td->urb->actual_length = | |
1546 | td->urb->transfer_buffer_length - | |
1547 | TRB_LEN(event->transfer_len); | |
1548 | xhci_dbg(xhci, "Waiting for status " | |
1549 | "stage event\n"); | |
1550 | return 0; | |
1551 | } | |
1552 | } | |
1553 | } | |
1554 | ||
1555 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1556 | } | |
1557 | ||
04e51901 AX |
1558 | /* |
1559 | * Process isochronous tds, update urb packet status and actual_length. | |
1560 | */ | |
1561 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1562 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1563 | struct xhci_virt_ep *ep, int *status) | |
1564 | { | |
1565 | struct xhci_ring *ep_ring; | |
1566 | struct urb_priv *urb_priv; | |
1567 | int idx; | |
1568 | int len = 0; | |
1569 | int skip_td = 0; | |
1570 | union xhci_trb *cur_trb; | |
1571 | struct xhci_segment *cur_seg; | |
1572 | u32 trb_comp_code; | |
1573 | ||
1574 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | |
1575 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | |
1576 | urb_priv = td->urb->hcpriv; | |
1577 | idx = urb_priv->td_cnt; | |
1578 | ||
1579 | if (ep->skip) { | |
1580 | /* The transfer is partly done */ | |
1581 | *status = -EXDEV; | |
1582 | td->urb->iso_frame_desc[idx].status = -EXDEV; | |
1583 | } else { | |
1584 | /* handle completion code */ | |
1585 | switch (trb_comp_code) { | |
1586 | case COMP_SUCCESS: | |
1587 | td->urb->iso_frame_desc[idx].status = 0; | |
1588 | xhci_dbg(xhci, "Successful isoc transfer!\n"); | |
1589 | break; | |
1590 | case COMP_SHORT_TX: | |
1591 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1592 | td->urb->iso_frame_desc[idx].status = | |
1593 | -EREMOTEIO; | |
1594 | else | |
1595 | td->urb->iso_frame_desc[idx].status = 0; | |
1596 | break; | |
1597 | case COMP_BW_OVER: | |
1598 | td->urb->iso_frame_desc[idx].status = -ECOMM; | |
1599 | skip_td = 1; | |
1600 | break; | |
1601 | case COMP_BUFF_OVER: | |
1602 | case COMP_BABBLE: | |
1603 | td->urb->iso_frame_desc[idx].status = -EOVERFLOW; | |
1604 | skip_td = 1; | |
1605 | break; | |
1606 | case COMP_STALL: | |
1607 | td->urb->iso_frame_desc[idx].status = -EPROTO; | |
1608 | skip_td = 1; | |
1609 | break; | |
1610 | case COMP_STOP: | |
1611 | case COMP_STOP_INVAL: | |
1612 | break; | |
1613 | default: | |
1614 | td->urb->iso_frame_desc[idx].status = -1; | |
1615 | break; | |
1616 | } | |
1617 | } | |
1618 | ||
1619 | /* calc actual length */ | |
1620 | if (ep->skip) { | |
1621 | td->urb->iso_frame_desc[idx].actual_length = 0; | |
14184f9b AX |
1622 | /* Update ring dequeue pointer */ |
1623 | while (ep_ring->dequeue != td->last_trb) | |
1624 | inc_deq(xhci, ep_ring, false); | |
1625 | inc_deq(xhci, ep_ring, false); | |
04e51901 AX |
1626 | return finish_td(xhci, td, event_trb, event, ep, status, true); |
1627 | } | |
1628 | ||
1629 | if (trb_comp_code == COMP_SUCCESS || skip_td == 1) { | |
1630 | td->urb->iso_frame_desc[idx].actual_length = | |
1631 | td->urb->iso_frame_desc[idx].length; | |
1632 | td->urb->actual_length += | |
1633 | td->urb->iso_frame_desc[idx].length; | |
1634 | } else { | |
1635 | for (cur_trb = ep_ring->dequeue, | |
1636 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | |
1637 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
1638 | if ((cur_trb->generic.field[3] & | |
1639 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && | |
1640 | (cur_trb->generic.field[3] & | |
1641 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) | |
1642 | len += | |
1643 | TRB_LEN(cur_trb->generic.field[2]); | |
1644 | } | |
1645 | len += TRB_LEN(cur_trb->generic.field[2]) - | |
1646 | TRB_LEN(event->transfer_len); | |
1647 | ||
1648 | if (trb_comp_code != COMP_STOP_INVAL) { | |
1649 | td->urb->iso_frame_desc[idx].actual_length = len; | |
1650 | td->urb->actual_length += len; | |
1651 | } | |
1652 | } | |
1653 | ||
1654 | if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS) | |
1655 | *status = 0; | |
1656 | ||
1657 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1658 | } | |
1659 | ||
22405ed2 AX |
1660 | /* |
1661 | * Process bulk and interrupt tds, update urb status and actual_length. | |
1662 | */ | |
1663 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1664 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1665 | struct xhci_virt_ep *ep, int *status) | |
1666 | { | |
1667 | struct xhci_ring *ep_ring; | |
1668 | union xhci_trb *cur_trb; | |
1669 | struct xhci_segment *cur_seg; | |
1670 | u32 trb_comp_code; | |
1671 | ||
1672 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | |
1673 | trb_comp_code = GET_COMP_CODE(event->transfer_len); | |
1674 | ||
1675 | switch (trb_comp_code) { | |
1676 | case COMP_SUCCESS: | |
1677 | /* Double check that the HW transferred everything. */ | |
1678 | if (event_trb != td->last_trb) { | |
1679 | xhci_warn(xhci, "WARN Successful completion " | |
1680 | "on short TX\n"); | |
1681 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1682 | *status = -EREMOTEIO; | |
1683 | else | |
1684 | *status = 0; | |
1685 | } else { | |
1686 | if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) | |
1687 | xhci_dbg(xhci, "Successful bulk " | |
1688 | "transfer!\n"); | |
1689 | else | |
1690 | xhci_dbg(xhci, "Successful interrupt " | |
1691 | "transfer!\n"); | |
1692 | *status = 0; | |
1693 | } | |
1694 | break; | |
1695 | case COMP_SHORT_TX: | |
1696 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1697 | *status = -EREMOTEIO; | |
1698 | else | |
1699 | *status = 0; | |
1700 | break; | |
1701 | default: | |
1702 | /* Others already handled above */ | |
1703 | break; | |
1704 | } | |
f2c565e2 | 1705 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " |
22405ed2 AX |
1706 | "%d bytes untransferred\n", |
1707 | td->urb->ep->desc.bEndpointAddress, | |
1708 | td->urb->transfer_buffer_length, | |
1709 | TRB_LEN(event->transfer_len)); | |
1710 | /* Fast path - was this the last TRB in the TD for this URB? */ | |
1711 | if (event_trb == td->last_trb) { | |
1712 | if (TRB_LEN(event->transfer_len) != 0) { | |
1713 | td->urb->actual_length = | |
1714 | td->urb->transfer_buffer_length - | |
1715 | TRB_LEN(event->transfer_len); | |
1716 | if (td->urb->transfer_buffer_length < | |
1717 | td->urb->actual_length) { | |
1718 | xhci_warn(xhci, "HC gave bad length " | |
1719 | "of %d bytes left\n", | |
1720 | TRB_LEN(event->transfer_len)); | |
1721 | td->urb->actual_length = 0; | |
1722 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1723 | *status = -EREMOTEIO; | |
1724 | else | |
1725 | *status = 0; | |
1726 | } | |
1727 | /* Don't overwrite a previously set error code */ | |
1728 | if (*status == -EINPROGRESS) { | |
1729 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1730 | *status = -EREMOTEIO; | |
1731 | else | |
1732 | *status = 0; | |
1733 | } | |
1734 | } else { | |
1735 | td->urb->actual_length = | |
1736 | td->urb->transfer_buffer_length; | |
1737 | /* Ignore a short packet completion if the | |
1738 | * untransferred length was zero. | |
1739 | */ | |
1740 | if (*status == -EREMOTEIO) | |
1741 | *status = 0; | |
1742 | } | |
1743 | } else { | |
1744 | /* Slow path - walk the list, starting from the dequeue | |
1745 | * pointer, to get the actual length transferred. | |
1746 | */ | |
1747 | td->urb->actual_length = 0; | |
1748 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | |
1749 | cur_trb != event_trb; | |
1750 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
1751 | if ((cur_trb->generic.field[3] & | |
1752 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && | |
1753 | (cur_trb->generic.field[3] & | |
1754 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) | |
1755 | td->urb->actual_length += | |
1756 | TRB_LEN(cur_trb->generic.field[2]); | |
1757 | } | |
1758 | /* If the ring didn't stop on a Link or No-op TRB, add | |
1759 | * in the actual bytes transferred from the Normal TRB | |
1760 | */ | |
1761 | if (trb_comp_code != COMP_STOP_INVAL) | |
1762 | td->urb->actual_length += | |
1763 | TRB_LEN(cur_trb->generic.field[2]) - | |
1764 | TRB_LEN(event->transfer_len); | |
1765 | } | |
1766 | ||
1767 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1768 | } | |
1769 | ||
d0e96f5a SS |
1770 | /* |
1771 | * If this function returns an error condition, it means it got a Transfer | |
1772 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
1773 | * At this point, the host controller is probably hosed and should be reset. | |
1774 | */ | |
1775 | static int handle_tx_event(struct xhci_hcd *xhci, | |
1776 | struct xhci_transfer_event *event) | |
1777 | { | |
1778 | struct xhci_virt_device *xdev; | |
63a0d9ab | 1779 | struct xhci_virt_ep *ep; |
d0e96f5a | 1780 | struct xhci_ring *ep_ring; |
82d1009f | 1781 | unsigned int slot_id; |
d0e96f5a | 1782 | int ep_index; |
326b4810 | 1783 | struct xhci_td *td = NULL; |
d0e96f5a SS |
1784 | dma_addr_t event_dma; |
1785 | struct xhci_segment *event_seg; | |
1786 | union xhci_trb *event_trb; | |
326b4810 | 1787 | struct urb *urb = NULL; |
d0e96f5a | 1788 | int status = -EINPROGRESS; |
8e51adcc | 1789 | struct urb_priv *urb_priv; |
d115b048 | 1790 | struct xhci_ep_ctx *ep_ctx; |
66d1eebc | 1791 | u32 trb_comp_code; |
4422da61 | 1792 | int ret = 0; |
d0e96f5a | 1793 | |
82d1009f SS |
1794 | slot_id = TRB_TO_SLOT_ID(event->flags); |
1795 | xdev = xhci->devs[slot_id]; | |
d0e96f5a SS |
1796 | if (!xdev) { |
1797 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
1798 | return -ENODEV; | |
1799 | } | |
1800 | ||
1801 | /* Endpoint ID is 1 based, our index is zero based */ | |
1802 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | |
66e49d87 | 1803 | xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); |
63a0d9ab | 1804 | ep = &xdev->eps[ep_index]; |
e9df17eb | 1805 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); |
d115b048 | 1806 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
986a92d4 AX |
1807 | if (!ep_ring || |
1808 | (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) { | |
e9df17eb SS |
1809 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
1810 | "or incorrect stream ring\n"); | |
d0e96f5a SS |
1811 | return -ENODEV; |
1812 | } | |
1813 | ||
8e595a5d | 1814 | event_dma = event->buffer; |
66d1eebc | 1815 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
986a92d4 | 1816 | /* Look for common error cases */ |
66d1eebc | 1817 | switch (trb_comp_code) { |
b10de142 SS |
1818 | /* Skip codes that require special handling depending on |
1819 | * transfer type | |
1820 | */ | |
1821 | case COMP_SUCCESS: | |
1822 | case COMP_SHORT_TX: | |
1823 | break; | |
ae636747 SS |
1824 | case COMP_STOP: |
1825 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
1826 | break; | |
1827 | case COMP_STOP_INVAL: | |
1828 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
1829 | break; | |
b10de142 SS |
1830 | case COMP_STALL: |
1831 | xhci_warn(xhci, "WARN: Stalled endpoint\n"); | |
63a0d9ab | 1832 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
1833 | status = -EPIPE; |
1834 | break; | |
1835 | case COMP_TRB_ERR: | |
1836 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
1837 | status = -EILSEQ; | |
1838 | break; | |
ec74e403 | 1839 | case COMP_SPLIT_ERR: |
b10de142 SS |
1840 | case COMP_TX_ERR: |
1841 | xhci_warn(xhci, "WARN: transfer error on endpoint\n"); | |
1842 | status = -EPROTO; | |
1843 | break; | |
4a73143c SS |
1844 | case COMP_BABBLE: |
1845 | xhci_warn(xhci, "WARN: babble error on endpoint\n"); | |
1846 | status = -EOVERFLOW; | |
1847 | break; | |
b10de142 SS |
1848 | case COMP_DB_ERR: |
1849 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
1850 | status = -ENOSR; | |
1851 | break; | |
986a92d4 AX |
1852 | case COMP_BW_OVER: |
1853 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
1854 | break; | |
1855 | case COMP_BUFF_OVER: | |
1856 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
1857 | break; | |
1858 | case COMP_UNDERRUN: | |
1859 | /* | |
1860 | * When the Isoch ring is empty, the xHC will generate | |
1861 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
1862 | * Underrun Event for OUT Isoch endpoint. | |
1863 | */ | |
1864 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
1865 | if (!list_empty(&ep_ring->td_list)) | |
1866 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
1867 | "still with TDs queued?\n", | |
1868 | TRB_TO_SLOT_ID(event->flags), ep_index); | |
1869 | goto cleanup; | |
1870 | case COMP_OVERRUN: | |
1871 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
1872 | if (!list_empty(&ep_ring->td_list)) | |
1873 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
1874 | "still with TDs queued?\n", | |
1875 | TRB_TO_SLOT_ID(event->flags), ep_index); | |
1876 | goto cleanup; | |
d18240db AX |
1877 | case COMP_MISSED_INT: |
1878 | /* | |
1879 | * When encounter missed service error, one or more isoc tds | |
1880 | * may be missed by xHC. | |
1881 | * Set skip flag of the ep_ring; Complete the missed tds as | |
1882 | * short transfer when process the ep_ring next time. | |
1883 | */ | |
1884 | ep->skip = true; | |
1885 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
1886 | goto cleanup; | |
b10de142 | 1887 | default: |
b45b5069 | 1888 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
1889 | status = 0; |
1890 | break; | |
1891 | } | |
986a92d4 AX |
1892 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably " |
1893 | "busted\n"); | |
1894 | goto cleanup; | |
1895 | } | |
1896 | ||
d18240db AX |
1897 | do { |
1898 | /* This TRB should be in the TD at the head of this ring's | |
1899 | * TD list. | |
1900 | */ | |
1901 | if (list_empty(&ep_ring->td_list)) { | |
1902 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " | |
1903 | "with no TDs queued?\n", | |
1904 | TRB_TO_SLOT_ID(event->flags), ep_index); | |
1905 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
1906 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); | |
1907 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
1908 | if (ep->skip) { | |
1909 | ep->skip = false; | |
1910 | xhci_dbg(xhci, "td_list is empty while skip " | |
1911 | "flag set. Clear skip flag.\n"); | |
1912 | } | |
1913 | ret = 0; | |
1914 | goto cleanup; | |
1915 | } | |
986a92d4 | 1916 | |
d18240db AX |
1917 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
1918 | /* Is this a TRB in the currently executing TD? */ | |
1919 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, | |
1920 | td->last_trb, event_dma); | |
1921 | if (event_seg && ep->skip) { | |
1922 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); | |
1923 | ep->skip = false; | |
1924 | } | |
1925 | if (!event_seg && | |
1926 | (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) { | |
1927 | /* HC is busted, give up! */ | |
1928 | xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not " | |
1929 | "part of current TD\n"); | |
1930 | return -ESHUTDOWN; | |
1931 | } | |
678539cf | 1932 | |
d18240db AX |
1933 | if (event_seg) { |
1934 | event_trb = &event_seg->trbs[(event_dma - | |
1935 | event_seg->dma) / sizeof(*event_trb)]; | |
1936 | /* | |
1937 | * No-op TRB should not trigger interrupts. | |
1938 | * If event_trb is a no-op TRB, it means the | |
1939 | * corresponding TD has been cancelled. Just ignore | |
1940 | * the TD. | |
1941 | */ | |
1942 | if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK) | |
1943 | == TRB_TYPE(TRB_TR_NOOP)) { | |
1944 | xhci_dbg(xhci, "event_trb is a no-op TRB. " | |
1945 | "Skip it\n"); | |
1946 | goto cleanup; | |
1947 | } | |
1948 | } | |
4422da61 | 1949 | |
d18240db AX |
1950 | /* Now update the urb's actual_length and give back to |
1951 | * the core | |
82d1009f | 1952 | */ |
d18240db AX |
1953 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
1954 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, | |
1955 | &status); | |
04e51901 AX |
1956 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
1957 | ret = process_isoc_td(xhci, td, event_trb, event, ep, | |
1958 | &status); | |
d18240db AX |
1959 | else |
1960 | ret = process_bulk_intr_td(xhci, td, event_trb, event, | |
1961 | ep, &status); | |
1962 | ||
1963 | cleanup: | |
1964 | /* | |
1965 | * Do not update event ring dequeue pointer if ep->skip is set. | |
1966 | * Will roll back to continue process missed tds. | |
1967 | */ | |
1968 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { | |
1969 | inc_deq(xhci, xhci->event_ring, true); | |
d18240db AX |
1970 | } |
1971 | ||
1972 | if (ret) { | |
1973 | urb = td->urb; | |
8e51adcc | 1974 | urb_priv = urb->hcpriv; |
d18240db AX |
1975 | /* Leave the TD around for the reset endpoint function |
1976 | * to use(but only if it's not a control endpoint, | |
1977 | * since we already queued the Set TR dequeue pointer | |
1978 | * command for stalled control endpoints). | |
1979 | */ | |
1980 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
1981 | (trb_comp_code != COMP_STALL && | |
1982 | trb_comp_code != COMP_BABBLE)) | |
8e51adcc | 1983 | xhci_urb_free_priv(xhci, urb_priv); |
d18240db AX |
1984 | |
1985 | usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb); | |
1986 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " | |
1987 | "status = %d\n", | |
1988 | urb, urb->actual_length, status); | |
1989 | spin_unlock(&xhci->lock); | |
1990 | usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status); | |
1991 | spin_lock(&xhci->lock); | |
1992 | } | |
1993 | ||
1994 | /* | |
1995 | * If ep->skip is set, it means there are missed tds on the | |
1996 | * endpoint ring need to take care of. | |
1997 | * Process them as short transfer until reach the td pointed by | |
1998 | * the event. | |
1999 | */ | |
2000 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); | |
2001 | ||
d0e96f5a SS |
2002 | return 0; |
2003 | } | |
2004 | ||
0f2a7930 SS |
2005 | /* |
2006 | * This function handles all OS-owned events on the event ring. It may drop | |
2007 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
2008 | */ | |
d6d98a4d | 2009 | static void xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2010 | { |
2011 | union xhci_trb *event; | |
0f2a7930 | 2012 | int update_ptrs = 1; |
d0e96f5a | 2013 | int ret; |
7f84eef0 | 2014 | |
66e49d87 | 2015 | xhci_dbg(xhci, "In %s\n", __func__); |
7f84eef0 SS |
2016 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
2017 | xhci->error_bitmask |= 1 << 1; | |
2018 | return; | |
2019 | } | |
2020 | ||
2021 | event = xhci->event_ring->dequeue; | |
2022 | /* Does the HC or OS own the TRB? */ | |
2023 | if ((event->event_cmd.flags & TRB_CYCLE) != | |
2024 | xhci->event_ring->cycle_state) { | |
2025 | xhci->error_bitmask |= 1 << 2; | |
2026 | return; | |
2027 | } | |
66e49d87 | 2028 | xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); |
7f84eef0 | 2029 | |
0f2a7930 | 2030 | /* FIXME: Handle more event types. */ |
7f84eef0 SS |
2031 | switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) { |
2032 | case TRB_TYPE(TRB_COMPLETION): | |
66e49d87 | 2033 | xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); |
7f84eef0 | 2034 | handle_cmd_completion(xhci, &event->event_cmd); |
66e49d87 | 2035 | xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); |
7f84eef0 | 2036 | break; |
0f2a7930 | 2037 | case TRB_TYPE(TRB_PORT_STATUS): |
66e49d87 | 2038 | xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); |
0f2a7930 | 2039 | handle_port_status(xhci, event); |
66e49d87 | 2040 | xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); |
0f2a7930 SS |
2041 | update_ptrs = 0; |
2042 | break; | |
d0e96f5a | 2043 | case TRB_TYPE(TRB_TRANSFER): |
66e49d87 | 2044 | xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); |
d0e96f5a | 2045 | ret = handle_tx_event(xhci, &event->trans_event); |
66e49d87 | 2046 | xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); |
d0e96f5a SS |
2047 | if (ret < 0) |
2048 | xhci->error_bitmask |= 1 << 9; | |
2049 | else | |
2050 | update_ptrs = 0; | |
2051 | break; | |
7f84eef0 | 2052 | default: |
0238634d SS |
2053 | if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48)) |
2054 | handle_vendor_event(xhci, event); | |
2055 | else | |
2056 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 2057 | } |
6f5165cf SS |
2058 | /* Any of the above functions may drop and re-acquire the lock, so check |
2059 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2060 | */ | |
2061 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2062 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2063 | "event handler.\n"); | |
2064 | return; | |
2065 | } | |
7f84eef0 | 2066 | |
c06d68b8 SS |
2067 | if (update_ptrs) |
2068 | /* Update SW event ring dequeue pointer */ | |
0f2a7930 | 2069 | inc_deq(xhci, xhci->event_ring, true); |
c06d68b8 | 2070 | |
7f84eef0 | 2071 | /* Are there more items on the event ring? */ |
b7258a4a | 2072 | xhci_handle_event(xhci); |
7f84eef0 | 2073 | } |
9032cd52 SS |
2074 | |
2075 | /* | |
2076 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2077 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2078 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2079 | */ | |
2080 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2081 | { | |
2082 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2083 | u32 status; |
9032cd52 | 2084 | union xhci_trb *trb; |
bda53145 | 2085 | u64 temp_64; |
c06d68b8 SS |
2086 | union xhci_trb *event_ring_deq; |
2087 | dma_addr_t deq; | |
9032cd52 SS |
2088 | |
2089 | spin_lock(&xhci->lock); | |
2090 | trb = xhci->event_ring->dequeue; | |
2091 | /* Check if the xHC generated the interrupt, or the irq is shared */ | |
27e0dd4d | 2092 | status = xhci_readl(xhci, &xhci->op_regs->status); |
c21599a3 | 2093 | if (status == 0xffffffff) |
9032cd52 SS |
2094 | goto hw_died; |
2095 | ||
c21599a3 | 2096 | if (!(status & STS_EINT)) { |
9032cd52 | 2097 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2098 | return IRQ_NONE; |
2099 | } | |
27e0dd4d | 2100 | xhci_dbg(xhci, "op reg status = %08x\n", status); |
9032cd52 SS |
2101 | xhci_dbg(xhci, "Event ring dequeue ptr:\n"); |
2102 | xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n", | |
2103 | (unsigned long long) | |
2104 | xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb), | |
2105 | lower_32_bits(trb->link.segment_ptr), | |
2106 | upper_32_bits(trb->link.segment_ptr), | |
2107 | (unsigned int) trb->link.intr_target, | |
2108 | (unsigned int) trb->link.control); | |
2109 | ||
27e0dd4d | 2110 | if (status & STS_FATAL) { |
9032cd52 SS |
2111 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2112 | xhci_halt(xhci); | |
2113 | hw_died: | |
9032cd52 SS |
2114 | spin_unlock(&xhci->lock); |
2115 | return -ESHUTDOWN; | |
2116 | } | |
2117 | ||
bda53145 SS |
2118 | /* |
2119 | * Clear the op reg interrupt status first, | |
2120 | * so we can receive interrupts from other MSI-X interrupters. | |
2121 | * Write 1 to clear the interrupt status. | |
2122 | */ | |
27e0dd4d SS |
2123 | status |= STS_EINT; |
2124 | xhci_writel(xhci, status, &xhci->op_regs->status); | |
bda53145 SS |
2125 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2126 | /* Clear the MSI-X event interrupt status */ | |
2127 | ||
c21599a3 SS |
2128 | if (hcd->irq != -1) { |
2129 | u32 irq_pending; | |
2130 | /* Acknowledge the PCI interrupt */ | |
2131 | irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
2132 | irq_pending |= 0x3; | |
2133 | xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending); | |
2134 | } | |
bda53145 | 2135 | |
c06d68b8 | 2136 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
bda53145 SS |
2137 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2138 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2139 | /* Clear the event handler busy flag (RW1C); |
2140 | * the event ring should be empty. | |
bda53145 | 2141 | */ |
c06d68b8 SS |
2142 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
2143 | xhci_write_64(xhci, temp_64 | ERST_EHB, | |
2144 | &xhci->ir_set->erst_dequeue); | |
2145 | spin_unlock(&xhci->lock); | |
2146 | ||
2147 | return IRQ_HANDLED; | |
2148 | } | |
2149 | ||
2150 | event_ring_deq = xhci->event_ring->dequeue; | |
2151 | /* FIXME this should be a delayed service routine | |
2152 | * that clears the EHB. | |
2153 | */ | |
2154 | xhci_handle_event(xhci); | |
bda53145 | 2155 | |
bda53145 | 2156 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2157 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2158 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2159 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2160 | xhci->event_ring->dequeue); | |
2161 | if (deq == 0) | |
2162 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2163 | "ring dequeue ptr.\n"); | |
2164 | /* Update HC event ring dequeue pointer */ | |
2165 | temp_64 &= ERST_PTR_MASK; | |
2166 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2167 | } | |
2168 | ||
2169 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2170 | temp_64 |= ERST_EHB; | |
2171 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); | |
2172 | ||
9032cd52 SS |
2173 | spin_unlock(&xhci->lock); |
2174 | ||
2175 | return IRQ_HANDLED; | |
2176 | } | |
2177 | ||
2178 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) | |
2179 | { | |
2180 | irqreturn_t ret; | |
2181 | ||
2182 | set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); | |
2183 | ||
2184 | ret = xhci_irq(hcd); | |
2185 | ||
2186 | return ret; | |
2187 | } | |
7f84eef0 | 2188 | |
d0e96f5a SS |
2189 | /**** Endpoint Ring Operations ****/ |
2190 | ||
7f84eef0 SS |
2191 | /* |
2192 | * Generic function for queueing a TRB on a ring. | |
2193 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2194 | * |
2195 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2196 | * prepare_transfer()? | |
7f84eef0 SS |
2197 | */ |
2198 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
6cc30d85 | 2199 | bool consumer, bool more_trbs_coming, |
7f84eef0 SS |
2200 | u32 field1, u32 field2, u32 field3, u32 field4) |
2201 | { | |
2202 | struct xhci_generic_trb *trb; | |
2203 | ||
2204 | trb = &ring->enqueue->generic; | |
2205 | trb->field[0] = field1; | |
2206 | trb->field[1] = field2; | |
2207 | trb->field[2] = field3; | |
2208 | trb->field[3] = field4; | |
6cc30d85 | 2209 | inc_enq(xhci, ring, consumer, more_trbs_coming); |
7f84eef0 SS |
2210 | } |
2211 | ||
d0e96f5a SS |
2212 | /* |
2213 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2214 | * FIXME allocate segments if the ring is full. | |
2215 | */ | |
2216 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
2217 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) | |
2218 | { | |
2219 | /* Make sure the endpoint has been added to xHC schedule */ | |
2220 | xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); | |
2221 | switch (ep_state) { | |
2222 | case EP_STATE_DISABLED: | |
2223 | /* | |
2224 | * USB core changed config/interfaces without notifying us, | |
2225 | * or hardware is reporting the wrong state. | |
2226 | */ | |
2227 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2228 | return -ENOENT; | |
d0e96f5a | 2229 | case EP_STATE_ERROR: |
c92bcfa7 | 2230 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2231 | /* FIXME event handling code for error needs to clear it */ |
2232 | /* XXX not sure if this should be -ENOENT or not */ | |
2233 | return -EINVAL; | |
c92bcfa7 SS |
2234 | case EP_STATE_HALTED: |
2235 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2236 | case EP_STATE_STOPPED: |
2237 | case EP_STATE_RUNNING: | |
2238 | break; | |
2239 | default: | |
2240 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2241 | /* | |
2242 | * FIXME issue Configure Endpoint command to try to get the HC | |
2243 | * back into a known state. | |
2244 | */ | |
2245 | return -EINVAL; | |
2246 | } | |
2247 | if (!room_on_ring(xhci, ep_ring, num_trbs)) { | |
2248 | /* FIXME allocate more room */ | |
2249 | xhci_err(xhci, "ERROR no room on ep ring\n"); | |
2250 | return -ENOMEM; | |
2251 | } | |
6c12db90 JY |
2252 | |
2253 | if (enqueue_is_link_trb(ep_ring)) { | |
2254 | struct xhci_ring *ring = ep_ring; | |
2255 | union xhci_trb *next; | |
6c12db90 JY |
2256 | |
2257 | xhci_dbg(xhci, "prepare_ring: pointing to link trb\n"); | |
2258 | next = ring->enqueue; | |
2259 | ||
2260 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
2261 | ||
2262 | /* If we're not dealing with 0.95 hardware, | |
2263 | * clear the chain bit. | |
2264 | */ | |
2265 | if (!xhci_link_trb_quirk(xhci)) | |
2266 | next->link.control &= ~TRB_CHAIN; | |
2267 | else | |
2268 | next->link.control |= TRB_CHAIN; | |
2269 | ||
2270 | wmb(); | |
2271 | next->link.control ^= (u32) TRB_CYCLE; | |
2272 | ||
2273 | /* Toggle the cycle bit after the last ring segment. */ | |
2274 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
2275 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
2276 | if (!in_interrupt()) { | |
2277 | xhci_dbg(xhci, "queue_trb: Toggle cycle " | |
2278 | "state for ring %p = %i\n", | |
2279 | ring, (unsigned int)ring->cycle_state); | |
2280 | } | |
2281 | } | |
2282 | ring->enq_seg = ring->enq_seg->next; | |
2283 | ring->enqueue = ring->enq_seg->trbs; | |
2284 | next = ring->enqueue; | |
2285 | } | |
2286 | } | |
2287 | ||
d0e96f5a SS |
2288 | return 0; |
2289 | } | |
2290 | ||
23e3be11 | 2291 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2292 | struct xhci_virt_device *xdev, |
2293 | unsigned int ep_index, | |
e9df17eb | 2294 | unsigned int stream_id, |
d0e96f5a SS |
2295 | unsigned int num_trbs, |
2296 | struct urb *urb, | |
8e51adcc | 2297 | unsigned int td_index, |
d0e96f5a SS |
2298 | gfp_t mem_flags) |
2299 | { | |
2300 | int ret; | |
8e51adcc AX |
2301 | struct urb_priv *urb_priv; |
2302 | struct xhci_td *td; | |
e9df17eb | 2303 | struct xhci_ring *ep_ring; |
d115b048 | 2304 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2305 | |
2306 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2307 | if (!ep_ring) { | |
2308 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2309 | stream_id); | |
2310 | return -EINVAL; | |
2311 | } | |
2312 | ||
2313 | ret = prepare_ring(xhci, ep_ring, | |
d115b048 | 2314 | ep_ctx->ep_info & EP_STATE_MASK, |
d0e96f5a SS |
2315 | num_trbs, mem_flags); |
2316 | if (ret) | |
2317 | return ret; | |
d0e96f5a | 2318 | |
8e51adcc AX |
2319 | urb_priv = urb->hcpriv; |
2320 | td = urb_priv->td[td_index]; | |
2321 | ||
2322 | INIT_LIST_HEAD(&td->td_list); | |
2323 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2324 | ||
2325 | if (td_index == 0) { | |
2326 | ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb); | |
2327 | if (unlikely(ret)) { | |
2328 | xhci_urb_free_priv(xhci, urb_priv); | |
2329 | urb->hcpriv = NULL; | |
2330 | return ret; | |
2331 | } | |
d0e96f5a SS |
2332 | } |
2333 | ||
8e51adcc | 2334 | td->urb = urb; |
d0e96f5a | 2335 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2336 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2337 | td->start_seg = ep_ring->enq_seg; | |
2338 | td->first_trb = ep_ring->enqueue; | |
2339 | ||
2340 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
2341 | |
2342 | return 0; | |
2343 | } | |
2344 | ||
23e3be11 | 2345 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
2346 | { |
2347 | int num_sgs, num_trbs, running_total, temp, i; | |
2348 | struct scatterlist *sg; | |
2349 | ||
2350 | sg = NULL; | |
2351 | num_sgs = urb->num_sgs; | |
2352 | temp = urb->transfer_buffer_length; | |
2353 | ||
2354 | xhci_dbg(xhci, "count sg list trbs: \n"); | |
2355 | num_trbs = 0; | |
910f8d0c | 2356 | for_each_sg(urb->sg, sg, num_sgs, i) { |
8a96c052 SS |
2357 | unsigned int previous_total_trbs = num_trbs; |
2358 | unsigned int len = sg_dma_len(sg); | |
2359 | ||
2360 | /* Scatter gather list entries may cross 64KB boundaries */ | |
2361 | running_total = TRB_MAX_BUFF_SIZE - | |
2362 | (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2363 | if (running_total != 0) | |
2364 | num_trbs++; | |
2365 | ||
2366 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
2367 | while (running_total < sg_dma_len(sg)) { | |
2368 | num_trbs++; | |
2369 | running_total += TRB_MAX_BUFF_SIZE; | |
2370 | } | |
700e2052 GKH |
2371 | xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n", |
2372 | i, (unsigned long long)sg_dma_address(sg), | |
2373 | len, len, num_trbs - previous_total_trbs); | |
8a96c052 SS |
2374 | |
2375 | len = min_t(int, len, temp); | |
2376 | temp -= len; | |
2377 | if (temp == 0) | |
2378 | break; | |
2379 | } | |
2380 | xhci_dbg(xhci, "\n"); | |
2381 | if (!in_interrupt()) | |
f2c565e2 AX |
2382 | xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, " |
2383 | "num_trbs = %d\n", | |
8a96c052 SS |
2384 | urb->ep->desc.bEndpointAddress, |
2385 | urb->transfer_buffer_length, | |
2386 | num_trbs); | |
2387 | return num_trbs; | |
2388 | } | |
2389 | ||
23e3be11 | 2390 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
2391 | { |
2392 | if (num_trbs != 0) | |
2393 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " | |
2394 | "TRBs, %d left\n", __func__, | |
2395 | urb->ep->desc.bEndpointAddress, num_trbs); | |
2396 | if (running_total != urb->transfer_buffer_length) | |
2397 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " | |
2398 | "queued %#x (%d), asked for %#x (%d)\n", | |
2399 | __func__, | |
2400 | urb->ep->desc.bEndpointAddress, | |
2401 | running_total, running_total, | |
2402 | urb->transfer_buffer_length, | |
2403 | urb->transfer_buffer_length); | |
2404 | } | |
2405 | ||
23e3be11 | 2406 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 2407 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 2408 | struct xhci_generic_trb *start_trb) |
8a96c052 | 2409 | { |
8a96c052 SS |
2410 | /* |
2411 | * Pass all the TRBs to the hardware at once and make sure this write | |
2412 | * isn't reordered. | |
2413 | */ | |
2414 | wmb(); | |
50f7b52a AX |
2415 | if (start_cycle) |
2416 | start_trb->field[3] |= start_cycle; | |
2417 | else | |
2418 | start_trb->field[3] &= ~0x1; | |
be88fe4f | 2419 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
2420 | } |
2421 | ||
624defa1 SS |
2422 | /* |
2423 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
2424 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
2425 | * (comprised of sg list entries) can take several service intervals to | |
2426 | * transmit. | |
2427 | */ | |
2428 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
2429 | struct urb *urb, int slot_id, unsigned int ep_index) | |
2430 | { | |
2431 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
2432 | xhci->devs[slot_id]->out_ctx, ep_index); | |
2433 | int xhci_interval; | |
2434 | int ep_interval; | |
2435 | ||
2436 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); | |
2437 | ep_interval = urb->interval; | |
2438 | /* Convert to microframes */ | |
2439 | if (urb->dev->speed == USB_SPEED_LOW || | |
2440 | urb->dev->speed == USB_SPEED_FULL) | |
2441 | ep_interval *= 8; | |
2442 | /* FIXME change this to a warning and a suggestion to use the new API | |
2443 | * to set the polling interval (once the API is added). | |
2444 | */ | |
2445 | if (xhci_interval != ep_interval) { | |
7961acd7 | 2446 | if (printk_ratelimit()) |
624defa1 SS |
2447 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
2448 | " (%d microframe%s) than xHCI " | |
2449 | "(%d microframe%s)\n", | |
2450 | ep_interval, | |
2451 | ep_interval == 1 ? "" : "s", | |
2452 | xhci_interval, | |
2453 | xhci_interval == 1 ? "" : "s"); | |
2454 | urb->interval = xhci_interval; | |
2455 | /* Convert back to frames for LS/FS devices */ | |
2456 | if (urb->dev->speed == USB_SPEED_LOW || | |
2457 | urb->dev->speed == USB_SPEED_FULL) | |
2458 | urb->interval /= 8; | |
2459 | } | |
2460 | return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); | |
2461 | } | |
2462 | ||
04dd950d SS |
2463 | /* |
2464 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
2465 | * right shifted by 10. | |
2466 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
2467 | */ | |
2468 | static u32 xhci_td_remainder(unsigned int remainder) | |
2469 | { | |
2470 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
2471 | ||
2472 | if ((remainder >> 10) >= max) | |
2473 | return max << 17; | |
2474 | else | |
2475 | return (remainder >> 10) << 17; | |
2476 | } | |
2477 | ||
23e3be11 | 2478 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
2479 | struct urb *urb, int slot_id, unsigned int ep_index) |
2480 | { | |
2481 | struct xhci_ring *ep_ring; | |
2482 | unsigned int num_trbs; | |
8e51adcc | 2483 | struct urb_priv *urb_priv; |
8a96c052 SS |
2484 | struct xhci_td *td; |
2485 | struct scatterlist *sg; | |
2486 | int num_sgs; | |
2487 | int trb_buff_len, this_sg_len, running_total; | |
2488 | bool first_trb; | |
2489 | u64 addr; | |
6cc30d85 | 2490 | bool more_trbs_coming; |
8a96c052 SS |
2491 | |
2492 | struct xhci_generic_trb *start_trb; | |
2493 | int start_cycle; | |
2494 | ||
e9df17eb SS |
2495 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2496 | if (!ep_ring) | |
2497 | return -EINVAL; | |
2498 | ||
8a96c052 SS |
2499 | num_trbs = count_sg_trbs_needed(xhci, urb); |
2500 | num_sgs = urb->num_sgs; | |
2501 | ||
23e3be11 | 2502 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 2503 | ep_index, urb->stream_id, |
8e51adcc | 2504 | num_trbs, urb, 0, mem_flags); |
8a96c052 SS |
2505 | if (trb_buff_len < 0) |
2506 | return trb_buff_len; | |
8e51adcc AX |
2507 | |
2508 | urb_priv = urb->hcpriv; | |
2509 | td = urb_priv->td[0]; | |
2510 | ||
8a96c052 SS |
2511 | /* |
2512 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2513 | * until we've finished creating all the other TRBs. The ring's cycle | |
2514 | * state may change as we enqueue the other TRBs, so save it too. | |
2515 | */ | |
2516 | start_trb = &ep_ring->enqueue->generic; | |
2517 | start_cycle = ep_ring->cycle_state; | |
2518 | ||
2519 | running_total = 0; | |
2520 | /* | |
2521 | * How much data is in the first TRB? | |
2522 | * | |
2523 | * There are three forces at work for TRB buffer pointers and lengths: | |
2524 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
2525 | * 2. The transfer length that the driver requested may be smaller than | |
2526 | * the amount of memory allocated for this scatter-gather list. | |
2527 | * 3. TRBs buffers can't cross 64KB boundaries. | |
2528 | */ | |
910f8d0c | 2529 | sg = urb->sg; |
8a96c052 SS |
2530 | addr = (u64) sg_dma_address(sg); |
2531 | this_sg_len = sg_dma_len(sg); | |
2532 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
2533 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2534 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | |
2535 | if (trb_buff_len > urb->transfer_buffer_length) | |
2536 | trb_buff_len = urb->transfer_buffer_length; | |
2537 | xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n", | |
2538 | trb_buff_len); | |
2539 | ||
2540 | first_trb = true; | |
2541 | /* Queue the first TRB, even if it's zero-length */ | |
2542 | do { | |
2543 | u32 field = 0; | |
f9dc68fe | 2544 | u32 length_field = 0; |
04dd950d | 2545 | u32 remainder = 0; |
8a96c052 SS |
2546 | |
2547 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 2548 | if (first_trb) { |
8a96c052 | 2549 | first_trb = false; |
50f7b52a AX |
2550 | if (start_cycle == 0) |
2551 | field |= 0x1; | |
2552 | } else | |
8a96c052 SS |
2553 | field |= ep_ring->cycle_state; |
2554 | ||
2555 | /* Chain all the TRBs together; clear the chain bit in the last | |
2556 | * TRB to indicate it's the last TRB in the chain. | |
2557 | */ | |
2558 | if (num_trbs > 1) { | |
2559 | field |= TRB_CHAIN; | |
2560 | } else { | |
2561 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
2562 | td->last_trb = ep_ring->enqueue; | |
2563 | field |= TRB_IOC; | |
2564 | } | |
2565 | xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " | |
2566 | "64KB boundary at %#x, end dma = %#x\n", | |
2567 | (unsigned int) addr, trb_buff_len, trb_buff_len, | |
2568 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
2569 | (unsigned int) addr + trb_buff_len); | |
2570 | if (TRB_MAX_BUFF_SIZE - | |
2571 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) { | |
2572 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); | |
2573 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
2574 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
2575 | (unsigned int) addr + trb_buff_len); | |
2576 | } | |
04dd950d SS |
2577 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
2578 | running_total) ; | |
f9dc68fe | 2579 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 2580 | remainder | |
f9dc68fe | 2581 | TRB_INTR_TARGET(0); |
6cc30d85 SS |
2582 | if (num_trbs > 1) |
2583 | more_trbs_coming = true; | |
2584 | else | |
2585 | more_trbs_coming = false; | |
2586 | queue_trb(xhci, ep_ring, false, more_trbs_coming, | |
8e595a5d SS |
2587 | lower_32_bits(addr), |
2588 | upper_32_bits(addr), | |
f9dc68fe | 2589 | length_field, |
8a96c052 SS |
2590 | /* We always want to know if the TRB was short, |
2591 | * or we won't get an event when it completes. | |
2592 | * (Unless we use event data TRBs, which are a | |
2593 | * waste of space and HC resources.) | |
2594 | */ | |
2595 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
2596 | --num_trbs; | |
2597 | running_total += trb_buff_len; | |
2598 | ||
2599 | /* Calculate length for next transfer -- | |
2600 | * Are we done queueing all the TRBs for this sg entry? | |
2601 | */ | |
2602 | this_sg_len -= trb_buff_len; | |
2603 | if (this_sg_len == 0) { | |
2604 | --num_sgs; | |
2605 | if (num_sgs == 0) | |
2606 | break; | |
2607 | sg = sg_next(sg); | |
2608 | addr = (u64) sg_dma_address(sg); | |
2609 | this_sg_len = sg_dma_len(sg); | |
2610 | } else { | |
2611 | addr += trb_buff_len; | |
2612 | } | |
2613 | ||
2614 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
2615 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2616 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | |
2617 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
2618 | trb_buff_len = | |
2619 | urb->transfer_buffer_length - running_total; | |
2620 | } while (running_total < urb->transfer_buffer_length); | |
2621 | ||
2622 | check_trb_math(urb, num_trbs, running_total); | |
e9df17eb | 2623 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 2624 | start_cycle, start_trb); |
8a96c052 SS |
2625 | return 0; |
2626 | } | |
2627 | ||
b10de142 | 2628 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 2629 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
2630 | struct urb *urb, int slot_id, unsigned int ep_index) |
2631 | { | |
2632 | struct xhci_ring *ep_ring; | |
8e51adcc | 2633 | struct urb_priv *urb_priv; |
b10de142 SS |
2634 | struct xhci_td *td; |
2635 | int num_trbs; | |
2636 | struct xhci_generic_trb *start_trb; | |
2637 | bool first_trb; | |
6cc30d85 | 2638 | bool more_trbs_coming; |
b10de142 | 2639 | int start_cycle; |
f9dc68fe | 2640 | u32 field, length_field; |
b10de142 SS |
2641 | |
2642 | int running_total, trb_buff_len, ret; | |
2643 | u64 addr; | |
2644 | ||
ff9c895f | 2645 | if (urb->num_sgs) |
8a96c052 SS |
2646 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
2647 | ||
e9df17eb SS |
2648 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2649 | if (!ep_ring) | |
2650 | return -EINVAL; | |
b10de142 SS |
2651 | |
2652 | num_trbs = 0; | |
2653 | /* How much data is (potentially) left before the 64KB boundary? */ | |
2654 | running_total = TRB_MAX_BUFF_SIZE - | |
2655 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2656 | ||
2657 | /* If there's some data on this 64KB chunk, or we have to send a | |
2658 | * zero-length transfer, we need at least one TRB | |
2659 | */ | |
2660 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
2661 | num_trbs++; | |
2662 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
2663 | while (running_total < urb->transfer_buffer_length) { | |
2664 | num_trbs++; | |
2665 | running_total += TRB_MAX_BUFF_SIZE; | |
2666 | } | |
2667 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
2668 | ||
2669 | if (!in_interrupt()) | |
f2c565e2 AX |
2670 | xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), " |
2671 | "addr = %#llx, num_trbs = %d\n", | |
b10de142 | 2672 | urb->ep->desc.bEndpointAddress, |
8a96c052 SS |
2673 | urb->transfer_buffer_length, |
2674 | urb->transfer_buffer_length, | |
700e2052 | 2675 | (unsigned long long)urb->transfer_dma, |
b10de142 | 2676 | num_trbs); |
8a96c052 | 2677 | |
e9df17eb SS |
2678 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
2679 | ep_index, urb->stream_id, | |
8e51adcc | 2680 | num_trbs, urb, 0, mem_flags); |
b10de142 SS |
2681 | if (ret < 0) |
2682 | return ret; | |
2683 | ||
8e51adcc AX |
2684 | urb_priv = urb->hcpriv; |
2685 | td = urb_priv->td[0]; | |
2686 | ||
b10de142 SS |
2687 | /* |
2688 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2689 | * until we've finished creating all the other TRBs. The ring's cycle | |
2690 | * state may change as we enqueue the other TRBs, so save it too. | |
2691 | */ | |
2692 | start_trb = &ep_ring->enqueue->generic; | |
2693 | start_cycle = ep_ring->cycle_state; | |
2694 | ||
2695 | running_total = 0; | |
2696 | /* How much data is in the first TRB? */ | |
2697 | addr = (u64) urb->transfer_dma; | |
2698 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
2699 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2700 | if (urb->transfer_buffer_length < trb_buff_len) | |
2701 | trb_buff_len = urb->transfer_buffer_length; | |
2702 | ||
2703 | first_trb = true; | |
2704 | ||
2705 | /* Queue the first TRB, even if it's zero-length */ | |
2706 | do { | |
04dd950d | 2707 | u32 remainder = 0; |
b10de142 SS |
2708 | field = 0; |
2709 | ||
2710 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 2711 | if (first_trb) { |
b10de142 | 2712 | first_trb = false; |
50f7b52a AX |
2713 | if (start_cycle == 0) |
2714 | field |= 0x1; | |
2715 | } else | |
b10de142 SS |
2716 | field |= ep_ring->cycle_state; |
2717 | ||
2718 | /* Chain all the TRBs together; clear the chain bit in the last | |
2719 | * TRB to indicate it's the last TRB in the chain. | |
2720 | */ | |
2721 | if (num_trbs > 1) { | |
2722 | field |= TRB_CHAIN; | |
2723 | } else { | |
2724 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
2725 | td->last_trb = ep_ring->enqueue; | |
2726 | field |= TRB_IOC; | |
2727 | } | |
04dd950d SS |
2728 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
2729 | running_total); | |
f9dc68fe | 2730 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 2731 | remainder | |
f9dc68fe | 2732 | TRB_INTR_TARGET(0); |
6cc30d85 SS |
2733 | if (num_trbs > 1) |
2734 | more_trbs_coming = true; | |
2735 | else | |
2736 | more_trbs_coming = false; | |
2737 | queue_trb(xhci, ep_ring, false, more_trbs_coming, | |
8e595a5d SS |
2738 | lower_32_bits(addr), |
2739 | upper_32_bits(addr), | |
f9dc68fe | 2740 | length_field, |
b10de142 SS |
2741 | /* We always want to know if the TRB was short, |
2742 | * or we won't get an event when it completes. | |
2743 | * (Unless we use event data TRBs, which are a | |
2744 | * waste of space and HC resources.) | |
2745 | */ | |
2746 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
2747 | --num_trbs; | |
2748 | running_total += trb_buff_len; | |
2749 | ||
2750 | /* Calculate length for next transfer */ | |
2751 | addr += trb_buff_len; | |
2752 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
2753 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
2754 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
2755 | } while (running_total < urb->transfer_buffer_length); | |
2756 | ||
8a96c052 | 2757 | check_trb_math(urb, num_trbs, running_total); |
e9df17eb | 2758 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 2759 | start_cycle, start_trb); |
b10de142 SS |
2760 | return 0; |
2761 | } | |
2762 | ||
d0e96f5a | 2763 | /* Caller must have locked xhci->lock */ |
23e3be11 | 2764 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
2765 | struct urb *urb, int slot_id, unsigned int ep_index) |
2766 | { | |
2767 | struct xhci_ring *ep_ring; | |
2768 | int num_trbs; | |
2769 | int ret; | |
2770 | struct usb_ctrlrequest *setup; | |
2771 | struct xhci_generic_trb *start_trb; | |
2772 | int start_cycle; | |
f9dc68fe | 2773 | u32 field, length_field; |
8e51adcc | 2774 | struct urb_priv *urb_priv; |
d0e96f5a SS |
2775 | struct xhci_td *td; |
2776 | ||
e9df17eb SS |
2777 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2778 | if (!ep_ring) | |
2779 | return -EINVAL; | |
d0e96f5a SS |
2780 | |
2781 | /* | |
2782 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
2783 | * DMA address. | |
2784 | */ | |
2785 | if (!urb->setup_packet) | |
2786 | return -EINVAL; | |
2787 | ||
2788 | if (!in_interrupt()) | |
2789 | xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n", | |
2790 | slot_id, ep_index); | |
2791 | /* 1 TRB for setup, 1 for status */ | |
2792 | num_trbs = 2; | |
2793 | /* | |
2794 | * Don't need to check if we need additional event data and normal TRBs, | |
2795 | * since data in control transfers will never get bigger than 16MB | |
2796 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
2797 | */ | |
2798 | if (urb->transfer_buffer_length > 0) | |
2799 | num_trbs++; | |
e9df17eb SS |
2800 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
2801 | ep_index, urb->stream_id, | |
8e51adcc | 2802 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
2803 | if (ret < 0) |
2804 | return ret; | |
2805 | ||
8e51adcc AX |
2806 | urb_priv = urb->hcpriv; |
2807 | td = urb_priv->td[0]; | |
2808 | ||
d0e96f5a SS |
2809 | /* |
2810 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2811 | * until we've finished creating all the other TRBs. The ring's cycle | |
2812 | * state may change as we enqueue the other TRBs, so save it too. | |
2813 | */ | |
2814 | start_trb = &ep_ring->enqueue->generic; | |
2815 | start_cycle = ep_ring->cycle_state; | |
2816 | ||
2817 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
2818 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
2819 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
2820 | field = 0; |
2821 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
2822 | if (start_cycle == 0) | |
2823 | field |= 0x1; | |
6cc30d85 | 2824 | queue_trb(xhci, ep_ring, false, true, |
d0e96f5a SS |
2825 | /* FIXME endianness is probably going to bite my ass here. */ |
2826 | setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16, | |
2827 | setup->wIndex | setup->wLength << 16, | |
2828 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
2829 | /* Immediate data in pointer */ | |
50f7b52a | 2830 | field); |
d0e96f5a SS |
2831 | |
2832 | /* If there's data, queue data TRBs */ | |
2833 | field = 0; | |
f9dc68fe | 2834 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 2835 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 2836 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
2837 | if (urb->transfer_buffer_length > 0) { |
2838 | if (setup->bRequestType & USB_DIR_IN) | |
2839 | field |= TRB_DIR_IN; | |
6cc30d85 | 2840 | queue_trb(xhci, ep_ring, false, true, |
d0e96f5a SS |
2841 | lower_32_bits(urb->transfer_dma), |
2842 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 2843 | length_field, |
d0e96f5a SS |
2844 | /* Event on short tx */ |
2845 | field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state); | |
2846 | } | |
2847 | ||
2848 | /* Save the DMA address of the last TRB in the TD */ | |
2849 | td->last_trb = ep_ring->enqueue; | |
2850 | ||
2851 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
2852 | /* If the device sent data, the status stage is an OUT transfer */ | |
2853 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
2854 | field = 0; | |
2855 | else | |
2856 | field = TRB_DIR_IN; | |
6cc30d85 | 2857 | queue_trb(xhci, ep_ring, false, false, |
d0e96f5a SS |
2858 | 0, |
2859 | 0, | |
2860 | TRB_INTR_TARGET(0), | |
2861 | /* Event on completion */ | |
2862 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
2863 | ||
e9df17eb | 2864 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 2865 | start_cycle, start_trb); |
d0e96f5a SS |
2866 | return 0; |
2867 | } | |
2868 | ||
04e51901 AX |
2869 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
2870 | struct urb *urb, int i) | |
2871 | { | |
2872 | int num_trbs = 0; | |
2873 | u64 addr, td_len, running_total; | |
2874 | ||
2875 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
2876 | td_len = urb->iso_frame_desc[i].length; | |
2877 | ||
2878 | running_total = TRB_MAX_BUFF_SIZE - | |
2879 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2880 | if (running_total != 0) | |
2881 | num_trbs++; | |
2882 | ||
2883 | while (running_total < td_len) { | |
2884 | num_trbs++; | |
2885 | running_total += TRB_MAX_BUFF_SIZE; | |
2886 | } | |
2887 | ||
2888 | return num_trbs; | |
2889 | } | |
2890 | ||
2891 | /* This is for isoc transfer */ | |
2892 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
2893 | struct urb *urb, int slot_id, unsigned int ep_index) | |
2894 | { | |
2895 | struct xhci_ring *ep_ring; | |
2896 | struct urb_priv *urb_priv; | |
2897 | struct xhci_td *td; | |
2898 | int num_tds, trbs_per_td; | |
2899 | struct xhci_generic_trb *start_trb; | |
2900 | bool first_trb; | |
2901 | int start_cycle; | |
2902 | u32 field, length_field; | |
2903 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
2904 | u64 start_addr, addr; | |
2905 | int i, j; | |
47cbf692 | 2906 | bool more_trbs_coming; |
04e51901 AX |
2907 | |
2908 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
2909 | ||
2910 | num_tds = urb->number_of_packets; | |
2911 | if (num_tds < 1) { | |
2912 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
2913 | return -EINVAL; | |
2914 | } | |
2915 | ||
2916 | if (!in_interrupt()) | |
f2c565e2 | 2917 | xhci_dbg(xhci, "ep %#x - urb len = %#x (%d)," |
04e51901 AX |
2918 | " addr = %#llx, num_tds = %d\n", |
2919 | urb->ep->desc.bEndpointAddress, | |
2920 | urb->transfer_buffer_length, | |
2921 | urb->transfer_buffer_length, | |
2922 | (unsigned long long)urb->transfer_dma, | |
2923 | num_tds); | |
2924 | ||
2925 | start_addr = (u64) urb->transfer_dma; | |
2926 | start_trb = &ep_ring->enqueue->generic; | |
2927 | start_cycle = ep_ring->cycle_state; | |
2928 | ||
2929 | /* Queue the first TRB, even if it's zero-length */ | |
2930 | for (i = 0; i < num_tds; i++) { | |
2931 | first_trb = true; | |
2932 | ||
2933 | running_total = 0; | |
2934 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
2935 | td_len = urb->iso_frame_desc[i].length; | |
2936 | td_remain_len = td_len; | |
2937 | ||
2938 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); | |
2939 | ||
2940 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
2941 | urb->stream_id, trbs_per_td, urb, i, mem_flags); | |
2942 | if (ret < 0) | |
2943 | return ret; | |
2944 | ||
2945 | urb_priv = urb->hcpriv; | |
2946 | td = urb_priv->td[i]; | |
2947 | ||
2948 | for (j = 0; j < trbs_per_td; j++) { | |
2949 | u32 remainder = 0; | |
2950 | field = 0; | |
2951 | ||
2952 | if (first_trb) { | |
2953 | /* Queue the isoc TRB */ | |
2954 | field |= TRB_TYPE(TRB_ISOC); | |
2955 | /* Assume URB_ISO_ASAP is set */ | |
2956 | field |= TRB_SIA; | |
50f7b52a AX |
2957 | if (i == 0) { |
2958 | if (start_cycle == 0) | |
2959 | field |= 0x1; | |
2960 | } else | |
04e51901 AX |
2961 | field |= ep_ring->cycle_state; |
2962 | first_trb = false; | |
2963 | } else { | |
2964 | /* Queue other normal TRBs */ | |
2965 | field |= TRB_TYPE(TRB_NORMAL); | |
2966 | field |= ep_ring->cycle_state; | |
2967 | } | |
2968 | ||
2969 | /* Chain all the TRBs together; clear the chain bit in | |
2970 | * the last TRB to indicate it's the last TRB in the | |
2971 | * chain. | |
2972 | */ | |
2973 | if (j < trbs_per_td - 1) { | |
2974 | field |= TRB_CHAIN; | |
47cbf692 | 2975 | more_trbs_coming = true; |
04e51901 AX |
2976 | } else { |
2977 | td->last_trb = ep_ring->enqueue; | |
2978 | field |= TRB_IOC; | |
47cbf692 | 2979 | more_trbs_coming = false; |
04e51901 AX |
2980 | } |
2981 | ||
2982 | /* Calculate TRB length */ | |
2983 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
2984 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2985 | if (trb_buff_len > td_remain_len) | |
2986 | trb_buff_len = td_remain_len; | |
2987 | ||
2988 | remainder = xhci_td_remainder(td_len - running_total); | |
2989 | length_field = TRB_LEN(trb_buff_len) | | |
2990 | remainder | | |
2991 | TRB_INTR_TARGET(0); | |
47cbf692 | 2992 | queue_trb(xhci, ep_ring, false, more_trbs_coming, |
04e51901 AX |
2993 | lower_32_bits(addr), |
2994 | upper_32_bits(addr), | |
2995 | length_field, | |
2996 | /* We always want to know if the TRB was short, | |
2997 | * or we won't get an event when it completes. | |
2998 | * (Unless we use event data TRBs, which are a | |
2999 | * waste of space and HC resources.) | |
3000 | */ | |
3001 | field | TRB_ISP); | |
3002 | running_total += trb_buff_len; | |
3003 | ||
3004 | addr += trb_buff_len; | |
3005 | td_remain_len -= trb_buff_len; | |
3006 | } | |
3007 | ||
3008 | /* Check TD length */ | |
3009 | if (running_total != td_len) { | |
3010 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
3011 | return -EINVAL; | |
3012 | } | |
3013 | } | |
3014 | ||
e1eab2e0 AX |
3015 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3016 | start_cycle, start_trb); | |
04e51901 AX |
3017 | return 0; |
3018 | } | |
3019 | ||
3020 | /* | |
3021 | * Check transfer ring to guarantee there is enough room for the urb. | |
3022 | * Update ISO URB start_frame and interval. | |
3023 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to | |
3024 | * update the urb->start_frame by now. | |
3025 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. | |
3026 | */ | |
3027 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3028 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3029 | { | |
3030 | struct xhci_virt_device *xdev; | |
3031 | struct xhci_ring *ep_ring; | |
3032 | struct xhci_ep_ctx *ep_ctx; | |
3033 | int start_frame; | |
3034 | int xhci_interval; | |
3035 | int ep_interval; | |
3036 | int num_tds, num_trbs, i; | |
3037 | int ret; | |
3038 | ||
3039 | xdev = xhci->devs[slot_id]; | |
3040 | ep_ring = xdev->eps[ep_index].ring; | |
3041 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3042 | ||
3043 | num_trbs = 0; | |
3044 | num_tds = urb->number_of_packets; | |
3045 | for (i = 0; i < num_tds; i++) | |
3046 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); | |
3047 | ||
3048 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3049 | * Do not insert any td of the urb to the ring if the check failed. | |
3050 | */ | |
3051 | ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK, | |
3052 | num_trbs, mem_flags); | |
3053 | if (ret) | |
3054 | return ret; | |
3055 | ||
3056 | start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index); | |
3057 | start_frame &= 0x3fff; | |
3058 | ||
3059 | urb->start_frame = start_frame; | |
3060 | if (urb->dev->speed == USB_SPEED_LOW || | |
3061 | urb->dev->speed == USB_SPEED_FULL) | |
3062 | urb->start_frame >>= 3; | |
3063 | ||
3064 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); | |
3065 | ep_interval = urb->interval; | |
3066 | /* Convert to microframes */ | |
3067 | if (urb->dev->speed == USB_SPEED_LOW || | |
3068 | urb->dev->speed == USB_SPEED_FULL) | |
3069 | ep_interval *= 8; | |
3070 | /* FIXME change this to a warning and a suggestion to use the new API | |
3071 | * to set the polling interval (once the API is added). | |
3072 | */ | |
3073 | if (xhci_interval != ep_interval) { | |
7961acd7 | 3074 | if (printk_ratelimit()) |
04e51901 AX |
3075 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
3076 | " (%d microframe%s) than xHCI " | |
3077 | "(%d microframe%s)\n", | |
3078 | ep_interval, | |
3079 | ep_interval == 1 ? "" : "s", | |
3080 | xhci_interval, | |
3081 | xhci_interval == 1 ? "" : "s"); | |
3082 | urb->interval = xhci_interval; | |
3083 | /* Convert back to frames for LS/FS devices */ | |
3084 | if (urb->dev->speed == USB_SPEED_LOW || | |
3085 | urb->dev->speed == USB_SPEED_FULL) | |
3086 | urb->interval /= 8; | |
3087 | } | |
3088 | return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); | |
3089 | } | |
3090 | ||
d0e96f5a SS |
3091 | /**** Command Ring Operations ****/ |
3092 | ||
913a8a34 SS |
3093 | /* Generic function for queueing a command TRB on the command ring. |
3094 | * Check to make sure there's room on the command ring for one command TRB. | |
3095 | * Also check that there's room reserved for commands that must not fail. | |
3096 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3097 | * then only check for the number of reserved spots. | |
3098 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3099 | * because the command event handler may want to resubmit a failed command. | |
3100 | */ | |
3101 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, | |
3102 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3103 | { |
913a8a34 | 3104 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a SS |
3105 | int ret; |
3106 | ||
913a8a34 SS |
3107 | if (!command_must_succeed) |
3108 | reserved_trbs++; | |
3109 | ||
d1dc908a SS |
3110 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3111 | reserved_trbs, GFP_ATOMIC); | |
3112 | if (ret < 0) { | |
3113 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3114 | if (command_must_succeed) |
3115 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3116 | "unfailable commands failed.\n"); | |
d1dc908a | 3117 | return ret; |
7f84eef0 | 3118 | } |
6cc30d85 | 3119 | queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3, |
7f84eef0 SS |
3120 | field4 | xhci->cmd_ring->cycle_state); |
3121 | return 0; | |
3122 | } | |
3123 | ||
3ffbba95 | 3124 | /* Queue a slot enable or disable request on the command ring */ |
23e3be11 | 3125 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
3ffbba95 SS |
3126 | { |
3127 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 3128 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3129 | } |
3130 | ||
3131 | /* Queue an address device command TRB */ | |
23e3be11 SS |
3132 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
3133 | u32 slot_id) | |
3ffbba95 | 3134 | { |
8e595a5d SS |
3135 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
3136 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 | 3137 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), |
2a8f82c4 SS |
3138 | false); |
3139 | } | |
3140 | ||
0238634d SS |
3141 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
3142 | u32 field1, u32 field2, u32 field3, u32 field4) | |
3143 | { | |
3144 | return queue_command(xhci, field1, field2, field3, field4, false); | |
3145 | } | |
3146 | ||
2a8f82c4 SS |
3147 | /* Queue a reset device command TRB */ |
3148 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) | |
3149 | { | |
3150 | return queue_command(xhci, 0, 0, 0, | |
3151 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), | |
913a8a34 | 3152 | false); |
3ffbba95 | 3153 | } |
f94e0186 SS |
3154 | |
3155 | /* Queue a configure endpoint command TRB */ | |
23e3be11 | 3156 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
913a8a34 | 3157 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3158 | { |
8e595a5d SS |
3159 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
3160 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
3161 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3162 | command_must_succeed); | |
f94e0186 | 3163 | } |
ae636747 | 3164 | |
f2217e8e SS |
3165 | /* Queue an evaluate context command TRB */ |
3166 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | |
3167 | u32 slot_id) | |
3168 | { | |
3169 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), | |
3170 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
3171 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
3172 | false); | |
f2217e8e SS |
3173 | } |
3174 | ||
be88fe4f AX |
3175 | /* |
3176 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3177 | * activity on an endpoint that is about to be suspended. | |
3178 | */ | |
23e3be11 | 3179 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 3180 | unsigned int ep_index, int suspend) |
ae636747 SS |
3181 | { |
3182 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3183 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3184 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3185 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 SS |
3186 | |
3187 | return queue_command(xhci, 0, 0, 0, | |
be88fe4f | 3188 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
3189 | } |
3190 | ||
3191 | /* Set Transfer Ring Dequeue Pointer command. | |
3192 | * This should not be used for endpoints that have streams enabled. | |
3193 | */ | |
3194 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
3195 | unsigned int ep_index, unsigned int stream_id, |
3196 | struct xhci_segment *deq_seg, | |
ae636747 SS |
3197 | union xhci_trb *deq_ptr, u32 cycle_state) |
3198 | { | |
3199 | dma_addr_t addr; | |
3200 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3201 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 3202 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
ae636747 SS |
3203 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
3204 | ||
23e3be11 | 3205 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
c92bcfa7 | 3206 | if (addr == 0) { |
ae636747 | 3207 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 GKH |
3208 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
3209 | deq_seg, deq_ptr); | |
c92bcfa7 SS |
3210 | return 0; |
3211 | } | |
8e595a5d | 3212 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
e9df17eb | 3213 | upper_32_bits(addr), trb_stream_id, |
913a8a34 | 3214 | trb_slot_id | trb_ep_index | type, false); |
ae636747 | 3215 | } |
a1587d97 SS |
3216 | |
3217 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, | |
3218 | unsigned int ep_index) | |
3219 | { | |
3220 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3221 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3222 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
3223 | ||
913a8a34 SS |
3224 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
3225 | false); | |
a1587d97 | 3226 | } |