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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver peripheral support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
cea83241 | 7 | * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> |
550a7375 FB |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/list.h> | |
38 | #include <linux/timer.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/smp.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/moduleparam.h> | |
44 | #include <linux/stat.h> | |
45 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 46 | #include <linux/slab.h> |
550a7375 FB |
47 | |
48 | #include "musb_core.h" | |
49 | ||
50 | ||
51 | /* MUSB PERIPHERAL status 3-mar-2006: | |
52 | * | |
53 | * - EP0 seems solid. It passes both USBCV and usbtest control cases. | |
54 | * Minor glitches: | |
55 | * | |
56 | * + remote wakeup to Linux hosts work, but saw USBCV failures; | |
57 | * in one test run (operator error?) | |
58 | * + endpoint halt tests -- in both usbtest and usbcv -- seem | |
59 | * to break when dma is enabled ... is something wrongly | |
60 | * clearing SENDSTALL? | |
61 | * | |
62 | * - Mass storage behaved ok when last tested. Network traffic patterns | |
63 | * (with lots of short transfers etc) need retesting; they turn up the | |
64 | * worst cases of the DMA, since short packets are typical but are not | |
65 | * required. | |
66 | * | |
67 | * - TX/IN | |
68 | * + both pio and dma behave in with network and g_zero tests | |
69 | * + no cppi throughput issues other than no-hw-queueing | |
70 | * + failed with FLAT_REG (DaVinci) | |
71 | * + seems to behave with double buffering, PIO -and- CPPI | |
72 | * + with gadgetfs + AIO, requests got lost? | |
73 | * | |
74 | * - RX/OUT | |
75 | * + both pio and dma behave in with network and g_zero tests | |
76 | * + dma is slow in typical case (short_not_ok is clear) | |
77 | * + double buffering ok with PIO | |
78 | * + double buffering *FAILS* with CPPI, wrong data bytes sometimes | |
79 | * + request lossage observed with gadgetfs | |
80 | * | |
81 | * - ISO not tested ... might work, but only weakly isochronous | |
82 | * | |
83 | * - Gadget driver disabling of softconnect during bind() is ignored; so | |
84 | * drivers can't hold off host requests until userspace is ready. | |
85 | * (Workaround: they can turn it off later.) | |
86 | * | |
87 | * - PORTABILITY (assumes PIO works): | |
88 | * + DaVinci, basically works with cppi dma | |
89 | * + OMAP 2430, ditto with mentor dma | |
90 | * + TUSB 6010, platform-specific dma in the works | |
91 | */ | |
92 | ||
93 | /* ----------------------------------------------------------------------- */ | |
94 | ||
95 | /* | |
96 | * Immediately complete a request. | |
97 | * | |
98 | * @param request the request to complete | |
99 | * @param status the status to complete the request with | |
100 | * Context: controller locked, IRQs blocked. | |
101 | */ | |
102 | void musb_g_giveback( | |
103 | struct musb_ep *ep, | |
104 | struct usb_request *request, | |
105 | int status) | |
106 | __releases(ep->musb->lock) | |
107 | __acquires(ep->musb->lock) | |
108 | { | |
109 | struct musb_request *req; | |
110 | struct musb *musb; | |
111 | int busy = ep->busy; | |
112 | ||
113 | req = to_musb_request(request); | |
114 | ||
115 | list_del(&request->list); | |
116 | if (req->request.status == -EINPROGRESS) | |
117 | req->request.status = status; | |
118 | musb = req->musb; | |
119 | ||
120 | ep->busy = 1; | |
121 | spin_unlock(&musb->lock); | |
122 | if (is_dma_capable()) { | |
123 | if (req->mapped) { | |
124 | dma_unmap_single(musb->controller, | |
125 | req->request.dma, | |
126 | req->request.length, | |
127 | req->tx | |
128 | ? DMA_TO_DEVICE | |
129 | : DMA_FROM_DEVICE); | |
130 | req->request.dma = DMA_ADDR_INVALID; | |
131 | req->mapped = 0; | |
132 | } else if (req->request.dma != DMA_ADDR_INVALID) | |
133 | dma_sync_single_for_cpu(musb->controller, | |
134 | req->request.dma, | |
135 | req->request.length, | |
136 | req->tx | |
137 | ? DMA_TO_DEVICE | |
138 | : DMA_FROM_DEVICE); | |
139 | } | |
140 | if (request->status == 0) | |
141 | DBG(5, "%s done request %p, %d/%d\n", | |
142 | ep->end_point.name, request, | |
143 | req->request.actual, req->request.length); | |
144 | else | |
145 | DBG(2, "%s request %p, %d/%d fault %d\n", | |
146 | ep->end_point.name, request, | |
147 | req->request.actual, req->request.length, | |
148 | request->status); | |
149 | req->request.complete(&req->ep->end_point, &req->request); | |
150 | spin_lock(&musb->lock); | |
151 | ep->busy = busy; | |
152 | } | |
153 | ||
154 | /* ----------------------------------------------------------------------- */ | |
155 | ||
156 | /* | |
157 | * Abort requests queued to an endpoint using the status. Synchronous. | |
158 | * caller locked controller and blocked irqs, and selected this ep. | |
159 | */ | |
160 | static void nuke(struct musb_ep *ep, const int status) | |
161 | { | |
162 | struct musb_request *req = NULL; | |
163 | void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; | |
164 | ||
165 | ep->busy = 1; | |
166 | ||
167 | if (is_dma_capable() && ep->dma) { | |
168 | struct dma_controller *c = ep->musb->dma_controller; | |
169 | int value; | |
b6e434a5 | 170 | |
550a7375 | 171 | if (ep->is_in) { |
b6e434a5 SS |
172 | /* |
173 | * The programming guide says that we must not clear | |
174 | * the DMAMODE bit before DMAENAB, so we only | |
175 | * clear it in the second write... | |
176 | */ | |
550a7375 | 177 | musb_writew(epio, MUSB_TXCSR, |
b6e434a5 | 178 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); |
550a7375 FB |
179 | musb_writew(epio, MUSB_TXCSR, |
180 | 0 | MUSB_TXCSR_FLUSHFIFO); | |
181 | } else { | |
182 | musb_writew(epio, MUSB_RXCSR, | |
183 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
184 | musb_writew(epio, MUSB_RXCSR, | |
185 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
186 | } | |
187 | ||
188 | value = c->channel_abort(ep->dma); | |
189 | DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value); | |
190 | c->channel_release(ep->dma); | |
191 | ep->dma = NULL; | |
192 | } | |
193 | ||
194 | while (!list_empty(&(ep->req_list))) { | |
195 | req = container_of(ep->req_list.next, struct musb_request, | |
196 | request.list); | |
197 | musb_g_giveback(ep, &req->request, status); | |
198 | } | |
199 | } | |
200 | ||
201 | /* ----------------------------------------------------------------------- */ | |
202 | ||
203 | /* Data transfers - pure PIO, pure DMA, or mixed mode */ | |
204 | ||
205 | /* | |
206 | * This assumes the separate CPPI engine is responding to DMA requests | |
207 | * from the usb core ... sequenced a bit differently from mentor dma. | |
208 | */ | |
209 | ||
210 | static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) | |
211 | { | |
212 | if (can_bulk_split(musb, ep->type)) | |
213 | return ep->hw_ep->max_packet_sz_tx; | |
214 | else | |
215 | return ep->packet_sz; | |
216 | } | |
217 | ||
218 | ||
219 | #ifdef CONFIG_USB_INVENTRA_DMA | |
220 | ||
221 | /* Peripheral tx (IN) using Mentor DMA works as follows: | |
222 | Only mode 0 is used for transfers <= wPktSize, | |
223 | mode 1 is used for larger transfers, | |
224 | ||
225 | One of the following happens: | |
226 | - Host sends IN token which causes an endpoint interrupt | |
227 | -> TxAvail | |
228 | -> if DMA is currently busy, exit. | |
229 | -> if queue is non-empty, txstate(). | |
230 | ||
231 | - Request is queued by the gadget driver. | |
232 | -> if queue was previously empty, txstate() | |
233 | ||
234 | txstate() | |
235 | -> start | |
236 | /\ -> setup DMA | |
237 | | (data is transferred to the FIFO, then sent out when | |
238 | | IN token(s) are recd from Host. | |
239 | | -> DMA interrupt on completion | |
240 | | calls TxAvail. | |
b6e434a5 | 241 | | -> stop DMA, ~DMAENAB, |
550a7375 FB |
242 | | -> set TxPktRdy for last short pkt or zlp |
243 | | -> Complete Request | |
244 | | -> Continue next request (call txstate) | |
245 | |___________________________________| | |
246 | ||
247 | * Non-Mentor DMA engines can of course work differently, such as by | |
248 | * upleveling from irq-per-packet to irq-per-buffer. | |
249 | */ | |
250 | ||
251 | #endif | |
252 | ||
253 | /* | |
254 | * An endpoint is transmitting data. This can be called either from | |
255 | * the IRQ routine or from ep.queue() to kickstart a request on an | |
256 | * endpoint. | |
257 | * | |
258 | * Context: controller locked, IRQs blocked, endpoint selected | |
259 | */ | |
260 | static void txstate(struct musb *musb, struct musb_request *req) | |
261 | { | |
262 | u8 epnum = req->epnum; | |
263 | struct musb_ep *musb_ep; | |
264 | void __iomem *epio = musb->endpoints[epnum].regs; | |
265 | struct usb_request *request; | |
266 | u16 fifo_count = 0, csr; | |
267 | int use_dma = 0; | |
268 | ||
269 | musb_ep = req->ep; | |
270 | ||
271 | /* we shouldn't get here while DMA is active ... but we do ... */ | |
272 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
273 | DBG(4, "dma pending...\n"); | |
274 | return; | |
275 | } | |
276 | ||
277 | /* read TXCSR before */ | |
278 | csr = musb_readw(epio, MUSB_TXCSR); | |
279 | ||
280 | request = &req->request; | |
281 | fifo_count = min(max_ep_writesize(musb, musb_ep), | |
282 | (int)(request->length - request->actual)); | |
283 | ||
284 | if (csr & MUSB_TXCSR_TXPKTRDY) { | |
285 | DBG(5, "%s old packet still ready , txcsr %03x\n", | |
286 | musb_ep->end_point.name, csr); | |
287 | return; | |
288 | } | |
289 | ||
290 | if (csr & MUSB_TXCSR_P_SENDSTALL) { | |
291 | DBG(5, "%s stalling, txcsr %03x\n", | |
292 | musb_ep->end_point.name, csr); | |
293 | return; | |
294 | } | |
295 | ||
296 | DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", | |
297 | epnum, musb_ep->packet_sz, fifo_count, | |
298 | csr); | |
299 | ||
300 | #ifndef CONFIG_MUSB_PIO_ONLY | |
301 | if (is_dma_capable() && musb_ep->dma) { | |
302 | struct dma_controller *c = musb->dma_controller; | |
66af83dd ML |
303 | size_t request_size; |
304 | ||
305 | /* setup DMA, then program endpoint CSR */ | |
306 | request_size = min_t(size_t, request->length - request->actual, | |
307 | musb_ep->dma->max_len); | |
550a7375 FB |
308 | |
309 | use_dma = (request->dma != DMA_ADDR_INVALID); | |
310 | ||
311 | /* MUSB_TXCSR_P_ISO is still set correctly */ | |
312 | ||
313 | #ifdef CONFIG_USB_INVENTRA_DMA | |
314 | { | |
d1043a26 | 315 | if (request_size < musb_ep->packet_sz) |
550a7375 FB |
316 | musb_ep->dma->desired_mode = 0; |
317 | else | |
318 | musb_ep->dma->desired_mode = 1; | |
319 | ||
320 | use_dma = use_dma && c->channel_program( | |
321 | musb_ep->dma, musb_ep->packet_sz, | |
322 | musb_ep->dma->desired_mode, | |
796a83fa | 323 | request->dma + request->actual, request_size); |
550a7375 FB |
324 | if (use_dma) { |
325 | if (musb_ep->dma->desired_mode == 0) { | |
b6e434a5 SS |
326 | /* |
327 | * We must not clear the DMAMODE bit | |
328 | * before the DMAENAB bit -- and the | |
329 | * latter doesn't always get cleared | |
330 | * before we get here... | |
331 | */ | |
332 | csr &= ~(MUSB_TXCSR_AUTOSET | |
333 | | MUSB_TXCSR_DMAENAB); | |
334 | musb_writew(epio, MUSB_TXCSR, csr | |
335 | | MUSB_TXCSR_P_WZC_BITS); | |
336 | csr &= ~MUSB_TXCSR_DMAMODE; | |
550a7375 FB |
337 | csr |= (MUSB_TXCSR_DMAENAB | |
338 | MUSB_TXCSR_MODE); | |
339 | /* against programming guide */ | |
f11d893d ML |
340 | } else { |
341 | csr |= (MUSB_TXCSR_DMAENAB | |
550a7375 FB |
342 | | MUSB_TXCSR_DMAMODE |
343 | | MUSB_TXCSR_MODE); | |
f11d893d ML |
344 | if (!musb_ep->hb_mult) |
345 | csr |= MUSB_TXCSR_AUTOSET; | |
346 | } | |
550a7375 | 347 | csr &= ~MUSB_TXCSR_P_UNDERRUN; |
f11d893d | 348 | |
550a7375 FB |
349 | musb_writew(epio, MUSB_TXCSR, csr); |
350 | } | |
351 | } | |
352 | ||
353 | #elif defined(CONFIG_USB_TI_CPPI_DMA) | |
354 | /* program endpoint CSR first, then setup DMA */ | |
b6e434a5 | 355 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); |
37e3ee99 SS |
356 | csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | |
357 | MUSB_TXCSR_MODE; | |
550a7375 FB |
358 | musb_writew(epio, MUSB_TXCSR, |
359 | (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) | |
360 | | csr); | |
361 | ||
362 | /* ensure writebuffer is empty */ | |
363 | csr = musb_readw(epio, MUSB_TXCSR); | |
364 | ||
365 | /* NOTE host side sets DMAENAB later than this; both are | |
366 | * OK since the transfer dma glue (between CPPI and Mentor | |
367 | * fifos) just tells CPPI it could start. Data only moves | |
368 | * to the USB TX fifo when both fifos are ready. | |
369 | */ | |
370 | ||
371 | /* "mode" is irrelevant here; handle terminating ZLPs like | |
372 | * PIO does, since the hardware RNDIS mode seems unreliable | |
373 | * except for the last-packet-is-already-short case. | |
374 | */ | |
375 | use_dma = use_dma && c->channel_program( | |
376 | musb_ep->dma, musb_ep->packet_sz, | |
377 | 0, | |
66af83dd ML |
378 | request->dma + request->actual, |
379 | request_size); | |
550a7375 FB |
380 | if (!use_dma) { |
381 | c->channel_release(musb_ep->dma); | |
382 | musb_ep->dma = NULL; | |
b6e434a5 SS |
383 | csr &= ~MUSB_TXCSR_DMAENAB; |
384 | musb_writew(epio, MUSB_TXCSR, csr); | |
550a7375 FB |
385 | /* invariant: prequest->buf is non-null */ |
386 | } | |
387 | #elif defined(CONFIG_USB_TUSB_OMAP_DMA) | |
388 | use_dma = use_dma && c->channel_program( | |
389 | musb_ep->dma, musb_ep->packet_sz, | |
390 | request->zero, | |
66af83dd ML |
391 | request->dma + request->actual, |
392 | request_size); | |
550a7375 FB |
393 | #endif |
394 | } | |
395 | #endif | |
396 | ||
397 | if (!use_dma) { | |
398 | musb_write_fifo(musb_ep->hw_ep, fifo_count, | |
399 | (u8 *) (request->buf + request->actual)); | |
400 | request->actual += fifo_count; | |
401 | csr |= MUSB_TXCSR_TXPKTRDY; | |
402 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
403 | musb_writew(epio, MUSB_TXCSR, csr); | |
404 | } | |
405 | ||
406 | /* host may already have the data when this message shows... */ | |
407 | DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", | |
408 | musb_ep->end_point.name, use_dma ? "dma" : "pio", | |
409 | request->actual, request->length, | |
410 | musb_readw(epio, MUSB_TXCSR), | |
411 | fifo_count, | |
412 | musb_readw(epio, MUSB_TXMAXP)); | |
413 | } | |
414 | ||
415 | /* | |
416 | * FIFO state update (e.g. data ready). | |
417 | * Called from IRQ, with controller locked. | |
418 | */ | |
419 | void musb_g_tx(struct musb *musb, u8 epnum) | |
420 | { | |
421 | u16 csr; | |
422 | struct usb_request *request; | |
423 | u8 __iomem *mbase = musb->mregs; | |
424 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; | |
425 | void __iomem *epio = musb->endpoints[epnum].regs; | |
426 | struct dma_channel *dma; | |
427 | ||
428 | musb_ep_select(mbase, epnum); | |
429 | request = next_request(musb_ep); | |
430 | ||
431 | csr = musb_readw(epio, MUSB_TXCSR); | |
432 | DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); | |
433 | ||
434 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
7723de7e SS |
435 | |
436 | /* | |
437 | * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX | |
438 | * probably rates reporting as a host error. | |
439 | */ | |
440 | if (csr & MUSB_TXCSR_P_SENTSTALL) { | |
441 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
442 | csr &= ~MUSB_TXCSR_P_SENTSTALL; | |
443 | musb_writew(epio, MUSB_TXCSR, csr); | |
444 | return; | |
445 | } | |
446 | ||
447 | if (csr & MUSB_TXCSR_P_UNDERRUN) { | |
448 | /* We NAKed, no big deal... little reason to care. */ | |
449 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
450 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); | |
451 | musb_writew(epio, MUSB_TXCSR, csr); | |
452 | DBG(20, "underrun on ep%d, req %p\n", epnum, request); | |
453 | } | |
454 | ||
455 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
456 | /* | |
457 | * SHOULD NOT HAPPEN... has with CPPI though, after | |
458 | * changing SENDSTALL (and other cases); harmless? | |
550a7375 | 459 | */ |
7723de7e SS |
460 | DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); |
461 | return; | |
462 | } | |
550a7375 | 463 | |
7723de7e SS |
464 | if (request) { |
465 | u8 is_dma = 0; | |
466 | ||
467 | if (dma && (csr & MUSB_TXCSR_DMAENAB)) { | |
468 | is_dma = 1; | |
550a7375 | 469 | csr |= MUSB_TXCSR_P_WZC_BITS; |
7723de7e SS |
470 | csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | |
471 | MUSB_TXCSR_TXPKTRDY); | |
550a7375 | 472 | musb_writew(epio, MUSB_TXCSR, csr); |
7723de7e SS |
473 | /* Ensure writebuffer is empty. */ |
474 | csr = musb_readw(epio, MUSB_TXCSR); | |
475 | request->actual += musb_ep->dma->actual_len; | |
476 | DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n", | |
477 | epnum, csr, musb_ep->dma->actual_len, request); | |
550a7375 FB |
478 | } |
479 | ||
7723de7e SS |
480 | if (is_dma || request->actual == request->length) { |
481 | /* | |
482 | * First, maybe a terminating short packet. Some DMA | |
483 | * engines might handle this by themselves. | |
550a7375 | 484 | */ |
7723de7e SS |
485 | if ((request->zero && request->length |
486 | && request->length % musb_ep->packet_sz == 0) | |
550a7375 | 487 | #ifdef CONFIG_USB_INVENTRA_DMA |
7723de7e SS |
488 | || (is_dma && (!dma->desired_mode || |
489 | (request->actual & | |
490 | (musb_ep->packet_sz - 1)))) | |
550a7375 | 491 | #endif |
7723de7e SS |
492 | ) { |
493 | /* | |
494 | * On DMA completion, FIFO may not be | |
495 | * available yet... | |
550a7375 | 496 | */ |
7723de7e SS |
497 | if (csr & MUSB_TXCSR_TXPKTRDY) |
498 | return; | |
499 | ||
500 | DBG(4, "sending zero pkt\n"); | |
501 | musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE | |
502 | | MUSB_TXCSR_TXPKTRDY); | |
503 | request->zero = 0; | |
550a7375 FB |
504 | } |
505 | ||
bb27bc2c ML |
506 | if (request->actual == request->length) { |
507 | musb_g_giveback(musb_ep, request, 0); | |
508 | request = musb_ep->desc ? next_request(musb_ep) : NULL; | |
509 | if (!request) { | |
510 | DBG(4, "%s idle now\n", | |
511 | musb_ep->end_point.name); | |
512 | return; | |
513 | } | |
95962a77 | 514 | } |
550a7375 FB |
515 | } |
516 | ||
7723de7e SS |
517 | txstate(musb, to_musb_request(request)); |
518 | } | |
550a7375 FB |
519 | } |
520 | ||
521 | /* ------------------------------------------------------------ */ | |
522 | ||
523 | #ifdef CONFIG_USB_INVENTRA_DMA | |
524 | ||
525 | /* Peripheral rx (OUT) using Mentor DMA works as follows: | |
526 | - Only mode 0 is used. | |
527 | ||
528 | - Request is queued by the gadget class driver. | |
529 | -> if queue was previously empty, rxstate() | |
530 | ||
531 | - Host sends OUT token which causes an endpoint interrupt | |
532 | /\ -> RxReady | |
533 | | -> if request queued, call rxstate | |
534 | | /\ -> setup DMA | |
535 | | | -> DMA interrupt on completion | |
536 | | | -> RxReady | |
537 | | | -> stop DMA | |
538 | | | -> ack the read | |
539 | | | -> if data recd = max expected | |
540 | | | by the request, or host | |
541 | | | sent a short packet, | |
542 | | | complete the request, | |
543 | | | and start the next one. | |
544 | | |_____________________________________| | |
545 | | else just wait for the host | |
546 | | to send the next OUT token. | |
547 | |__________________________________________________| | |
548 | ||
549 | * Non-Mentor DMA engines can of course work differently. | |
550 | */ | |
551 | ||
552 | #endif | |
553 | ||
554 | /* | |
555 | * Context: controller locked, IRQs blocked, endpoint selected | |
556 | */ | |
557 | static void rxstate(struct musb *musb, struct musb_request *req) | |
558 | { | |
550a7375 FB |
559 | const u8 epnum = req->epnum; |
560 | struct usb_request *request = &req->request; | |
bd2e74d6 | 561 | struct musb_ep *musb_ep; |
550a7375 | 562 | void __iomem *epio = musb->endpoints[epnum].regs; |
c2c96321 | 563 | unsigned fifo_count = 0; |
bd2e74d6 | 564 | u16 len; |
cea83241 | 565 | u16 csr = musb_readw(epio, MUSB_RXCSR); |
bd2e74d6 ML |
566 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
567 | ||
568 | if (hw_ep->is_shared_fifo) | |
569 | musb_ep = &hw_ep->ep_in; | |
570 | else | |
571 | musb_ep = &hw_ep->ep_out; | |
572 | ||
573 | len = musb_ep->packet_sz; | |
550a7375 | 574 | |
cea83241 SS |
575 | /* We shouldn't get here while DMA is active, but we do... */ |
576 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
577 | DBG(4, "DMA pending...\n"); | |
578 | return; | |
579 | } | |
580 | ||
581 | if (csr & MUSB_RXCSR_P_SENDSTALL) { | |
582 | DBG(5, "%s stalling, RXCSR %04x\n", | |
583 | musb_ep->end_point.name, csr); | |
584 | return; | |
585 | } | |
550a7375 FB |
586 | |
587 | if (is_cppi_enabled() && musb_ep->dma) { | |
588 | struct dma_controller *c = musb->dma_controller; | |
589 | struct dma_channel *channel = musb_ep->dma; | |
590 | ||
591 | /* NOTE: CPPI won't actually stop advancing the DMA | |
592 | * queue after short packet transfers, so this is almost | |
593 | * always going to run as IRQ-per-packet DMA so that | |
594 | * faults will be handled correctly. | |
595 | */ | |
596 | if (c->channel_program(channel, | |
597 | musb_ep->packet_sz, | |
598 | !request->short_not_ok, | |
599 | request->dma + request->actual, | |
600 | request->length - request->actual)) { | |
601 | ||
602 | /* make sure that if an rxpkt arrived after the irq, | |
603 | * the cppi engine will be ready to take it as soon | |
604 | * as DMA is enabled | |
605 | */ | |
606 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
607 | | MUSB_RXCSR_DMAMODE); | |
608 | csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; | |
609 | musb_writew(epio, MUSB_RXCSR, csr); | |
610 | return; | |
611 | } | |
612 | } | |
613 | ||
614 | if (csr & MUSB_RXCSR_RXPKTRDY) { | |
615 | len = musb_readw(epio, MUSB_RXCOUNT); | |
616 | if (request->actual < request->length) { | |
617 | #ifdef CONFIG_USB_INVENTRA_DMA | |
618 | if (is_dma_capable() && musb_ep->dma) { | |
619 | struct dma_controller *c; | |
620 | struct dma_channel *channel; | |
621 | int use_dma = 0; | |
622 | ||
623 | c = musb->dma_controller; | |
624 | channel = musb_ep->dma; | |
625 | ||
626 | /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in | |
627 | * mode 0 only. So we do not get endpoint interrupts due to DMA | |
628 | * completion. We only get interrupts from DMA controller. | |
629 | * | |
630 | * We could operate in DMA mode 1 if we knew the size of the tranfer | |
631 | * in advance. For mass storage class, request->length = what the host | |
632 | * sends, so that'd work. But for pretty much everything else, | |
633 | * request->length is routinely more than what the host sends. For | |
634 | * most these gadgets, end of is signified either by a short packet, | |
635 | * or filling the last byte of the buffer. (Sending extra data in | |
636 | * that last pckate should trigger an overflow fault.) But in mode 1, | |
637 | * we don't get DMA completion interrrupt for short packets. | |
638 | * | |
639 | * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), | |
640 | * to get endpoint interrupt on every DMA req, but that didn't seem | |
641 | * to work reliably. | |
642 | * | |
643 | * REVISIT an updated g_file_storage can set req->short_not_ok, which | |
644 | * then becomes usable as a runtime "use mode 1" hint... | |
645 | */ | |
646 | ||
647 | csr |= MUSB_RXCSR_DMAENAB; | |
f11d893d ML |
648 | if (!musb_ep->hb_mult) |
649 | csr |= MUSB_RXCSR_AUTOCLEAR; | |
490e5fbe | 650 | #ifdef USE_MODE1 |
550a7375 FB |
651 | /* csr |= MUSB_RXCSR_DMAMODE; */ |
652 | ||
653 | /* this special sequence (enabling and then | |
654 | * disabling MUSB_RXCSR_DMAMODE) is required | |
655 | * to get DMAReq to activate | |
656 | */ | |
657 | musb_writew(epio, MUSB_RXCSR, | |
658 | csr | MUSB_RXCSR_DMAMODE); | |
659 | #endif | |
660 | musb_writew(epio, MUSB_RXCSR, csr); | |
661 | ||
662 | if (request->actual < request->length) { | |
663 | int transfer_size = 0; | |
664 | #ifdef USE_MODE1 | |
1018b4e4 | 665 | transfer_size = min(request->length - request->actual, |
550a7375 FB |
666 | channel->max_len); |
667 | #else | |
1018b4e4 ML |
668 | transfer_size = min(request->length - request->actual, |
669 | (unsigned)len); | |
550a7375 FB |
670 | #endif |
671 | if (transfer_size <= musb_ep->packet_sz) | |
672 | musb_ep->dma->desired_mode = 0; | |
673 | else | |
674 | musb_ep->dma->desired_mode = 1; | |
675 | ||
676 | use_dma = c->channel_program( | |
677 | channel, | |
678 | musb_ep->packet_sz, | |
679 | channel->desired_mode, | |
680 | request->dma | |
681 | + request->actual, | |
682 | transfer_size); | |
683 | } | |
684 | ||
685 | if (use_dma) | |
686 | return; | |
687 | } | |
688 | #endif /* Mentor's DMA */ | |
689 | ||
690 | fifo_count = request->length - request->actual; | |
691 | DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", | |
692 | musb_ep->end_point.name, | |
693 | len, fifo_count, | |
694 | musb_ep->packet_sz); | |
695 | ||
c2c96321 | 696 | fifo_count = min_t(unsigned, len, fifo_count); |
550a7375 FB |
697 | |
698 | #ifdef CONFIG_USB_TUSB_OMAP_DMA | |
699 | if (tusb_dma_omap() && musb_ep->dma) { | |
700 | struct dma_controller *c = musb->dma_controller; | |
701 | struct dma_channel *channel = musb_ep->dma; | |
702 | u32 dma_addr = request->dma + request->actual; | |
703 | int ret; | |
704 | ||
705 | ret = c->channel_program(channel, | |
706 | musb_ep->packet_sz, | |
707 | channel->desired_mode, | |
708 | dma_addr, | |
709 | fifo_count); | |
710 | if (ret) | |
711 | return; | |
712 | } | |
713 | #endif | |
714 | ||
715 | musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) | |
716 | (request->buf + request->actual)); | |
717 | request->actual += fifo_count; | |
718 | ||
719 | /* REVISIT if we left anything in the fifo, flush | |
720 | * it and report -EOVERFLOW | |
721 | */ | |
722 | ||
723 | /* ack the read! */ | |
724 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
725 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
726 | musb_writew(epio, MUSB_RXCSR, csr); | |
727 | } | |
728 | } | |
729 | ||
730 | /* reach the end or short packet detected */ | |
731 | if (request->actual == request->length || len < musb_ep->packet_sz) | |
732 | musb_g_giveback(musb_ep, request, 0); | |
733 | } | |
734 | ||
735 | /* | |
736 | * Data ready for a request; called from IRQ | |
737 | */ | |
738 | void musb_g_rx(struct musb *musb, u8 epnum) | |
739 | { | |
740 | u16 csr; | |
741 | struct usb_request *request; | |
742 | void __iomem *mbase = musb->mregs; | |
bd2e74d6 | 743 | struct musb_ep *musb_ep; |
550a7375 FB |
744 | void __iomem *epio = musb->endpoints[epnum].regs; |
745 | struct dma_channel *dma; | |
bd2e74d6 ML |
746 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
747 | ||
748 | if (hw_ep->is_shared_fifo) | |
749 | musb_ep = &hw_ep->ep_in; | |
750 | else | |
751 | musb_ep = &hw_ep->ep_out; | |
550a7375 FB |
752 | |
753 | musb_ep_select(mbase, epnum); | |
754 | ||
755 | request = next_request(musb_ep); | |
0abdc36f MM |
756 | if (!request) |
757 | return; | |
550a7375 FB |
758 | |
759 | csr = musb_readw(epio, MUSB_RXCSR); | |
760 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
761 | ||
762 | DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, | |
763 | csr, dma ? " (dma)" : "", request); | |
764 | ||
765 | if (csr & MUSB_RXCSR_P_SENTSTALL) { | |
550a7375 FB |
766 | csr |= MUSB_RXCSR_P_WZC_BITS; |
767 | csr &= ~MUSB_RXCSR_P_SENTSTALL; | |
768 | musb_writew(epio, MUSB_RXCSR, csr); | |
cea83241 | 769 | return; |
550a7375 FB |
770 | } |
771 | ||
772 | if (csr & MUSB_RXCSR_P_OVERRUN) { | |
773 | /* csr |= MUSB_RXCSR_P_WZC_BITS; */ | |
774 | csr &= ~MUSB_RXCSR_P_OVERRUN; | |
775 | musb_writew(epio, MUSB_RXCSR, csr); | |
776 | ||
777 | DBG(3, "%s iso overrun on %p\n", musb_ep->name, request); | |
778 | if (request && request->status == -EINPROGRESS) | |
779 | request->status = -EOVERFLOW; | |
780 | } | |
781 | if (csr & MUSB_RXCSR_INCOMPRX) { | |
782 | /* REVISIT not necessarily an error */ | |
783 | DBG(4, "%s, incomprx\n", musb_ep->end_point.name); | |
784 | } | |
785 | ||
786 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
787 | /* "should not happen"; likely RXPKTRDY pending for DMA */ | |
788 | DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1, | |
789 | "%s busy, csr %04x\n", | |
790 | musb_ep->end_point.name, csr); | |
cea83241 | 791 | return; |
550a7375 FB |
792 | } |
793 | ||
794 | if (dma && (csr & MUSB_RXCSR_DMAENAB)) { | |
795 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
796 | | MUSB_RXCSR_DMAENAB | |
797 | | MUSB_RXCSR_DMAMODE); | |
798 | musb_writew(epio, MUSB_RXCSR, | |
799 | MUSB_RXCSR_P_WZC_BITS | csr); | |
800 | ||
801 | request->actual += musb_ep->dma->actual_len; | |
802 | ||
803 | DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", | |
804 | epnum, csr, | |
805 | musb_readw(epio, MUSB_RXCSR), | |
806 | musb_ep->dma->actual_len, request); | |
807 | ||
808 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) | |
809 | /* Autoclear doesn't clear RxPktRdy for short packets */ | |
810 | if ((dma->desired_mode == 0) | |
811 | || (dma->actual_len | |
812 | & (musb_ep->packet_sz - 1))) { | |
813 | /* ack the read! */ | |
814 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
815 | musb_writew(epio, MUSB_RXCSR, csr); | |
816 | } | |
817 | ||
818 | /* incomplete, and not short? wait for next IN packet */ | |
819 | if ((request->actual < request->length) | |
820 | && (musb_ep->dma->actual_len | |
821 | == musb_ep->packet_sz)) | |
cea83241 | 822 | return; |
550a7375 FB |
823 | #endif |
824 | musb_g_giveback(musb_ep, request, 0); | |
825 | ||
826 | request = next_request(musb_ep); | |
827 | if (!request) | |
cea83241 | 828 | return; |
550a7375 FB |
829 | } |
830 | ||
550a7375 FB |
831 | /* analyze request if the ep is hot */ |
832 | if (request) | |
833 | rxstate(musb, to_musb_request(request)); | |
834 | else | |
835 | DBG(3, "packet waiting for %s%s request\n", | |
836 | musb_ep->desc ? "" : "inactive ", | |
837 | musb_ep->end_point.name); | |
550a7375 FB |
838 | return; |
839 | } | |
840 | ||
841 | /* ------------------------------------------------------------ */ | |
842 | ||
843 | static int musb_gadget_enable(struct usb_ep *ep, | |
844 | const struct usb_endpoint_descriptor *desc) | |
845 | { | |
846 | unsigned long flags; | |
847 | struct musb_ep *musb_ep; | |
848 | struct musb_hw_ep *hw_ep; | |
849 | void __iomem *regs; | |
850 | struct musb *musb; | |
851 | void __iomem *mbase; | |
852 | u8 epnum; | |
853 | u16 csr; | |
854 | unsigned tmp; | |
855 | int status = -EINVAL; | |
856 | ||
857 | if (!ep || !desc) | |
858 | return -EINVAL; | |
859 | ||
860 | musb_ep = to_musb_ep(ep); | |
861 | hw_ep = musb_ep->hw_ep; | |
862 | regs = hw_ep->regs; | |
863 | musb = musb_ep->musb; | |
864 | mbase = musb->mregs; | |
865 | epnum = musb_ep->current_epnum; | |
866 | ||
867 | spin_lock_irqsave(&musb->lock, flags); | |
868 | ||
869 | if (musb_ep->desc) { | |
870 | status = -EBUSY; | |
871 | goto fail; | |
872 | } | |
96bcd090 | 873 | musb_ep->type = usb_endpoint_type(desc); |
550a7375 FB |
874 | |
875 | /* check direction and (later) maxpacket size against endpoint */ | |
96bcd090 | 876 | if (usb_endpoint_num(desc) != epnum) |
550a7375 FB |
877 | goto fail; |
878 | ||
879 | /* REVISIT this rules out high bandwidth periodic transfers */ | |
880 | tmp = le16_to_cpu(desc->wMaxPacketSize); | |
f11d893d ML |
881 | if (tmp & ~0x07ff) { |
882 | int ok; | |
883 | ||
884 | if (usb_endpoint_dir_in(desc)) | |
885 | ok = musb->hb_iso_tx; | |
886 | else | |
887 | ok = musb->hb_iso_rx; | |
888 | ||
889 | if (!ok) { | |
890 | DBG(4, "%s: not support ISO high bandwidth\n", __func__); | |
891 | goto fail; | |
892 | } | |
893 | musb_ep->hb_mult = (tmp >> 11) & 3; | |
894 | } else { | |
895 | musb_ep->hb_mult = 0; | |
896 | } | |
897 | ||
898 | musb_ep->packet_sz = tmp & 0x7ff; | |
899 | tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1); | |
550a7375 FB |
900 | |
901 | /* enable the interrupts for the endpoint, set the endpoint | |
902 | * packet size (or fail), set the mode, clear the fifo | |
903 | */ | |
904 | musb_ep_select(mbase, epnum); | |
96bcd090 | 905 | if (usb_endpoint_dir_in(desc)) { |
550a7375 FB |
906 | u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); |
907 | ||
908 | if (hw_ep->is_shared_fifo) | |
909 | musb_ep->is_in = 1; | |
910 | if (!musb_ep->is_in) | |
911 | goto fail; | |
f11d893d ML |
912 | |
913 | if (tmp > hw_ep->max_packet_sz_tx) { | |
914 | DBG(4, "%s: packet size beyond hw fifo size\n", __func__); | |
550a7375 | 915 | goto fail; |
f11d893d | 916 | } |
550a7375 FB |
917 | |
918 | int_txe |= (1 << epnum); | |
919 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
920 | ||
921 | /* REVISIT if can_bulk_split(), use by updating "tmp"; | |
922 | * likewise high bandwidth periodic tx | |
923 | */ | |
9f445cb2 CC |
924 | /* Set TXMAXP with the FIFO size of the endpoint |
925 | * to disable double buffering mode. Currently, It seems that double | |
926 | * buffering has problem if musb RTL revision number < 2.0. | |
927 | */ | |
928 | if (musb->hwvers < MUSB_HWVERS_2000) | |
929 | musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); | |
930 | else | |
f11d893d | 931 | musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz | (musb_ep->hb_mult << 11)); |
550a7375 FB |
932 | |
933 | csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; | |
934 | if (musb_readw(regs, MUSB_TXCSR) | |
935 | & MUSB_TXCSR_FIFONOTEMPTY) | |
936 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
937 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
938 | csr |= MUSB_TXCSR_P_ISO; | |
939 | ||
940 | /* set twice in case of double buffering */ | |
941 | musb_writew(regs, MUSB_TXCSR, csr); | |
942 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
943 | musb_writew(regs, MUSB_TXCSR, csr); | |
944 | ||
945 | } else { | |
946 | u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); | |
947 | ||
948 | if (hw_ep->is_shared_fifo) | |
949 | musb_ep->is_in = 0; | |
950 | if (musb_ep->is_in) | |
951 | goto fail; | |
f11d893d ML |
952 | |
953 | if (tmp > hw_ep->max_packet_sz_rx) { | |
954 | DBG(4, "%s: packet size beyond hw fifo size\n", __func__); | |
550a7375 | 955 | goto fail; |
f11d893d | 956 | } |
550a7375 FB |
957 | |
958 | int_rxe |= (1 << epnum); | |
959 | musb_writew(mbase, MUSB_INTRRXE, int_rxe); | |
960 | ||
961 | /* REVISIT if can_bulk_combine() use by updating "tmp" | |
962 | * likewise high bandwidth periodic rx | |
963 | */ | |
9f445cb2 CC |
964 | /* Set RXMAXP with the FIFO size of the endpoint |
965 | * to disable double buffering mode. | |
966 | */ | |
967 | if (musb->hwvers < MUSB_HWVERS_2000) | |
968 | musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_rx); | |
969 | else | |
f11d893d | 970 | musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz | (musb_ep->hb_mult << 11)); |
550a7375 FB |
971 | |
972 | /* force shared fifo to OUT-only mode */ | |
973 | if (hw_ep->is_shared_fifo) { | |
974 | csr = musb_readw(regs, MUSB_TXCSR); | |
975 | csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); | |
976 | musb_writew(regs, MUSB_TXCSR, csr); | |
977 | } | |
978 | ||
979 | csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; | |
980 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
981 | csr |= MUSB_RXCSR_P_ISO; | |
982 | else if (musb_ep->type == USB_ENDPOINT_XFER_INT) | |
983 | csr |= MUSB_RXCSR_DISNYET; | |
984 | ||
985 | /* set twice in case of double buffering */ | |
986 | musb_writew(regs, MUSB_RXCSR, csr); | |
987 | musb_writew(regs, MUSB_RXCSR, csr); | |
988 | } | |
989 | ||
990 | /* NOTE: all the I/O code _should_ work fine without DMA, in case | |
991 | * for some reason you run out of channels here. | |
992 | */ | |
993 | if (is_dma_capable() && musb->dma_controller) { | |
994 | struct dma_controller *c = musb->dma_controller; | |
995 | ||
996 | musb_ep->dma = c->channel_alloc(c, hw_ep, | |
997 | (desc->bEndpointAddress & USB_DIR_IN)); | |
998 | } else | |
999 | musb_ep->dma = NULL; | |
1000 | ||
1001 | musb_ep->desc = desc; | |
1002 | musb_ep->busy = 0; | |
47e97605 | 1003 | musb_ep->wedged = 0; |
550a7375 FB |
1004 | status = 0; |
1005 | ||
1006 | pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", | |
1007 | musb_driver_name, musb_ep->end_point.name, | |
1008 | ({ char *s; switch (musb_ep->type) { | |
1009 | case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; | |
1010 | case USB_ENDPOINT_XFER_INT: s = "int"; break; | |
1011 | default: s = "iso"; break; | |
1012 | }; s; }), | |
1013 | musb_ep->is_in ? "IN" : "OUT", | |
1014 | musb_ep->dma ? "dma, " : "", | |
1015 | musb_ep->packet_sz); | |
1016 | ||
1017 | schedule_work(&musb->irq_work); | |
1018 | ||
1019 | fail: | |
1020 | spin_unlock_irqrestore(&musb->lock, flags); | |
1021 | return status; | |
1022 | } | |
1023 | ||
1024 | /* | |
1025 | * Disable an endpoint flushing all requests queued. | |
1026 | */ | |
1027 | static int musb_gadget_disable(struct usb_ep *ep) | |
1028 | { | |
1029 | unsigned long flags; | |
1030 | struct musb *musb; | |
1031 | u8 epnum; | |
1032 | struct musb_ep *musb_ep; | |
1033 | void __iomem *epio; | |
1034 | int status = 0; | |
1035 | ||
1036 | musb_ep = to_musb_ep(ep); | |
1037 | musb = musb_ep->musb; | |
1038 | epnum = musb_ep->current_epnum; | |
1039 | epio = musb->endpoints[epnum].regs; | |
1040 | ||
1041 | spin_lock_irqsave(&musb->lock, flags); | |
1042 | musb_ep_select(musb->mregs, epnum); | |
1043 | ||
1044 | /* zero the endpoint sizes */ | |
1045 | if (musb_ep->is_in) { | |
1046 | u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); | |
1047 | int_txe &= ~(1 << epnum); | |
1048 | musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); | |
1049 | musb_writew(epio, MUSB_TXMAXP, 0); | |
1050 | } else { | |
1051 | u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); | |
1052 | int_rxe &= ~(1 << epnum); | |
1053 | musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); | |
1054 | musb_writew(epio, MUSB_RXMAXP, 0); | |
1055 | } | |
1056 | ||
1057 | musb_ep->desc = NULL; | |
1058 | ||
1059 | /* abort all pending DMA and requests */ | |
1060 | nuke(musb_ep, -ESHUTDOWN); | |
1061 | ||
1062 | schedule_work(&musb->irq_work); | |
1063 | ||
1064 | spin_unlock_irqrestore(&(musb->lock), flags); | |
1065 | ||
1066 | DBG(2, "%s\n", musb_ep->end_point.name); | |
1067 | ||
1068 | return status; | |
1069 | } | |
1070 | ||
1071 | /* | |
1072 | * Allocate a request for an endpoint. | |
1073 | * Reused by ep0 code. | |
1074 | */ | |
1075 | struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) | |
1076 | { | |
1077 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1078 | struct musb_request *request = NULL; | |
1079 | ||
1080 | request = kzalloc(sizeof *request, gfp_flags); | |
1081 | if (request) { | |
1082 | INIT_LIST_HEAD(&request->request.list); | |
1083 | request->request.dma = DMA_ADDR_INVALID; | |
1084 | request->epnum = musb_ep->current_epnum; | |
1085 | request->ep = musb_ep; | |
1086 | } | |
1087 | ||
1088 | return &request->request; | |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * Free a request | |
1093 | * Reused by ep0 code. | |
1094 | */ | |
1095 | void musb_free_request(struct usb_ep *ep, struct usb_request *req) | |
1096 | { | |
1097 | kfree(to_musb_request(req)); | |
1098 | } | |
1099 | ||
1100 | static LIST_HEAD(buffers); | |
1101 | ||
1102 | struct free_record { | |
1103 | struct list_head list; | |
1104 | struct device *dev; | |
1105 | unsigned bytes; | |
1106 | dma_addr_t dma; | |
1107 | }; | |
1108 | ||
1109 | /* | |
1110 | * Context: controller locked, IRQs blocked. | |
1111 | */ | |
a666e3e6 | 1112 | void musb_ep_restart(struct musb *musb, struct musb_request *req) |
550a7375 FB |
1113 | { |
1114 | DBG(3, "<== %s request %p len %u on hw_ep%d\n", | |
1115 | req->tx ? "TX/IN" : "RX/OUT", | |
1116 | &req->request, req->request.length, req->epnum); | |
1117 | ||
1118 | musb_ep_select(musb->mregs, req->epnum); | |
1119 | if (req->tx) | |
1120 | txstate(musb, req); | |
1121 | else | |
1122 | rxstate(musb, req); | |
1123 | } | |
1124 | ||
1125 | static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, | |
1126 | gfp_t gfp_flags) | |
1127 | { | |
1128 | struct musb_ep *musb_ep; | |
1129 | struct musb_request *request; | |
1130 | struct musb *musb; | |
1131 | int status = 0; | |
1132 | unsigned long lockflags; | |
1133 | ||
1134 | if (!ep || !req) | |
1135 | return -EINVAL; | |
1136 | if (!req->buf) | |
1137 | return -ENODATA; | |
1138 | ||
1139 | musb_ep = to_musb_ep(ep); | |
1140 | musb = musb_ep->musb; | |
1141 | ||
1142 | request = to_musb_request(req); | |
1143 | request->musb = musb; | |
1144 | ||
1145 | if (request->ep != musb_ep) | |
1146 | return -EINVAL; | |
1147 | ||
1148 | DBG(4, "<== to %s request=%p\n", ep->name, req); | |
1149 | ||
1150 | /* request is mine now... */ | |
1151 | request->request.actual = 0; | |
1152 | request->request.status = -EINPROGRESS; | |
1153 | request->epnum = musb_ep->current_epnum; | |
1154 | request->tx = musb_ep->is_in; | |
1155 | ||
1156 | if (is_dma_capable() && musb_ep->dma) { | |
1157 | if (request->request.dma == DMA_ADDR_INVALID) { | |
1158 | request->request.dma = dma_map_single( | |
1159 | musb->controller, | |
1160 | request->request.buf, | |
1161 | request->request.length, | |
1162 | request->tx | |
1163 | ? DMA_TO_DEVICE | |
1164 | : DMA_FROM_DEVICE); | |
1165 | request->mapped = 1; | |
1166 | } else { | |
1167 | dma_sync_single_for_device(musb->controller, | |
1168 | request->request.dma, | |
1169 | request->request.length, | |
1170 | request->tx | |
1171 | ? DMA_TO_DEVICE | |
1172 | : DMA_FROM_DEVICE); | |
1173 | request->mapped = 0; | |
1174 | } | |
1175 | } else if (!req->buf) { | |
1176 | return -ENODATA; | |
1177 | } else | |
1178 | request->mapped = 0; | |
1179 | ||
1180 | spin_lock_irqsave(&musb->lock, lockflags); | |
1181 | ||
1182 | /* don't queue if the ep is down */ | |
1183 | if (!musb_ep->desc) { | |
1184 | DBG(4, "req %p queued to %s while ep %s\n", | |
1185 | req, ep->name, "disabled"); | |
1186 | status = -ESHUTDOWN; | |
1187 | goto cleanup; | |
1188 | } | |
1189 | ||
1190 | /* add request to the list */ | |
1191 | list_add_tail(&(request->request.list), &(musb_ep->req_list)); | |
1192 | ||
1193 | /* it this is the head of the queue, start i/o ... */ | |
1194 | if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next) | |
1195 | musb_ep_restart(musb, request); | |
1196 | ||
1197 | cleanup: | |
1198 | spin_unlock_irqrestore(&musb->lock, lockflags); | |
1199 | return status; | |
1200 | } | |
1201 | ||
1202 | static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) | |
1203 | { | |
1204 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1205 | struct usb_request *r; | |
1206 | unsigned long flags; | |
1207 | int status = 0; | |
1208 | struct musb *musb = musb_ep->musb; | |
1209 | ||
1210 | if (!ep || !request || to_musb_request(request)->ep != musb_ep) | |
1211 | return -EINVAL; | |
1212 | ||
1213 | spin_lock_irqsave(&musb->lock, flags); | |
1214 | ||
1215 | list_for_each_entry(r, &musb_ep->req_list, list) { | |
1216 | if (r == request) | |
1217 | break; | |
1218 | } | |
1219 | if (r != request) { | |
1220 | DBG(3, "request %p not queued to %s\n", request, ep->name); | |
1221 | status = -EINVAL; | |
1222 | goto done; | |
1223 | } | |
1224 | ||
1225 | /* if the hardware doesn't have the request, easy ... */ | |
1226 | if (musb_ep->req_list.next != &request->list || musb_ep->busy) | |
1227 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1228 | ||
1229 | /* ... else abort the dma transfer ... */ | |
1230 | else if (is_dma_capable() && musb_ep->dma) { | |
1231 | struct dma_controller *c = musb->dma_controller; | |
1232 | ||
1233 | musb_ep_select(musb->mregs, musb_ep->current_epnum); | |
1234 | if (c->channel_abort) | |
1235 | status = c->channel_abort(musb_ep->dma); | |
1236 | else | |
1237 | status = -EBUSY; | |
1238 | if (status == 0) | |
1239 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1240 | } else { | |
1241 | /* NOTE: by sticking to easily tested hardware/driver states, | |
1242 | * we leave counting of in-flight packets imprecise. | |
1243 | */ | |
1244 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1245 | } | |
1246 | ||
1247 | done: | |
1248 | spin_unlock_irqrestore(&musb->lock, flags); | |
1249 | return status; | |
1250 | } | |
1251 | ||
1252 | /* | |
1253 | * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any | |
1254 | * data but will queue requests. | |
1255 | * | |
1256 | * exported to ep0 code | |
1257 | */ | |
1b6c3b0f | 1258 | static int musb_gadget_set_halt(struct usb_ep *ep, int value) |
550a7375 FB |
1259 | { |
1260 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1261 | u8 epnum = musb_ep->current_epnum; | |
1262 | struct musb *musb = musb_ep->musb; | |
1263 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1264 | void __iomem *mbase; | |
1265 | unsigned long flags; | |
1266 | u16 csr; | |
cea83241 | 1267 | struct musb_request *request; |
550a7375 FB |
1268 | int status = 0; |
1269 | ||
1270 | if (!ep) | |
1271 | return -EINVAL; | |
1272 | mbase = musb->mregs; | |
1273 | ||
1274 | spin_lock_irqsave(&musb->lock, flags); | |
1275 | ||
1276 | if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { | |
1277 | status = -EINVAL; | |
1278 | goto done; | |
1279 | } | |
1280 | ||
1281 | musb_ep_select(mbase, epnum); | |
1282 | ||
550a7375 | 1283 | request = to_musb_request(next_request(musb_ep)); |
cea83241 SS |
1284 | if (value) { |
1285 | if (request) { | |
1286 | DBG(3, "request in progress, cannot halt %s\n", | |
1287 | ep->name); | |
1288 | status = -EAGAIN; | |
1289 | goto done; | |
1290 | } | |
1291 | /* Cannot portably stall with non-empty FIFO */ | |
1292 | if (musb_ep->is_in) { | |
1293 | csr = musb_readw(epio, MUSB_TXCSR); | |
1294 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1295 | DBG(3, "FIFO busy, cannot halt %s\n", ep->name); | |
1296 | status = -EAGAIN; | |
1297 | goto done; | |
1298 | } | |
550a7375 | 1299 | } |
47e97605 SS |
1300 | } else |
1301 | musb_ep->wedged = 0; | |
550a7375 FB |
1302 | |
1303 | /* set/clear the stall and toggle bits */ | |
1304 | DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); | |
1305 | if (musb_ep->is_in) { | |
1306 | csr = musb_readw(epio, MUSB_TXCSR); | |
550a7375 FB |
1307 | csr |= MUSB_TXCSR_P_WZC_BITS |
1308 | | MUSB_TXCSR_CLRDATATOG; | |
1309 | if (value) | |
1310 | csr |= MUSB_TXCSR_P_SENDSTALL; | |
1311 | else | |
1312 | csr &= ~(MUSB_TXCSR_P_SENDSTALL | |
1313 | | MUSB_TXCSR_P_SENTSTALL); | |
1314 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
1315 | musb_writew(epio, MUSB_TXCSR, csr); | |
1316 | } else { | |
1317 | csr = musb_readw(epio, MUSB_RXCSR); | |
1318 | csr |= MUSB_RXCSR_P_WZC_BITS | |
1319 | | MUSB_RXCSR_FLUSHFIFO | |
1320 | | MUSB_RXCSR_CLRDATATOG; | |
1321 | if (value) | |
1322 | csr |= MUSB_RXCSR_P_SENDSTALL; | |
1323 | else | |
1324 | csr &= ~(MUSB_RXCSR_P_SENDSTALL | |
1325 | | MUSB_RXCSR_P_SENTSTALL); | |
1326 | musb_writew(epio, MUSB_RXCSR, csr); | |
1327 | } | |
1328 | ||
550a7375 FB |
1329 | /* maybe start the first request in the queue */ |
1330 | if (!musb_ep->busy && !value && request) { | |
1331 | DBG(3, "restarting the request\n"); | |
1332 | musb_ep_restart(musb, request); | |
1333 | } | |
1334 | ||
cea83241 | 1335 | done: |
550a7375 FB |
1336 | spin_unlock_irqrestore(&musb->lock, flags); |
1337 | return status; | |
1338 | } | |
1339 | ||
47e97605 SS |
1340 | /* |
1341 | * Sets the halt feature with the clear requests ignored | |
1342 | */ | |
1b6c3b0f | 1343 | static int musb_gadget_set_wedge(struct usb_ep *ep) |
47e97605 SS |
1344 | { |
1345 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1346 | ||
1347 | if (!ep) | |
1348 | return -EINVAL; | |
1349 | ||
1350 | musb_ep->wedged = 1; | |
1351 | ||
1352 | return usb_ep_set_halt(ep); | |
1353 | } | |
1354 | ||
550a7375 FB |
1355 | static int musb_gadget_fifo_status(struct usb_ep *ep) |
1356 | { | |
1357 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1358 | void __iomem *epio = musb_ep->hw_ep->regs; | |
1359 | int retval = -EINVAL; | |
1360 | ||
1361 | if (musb_ep->desc && !musb_ep->is_in) { | |
1362 | struct musb *musb = musb_ep->musb; | |
1363 | int epnum = musb_ep->current_epnum; | |
1364 | void __iomem *mbase = musb->mregs; | |
1365 | unsigned long flags; | |
1366 | ||
1367 | spin_lock_irqsave(&musb->lock, flags); | |
1368 | ||
1369 | musb_ep_select(mbase, epnum); | |
1370 | /* FIXME return zero unless RXPKTRDY is set */ | |
1371 | retval = musb_readw(epio, MUSB_RXCOUNT); | |
1372 | ||
1373 | spin_unlock_irqrestore(&musb->lock, flags); | |
1374 | } | |
1375 | return retval; | |
1376 | } | |
1377 | ||
1378 | static void musb_gadget_fifo_flush(struct usb_ep *ep) | |
1379 | { | |
1380 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1381 | struct musb *musb = musb_ep->musb; | |
1382 | u8 epnum = musb_ep->current_epnum; | |
1383 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1384 | void __iomem *mbase; | |
1385 | unsigned long flags; | |
1386 | u16 csr, int_txe; | |
1387 | ||
1388 | mbase = musb->mregs; | |
1389 | ||
1390 | spin_lock_irqsave(&musb->lock, flags); | |
1391 | musb_ep_select(mbase, (u8) epnum); | |
1392 | ||
1393 | /* disable interrupts */ | |
1394 | int_txe = musb_readw(mbase, MUSB_INTRTXE); | |
1395 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); | |
1396 | ||
1397 | if (musb_ep->is_in) { | |
1398 | csr = musb_readw(epio, MUSB_TXCSR); | |
1399 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1400 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; | |
1401 | musb_writew(epio, MUSB_TXCSR, csr); | |
1402 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1403 | musb_writew(epio, MUSB_TXCSR, csr); | |
1404 | } | |
1405 | } else { | |
1406 | csr = musb_readw(epio, MUSB_RXCSR); | |
1407 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; | |
1408 | musb_writew(epio, MUSB_RXCSR, csr); | |
1409 | musb_writew(epio, MUSB_RXCSR, csr); | |
1410 | } | |
1411 | ||
1412 | /* re-enable interrupt */ | |
1413 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
1414 | spin_unlock_irqrestore(&musb->lock, flags); | |
1415 | } | |
1416 | ||
1417 | static const struct usb_ep_ops musb_ep_ops = { | |
1418 | .enable = musb_gadget_enable, | |
1419 | .disable = musb_gadget_disable, | |
1420 | .alloc_request = musb_alloc_request, | |
1421 | .free_request = musb_free_request, | |
1422 | .queue = musb_gadget_queue, | |
1423 | .dequeue = musb_gadget_dequeue, | |
1424 | .set_halt = musb_gadget_set_halt, | |
47e97605 | 1425 | .set_wedge = musb_gadget_set_wedge, |
550a7375 FB |
1426 | .fifo_status = musb_gadget_fifo_status, |
1427 | .fifo_flush = musb_gadget_fifo_flush | |
1428 | }; | |
1429 | ||
1430 | /* ----------------------------------------------------------------------- */ | |
1431 | ||
1432 | static int musb_gadget_get_frame(struct usb_gadget *gadget) | |
1433 | { | |
1434 | struct musb *musb = gadget_to_musb(gadget); | |
1435 | ||
1436 | return (int)musb_readw(musb->mregs, MUSB_FRAME); | |
1437 | } | |
1438 | ||
1439 | static int musb_gadget_wakeup(struct usb_gadget *gadget) | |
1440 | { | |
1441 | struct musb *musb = gadget_to_musb(gadget); | |
1442 | void __iomem *mregs = musb->mregs; | |
1443 | unsigned long flags; | |
1444 | int status = -EINVAL; | |
1445 | u8 power, devctl; | |
1446 | int retries; | |
1447 | ||
1448 | spin_lock_irqsave(&musb->lock, flags); | |
1449 | ||
84e250ff | 1450 | switch (musb->xceiv->state) { |
550a7375 FB |
1451 | case OTG_STATE_B_PERIPHERAL: |
1452 | /* NOTE: OTG state machine doesn't include B_SUSPENDED; | |
1453 | * that's part of the standard usb 1.1 state machine, and | |
1454 | * doesn't affect OTG transitions. | |
1455 | */ | |
1456 | if (musb->may_wakeup && musb->is_suspended) | |
1457 | break; | |
1458 | goto done; | |
1459 | case OTG_STATE_B_IDLE: | |
1460 | /* Start SRP ... OTG not required. */ | |
1461 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1462 | DBG(2, "Sending SRP: devctl: %02x\n", devctl); | |
1463 | devctl |= MUSB_DEVCTL_SESSION; | |
1464 | musb_writeb(mregs, MUSB_DEVCTL, devctl); | |
1465 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1466 | retries = 100; | |
1467 | while (!(devctl & MUSB_DEVCTL_SESSION)) { | |
1468 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1469 | if (retries-- < 1) | |
1470 | break; | |
1471 | } | |
1472 | retries = 10000; | |
1473 | while (devctl & MUSB_DEVCTL_SESSION) { | |
1474 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1475 | if (retries-- < 1) | |
1476 | break; | |
1477 | } | |
1478 | ||
1479 | /* Block idling for at least 1s */ | |
1480 | musb_platform_try_idle(musb, | |
1481 | jiffies + msecs_to_jiffies(1 * HZ)); | |
1482 | ||
1483 | status = 0; | |
1484 | goto done; | |
1485 | default: | |
1486 | DBG(2, "Unhandled wake: %s\n", otg_state_string(musb)); | |
1487 | goto done; | |
1488 | } | |
1489 | ||
1490 | status = 0; | |
1491 | ||
1492 | power = musb_readb(mregs, MUSB_POWER); | |
1493 | power |= MUSB_POWER_RESUME; | |
1494 | musb_writeb(mregs, MUSB_POWER, power); | |
1495 | DBG(2, "issue wakeup\n"); | |
1496 | ||
1497 | /* FIXME do this next chunk in a timer callback, no udelay */ | |
1498 | mdelay(2); | |
1499 | ||
1500 | power = musb_readb(mregs, MUSB_POWER); | |
1501 | power &= ~MUSB_POWER_RESUME; | |
1502 | musb_writeb(mregs, MUSB_POWER, power); | |
1503 | done: | |
1504 | spin_unlock_irqrestore(&musb->lock, flags); | |
1505 | return status; | |
1506 | } | |
1507 | ||
1508 | static int | |
1509 | musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) | |
1510 | { | |
1511 | struct musb *musb = gadget_to_musb(gadget); | |
1512 | ||
1513 | musb->is_self_powered = !!is_selfpowered; | |
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | static void musb_pullup(struct musb *musb, int is_on) | |
1518 | { | |
1519 | u8 power; | |
1520 | ||
1521 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1522 | if (is_on) | |
1523 | power |= MUSB_POWER_SOFTCONN; | |
1524 | else | |
1525 | power &= ~MUSB_POWER_SOFTCONN; | |
1526 | ||
1527 | /* FIXME if on, HdrcStart; if off, HdrcStop */ | |
1528 | ||
1529 | DBG(3, "gadget %s D+ pullup %s\n", | |
1530 | musb->gadget_driver->function, is_on ? "on" : "off"); | |
1531 | musb_writeb(musb->mregs, MUSB_POWER, power); | |
1532 | } | |
1533 | ||
1534 | #if 0 | |
1535 | static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) | |
1536 | { | |
1537 | DBG(2, "<= %s =>\n", __func__); | |
1538 | ||
1539 | /* | |
1540 | * FIXME iff driver's softconnect flag is set (as it is during probe, | |
1541 | * though that can clear it), just musb_pullup(). | |
1542 | */ | |
1543 | ||
1544 | return -EINVAL; | |
1545 | } | |
1546 | #endif | |
1547 | ||
1548 | static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1549 | { | |
1550 | struct musb *musb = gadget_to_musb(gadget); | |
1551 | ||
84e250ff | 1552 | if (!musb->xceiv->set_power) |
550a7375 | 1553 | return -EOPNOTSUPP; |
84e250ff | 1554 | return otg_set_power(musb->xceiv, mA); |
550a7375 FB |
1555 | } |
1556 | ||
1557 | static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
1558 | { | |
1559 | struct musb *musb = gadget_to_musb(gadget); | |
1560 | unsigned long flags; | |
1561 | ||
1562 | is_on = !!is_on; | |
1563 | ||
1564 | /* NOTE: this assumes we are sensing vbus; we'd rather | |
1565 | * not pullup unless the B-session is active. | |
1566 | */ | |
1567 | spin_lock_irqsave(&musb->lock, flags); | |
1568 | if (is_on != musb->softconnect) { | |
1569 | musb->softconnect = is_on; | |
1570 | musb_pullup(musb, is_on); | |
1571 | } | |
1572 | spin_unlock_irqrestore(&musb->lock, flags); | |
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | static const struct usb_gadget_ops musb_gadget_operations = { | |
1577 | .get_frame = musb_gadget_get_frame, | |
1578 | .wakeup = musb_gadget_wakeup, | |
1579 | .set_selfpowered = musb_gadget_set_self_powered, | |
1580 | /* .vbus_session = musb_gadget_vbus_session, */ | |
1581 | .vbus_draw = musb_gadget_vbus_draw, | |
1582 | .pullup = musb_gadget_pullup, | |
1583 | }; | |
1584 | ||
1585 | /* ----------------------------------------------------------------------- */ | |
1586 | ||
1587 | /* Registration */ | |
1588 | ||
1589 | /* Only this registration code "knows" the rule (from USB standards) | |
1590 | * about there being only one external upstream port. It assumes | |
1591 | * all peripheral ports are external... | |
1592 | */ | |
1593 | static struct musb *the_gadget; | |
1594 | ||
1595 | static void musb_gadget_release(struct device *dev) | |
1596 | { | |
1597 | /* kref_put(WHAT) */ | |
1598 | dev_dbg(dev, "%s\n", __func__); | |
1599 | } | |
1600 | ||
1601 | ||
1602 | static void __init | |
1603 | init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) | |
1604 | { | |
1605 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1606 | ||
1607 | memset(ep, 0, sizeof *ep); | |
1608 | ||
1609 | ep->current_epnum = epnum; | |
1610 | ep->musb = musb; | |
1611 | ep->hw_ep = hw_ep; | |
1612 | ep->is_in = is_in; | |
1613 | ||
1614 | INIT_LIST_HEAD(&ep->req_list); | |
1615 | ||
1616 | sprintf(ep->name, "ep%d%s", epnum, | |
1617 | (!epnum || hw_ep->is_shared_fifo) ? "" : ( | |
1618 | is_in ? "in" : "out")); | |
1619 | ep->end_point.name = ep->name; | |
1620 | INIT_LIST_HEAD(&ep->end_point.ep_list); | |
1621 | if (!epnum) { | |
1622 | ep->end_point.maxpacket = 64; | |
1623 | ep->end_point.ops = &musb_g_ep0_ops; | |
1624 | musb->g.ep0 = &ep->end_point; | |
1625 | } else { | |
1626 | if (is_in) | |
1627 | ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; | |
1628 | else | |
1629 | ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; | |
1630 | ep->end_point.ops = &musb_ep_ops; | |
1631 | list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); | |
1632 | } | |
1633 | } | |
1634 | ||
1635 | /* | |
1636 | * Initialize the endpoints exposed to peripheral drivers, with backlinks | |
1637 | * to the rest of the driver state. | |
1638 | */ | |
1639 | static inline void __init musb_g_init_endpoints(struct musb *musb) | |
1640 | { | |
1641 | u8 epnum; | |
1642 | struct musb_hw_ep *hw_ep; | |
1643 | unsigned count = 0; | |
1644 | ||
1645 | /* intialize endpoint list just once */ | |
1646 | INIT_LIST_HEAD(&(musb->g.ep_list)); | |
1647 | ||
1648 | for (epnum = 0, hw_ep = musb->endpoints; | |
1649 | epnum < musb->nr_endpoints; | |
1650 | epnum++, hw_ep++) { | |
1651 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1652 | init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); | |
1653 | count++; | |
1654 | } else { | |
1655 | if (hw_ep->max_packet_sz_tx) { | |
1656 | init_peripheral_ep(musb, &hw_ep->ep_in, | |
1657 | epnum, 1); | |
1658 | count++; | |
1659 | } | |
1660 | if (hw_ep->max_packet_sz_rx) { | |
1661 | init_peripheral_ep(musb, &hw_ep->ep_out, | |
1662 | epnum, 0); | |
1663 | count++; | |
1664 | } | |
1665 | } | |
1666 | } | |
1667 | } | |
1668 | ||
1669 | /* called once during driver setup to initialize and link into | |
1670 | * the driver model; memory is zeroed. | |
1671 | */ | |
1672 | int __init musb_gadget_setup(struct musb *musb) | |
1673 | { | |
1674 | int status; | |
1675 | ||
1676 | /* REVISIT minor race: if (erroneously) setting up two | |
1677 | * musb peripherals at the same time, only the bus lock | |
1678 | * is probably held. | |
1679 | */ | |
1680 | if (the_gadget) | |
1681 | return -EBUSY; | |
1682 | the_gadget = musb; | |
1683 | ||
1684 | musb->g.ops = &musb_gadget_operations; | |
1685 | musb->g.is_dualspeed = 1; | |
1686 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1687 | ||
1688 | /* this "gadget" abstracts/virtualizes the controller */ | |
427c4f33 | 1689 | dev_set_name(&musb->g.dev, "gadget"); |
550a7375 FB |
1690 | musb->g.dev.parent = musb->controller; |
1691 | musb->g.dev.dma_mask = musb->controller->dma_mask; | |
1692 | musb->g.dev.release = musb_gadget_release; | |
1693 | musb->g.name = musb_driver_name; | |
1694 | ||
1695 | if (is_otg_enabled(musb)) | |
1696 | musb->g.is_otg = 1; | |
1697 | ||
1698 | musb_g_init_endpoints(musb); | |
1699 | ||
1700 | musb->is_active = 0; | |
1701 | musb_platform_try_idle(musb, 0); | |
1702 | ||
1703 | status = device_register(&musb->g.dev); | |
1704 | if (status != 0) | |
1705 | the_gadget = NULL; | |
1706 | return status; | |
1707 | } | |
1708 | ||
1709 | void musb_gadget_cleanup(struct musb *musb) | |
1710 | { | |
1711 | if (musb != the_gadget) | |
1712 | return; | |
1713 | ||
1714 | device_unregister(&musb->g.dev); | |
1715 | the_gadget = NULL; | |
1716 | } | |
1717 | ||
1718 | /* | |
1719 | * Register the gadget driver. Used by gadget drivers when | |
1720 | * registering themselves with the controller. | |
1721 | * | |
1722 | * -EINVAL something went wrong (not driver) | |
1723 | * -EBUSY another gadget is already using the controller | |
1724 | * -ENOMEM no memeory to perform the operation | |
1725 | * | |
1726 | * @param driver the gadget driver | |
b0fca50f | 1727 | * @param bind the driver's bind function |
550a7375 FB |
1728 | * @return <0 if error, 0 if everything is fine |
1729 | */ | |
b0fca50f UKK |
1730 | int usb_gadget_probe_driver(struct usb_gadget_driver *driver, |
1731 | int (*bind)(struct usb_gadget *)) | |
550a7375 FB |
1732 | { |
1733 | int retval; | |
1734 | unsigned long flags; | |
1735 | struct musb *musb = the_gadget; | |
1736 | ||
1737 | if (!driver | |
1738 | || driver->speed != USB_SPEED_HIGH | |
b0fca50f | 1739 | || !bind || !driver->setup) |
550a7375 FB |
1740 | return -EINVAL; |
1741 | ||
1742 | /* driver must be initialized to support peripheral mode */ | |
08e6c972 | 1743 | if (!musb) { |
550a7375 FB |
1744 | DBG(1, "%s, no dev??\n", __func__); |
1745 | return -ENODEV; | |
1746 | } | |
1747 | ||
1748 | DBG(3, "registering driver %s\n", driver->function); | |
1749 | spin_lock_irqsave(&musb->lock, flags); | |
1750 | ||
1751 | if (musb->gadget_driver) { | |
1752 | DBG(1, "%s is already bound to %s\n", | |
1753 | musb_driver_name, | |
1754 | musb->gadget_driver->driver.name); | |
1755 | retval = -EBUSY; | |
1756 | } else { | |
1757 | musb->gadget_driver = driver; | |
1758 | musb->g.dev.driver = &driver->driver; | |
1759 | driver->driver.bus = NULL; | |
1760 | musb->softconnect = 1; | |
1761 | retval = 0; | |
1762 | } | |
1763 | ||
1764 | spin_unlock_irqrestore(&musb->lock, flags); | |
1765 | ||
f362a475 | 1766 | if (retval == 0) { |
b0fca50f | 1767 | retval = bind(&musb->g); |
f362a475 FB |
1768 | if (retval != 0) { |
1769 | DBG(3, "bind to driver %s failed --> %d\n", | |
1770 | driver->driver.name, retval); | |
1771 | musb->gadget_driver = NULL; | |
1772 | musb->g.dev.driver = NULL; | |
1773 | } | |
550a7375 | 1774 | |
550a7375 FB |
1775 | spin_lock_irqsave(&musb->lock, flags); |
1776 | ||
84e250ff | 1777 | otg_set_peripheral(musb->xceiv, &musb->g); |
d4c433fe | 1778 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
1779 | musb->is_active = 1; |
1780 | ||
1781 | /* FIXME this ignores the softconnect flag. Drivers are | |
1782 | * allowed hold the peripheral inactive until for example | |
1783 | * userspace hooks up printer hardware or DSP codecs, so | |
1784 | * hosts only see fully functional devices. | |
1785 | */ | |
1786 | ||
1787 | if (!is_otg_enabled(musb)) | |
1788 | musb_start(musb); | |
1789 | ||
84e250ff DB |
1790 | otg_set_peripheral(musb->xceiv, &musb->g); |
1791 | ||
550a7375 FB |
1792 | spin_unlock_irqrestore(&musb->lock, flags); |
1793 | ||
1794 | if (is_otg_enabled(musb)) { | |
1795 | DBG(3, "OTG startup...\n"); | |
1796 | ||
1797 | /* REVISIT: funcall to other code, which also | |
1798 | * handles power budgeting ... this way also | |
1799 | * ensures HdrcStart is indirectly called. | |
1800 | */ | |
1801 | retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
1802 | if (retval < 0) { | |
1803 | DBG(1, "add_hcd failed, %d\n", retval); | |
1804 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 1805 | otg_set_peripheral(musb->xceiv, NULL); |
550a7375 FB |
1806 | musb->gadget_driver = NULL; |
1807 | musb->g.dev.driver = NULL; | |
1808 | spin_unlock_irqrestore(&musb->lock, flags); | |
1809 | } | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | return retval; | |
1814 | } | |
b0fca50f | 1815 | EXPORT_SYMBOL(usb_gadget_probe_driver); |
550a7375 FB |
1816 | |
1817 | static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) | |
1818 | { | |
1819 | int i; | |
1820 | struct musb_hw_ep *hw_ep; | |
1821 | ||
1822 | /* don't disconnect if it's not connected */ | |
1823 | if (musb->g.speed == USB_SPEED_UNKNOWN) | |
1824 | driver = NULL; | |
1825 | else | |
1826 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1827 | ||
1828 | /* deactivate the hardware */ | |
1829 | if (musb->softconnect) { | |
1830 | musb->softconnect = 0; | |
1831 | musb_pullup(musb, 0); | |
1832 | } | |
1833 | musb_stop(musb); | |
1834 | ||
1835 | /* killing any outstanding requests will quiesce the driver; | |
1836 | * then report disconnect | |
1837 | */ | |
1838 | if (driver) { | |
1839 | for (i = 0, hw_ep = musb->endpoints; | |
1840 | i < musb->nr_endpoints; | |
1841 | i++, hw_ep++) { | |
1842 | musb_ep_select(musb->mregs, i); | |
1843 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1844 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1845 | } else { | |
1846 | if (hw_ep->max_packet_sz_tx) | |
1847 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1848 | if (hw_ep->max_packet_sz_rx) | |
1849 | nuke(&hw_ep->ep_out, -ESHUTDOWN); | |
1850 | } | |
1851 | } | |
1852 | ||
1853 | spin_unlock(&musb->lock); | |
1854 | driver->disconnect(&musb->g); | |
1855 | spin_lock(&musb->lock); | |
1856 | } | |
1857 | } | |
1858 | ||
1859 | /* | |
1860 | * Unregister the gadget driver. Used by gadget drivers when | |
1861 | * unregistering themselves from the controller. | |
1862 | * | |
1863 | * @param driver the gadget driver to unregister | |
1864 | */ | |
1865 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1866 | { | |
1867 | unsigned long flags; | |
1868 | int retval = 0; | |
1869 | struct musb *musb = the_gadget; | |
1870 | ||
1871 | if (!driver || !driver->unbind || !musb) | |
1872 | return -EINVAL; | |
1873 | ||
1874 | /* REVISIT always use otg_set_peripheral() here too; | |
1875 | * this needs to shut down the OTG engine. | |
1876 | */ | |
1877 | ||
1878 | spin_lock_irqsave(&musb->lock, flags); | |
1879 | ||
1880 | #ifdef CONFIG_USB_MUSB_OTG | |
1881 | musb_hnp_stop(musb); | |
1882 | #endif | |
1883 | ||
1884 | if (musb->gadget_driver == driver) { | |
1885 | ||
1886 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
1887 | ||
84e250ff | 1888 | musb->xceiv->state = OTG_STATE_UNDEFINED; |
550a7375 | 1889 | stop_activity(musb, driver); |
84e250ff | 1890 | otg_set_peripheral(musb->xceiv, NULL); |
550a7375 FB |
1891 | |
1892 | DBG(3, "unregistering driver %s\n", driver->function); | |
1893 | spin_unlock_irqrestore(&musb->lock, flags); | |
1894 | driver->unbind(&musb->g); | |
1895 | spin_lock_irqsave(&musb->lock, flags); | |
1896 | ||
1897 | musb->gadget_driver = NULL; | |
1898 | musb->g.dev.driver = NULL; | |
1899 | ||
1900 | musb->is_active = 0; | |
1901 | musb_platform_try_idle(musb, 0); | |
1902 | } else | |
1903 | retval = -EINVAL; | |
1904 | spin_unlock_irqrestore(&musb->lock, flags); | |
1905 | ||
1906 | if (is_otg_enabled(musb) && retval == 0) { | |
1907 | usb_remove_hcd(musb_to_hcd(musb)); | |
1908 | /* FIXME we need to be able to register another | |
1909 | * gadget driver here and have everything work; | |
1910 | * that currently misbehaves. | |
1911 | */ | |
1912 | } | |
1913 | ||
1914 | return retval; | |
1915 | } | |
1916 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1917 | ||
1918 | ||
1919 | /* ----------------------------------------------------------------------- */ | |
1920 | ||
1921 | /* lifecycle operations called through plat_uds.c */ | |
1922 | ||
1923 | void musb_g_resume(struct musb *musb) | |
1924 | { | |
1925 | musb->is_suspended = 0; | |
84e250ff | 1926 | switch (musb->xceiv->state) { |
550a7375 FB |
1927 | case OTG_STATE_B_IDLE: |
1928 | break; | |
1929 | case OTG_STATE_B_WAIT_ACON: | |
1930 | case OTG_STATE_B_PERIPHERAL: | |
1931 | musb->is_active = 1; | |
1932 | if (musb->gadget_driver && musb->gadget_driver->resume) { | |
1933 | spin_unlock(&musb->lock); | |
1934 | musb->gadget_driver->resume(&musb->g); | |
1935 | spin_lock(&musb->lock); | |
1936 | } | |
1937 | break; | |
1938 | default: | |
1939 | WARNING("unhandled RESUME transition (%s)\n", | |
1940 | otg_state_string(musb)); | |
1941 | } | |
1942 | } | |
1943 | ||
1944 | /* called when SOF packets stop for 3+ msec */ | |
1945 | void musb_g_suspend(struct musb *musb) | |
1946 | { | |
1947 | u8 devctl; | |
1948 | ||
1949 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1950 | DBG(3, "devctl %02x\n", devctl); | |
1951 | ||
84e250ff | 1952 | switch (musb->xceiv->state) { |
550a7375 FB |
1953 | case OTG_STATE_B_IDLE: |
1954 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
84e250ff | 1955 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
1956 | break; |
1957 | case OTG_STATE_B_PERIPHERAL: | |
1958 | musb->is_suspended = 1; | |
1959 | if (musb->gadget_driver && musb->gadget_driver->suspend) { | |
1960 | spin_unlock(&musb->lock); | |
1961 | musb->gadget_driver->suspend(&musb->g); | |
1962 | spin_lock(&musb->lock); | |
1963 | } | |
1964 | break; | |
1965 | default: | |
1966 | /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; | |
1967 | * A_PERIPHERAL may need care too | |
1968 | */ | |
1969 | WARNING("unhandled SUSPEND transition (%s)\n", | |
1970 | otg_state_string(musb)); | |
1971 | } | |
1972 | } | |
1973 | ||
1974 | /* Called during SRP */ | |
1975 | void musb_g_wakeup(struct musb *musb) | |
1976 | { | |
1977 | musb_gadget_wakeup(&musb->g); | |
1978 | } | |
1979 | ||
1980 | /* called when VBUS drops below session threshold, and in other cases */ | |
1981 | void musb_g_disconnect(struct musb *musb) | |
1982 | { | |
1983 | void __iomem *mregs = musb->mregs; | |
1984 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1985 | ||
1986 | DBG(3, "devctl %02x\n", devctl); | |
1987 | ||
1988 | /* clear HR */ | |
1989 | musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); | |
1990 | ||
1991 | /* don't draw vbus until new b-default session */ | |
1992 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
1993 | ||
1994 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1995 | if (musb->gadget_driver && musb->gadget_driver->disconnect) { | |
1996 | spin_unlock(&musb->lock); | |
1997 | musb->gadget_driver->disconnect(&musb->g); | |
1998 | spin_lock(&musb->lock); | |
1999 | } | |
2000 | ||
84e250ff | 2001 | switch (musb->xceiv->state) { |
550a7375 FB |
2002 | default: |
2003 | #ifdef CONFIG_USB_MUSB_OTG | |
2004 | DBG(2, "Unhandled disconnect %s, setting a_idle\n", | |
2005 | otg_state_string(musb)); | |
84e250ff | 2006 | musb->xceiv->state = OTG_STATE_A_IDLE; |
ab983f2a | 2007 | MUSB_HST_MODE(musb); |
550a7375 FB |
2008 | break; |
2009 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae | 2010 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; |
ab983f2a | 2011 | MUSB_HST_MODE(musb); |
550a7375 FB |
2012 | break; |
2013 | case OTG_STATE_B_WAIT_ACON: | |
2014 | case OTG_STATE_B_HOST: | |
2015 | #endif | |
2016 | case OTG_STATE_B_PERIPHERAL: | |
2017 | case OTG_STATE_B_IDLE: | |
84e250ff | 2018 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
2019 | break; |
2020 | case OTG_STATE_B_SRP_INIT: | |
2021 | break; | |
2022 | } | |
2023 | ||
2024 | musb->is_active = 0; | |
2025 | } | |
2026 | ||
2027 | void musb_g_reset(struct musb *musb) | |
2028 | __releases(musb->lock) | |
2029 | __acquires(musb->lock) | |
2030 | { | |
2031 | void __iomem *mbase = musb->mregs; | |
2032 | u8 devctl = musb_readb(mbase, MUSB_DEVCTL); | |
2033 | u8 power; | |
2034 | ||
2035 | DBG(3, "<== %s addr=%x driver '%s'\n", | |
2036 | (devctl & MUSB_DEVCTL_BDEVICE) | |
2037 | ? "B-Device" : "A-Device", | |
2038 | musb_readb(mbase, MUSB_FADDR), | |
2039 | musb->gadget_driver | |
2040 | ? musb->gadget_driver->driver.name | |
2041 | : NULL | |
2042 | ); | |
2043 | ||
2044 | /* report disconnect, if we didn't already (flushing EP state) */ | |
2045 | if (musb->g.speed != USB_SPEED_UNKNOWN) | |
2046 | musb_g_disconnect(musb); | |
2047 | ||
2048 | /* clear HR */ | |
2049 | else if (devctl & MUSB_DEVCTL_HR) | |
2050 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
2051 | ||
2052 | ||
2053 | /* what speed did we negotiate? */ | |
2054 | power = musb_readb(mbase, MUSB_POWER); | |
2055 | musb->g.speed = (power & MUSB_POWER_HSMODE) | |
2056 | ? USB_SPEED_HIGH : USB_SPEED_FULL; | |
2057 | ||
2058 | /* start in USB_STATE_DEFAULT */ | |
2059 | musb->is_active = 1; | |
2060 | musb->is_suspended = 0; | |
2061 | MUSB_DEV_MODE(musb); | |
2062 | musb->address = 0; | |
2063 | musb->ep0_state = MUSB_EP0_STAGE_SETUP; | |
2064 | ||
2065 | musb->may_wakeup = 0; | |
2066 | musb->g.b_hnp_enable = 0; | |
2067 | musb->g.a_alt_hnp_support = 0; | |
2068 | musb->g.a_hnp_support = 0; | |
2069 | ||
2070 | /* Normal reset, as B-Device; | |
2071 | * or else after HNP, as A-Device | |
2072 | */ | |
2073 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
84e250ff | 2074 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
2075 | musb->g.is_a_peripheral = 0; |
2076 | } else if (is_otg_enabled(musb)) { | |
84e250ff | 2077 | musb->xceiv->state = OTG_STATE_A_PERIPHERAL; |
550a7375 FB |
2078 | musb->g.is_a_peripheral = 1; |
2079 | } else | |
2080 | WARN_ON(1); | |
2081 | ||
2082 | /* start with default limits on VBUS power draw */ | |
2083 | (void) musb_gadget_vbus_draw(&musb->g, | |
2084 | is_otg_enabled(musb) ? 8 : 100); | |
2085 | } |