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744543c5 HG |
1 | /* |
2 | * Allwinner sun4i MUSB Glue Layer | |
3 | * | |
4 | * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> | |
5 | * | |
6 | * Based on code from | |
7 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | */ | |
19 | ||
20 | #include <linux/clk.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/extcon.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/phy/phy-sun4i-usb.h> | |
28 | #include <linux/platform_device.h> | |
132e2377 | 29 | #include <linux/reset.h> |
744543c5 HG |
30 | #include <linux/soc/sunxi/sunxi_sram.h> |
31 | #include <linux/usb/musb.h> | |
32 | #include <linux/usb/of.h> | |
33 | #include <linux/usb/usb_phy_generic.h> | |
34 | #include <linux/workqueue.h> | |
35 | #include "musb_core.h" | |
36 | ||
37 | /* | |
38 | * Register offsets, note sunxi musb has a different layout then most | |
39 | * musb implementations, we translate the layout in musb_readb & friends. | |
40 | */ | |
41 | #define SUNXI_MUSB_POWER 0x0040 | |
42 | #define SUNXI_MUSB_DEVCTL 0x0041 | |
43 | #define SUNXI_MUSB_INDEX 0x0042 | |
44 | #define SUNXI_MUSB_VEND0 0x0043 | |
45 | #define SUNXI_MUSB_INTRTX 0x0044 | |
46 | #define SUNXI_MUSB_INTRRX 0x0046 | |
47 | #define SUNXI_MUSB_INTRTXE 0x0048 | |
48 | #define SUNXI_MUSB_INTRRXE 0x004a | |
49 | #define SUNXI_MUSB_INTRUSB 0x004c | |
50 | #define SUNXI_MUSB_INTRUSBE 0x0050 | |
51 | #define SUNXI_MUSB_FRAME 0x0054 | |
52 | #define SUNXI_MUSB_TXFIFOSZ 0x0090 | |
53 | #define SUNXI_MUSB_TXFIFOADD 0x0092 | |
54 | #define SUNXI_MUSB_RXFIFOSZ 0x0094 | |
55 | #define SUNXI_MUSB_RXFIFOADD 0x0096 | |
56 | #define SUNXI_MUSB_FADDR 0x0098 | |
57 | #define SUNXI_MUSB_TXFUNCADDR 0x0098 | |
58 | #define SUNXI_MUSB_TXHUBADDR 0x009a | |
59 | #define SUNXI_MUSB_TXHUBPORT 0x009b | |
60 | #define SUNXI_MUSB_RXFUNCADDR 0x009c | |
61 | #define SUNXI_MUSB_RXHUBADDR 0x009e | |
62 | #define SUNXI_MUSB_RXHUBPORT 0x009f | |
63 | #define SUNXI_MUSB_CONFIGDATA 0x00c0 | |
64 | ||
65 | /* VEND0 bits */ | |
66 | #define SUNXI_MUSB_VEND0_PIO_MODE 0 | |
67 | ||
68 | /* flags */ | |
69 | #define SUNXI_MUSB_FL_ENABLED 0 | |
70 | #define SUNXI_MUSB_FL_HOSTMODE 1 | |
71 | #define SUNXI_MUSB_FL_HOSTMODE_PEND 2 | |
72 | #define SUNXI_MUSB_FL_VBUS_ON 3 | |
73 | #define SUNXI_MUSB_FL_PHY_ON 4 | |
132e2377 HG |
74 | #define SUNXI_MUSB_FL_HAS_SRAM 5 |
75 | #define SUNXI_MUSB_FL_HAS_RESET 6 | |
d91de093 | 76 | #define SUNXI_MUSB_FL_NO_CONFIGDATA 7 |
7cba17ec | 77 | #define SUNXI_MUSB_FL_PHY_MODE_PEND 8 |
744543c5 HG |
78 | |
79 | /* Our read/write methods need access and do not get passed in a musb ref :| */ | |
80 | static struct musb *sunxi_musb; | |
81 | ||
82 | struct sunxi_glue { | |
83 | struct device *dev; | |
969a1327 HG |
84 | struct musb *musb; |
85 | struct platform_device *musb_pdev; | |
744543c5 | 86 | struct clk *clk; |
132e2377 | 87 | struct reset_control *rst; |
744543c5 HG |
88 | struct phy *phy; |
89 | struct platform_device *usb_phy; | |
90 | struct usb_phy *xceiv; | |
7cba17ec | 91 | enum phy_mode phy_mode; |
744543c5 HG |
92 | unsigned long flags; |
93 | struct work_struct work; | |
94 | struct extcon_dev *extcon; | |
95 | struct notifier_block host_nb; | |
96 | }; | |
97 | ||
98 | /* phy_power_on / off may sleep, so we use a workqueue */ | |
99 | static void sunxi_musb_work(struct work_struct *work) | |
100 | { | |
101 | struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work); | |
102 | bool vbus_on, phy_on; | |
103 | ||
104 | if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) | |
105 | return; | |
106 | ||
107 | if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { | |
969a1327 | 108 | struct musb *musb = glue->musb; |
744543c5 HG |
109 | unsigned long flags; |
110 | u8 devctl; | |
111 | ||
112 | spin_lock_irqsave(&musb->lock, flags); | |
113 | ||
114 | devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); | |
115 | if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { | |
116 | set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); | |
117 | musb->xceiv->otg->default_a = 1; | |
a60d541a | 118 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
744543c5 HG |
119 | MUSB_HST_MODE(musb); |
120 | devctl |= MUSB_DEVCTL_SESSION; | |
121 | } else { | |
122 | clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); | |
123 | musb->xceiv->otg->default_a = 0; | |
124 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; | |
125 | MUSB_DEV_MODE(musb); | |
126 | devctl &= ~MUSB_DEVCTL_SESSION; | |
127 | } | |
128 | writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL); | |
129 | ||
130 | spin_unlock_irqrestore(&musb->lock, flags); | |
131 | } | |
132 | ||
133 | vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); | |
134 | phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); | |
135 | ||
136 | if (phy_on != vbus_on) { | |
137 | if (vbus_on) { | |
138 | phy_power_on(glue->phy); | |
139 | set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); | |
140 | } else { | |
141 | phy_power_off(glue->phy); | |
142 | clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); | |
143 | } | |
144 | } | |
7cba17ec HG |
145 | |
146 | if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags)) | |
147 | phy_set_mode(glue->phy, glue->phy_mode); | |
744543c5 HG |
148 | } |
149 | ||
150 | static void sunxi_musb_set_vbus(struct musb *musb, int is_on) | |
151 | { | |
152 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
153 | ||
a60d541a | 154 | if (is_on) { |
744543c5 | 155 | set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); |
a60d541a HG |
156 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
157 | } else { | |
744543c5 | 158 | clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); |
a60d541a | 159 | } |
744543c5 HG |
160 | |
161 | schedule_work(&glue->work); | |
162 | } | |
163 | ||
164 | static void sunxi_musb_pre_root_reset_end(struct musb *musb) | |
165 | { | |
166 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
167 | ||
168 | sun4i_usb_phy_set_squelch_detect(glue->phy, false); | |
169 | } | |
170 | ||
171 | static void sunxi_musb_post_root_reset_end(struct musb *musb) | |
172 | { | |
173 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
174 | ||
175 | sun4i_usb_phy_set_squelch_detect(glue->phy, true); | |
176 | } | |
177 | ||
178 | static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) | |
179 | { | |
180 | struct musb *musb = __hci; | |
181 | unsigned long flags; | |
182 | ||
183 | spin_lock_irqsave(&musb->lock, flags); | |
184 | ||
185 | musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB); | |
186 | if (musb->int_usb) | |
187 | writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB); | |
188 | ||
744543c5 HG |
189 | if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) { |
190 | /* ep0 FADDR must be 0 when (re)entering peripheral mode */ | |
191 | musb_ep_select(musb->mregs, 0); | |
192 | musb_writeb(musb->mregs, MUSB_FADDR, 0); | |
193 | } | |
194 | ||
195 | musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); | |
196 | if (musb->int_tx) | |
197 | writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX); | |
198 | ||
199 | musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); | |
200 | if (musb->int_rx) | |
201 | writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX); | |
202 | ||
203 | musb_interrupt(musb); | |
204 | ||
205 | spin_unlock_irqrestore(&musb->lock, flags); | |
206 | ||
207 | return IRQ_HANDLED; | |
208 | } | |
209 | ||
210 | static int sunxi_musb_host_notifier(struct notifier_block *nb, | |
211 | unsigned long event, void *ptr) | |
212 | { | |
213 | struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb); | |
214 | ||
215 | if (event) | |
216 | set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); | |
217 | else | |
218 | clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); | |
219 | ||
220 | set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags); | |
221 | schedule_work(&glue->work); | |
222 | ||
223 | return NOTIFY_DONE; | |
224 | } | |
225 | ||
226 | static int sunxi_musb_init(struct musb *musb) | |
227 | { | |
228 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
229 | int ret; | |
230 | ||
231 | sunxi_musb = musb; | |
232 | musb->phy = glue->phy; | |
233 | musb->xceiv = glue->xceiv; | |
234 | ||
132e2377 HG |
235 | if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) { |
236 | ret = sunxi_sram_claim(musb->controller->parent); | |
237 | if (ret) | |
238 | return ret; | |
239 | } | |
744543c5 HG |
240 | |
241 | ret = clk_prepare_enable(glue->clk); | |
242 | if (ret) | |
243 | goto error_sram_release; | |
244 | ||
132e2377 HG |
245 | if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { |
246 | ret = reset_control_deassert(glue->rst); | |
247 | if (ret) | |
248 | goto error_clk_disable; | |
249 | } | |
250 | ||
744543c5 HG |
251 | writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0); |
252 | ||
253 | /* Register notifier before calling phy_init() */ | |
bb1d1ce8 CC |
254 | ret = devm_extcon_register_notifier(glue->dev, glue->extcon, |
255 | EXTCON_USB_HOST, &glue->host_nb); | |
a1ca2c6b HG |
256 | if (ret) |
257 | goto error_reset_assert; | |
744543c5 HG |
258 | |
259 | ret = phy_init(glue->phy); | |
260 | if (ret) | |
bb1d1ce8 | 261 | goto error_reset_assert; |
744543c5 | 262 | |
744543c5 HG |
263 | musb->isr = sunxi_musb_interrupt; |
264 | ||
265 | /* Stop the musb-core from doing runtime pm (not supported on sunxi) */ | |
266 | pm_runtime_get(musb->controller); | |
267 | ||
268 | return 0; | |
269 | ||
132e2377 HG |
270 | error_reset_assert: |
271 | if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) | |
272 | reset_control_assert(glue->rst); | |
744543c5 HG |
273 | error_clk_disable: |
274 | clk_disable_unprepare(glue->clk); | |
275 | error_sram_release: | |
132e2377 HG |
276 | if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) |
277 | sunxi_sram_release(musb->controller->parent); | |
744543c5 HG |
278 | return ret; |
279 | } | |
280 | ||
281 | static int sunxi_musb_exit(struct musb *musb) | |
282 | { | |
283 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
284 | ||
285 | pm_runtime_put(musb->controller); | |
286 | ||
287 | cancel_work_sync(&glue->work); | |
288 | if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags)) | |
289 | phy_power_off(glue->phy); | |
290 | ||
291 | phy_exit(glue->phy); | |
292 | ||
132e2377 HG |
293 | if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) |
294 | reset_control_assert(glue->rst); | |
295 | ||
744543c5 | 296 | clk_disable_unprepare(glue->clk); |
132e2377 HG |
297 | if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) |
298 | sunxi_sram_release(musb->controller->parent); | |
744543c5 | 299 | |
6ed05c68 JL |
300 | devm_usb_put_phy(glue->dev, glue->xceiv); |
301 | ||
744543c5 HG |
302 | return 0; |
303 | } | |
304 | ||
305 | static void sunxi_musb_enable(struct musb *musb) | |
306 | { | |
307 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
308 | ||
969a1327 HG |
309 | glue->musb = musb; |
310 | ||
744543c5 HG |
311 | /* musb_core does not call us in a balanced manner */ |
312 | if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) | |
313 | return; | |
314 | ||
315 | schedule_work(&glue->work); | |
316 | } | |
317 | ||
318 | static void sunxi_musb_disable(struct musb *musb) | |
319 | { | |
320 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
321 | ||
322 | clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags); | |
323 | } | |
324 | ||
cd53bd68 BD |
325 | static struct dma_controller * |
326 | sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base) | |
f301fe22 HG |
327 | { |
328 | return NULL; | |
329 | } | |
330 | ||
cd53bd68 | 331 | static void sunxi_musb_dma_controller_destroy(struct dma_controller *c) |
f301fe22 HG |
332 | { |
333 | } | |
334 | ||
7cba17ec HG |
335 | static int sunxi_musb_set_mode(struct musb *musb, u8 mode) |
336 | { | |
337 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
338 | enum phy_mode new_mode; | |
339 | ||
340 | switch (mode) { | |
341 | case MUSB_HOST: | |
342 | new_mode = PHY_MODE_USB_HOST; | |
343 | break; | |
344 | case MUSB_PERIPHERAL: | |
345 | new_mode = PHY_MODE_USB_DEVICE; | |
346 | break; | |
347 | case MUSB_OTG: | |
348 | new_mode = PHY_MODE_USB_OTG; | |
349 | break; | |
350 | default: | |
351 | dev_err(musb->controller->parent, | |
352 | "Error requested mode not supported by this kernel\n"); | |
353 | return -EINVAL; | |
354 | } | |
355 | ||
356 | if (glue->phy_mode == new_mode) | |
357 | return 0; | |
358 | ||
359 | if (musb->port_mode != MUSB_PORT_MODE_DUAL_ROLE) { | |
360 | dev_err(musb->controller->parent, | |
361 | "Error changing modes is only supported in dual role mode\n"); | |
362 | return -EINVAL; | |
363 | } | |
364 | ||
365 | if (musb->port1_status & USB_PORT_STAT_ENABLE) | |
366 | musb_root_disconnect(musb); | |
367 | ||
368 | /* | |
369 | * phy_set_mode may sleep, and we're called with a spinlock held, | |
370 | * so let sunxi_musb_work deal with it. | |
371 | */ | |
372 | glue->phy_mode = new_mode; | |
373 | set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); | |
374 | schedule_work(&glue->work); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
454f83d5 HG |
379 | static int sunxi_musb_recover(struct musb *musb) |
380 | { | |
381 | struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); | |
382 | ||
383 | /* | |
384 | * Schedule a phy_set_mode with the current glue->phy_mode value, | |
385 | * this will force end the current session. | |
386 | */ | |
387 | set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); | |
388 | schedule_work(&glue->work); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
744543c5 HG |
393 | /* |
394 | * sunxi musb register layout | |
395 | * 0x00 - 0x17 fifo regs, 1 long per fifo | |
396 | * 0x40 - 0x57 generic control regs (power - frame) | |
397 | * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed) | |
398 | * 0x90 - 0x97 fifo control regs (indexed) | |
399 | * 0x98 - 0x9f multipoint / busctl regs (indexed) | |
400 | * 0xc0 configdata reg | |
401 | */ | |
402 | ||
403 | static u32 sunxi_musb_fifo_offset(u8 epnum) | |
404 | { | |
405 | return (epnum * 4); | |
406 | } | |
407 | ||
408 | static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset) | |
409 | { | |
410 | WARN_ONCE(offset != 0, | |
411 | "sunxi_musb_ep_offset called with non 0 offset\n"); | |
412 | ||
413 | return 0x80; /* indexed, so ignore epnum */ | |
414 | } | |
415 | ||
416 | static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset) | |
417 | { | |
418 | return SUNXI_MUSB_TXFUNCADDR + offset; | |
419 | } | |
420 | ||
421 | static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset) | |
422 | { | |
d91de093 HG |
423 | struct sunxi_glue *glue; |
424 | ||
744543c5 HG |
425 | if (addr == sunxi_musb->mregs) { |
426 | /* generic control or fifo control reg access */ | |
427 | switch (offset) { | |
428 | case MUSB_FADDR: | |
429 | return readb(addr + SUNXI_MUSB_FADDR); | |
430 | case MUSB_POWER: | |
431 | return readb(addr + SUNXI_MUSB_POWER); | |
432 | case MUSB_INTRUSB: | |
433 | return readb(addr + SUNXI_MUSB_INTRUSB); | |
434 | case MUSB_INTRUSBE: | |
435 | return readb(addr + SUNXI_MUSB_INTRUSBE); | |
436 | case MUSB_INDEX: | |
437 | return readb(addr + SUNXI_MUSB_INDEX); | |
438 | case MUSB_TESTMODE: | |
439 | return 0; /* No testmode on sunxi */ | |
440 | case MUSB_DEVCTL: | |
441 | return readb(addr + SUNXI_MUSB_DEVCTL); | |
442 | case MUSB_TXFIFOSZ: | |
443 | return readb(addr + SUNXI_MUSB_TXFIFOSZ); | |
444 | case MUSB_RXFIFOSZ: | |
445 | return readb(addr + SUNXI_MUSB_RXFIFOSZ); | |
446 | case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */ | |
d91de093 HG |
447 | glue = dev_get_drvdata(sunxi_musb->controller->parent); |
448 | /* A33 saves a reg, and we get to hardcode this */ | |
449 | if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, | |
450 | &glue->flags)) | |
451 | return 0xde; | |
452 | ||
744543c5 HG |
453 | return readb(addr + SUNXI_MUSB_CONFIGDATA); |
454 | /* Offset for these is fixed by sunxi_musb_busctl_offset() */ | |
455 | case SUNXI_MUSB_TXFUNCADDR: | |
456 | case SUNXI_MUSB_TXHUBADDR: | |
457 | case SUNXI_MUSB_TXHUBPORT: | |
458 | case SUNXI_MUSB_RXFUNCADDR: | |
459 | case SUNXI_MUSB_RXHUBADDR: | |
460 | case SUNXI_MUSB_RXHUBPORT: | |
461 | /* multipoint / busctl reg access */ | |
462 | return readb(addr + offset); | |
463 | default: | |
464 | dev_err(sunxi_musb->controller->parent, | |
465 | "Error unknown readb offset %u\n", offset); | |
466 | return 0; | |
467 | } | |
468 | } else if (addr == (sunxi_musb->mregs + 0x80)) { | |
469 | /* ep control reg access */ | |
470 | /* sunxi has a 2 byte hole before the txtype register */ | |
471 | if (offset >= MUSB_TXTYPE) | |
472 | offset += 2; | |
473 | return readb(addr + offset); | |
474 | } | |
475 | ||
476 | dev_err(sunxi_musb->controller->parent, | |
477 | "Error unknown readb at 0x%x bytes offset\n", | |
478 | (int)(addr - sunxi_musb->mregs)); | |
479 | return 0; | |
480 | } | |
481 | ||
482 | static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data) | |
483 | { | |
484 | if (addr == sunxi_musb->mregs) { | |
485 | /* generic control or fifo control reg access */ | |
486 | switch (offset) { | |
487 | case MUSB_FADDR: | |
488 | return writeb(data, addr + SUNXI_MUSB_FADDR); | |
489 | case MUSB_POWER: | |
490 | return writeb(data, addr + SUNXI_MUSB_POWER); | |
491 | case MUSB_INTRUSB: | |
492 | return writeb(data, addr + SUNXI_MUSB_INTRUSB); | |
493 | case MUSB_INTRUSBE: | |
494 | return writeb(data, addr + SUNXI_MUSB_INTRUSBE); | |
495 | case MUSB_INDEX: | |
496 | return writeb(data, addr + SUNXI_MUSB_INDEX); | |
497 | case MUSB_TESTMODE: | |
498 | if (data) | |
499 | dev_warn(sunxi_musb->controller->parent, | |
500 | "sunxi-musb does not have testmode\n"); | |
501 | return; | |
502 | case MUSB_DEVCTL: | |
503 | return writeb(data, addr + SUNXI_MUSB_DEVCTL); | |
504 | case MUSB_TXFIFOSZ: | |
505 | return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ); | |
506 | case MUSB_RXFIFOSZ: | |
507 | return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ); | |
508 | /* Offset for these is fixed by sunxi_musb_busctl_offset() */ | |
509 | case SUNXI_MUSB_TXFUNCADDR: | |
510 | case SUNXI_MUSB_TXHUBADDR: | |
511 | case SUNXI_MUSB_TXHUBPORT: | |
512 | case SUNXI_MUSB_RXFUNCADDR: | |
513 | case SUNXI_MUSB_RXHUBADDR: | |
514 | case SUNXI_MUSB_RXHUBPORT: | |
515 | /* multipoint / busctl reg access */ | |
516 | return writeb(data, addr + offset); | |
517 | default: | |
518 | dev_err(sunxi_musb->controller->parent, | |
519 | "Error unknown writeb offset %u\n", offset); | |
520 | return; | |
521 | } | |
522 | } else if (addr == (sunxi_musb->mregs + 0x80)) { | |
523 | /* ep control reg access */ | |
524 | if (offset >= MUSB_TXTYPE) | |
525 | offset += 2; | |
526 | return writeb(data, addr + offset); | |
527 | } | |
528 | ||
529 | dev_err(sunxi_musb->controller->parent, | |
530 | "Error unknown writeb at 0x%x bytes offset\n", | |
531 | (int)(addr - sunxi_musb->mregs)); | |
532 | } | |
533 | ||
534 | static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset) | |
535 | { | |
536 | if (addr == sunxi_musb->mregs) { | |
537 | /* generic control or fifo control reg access */ | |
538 | switch (offset) { | |
539 | case MUSB_INTRTX: | |
540 | return readw(addr + SUNXI_MUSB_INTRTX); | |
541 | case MUSB_INTRRX: | |
542 | return readw(addr + SUNXI_MUSB_INTRRX); | |
543 | case MUSB_INTRTXE: | |
544 | return readw(addr + SUNXI_MUSB_INTRTXE); | |
545 | case MUSB_INTRRXE: | |
546 | return readw(addr + SUNXI_MUSB_INTRRXE); | |
547 | case MUSB_FRAME: | |
548 | return readw(addr + SUNXI_MUSB_FRAME); | |
549 | case MUSB_TXFIFOADD: | |
550 | return readw(addr + SUNXI_MUSB_TXFIFOADD); | |
551 | case MUSB_RXFIFOADD: | |
552 | return readw(addr + SUNXI_MUSB_RXFIFOADD); | |
553 | case MUSB_HWVERS: | |
554 | return 0; /* sunxi musb version is not known */ | |
555 | default: | |
556 | dev_err(sunxi_musb->controller->parent, | |
557 | "Error unknown readw offset %u\n", offset); | |
558 | return 0; | |
559 | } | |
560 | } else if (addr == (sunxi_musb->mregs + 0x80)) { | |
561 | /* ep control reg access */ | |
562 | return readw(addr + offset); | |
563 | } | |
564 | ||
565 | dev_err(sunxi_musb->controller->parent, | |
566 | "Error unknown readw at 0x%x bytes offset\n", | |
567 | (int)(addr - sunxi_musb->mregs)); | |
568 | return 0; | |
569 | } | |
570 | ||
571 | static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data) | |
572 | { | |
573 | if (addr == sunxi_musb->mregs) { | |
574 | /* generic control or fifo control reg access */ | |
575 | switch (offset) { | |
576 | case MUSB_INTRTX: | |
577 | return writew(data, addr + SUNXI_MUSB_INTRTX); | |
578 | case MUSB_INTRRX: | |
579 | return writew(data, addr + SUNXI_MUSB_INTRRX); | |
580 | case MUSB_INTRTXE: | |
581 | return writew(data, addr + SUNXI_MUSB_INTRTXE); | |
582 | case MUSB_INTRRXE: | |
583 | return writew(data, addr + SUNXI_MUSB_INTRRXE); | |
584 | case MUSB_FRAME: | |
585 | return writew(data, addr + SUNXI_MUSB_FRAME); | |
586 | case MUSB_TXFIFOADD: | |
587 | return writew(data, addr + SUNXI_MUSB_TXFIFOADD); | |
588 | case MUSB_RXFIFOADD: | |
589 | return writew(data, addr + SUNXI_MUSB_RXFIFOADD); | |
590 | default: | |
591 | dev_err(sunxi_musb->controller->parent, | |
592 | "Error unknown writew offset %u\n", offset); | |
593 | return; | |
594 | } | |
595 | } else if (addr == (sunxi_musb->mregs + 0x80)) { | |
596 | /* ep control reg access */ | |
597 | return writew(data, addr + offset); | |
598 | } | |
599 | ||
600 | dev_err(sunxi_musb->controller->parent, | |
601 | "Error unknown writew at 0x%x bytes offset\n", | |
602 | (int)(addr - sunxi_musb->mregs)); | |
603 | } | |
604 | ||
605 | static const struct musb_platform_ops sunxi_musb_ops = { | |
606 | .quirks = MUSB_INDEXED_EP, | |
607 | .init = sunxi_musb_init, | |
608 | .exit = sunxi_musb_exit, | |
609 | .enable = sunxi_musb_enable, | |
610 | .disable = sunxi_musb_disable, | |
611 | .fifo_offset = sunxi_musb_fifo_offset, | |
612 | .ep_offset = sunxi_musb_ep_offset, | |
613 | .busctl_offset = sunxi_musb_busctl_offset, | |
614 | .readb = sunxi_musb_readb, | |
615 | .writeb = sunxi_musb_writeb, | |
616 | .readw = sunxi_musb_readw, | |
617 | .writew = sunxi_musb_writew, | |
f301fe22 HG |
618 | .dma_init = sunxi_musb_dma_controller_create, |
619 | .dma_exit = sunxi_musb_dma_controller_destroy, | |
7cba17ec | 620 | .set_mode = sunxi_musb_set_mode, |
454f83d5 | 621 | .recover = sunxi_musb_recover, |
744543c5 HG |
622 | .set_vbus = sunxi_musb_set_vbus, |
623 | .pre_root_reset_end = sunxi_musb_pre_root_reset_end, | |
624 | .post_root_reset_end = sunxi_musb_post_root_reset_end, | |
625 | }; | |
626 | ||
627 | /* Allwinner OTG supports up to 5 endpoints */ | |
628 | #define SUNXI_MUSB_MAX_EP_NUM 6 | |
629 | #define SUNXI_MUSB_RAM_BITS 11 | |
630 | ||
631 | static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = { | |
632 | MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), | |
633 | MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), | |
634 | MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), | |
635 | MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), | |
636 | MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), | |
637 | MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), | |
638 | MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), | |
639 | MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), | |
640 | MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), | |
641 | MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), | |
642 | }; | |
643 | ||
c1fce66e IZ |
644 | /* H3/V3s OTG supports only 4 endpoints */ |
645 | #define SUNXI_MUSB_MAX_EP_NUM_H3 5 | |
646 | ||
647 | static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = { | |
648 | MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), | |
649 | MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), | |
650 | MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), | |
651 | MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), | |
652 | MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), | |
653 | MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), | |
654 | MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), | |
655 | MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), | |
656 | }; | |
657 | ||
1e572aa5 | 658 | static const struct musb_hdrc_config sunxi_musb_hdrc_config = { |
744543c5 HG |
659 | .fifo_cfg = sunxi_musb_mode_cfg, |
660 | .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg), | |
661 | .multipoint = true, | |
662 | .dyn_fifo = true, | |
663 | .soft_con = true, | |
664 | .num_eps = SUNXI_MUSB_MAX_EP_NUM, | |
665 | .ram_bits = SUNXI_MUSB_RAM_BITS, | |
666 | .dma = 0, | |
667 | }; | |
668 | ||
c1fce66e IZ |
669 | static struct musb_hdrc_config sunxi_musb_hdrc_config_h3 = { |
670 | .fifo_cfg = sunxi_musb_mode_cfg_h3, | |
671 | .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3), | |
672 | .multipoint = true, | |
673 | .dyn_fifo = true, | |
674 | .soft_con = true, | |
675 | .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3, | |
676 | .ram_bits = SUNXI_MUSB_RAM_BITS, | |
677 | .dma = 0, | |
678 | }; | |
679 | ||
680 | ||
744543c5 HG |
681 | static int sunxi_musb_probe(struct platform_device *pdev) |
682 | { | |
683 | struct musb_hdrc_platform_data pdata; | |
684 | struct platform_device_info pinfo; | |
685 | struct sunxi_glue *glue; | |
686 | struct device_node *np = pdev->dev.of_node; | |
687 | int ret; | |
688 | ||
689 | if (!np) { | |
690 | dev_err(&pdev->dev, "Error no device tree node found\n"); | |
691 | return -EINVAL; | |
692 | } | |
693 | ||
7cba17ec HG |
694 | glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); |
695 | if (!glue) | |
696 | return -ENOMEM; | |
697 | ||
744543c5 | 698 | memset(&pdata, 0, sizeof(pdata)); |
06e7114f | 699 | switch (usb_get_dr_mode(&pdev->dev)) { |
744543c5 HG |
700 | #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST |
701 | case USB_DR_MODE_HOST: | |
702 | pdata.mode = MUSB_PORT_MODE_HOST; | |
7cba17ec | 703 | glue->phy_mode = PHY_MODE_USB_HOST; |
744543c5 HG |
704 | break; |
705 | #endif | |
a1ca2c6b HG |
706 | #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET |
707 | case USB_DR_MODE_PERIPHERAL: | |
708 | pdata.mode = MUSB_PORT_MODE_GADGET; | |
7cba17ec | 709 | glue->phy_mode = PHY_MODE_USB_DEVICE; |
a1ca2c6b HG |
710 | break; |
711 | #endif | |
744543c5 HG |
712 | #ifdef CONFIG_USB_MUSB_DUAL_ROLE |
713 | case USB_DR_MODE_OTG: | |
744543c5 | 714 | pdata.mode = MUSB_PORT_MODE_DUAL_ROLE; |
7cba17ec | 715 | glue->phy_mode = PHY_MODE_USB_OTG; |
744543c5 HG |
716 | break; |
717 | #endif | |
718 | default: | |
719 | dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n"); | |
720 | return -EINVAL; | |
721 | } | |
722 | pdata.platform_ops = &sunxi_musb_ops; | |
c1fce66e IZ |
723 | if (!of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) |
724 | pdata.config = &sunxi_musb_hdrc_config; | |
725 | else | |
726 | pdata.config = &sunxi_musb_hdrc_config_h3; | |
744543c5 HG |
727 | |
728 | glue->dev = &pdev->dev; | |
729 | INIT_WORK(&glue->work, sunxi_musb_work); | |
730 | glue->host_nb.notifier_call = sunxi_musb_host_notifier; | |
731 | ||
132e2377 HG |
732 | if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb")) |
733 | set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags); | |
734 | ||
735 | if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb")) | |
736 | set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); | |
737 | ||
c1fce66e IZ |
738 | if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") || |
739 | of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) { | |
d91de093 HG |
740 | set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); |
741 | set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags); | |
742 | } | |
743 | ||
744543c5 HG |
744 | glue->clk = devm_clk_get(&pdev->dev, NULL); |
745 | if (IS_ERR(glue->clk)) { | |
746 | dev_err(&pdev->dev, "Error getting clock: %ld\n", | |
747 | PTR_ERR(glue->clk)); | |
748 | return PTR_ERR(glue->clk); | |
749 | } | |
750 | ||
132e2377 HG |
751 | if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { |
752 | glue->rst = devm_reset_control_get(&pdev->dev, NULL); | |
753 | if (IS_ERR(glue->rst)) { | |
754 | if (PTR_ERR(glue->rst) == -EPROBE_DEFER) | |
755 | return -EPROBE_DEFER; | |
756 | dev_err(&pdev->dev, "Error getting reset %ld\n", | |
757 | PTR_ERR(glue->rst)); | |
758 | return PTR_ERR(glue->rst); | |
759 | } | |
760 | } | |
761 | ||
a1ca2c6b HG |
762 | glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0); |
763 | if (IS_ERR(glue->extcon)) { | |
764 | if (PTR_ERR(glue->extcon) == -EPROBE_DEFER) | |
765 | return -EPROBE_DEFER; | |
766 | dev_err(&pdev->dev, "Invalid or missing extcon\n"); | |
767 | return PTR_ERR(glue->extcon); | |
768 | } | |
769 | ||
744543c5 HG |
770 | glue->phy = devm_phy_get(&pdev->dev, "usb"); |
771 | if (IS_ERR(glue->phy)) { | |
772 | if (PTR_ERR(glue->phy) == -EPROBE_DEFER) | |
773 | return -EPROBE_DEFER; | |
774 | dev_err(&pdev->dev, "Error getting phy %ld\n", | |
775 | PTR_ERR(glue->phy)); | |
776 | return PTR_ERR(glue->phy); | |
777 | } | |
778 | ||
779 | glue->usb_phy = usb_phy_generic_register(); | |
780 | if (IS_ERR(glue->usb_phy)) { | |
781 | dev_err(&pdev->dev, "Error registering usb-phy %ld\n", | |
782 | PTR_ERR(glue->usb_phy)); | |
783 | return PTR_ERR(glue->usb_phy); | |
784 | } | |
785 | ||
786 | glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); | |
787 | if (IS_ERR(glue->xceiv)) { | |
788 | ret = PTR_ERR(glue->xceiv); | |
789 | dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret); | |
790 | goto err_unregister_usb_phy; | |
791 | } | |
792 | ||
793 | platform_set_drvdata(pdev, glue); | |
794 | ||
795 | memset(&pinfo, 0, sizeof(pinfo)); | |
796 | pinfo.name = "musb-hdrc"; | |
797 | pinfo.id = PLATFORM_DEVID_AUTO; | |
798 | pinfo.parent = &pdev->dev; | |
799 | pinfo.res = pdev->resource; | |
800 | pinfo.num_res = pdev->num_resources; | |
801 | pinfo.data = &pdata; | |
802 | pinfo.size_data = sizeof(pdata); | |
803 | ||
969a1327 HG |
804 | glue->musb_pdev = platform_device_register_full(&pinfo); |
805 | if (IS_ERR(glue->musb_pdev)) { | |
806 | ret = PTR_ERR(glue->musb_pdev); | |
744543c5 HG |
807 | dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret); |
808 | goto err_unregister_usb_phy; | |
809 | } | |
810 | ||
811 | return 0; | |
812 | ||
813 | err_unregister_usb_phy: | |
814 | usb_phy_generic_unregister(glue->usb_phy); | |
815 | return ret; | |
816 | } | |
817 | ||
818 | static int sunxi_musb_remove(struct platform_device *pdev) | |
819 | { | |
820 | struct sunxi_glue *glue = platform_get_drvdata(pdev); | |
821 | struct platform_device *usb_phy = glue->usb_phy; | |
822 | ||
1c4bf5ac | 823 | platform_device_unregister(glue->musb_pdev); |
744543c5 HG |
824 | usb_phy_generic_unregister(usb_phy); |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
829 | static const struct of_device_id sunxi_musb_match[] = { | |
830 | { .compatible = "allwinner,sun4i-a10-musb", }, | |
132e2377 | 831 | { .compatible = "allwinner,sun6i-a31-musb", }, |
d91de093 | 832 | { .compatible = "allwinner,sun8i-a33-musb", }, |
c1fce66e | 833 | { .compatible = "allwinner,sun8i-h3-musb", }, |
744543c5 HG |
834 | {} |
835 | }; | |
76485d8e | 836 | MODULE_DEVICE_TABLE(of, sunxi_musb_match); |
744543c5 HG |
837 | |
838 | static struct platform_driver sunxi_musb_driver = { | |
839 | .probe = sunxi_musb_probe, | |
840 | .remove = sunxi_musb_remove, | |
841 | .driver = { | |
842 | .name = "musb-sunxi", | |
843 | .of_match_table = sunxi_musb_match, | |
844 | }, | |
845 | }; | |
846 | module_platform_driver(sunxi_musb_driver); | |
847 | ||
848 | MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer"); | |
849 | MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); | |
850 | MODULE_LICENSE("GPL v2"); |