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1 | /* |
2 | * SBSA(Server Base System Architecture) Generic Watchdog driver | |
3 | * | |
4 | * Copyright (c) 2015, Linaro Ltd. | |
5 | * Author: Fu Wei <fu.wei@linaro.org> | |
6 | * Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> | |
7 | * Al Stone <al.stone@linaro.org> | |
8 | * Timur Tabi <timur@codeaurora.org> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License 2 as published | |
12 | * by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * ARM SBSA Generic Watchdog has two stage timeouts: | |
20 | * the first signal (WS0) is for alerting the system by interrupt, | |
21 | * the second one (WS1) is a real hardware reset. | |
22 | * More details about the hardware specification of this device: | |
23 | * ARM DEN0029B - Server Base System Architecture (SBSA) | |
24 | * | |
25 | * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog | |
26 | * or a two stages watchdog, it's set up by the module parameter "action". | |
27 | * In the single stage mode, when the timeout is reached, your system | |
28 | * will be reset by WS1. The first signal (WS0) is ignored. | |
29 | * In the two stages mode, when the timeout is reached, the first signal (WS0) | |
30 | * will trigger panic. If the system is getting into trouble and cannot be reset | |
31 | * by panic or restart properly by the kdump kernel(if supported), then the | |
32 | * second stage (as long as the first stage) will be reached, system will be | |
33 | * reset by WS1. This function can help administrator to backup the system | |
34 | * context info by panic console output or kdump. | |
35 | * | |
36 | * SBSA GWDT: | |
37 | * if action is 1 (the two stages mode): | |
38 | * |--------WOR-------WS0--------WOR-------WS1 | |
39 | * |----timeout-----(panic)----timeout-----reset | |
40 | * | |
41 | * if action is 0 (the single stage mode): | |
42 | * |------WOR-----WS0(ignored)-----WOR------WS1 | |
43 | * |--------------timeout-------------------reset | |
44 | * | |
45 | * Note: Since this watchdog timer has two stages, and each stage is determined | |
46 | * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two | |
47 | * stages mode, the timeout is WOR. The maximum timeout in the two stages mode | |
48 | * is half of that in the single stage mode. | |
49 | * | |
50 | */ | |
51 | ||
52 | #include <linux/io.h> | |
06928d94 | 53 | #include <linux/io-64-nonatomic-lo-hi.h> |
57d2caaa FW |
54 | #include <linux/interrupt.h> |
55 | #include <linux/module.h> | |
56 | #include <linux/moduleparam.h> | |
57 | #include <linux/of.h> | |
58 | #include <linux/of_device.h> | |
59 | #include <linux/platform_device.h> | |
60 | #include <linux/uaccess.h> | |
61 | #include <linux/watchdog.h> | |
62 | #include <asm/arch_timer.h> | |
63 | ||
64 | #define DRV_NAME "sbsa-gwdt" | |
65 | #define WATCHDOG_NAME "SBSA Generic Watchdog" | |
66 | ||
67 | /* SBSA Generic Watchdog register definitions */ | |
68 | /* refresh frame */ | |
69 | #define SBSA_GWDT_WRR 0x000 | |
70 | ||
71 | /* control frame */ | |
72 | #define SBSA_GWDT_WCS 0x000 | |
73 | #define SBSA_GWDT_WOR 0x008 | |
74 | #define SBSA_GWDT_WCV 0x010 | |
75 | ||
76 | /* refresh/control frame */ | |
77 | #define SBSA_GWDT_W_IIDR 0xfcc | |
78 | #define SBSA_GWDT_IDR 0xfd0 | |
79 | ||
80 | /* Watchdog Control and Status Register */ | |
81 | #define SBSA_GWDT_WCS_EN BIT(0) | |
82 | #define SBSA_GWDT_WCS_WS0 BIT(1) | |
83 | #define SBSA_GWDT_WCS_WS1 BIT(2) | |
84 | ||
85 | /** | |
86 | * struct sbsa_gwdt - Internal representation of the SBSA GWDT | |
87 | * @wdd: kernel watchdog_device structure | |
88 | * @clk: store the System Counter clock frequency, in Hz. | |
89 | * @refresh_base: Virtual address of the watchdog refresh frame | |
90 | * @control_base: Virtual address of the watchdog control frame | |
91 | */ | |
92 | struct sbsa_gwdt { | |
93 | struct watchdog_device wdd; | |
94 | u32 clk; | |
95 | void __iomem *refresh_base; | |
96 | void __iomem *control_base; | |
97 | }; | |
98 | ||
99 | #define DEFAULT_TIMEOUT 10 /* seconds */ | |
100 | ||
101 | static unsigned int timeout; | |
102 | module_param(timeout, uint, 0); | |
103 | MODULE_PARM_DESC(timeout, | |
104 | "Watchdog timeout in seconds. (>=0, default=" | |
105 | __MODULE_STRING(DEFAULT_TIMEOUT) ")"); | |
106 | ||
107 | /* | |
108 | * action refers to action taken when watchdog gets WS0 | |
109 | * 0 = skip | |
110 | * 1 = panic | |
111 | * defaults to skip (0) | |
112 | */ | |
113 | static int action; | |
114 | module_param(action, int, 0); | |
115 | MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: " | |
116 | "0 = skip(*) 1 = panic"); | |
117 | ||
118 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
119 | module_param(nowayout, bool, S_IRUGO); | |
120 | MODULE_PARM_DESC(nowayout, | |
121 | "Watchdog cannot be stopped once started (default=" | |
122 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
123 | ||
124 | /* | |
125 | * watchdog operation functions | |
126 | */ | |
127 | static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd, | |
128 | unsigned int timeout) | |
129 | { | |
130 | struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); | |
131 | ||
132 | wdd->timeout = timeout; | |
133 | ||
134 | if (action) | |
135 | writel(gwdt->clk * timeout, | |
136 | gwdt->control_base + SBSA_GWDT_WOR); | |
137 | else | |
138 | /* | |
139 | * In the single stage mode, The first signal (WS0) is ignored, | |
140 | * the timeout is (WOR * 2), so the WOR should be configured | |
141 | * to half value of timeout. | |
142 | */ | |
143 | writel(gwdt->clk / 2 * timeout, | |
144 | gwdt->control_base + SBSA_GWDT_WOR); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd) | |
150 | { | |
151 | struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); | |
152 | u64 timeleft = 0; | |
153 | ||
154 | /* | |
155 | * In the single stage mode, if WS0 is deasserted | |
156 | * (watchdog is in the first stage), | |
157 | * timeleft = WOR + (WCV - system counter) | |
158 | */ | |
159 | if (!action && | |
160 | !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0)) | |
161 | timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR); | |
162 | ||
06928d94 | 163 | timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) - |
57d2caaa FW |
164 | arch_counter_get_cntvct(); |
165 | ||
166 | do_div(timeleft, gwdt->clk); | |
167 | ||
168 | return timeleft; | |
169 | } | |
170 | ||
171 | static int sbsa_gwdt_keepalive(struct watchdog_device *wdd) | |
172 | { | |
173 | struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); | |
174 | ||
175 | /* | |
176 | * Writing WRR for an explicit watchdog refresh. | |
177 | * You can write anyting (like 0). | |
178 | */ | |
179 | writel(0, gwdt->refresh_base + SBSA_GWDT_WRR); | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
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184 | static int sbsa_gwdt_start(struct watchdog_device *wdd) |
185 | { | |
186 | struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); | |
187 | ||
188 | /* writing WCS will cause an explicit watchdog refresh */ | |
189 | writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS); | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | static int sbsa_gwdt_stop(struct watchdog_device *wdd) | |
195 | { | |
196 | struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); | |
197 | ||
198 | /* Simply write 0 to WCS to clean WCS_EN bit */ | |
199 | writel(0, gwdt->control_base + SBSA_GWDT_WCS); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id) | |
205 | { | |
206 | panic(WATCHDOG_NAME " timeout"); | |
207 | ||
208 | return IRQ_HANDLED; | |
209 | } | |
210 | ||
6c368932 | 211 | static const struct watchdog_info sbsa_gwdt_info = { |
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212 | .identity = WATCHDOG_NAME, |
213 | .options = WDIOF_SETTIMEOUT | | |
214 | WDIOF_KEEPALIVEPING | | |
215 | WDIOF_MAGICCLOSE | | |
216 | WDIOF_CARDRESET, | |
217 | }; | |
218 | ||
b893e344 | 219 | static const struct watchdog_ops sbsa_gwdt_ops = { |
57d2caaa FW |
220 | .owner = THIS_MODULE, |
221 | .start = sbsa_gwdt_start, | |
222 | .stop = sbsa_gwdt_stop, | |
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223 | .ping = sbsa_gwdt_keepalive, |
224 | .set_timeout = sbsa_gwdt_set_timeout, | |
225 | .get_timeleft = sbsa_gwdt_get_timeleft, | |
226 | }; | |
227 | ||
228 | static int sbsa_gwdt_probe(struct platform_device *pdev) | |
229 | { | |
230 | void __iomem *rf_base, *cf_base; | |
231 | struct device *dev = &pdev->dev; | |
232 | struct watchdog_device *wdd; | |
233 | struct sbsa_gwdt *gwdt; | |
234 | struct resource *res; | |
235 | int ret, irq; | |
236 | u32 status; | |
237 | ||
238 | gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL); | |
239 | if (!gwdt) | |
240 | return -ENOMEM; | |
241 | platform_set_drvdata(pdev, gwdt); | |
242 | ||
243 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
244 | cf_base = devm_ioremap_resource(dev, res); | |
245 | if (IS_ERR(cf_base)) | |
246 | return PTR_ERR(cf_base); | |
247 | ||
248 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
249 | rf_base = devm_ioremap_resource(dev, res); | |
250 | if (IS_ERR(rf_base)) | |
251 | return PTR_ERR(rf_base); | |
252 | ||
253 | /* | |
254 | * Get the frequency of system counter from the cp15 interface of ARM | |
255 | * Generic timer. We don't need to check it, because if it returns "0", | |
256 | * system would panic in very early stage. | |
257 | */ | |
258 | gwdt->clk = arch_timer_get_cntfrq(); | |
259 | gwdt->refresh_base = rf_base; | |
260 | gwdt->control_base = cf_base; | |
261 | ||
262 | wdd = &gwdt->wdd; | |
263 | wdd->parent = dev; | |
264 | wdd->info = &sbsa_gwdt_info; | |
265 | wdd->ops = &sbsa_gwdt_ops; | |
266 | wdd->min_timeout = 1; | |
e05e80eb | 267 | wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000; |
57d2caaa FW |
268 | wdd->timeout = DEFAULT_TIMEOUT; |
269 | watchdog_set_drvdata(wdd, gwdt); | |
270 | watchdog_set_nowayout(wdd, nowayout); | |
271 | ||
272 | status = readl(cf_base + SBSA_GWDT_WCS); | |
273 | if (status & SBSA_GWDT_WCS_WS1) { | |
274 | dev_warn(dev, "System reset by WDT.\n"); | |
275 | wdd->bootstatus |= WDIOF_CARDRESET; | |
276 | } | |
c3c1e29c PA |
277 | if (status & SBSA_GWDT_WCS_EN) |
278 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
57d2caaa FW |
279 | |
280 | if (action) { | |
281 | irq = platform_get_irq(pdev, 0); | |
282 | if (irq < 0) { | |
283 | action = 0; | |
284 | dev_warn(dev, "unable to get ws0 interrupt.\n"); | |
285 | } else { | |
286 | /* | |
287 | * In case there is a pending ws0 interrupt, just ping | |
288 | * the watchdog before registering the interrupt routine | |
289 | */ | |
290 | writel(0, rf_base + SBSA_GWDT_WRR); | |
291 | if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0, | |
292 | pdev->name, gwdt)) { | |
293 | action = 0; | |
294 | dev_warn(dev, "unable to request IRQ %d.\n", | |
295 | irq); | |
296 | } | |
297 | } | |
298 | if (!action) | |
299 | dev_warn(dev, "falling back to single stage mode.\n"); | |
300 | } | |
301 | /* | |
302 | * In the single stage mode, The first signal (WS0) is ignored, | |
303 | * the timeout is (WOR * 2), so the maximum timeout should be doubled. | |
304 | */ | |
305 | if (!action) | |
e05e80eb | 306 | wdd->max_hw_heartbeat_ms *= 2; |
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307 | |
308 | watchdog_init_timeout(wdd, timeout, dev); | |
309 | /* | |
310 | * Update timeout to WOR. | |
311 | * Because of the explicit watchdog refresh mechanism, | |
312 | * it's also a ping, if watchdog is enabled. | |
313 | */ | |
314 | sbsa_gwdt_set_timeout(wdd, wdd->timeout); | |
315 | ||
316 | ret = watchdog_register_device(wdd); | |
317 | if (ret) | |
318 | return ret; | |
319 | ||
320 | dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n", | |
321 | wdd->timeout, gwdt->clk, action, | |
322 | status & SBSA_GWDT_WCS_EN ? " [enabled]" : ""); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static void sbsa_gwdt_shutdown(struct platform_device *pdev) | |
328 | { | |
329 | struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev); | |
330 | ||
331 | sbsa_gwdt_stop(&gwdt->wdd); | |
332 | } | |
333 | ||
334 | static int sbsa_gwdt_remove(struct platform_device *pdev) | |
335 | { | |
336 | struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev); | |
337 | ||
338 | watchdog_unregister_device(&gwdt->wdd); | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | /* Disable watchdog if it is active during suspend */ | |
344 | static int __maybe_unused sbsa_gwdt_suspend(struct device *dev) | |
345 | { | |
346 | struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); | |
347 | ||
348 | if (watchdog_active(&gwdt->wdd)) | |
349 | sbsa_gwdt_stop(&gwdt->wdd); | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | /* Enable watchdog if necessary */ | |
355 | static int __maybe_unused sbsa_gwdt_resume(struct device *dev) | |
356 | { | |
357 | struct sbsa_gwdt *gwdt = dev_get_drvdata(dev); | |
358 | ||
359 | if (watchdog_active(&gwdt->wdd)) | |
360 | sbsa_gwdt_start(&gwdt->wdd); | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static const struct dev_pm_ops sbsa_gwdt_pm_ops = { | |
366 | SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume) | |
367 | }; | |
368 | ||
369 | static const struct of_device_id sbsa_gwdt_of_match[] = { | |
370 | { .compatible = "arm,sbsa-gwdt", }, | |
371 | {}, | |
372 | }; | |
373 | MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match); | |
374 | ||
375 | static const struct platform_device_id sbsa_gwdt_pdev_match[] = { | |
376 | { .name = DRV_NAME, }, | |
377 | {}, | |
378 | }; | |
379 | MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match); | |
380 | ||
381 | static struct platform_driver sbsa_gwdt_driver = { | |
382 | .driver = { | |
383 | .name = DRV_NAME, | |
384 | .pm = &sbsa_gwdt_pm_ops, | |
385 | .of_match_table = sbsa_gwdt_of_match, | |
386 | }, | |
387 | .probe = sbsa_gwdt_probe, | |
388 | .remove = sbsa_gwdt_remove, | |
389 | .shutdown = sbsa_gwdt_shutdown, | |
390 | .id_table = sbsa_gwdt_pdev_match, | |
391 | }; | |
392 | ||
393 | module_platform_driver(sbsa_gwdt_driver); | |
394 | ||
395 | MODULE_DESCRIPTION("SBSA Generic Watchdog Driver"); | |
396 | MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>"); | |
397 | MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>"); | |
398 | MODULE_AUTHOR("Al Stone <al.stone@linaro.org>"); | |
399 | MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>"); | |
400 | MODULE_LICENSE("GPL v2"); | |
401 | MODULE_ALIAS("platform:" DRV_NAME); |