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Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
d46a78b0 | 19 | * 4. PIRQs - Hardware interrupts. |
e46cdb66 JF |
20 | * |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
b21ddbf5 | 31 | #include <linux/irqnr.h> |
f731e3ef | 32 | #include <linux/pci.h> |
e46cdb66 | 33 | |
38e20b07 | 34 | #include <asm/desc.h> |
e46cdb66 JF |
35 | #include <asm/ptrace.h> |
36 | #include <asm/irq.h> | |
792dc4f6 | 37 | #include <asm/idle.h> |
0794bfc7 | 38 | #include <asm/io_apic.h> |
e46cdb66 | 39 | #include <asm/sync_bitops.h> |
42a1de56 | 40 | #include <asm/xen/pci.h> |
e46cdb66 | 41 | #include <asm/xen/hypercall.h> |
8d1b8753 | 42 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 43 | |
38e20b07 SY |
44 | #include <xen/xen.h> |
45 | #include <xen/hvm.h> | |
e04d0d07 | 46 | #include <xen/xen-ops.h> |
e46cdb66 JF |
47 | #include <xen/events.h> |
48 | #include <xen/interface/xen.h> | |
49 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
50 | #include <xen/interface/hvm/hvm_op.h> |
51 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 52 | |
e46cdb66 JF |
53 | /* |
54 | * This lock protects updates to the following mapping and reference-count | |
55 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
56 | */ | |
57 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
58 | ||
59 | /* IRQ <-> VIRQ mapping. */ | |
204fba4a | 60 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 61 | |
f87e4cac | 62 | /* IRQ <-> IPI mapping */ |
204fba4a | 63 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 64 | |
ced40d0f JF |
65 | /* Interrupt types. */ |
66 | enum xen_irq_type { | |
d77bbd4d | 67 | IRQT_UNBOUND = 0, |
f87e4cac JF |
68 | IRQT_PIRQ, |
69 | IRQT_VIRQ, | |
70 | IRQT_IPI, | |
71 | IRQT_EVTCHN | |
72 | }; | |
e46cdb66 | 73 | |
ced40d0f JF |
74 | /* |
75 | * Packed IRQ information: | |
76 | * type - enum xen_irq_type | |
77 | * event channel - irq->event channel mapping | |
78 | * cpu - cpu this event channel is bound to | |
79 | * index - type-specific information: | |
42a1de56 SS |
80 | * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM |
81 | * guest, or GSI (real passthrough IRQ) of the device. | |
ced40d0f JF |
82 | * VIRQ - virq number |
83 | * IPI - IPI vector | |
84 | * EVTCHN - | |
85 | */ | |
86 | struct irq_info | |
87 | { | |
88 | enum xen_irq_type type; /* type */ | |
89 | unsigned short evtchn; /* event channel */ | |
90 | unsigned short cpu; /* cpu bound */ | |
91 | ||
92 | union { | |
93 | unsigned short virq; | |
94 | enum ipi_vector ipi; | |
95 | struct { | |
7a043f11 | 96 | unsigned short pirq; |
ced40d0f | 97 | unsigned short gsi; |
d46a78b0 JF |
98 | unsigned char vector; |
99 | unsigned char flags; | |
ced40d0f JF |
100 | } pirq; |
101 | } u; | |
102 | }; | |
d46a78b0 | 103 | #define PIRQ_NEEDS_EOI (1 << 0) |
15ebbb82 | 104 | #define PIRQ_SHAREABLE (1 << 1) |
ced40d0f | 105 | |
b21ddbf5 | 106 | static struct irq_info *irq_info; |
7a043f11 | 107 | static int *pirq_to_irq; |
e46cdb66 | 108 | |
b21ddbf5 | 109 | static int *evtchn_to_irq; |
c7a3589e MT |
110 | struct cpu_evtchn_s { |
111 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
112 | }; | |
3b32f574 JF |
113 | |
114 | static __initdata struct cpu_evtchn_s init_evtchn_mask = { | |
115 | .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul, | |
116 | }; | |
117 | static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask; | |
118 | ||
c7a3589e MT |
119 | static inline unsigned long *cpu_evtchn_mask(int cpu) |
120 | { | |
121 | return cpu_evtchn_mask_p[cpu].bits; | |
122 | } | |
e46cdb66 | 123 | |
e46cdb66 JF |
124 | /* Xen will never allocate port zero for any purpose. */ |
125 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
126 | ||
e46cdb66 | 127 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 128 | static struct irq_chip xen_percpu_chip; |
d46a78b0 | 129 | static struct irq_chip xen_pirq_chip; |
e46cdb66 JF |
130 | |
131 | /* Constructor for packed IRQ information. */ | |
ced40d0f JF |
132 | static struct irq_info mk_unbound_info(void) |
133 | { | |
134 | return (struct irq_info) { .type = IRQT_UNBOUND }; | |
135 | } | |
136 | ||
137 | static struct irq_info mk_evtchn_info(unsigned short evtchn) | |
138 | { | |
90af9514 IC |
139 | return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn, |
140 | .cpu = 0 }; | |
ced40d0f JF |
141 | } |
142 | ||
143 | static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi) | |
e46cdb66 | 144 | { |
ced40d0f | 145 | return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn, |
90af9514 | 146 | .cpu = 0, .u.ipi = ipi }; |
ced40d0f JF |
147 | } |
148 | ||
149 | static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq) | |
150 | { | |
151 | return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn, | |
90af9514 | 152 | .cpu = 0, .u.virq = virq }; |
ced40d0f JF |
153 | } |
154 | ||
7a043f11 | 155 | static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq, |
ced40d0f JF |
156 | unsigned short gsi, unsigned short vector) |
157 | { | |
158 | return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn, | |
7a043f11 SS |
159 | .cpu = 0, |
160 | .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } }; | |
e46cdb66 JF |
161 | } |
162 | ||
163 | /* | |
164 | * Accessors for packed IRQ information. | |
165 | */ | |
ced40d0f | 166 | static struct irq_info *info_for_irq(unsigned irq) |
e46cdb66 | 167 | { |
ced40d0f | 168 | return &irq_info[irq]; |
e46cdb66 JF |
169 | } |
170 | ||
ced40d0f | 171 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 172 | { |
110e7c7e JJ |
173 | if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq))) |
174 | return 0; | |
175 | ||
ced40d0f | 176 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
177 | } |
178 | ||
d4c04536 IC |
179 | unsigned irq_from_evtchn(unsigned int evtchn) |
180 | { | |
181 | return evtchn_to_irq[evtchn]; | |
182 | } | |
183 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
184 | ||
ced40d0f | 185 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 186 | { |
ced40d0f JF |
187 | struct irq_info *info = info_for_irq(irq); |
188 | ||
189 | BUG_ON(info == NULL); | |
190 | BUG_ON(info->type != IRQT_IPI); | |
191 | ||
192 | return info->u.ipi; | |
193 | } | |
194 | ||
195 | static unsigned virq_from_irq(unsigned irq) | |
196 | { | |
197 | struct irq_info *info = info_for_irq(irq); | |
198 | ||
199 | BUG_ON(info == NULL); | |
200 | BUG_ON(info->type != IRQT_VIRQ); | |
201 | ||
202 | return info->u.virq; | |
203 | } | |
204 | ||
7a043f11 SS |
205 | static unsigned pirq_from_irq(unsigned irq) |
206 | { | |
207 | struct irq_info *info = info_for_irq(irq); | |
208 | ||
209 | BUG_ON(info == NULL); | |
210 | BUG_ON(info->type != IRQT_PIRQ); | |
211 | ||
212 | return info->u.pirq.pirq; | |
213 | } | |
214 | ||
ced40d0f JF |
215 | static unsigned gsi_from_irq(unsigned irq) |
216 | { | |
217 | struct irq_info *info = info_for_irq(irq); | |
218 | ||
219 | BUG_ON(info == NULL); | |
220 | BUG_ON(info->type != IRQT_PIRQ); | |
221 | ||
222 | return info->u.pirq.gsi; | |
223 | } | |
224 | ||
225 | static unsigned vector_from_irq(unsigned irq) | |
226 | { | |
227 | struct irq_info *info = info_for_irq(irq); | |
228 | ||
229 | BUG_ON(info == NULL); | |
230 | BUG_ON(info->type != IRQT_PIRQ); | |
231 | ||
232 | return info->u.pirq.vector; | |
233 | } | |
234 | ||
235 | static enum xen_irq_type type_from_irq(unsigned irq) | |
236 | { | |
237 | return info_for_irq(irq)->type; | |
238 | } | |
239 | ||
240 | static unsigned cpu_from_irq(unsigned irq) | |
241 | { | |
242 | return info_for_irq(irq)->cpu; | |
243 | } | |
244 | ||
245 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
246 | { | |
247 | int irq = evtchn_to_irq[evtchn]; | |
248 | unsigned ret = 0; | |
249 | ||
250 | if (irq != -1) | |
251 | ret = cpu_from_irq(irq); | |
252 | ||
253 | return ret; | |
e46cdb66 JF |
254 | } |
255 | ||
d46a78b0 JF |
256 | static bool pirq_needs_eoi(unsigned irq) |
257 | { | |
258 | struct irq_info *info = info_for_irq(irq); | |
259 | ||
260 | BUG_ON(info->type != IRQT_PIRQ); | |
261 | ||
262 | return info->u.pirq.flags & PIRQ_NEEDS_EOI; | |
263 | } | |
264 | ||
e46cdb66 JF |
265 | static inline unsigned long active_evtchns(unsigned int cpu, |
266 | struct shared_info *sh, | |
267 | unsigned int idx) | |
268 | { | |
269 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 270 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
271 | ~sh->evtchn_mask[idx]); |
272 | } | |
273 | ||
274 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
275 | { | |
276 | int irq = evtchn_to_irq[chn]; | |
277 | ||
278 | BUG_ON(irq == -1); | |
279 | #ifdef CONFIG_SMP | |
7f7ace0c | 280 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
281 | #endif |
282 | ||
e0419564 JF |
283 | clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq))); |
284 | set_bit(chn, cpu_evtchn_mask(cpu)); | |
e46cdb66 | 285 | |
ced40d0f | 286 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
287 | } |
288 | ||
289 | static void init_evtchn_cpu_bindings(void) | |
290 | { | |
1c6969ec | 291 | int i; |
e46cdb66 | 292 | #ifdef CONFIG_SMP |
10e58084 | 293 | struct irq_desc *desc; |
10e58084 | 294 | |
e46cdb66 | 295 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 296 | for_each_irq_desc(i, desc) { |
7f7ace0c | 297 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 298 | } |
e46cdb66 JF |
299 | #endif |
300 | ||
1c6969ec JB |
301 | for_each_possible_cpu(i) |
302 | memset(cpu_evtchn_mask(i), | |
303 | (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s)); | |
304 | ||
e46cdb66 JF |
305 | } |
306 | ||
e46cdb66 JF |
307 | static inline void clear_evtchn(int port) |
308 | { | |
309 | struct shared_info *s = HYPERVISOR_shared_info; | |
310 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
311 | } | |
312 | ||
313 | static inline void set_evtchn(int port) | |
314 | { | |
315 | struct shared_info *s = HYPERVISOR_shared_info; | |
316 | sync_set_bit(port, &s->evtchn_pending[0]); | |
317 | } | |
318 | ||
168d2f46 JF |
319 | static inline int test_evtchn(int port) |
320 | { | |
321 | struct shared_info *s = HYPERVISOR_shared_info; | |
322 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
323 | } | |
324 | ||
e46cdb66 JF |
325 | |
326 | /** | |
327 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
328 | * @irq: irq of event channel to send event to | |
329 | * | |
330 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
331 | * save/restore. Notifications on a broken connection are silently | |
332 | * dropped. | |
333 | */ | |
334 | void notify_remote_via_irq(int irq) | |
335 | { | |
336 | int evtchn = evtchn_from_irq(irq); | |
337 | ||
338 | if (VALID_EVTCHN(evtchn)) | |
339 | notify_remote_via_evtchn(evtchn); | |
340 | } | |
341 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
342 | ||
343 | static void mask_evtchn(int port) | |
344 | { | |
345 | struct shared_info *s = HYPERVISOR_shared_info; | |
346 | sync_set_bit(port, &s->evtchn_mask[0]); | |
347 | } | |
348 | ||
349 | static void unmask_evtchn(int port) | |
350 | { | |
351 | struct shared_info *s = HYPERVISOR_shared_info; | |
352 | unsigned int cpu = get_cpu(); | |
353 | ||
354 | BUG_ON(!irqs_disabled()); | |
355 | ||
356 | /* Slow path (hypercall) if this is a non-local port. */ | |
357 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
358 | struct evtchn_unmask unmask = { .port = port }; | |
359 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
360 | } else { | |
780f36d8 | 361 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
e46cdb66 JF |
362 | |
363 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
364 | ||
365 | /* | |
366 | * The following is basically the equivalent of | |
367 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
368 | * the interrupt edge' if the channel is masked. | |
369 | */ | |
370 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
371 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
372 | &vcpu_info->evtchn_pending_sel)) | |
373 | vcpu_info->evtchn_upcall_pending = 1; | |
374 | } | |
375 | ||
376 | put_cpu(); | |
377 | } | |
378 | ||
89911501 | 379 | static int xen_allocate_irq_dynamic(void) |
0794bfc7 | 380 | { |
89911501 IC |
381 | int first = 0; |
382 | int irq; | |
0794bfc7 KRW |
383 | |
384 | #ifdef CONFIG_X86_IO_APIC | |
89911501 IC |
385 | /* |
386 | * For an HVM guest or domain 0 which see "real" (emulated or | |
387 | * actual repectively) GSIs we allocate dynamic IRQs | |
388 | * e.g. those corresponding to event channels or MSIs | |
389 | * etc. from the range above those "real" GSIs to avoid | |
390 | * collisions. | |
391 | */ | |
392 | if (xen_initial_domain() || xen_hvm_domain()) | |
393 | first = get_nr_irqs_gsi(); | |
0794bfc7 KRW |
394 | #endif |
395 | ||
89911501 IC |
396 | retry: |
397 | irq = irq_alloc_desc_from(first, -1); | |
3a69e916 | 398 | |
89911501 IC |
399 | if (irq == -ENOMEM && first > NR_IRQS_LEGACY) { |
400 | printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n"); | |
401 | first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY); | |
402 | goto retry; | |
99ad198c | 403 | } |
e46cdb66 | 404 | |
89911501 IC |
405 | if (irq < 0) |
406 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
ced40d0f | 407 | |
e46cdb66 | 408 | return irq; |
d46a78b0 JF |
409 | } |
410 | ||
c9df1ce5 IC |
411 | static int xen_allocate_irq_gsi(unsigned gsi) |
412 | { | |
413 | int irq; | |
414 | ||
89911501 IC |
415 | /* |
416 | * A PV guest has no concept of a GSI (since it has no ACPI | |
417 | * nor access to/knowledge of the physical APICs). Therefore | |
418 | * all IRQs are dynamically allocated from the entire IRQ | |
419 | * space. | |
420 | */ | |
421 | if (xen_pv_domain() && !xen_initial_domain()) | |
c9df1ce5 IC |
422 | return xen_allocate_irq_dynamic(); |
423 | ||
424 | /* Legacy IRQ descriptors are already allocated by the arch. */ | |
425 | if (gsi < NR_IRQS_LEGACY) | |
426 | return gsi; | |
427 | ||
428 | irq = irq_alloc_desc_at(gsi, -1); | |
429 | if (irq < 0) | |
430 | panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq); | |
431 | ||
432 | return irq; | |
433 | } | |
434 | ||
435 | static void xen_free_irq(unsigned irq) | |
436 | { | |
437 | irq_free_desc(irq); | |
438 | } | |
439 | ||
d46a78b0 JF |
440 | static void pirq_unmask_notify(int irq) |
441 | { | |
7a043f11 | 442 | struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) }; |
d46a78b0 JF |
443 | |
444 | if (unlikely(pirq_needs_eoi(irq))) { | |
445 | int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi); | |
446 | WARN_ON(rc); | |
447 | } | |
448 | } | |
449 | ||
450 | static void pirq_query_unmask(int irq) | |
451 | { | |
452 | struct physdev_irq_status_query irq_status; | |
453 | struct irq_info *info = info_for_irq(irq); | |
454 | ||
455 | BUG_ON(info->type != IRQT_PIRQ); | |
456 | ||
7a043f11 | 457 | irq_status.irq = pirq_from_irq(irq); |
d46a78b0 JF |
458 | if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status)) |
459 | irq_status.flags = 0; | |
460 | ||
461 | info->u.pirq.flags &= ~PIRQ_NEEDS_EOI; | |
462 | if (irq_status.flags & XENIRQSTAT_needs_eoi) | |
463 | info->u.pirq.flags |= PIRQ_NEEDS_EOI; | |
464 | } | |
465 | ||
466 | static bool probing_irq(int irq) | |
467 | { | |
468 | struct irq_desc *desc = irq_to_desc(irq); | |
469 | ||
470 | return desc && desc->action == NULL; | |
471 | } | |
472 | ||
473 | static unsigned int startup_pirq(unsigned int irq) | |
474 | { | |
475 | struct evtchn_bind_pirq bind_pirq; | |
476 | struct irq_info *info = info_for_irq(irq); | |
477 | int evtchn = evtchn_from_irq(irq); | |
15ebbb82 | 478 | int rc; |
d46a78b0 JF |
479 | |
480 | BUG_ON(info->type != IRQT_PIRQ); | |
481 | ||
482 | if (VALID_EVTCHN(evtchn)) | |
483 | goto out; | |
484 | ||
7a043f11 | 485 | bind_pirq.pirq = pirq_from_irq(irq); |
d46a78b0 | 486 | /* NB. We are happy to share unless we are probing. */ |
15ebbb82 KRW |
487 | bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ? |
488 | BIND_PIRQ__WILL_SHARE : 0; | |
489 | rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq); | |
490 | if (rc != 0) { | |
d46a78b0 JF |
491 | if (!probing_irq(irq)) |
492 | printk(KERN_INFO "Failed to obtain physical IRQ %d\n", | |
493 | irq); | |
494 | return 0; | |
495 | } | |
496 | evtchn = bind_pirq.port; | |
497 | ||
498 | pirq_query_unmask(irq); | |
499 | ||
500 | evtchn_to_irq[evtchn] = irq; | |
501 | bind_evtchn_to_cpu(evtchn, 0); | |
502 | info->evtchn = evtchn; | |
503 | ||
504 | out: | |
505 | unmask_evtchn(evtchn); | |
506 | pirq_unmask_notify(irq); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
511 | static void shutdown_pirq(unsigned int irq) | |
512 | { | |
513 | struct evtchn_close close; | |
514 | struct irq_info *info = info_for_irq(irq); | |
515 | int evtchn = evtchn_from_irq(irq); | |
516 | ||
517 | BUG_ON(info->type != IRQT_PIRQ); | |
518 | ||
519 | if (!VALID_EVTCHN(evtchn)) | |
520 | return; | |
521 | ||
522 | mask_evtchn(evtchn); | |
523 | ||
524 | close.port = evtchn; | |
525 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
526 | BUG(); | |
527 | ||
528 | bind_evtchn_to_cpu(evtchn, 0); | |
529 | evtchn_to_irq[evtchn] = -1; | |
530 | info->evtchn = 0; | |
531 | } | |
532 | ||
533 | static void enable_pirq(unsigned int irq) | |
534 | { | |
535 | startup_pirq(irq); | |
536 | } | |
537 | ||
538 | static void disable_pirq(unsigned int irq) | |
539 | { | |
540 | } | |
541 | ||
542 | static void ack_pirq(unsigned int irq) | |
543 | { | |
544 | int evtchn = evtchn_from_irq(irq); | |
545 | ||
546 | move_native_irq(irq); | |
547 | ||
548 | if (VALID_EVTCHN(evtchn)) { | |
549 | mask_evtchn(evtchn); | |
550 | clear_evtchn(evtchn); | |
551 | } | |
552 | } | |
553 | ||
554 | static void end_pirq(unsigned int irq) | |
555 | { | |
556 | int evtchn = evtchn_from_irq(irq); | |
557 | struct irq_desc *desc = irq_to_desc(irq); | |
558 | ||
559 | if (WARN_ON(!desc)) | |
560 | return; | |
561 | ||
562 | if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) == | |
563 | (IRQ_DISABLED|IRQ_PENDING)) { | |
564 | shutdown_pirq(irq); | |
565 | } else if (VALID_EVTCHN(evtchn)) { | |
566 | unmask_evtchn(evtchn); | |
567 | pirq_unmask_notify(irq); | |
568 | } | |
569 | } | |
570 | ||
571 | static int find_irq_by_gsi(unsigned gsi) | |
572 | { | |
573 | int irq; | |
574 | ||
b21ddbf5 | 575 | for (irq = 0; irq < nr_irqs; irq++) { |
d46a78b0 JF |
576 | struct irq_info *info = info_for_irq(irq); |
577 | ||
578 | if (info == NULL || info->type != IRQT_PIRQ) | |
579 | continue; | |
580 | ||
581 | if (gsi_from_irq(irq) == gsi) | |
582 | return irq; | |
583 | } | |
584 | ||
585 | return -1; | |
586 | } | |
587 | ||
7a043f11 SS |
588 | int xen_allocate_pirq(unsigned gsi, int shareable, char *name) |
589 | { | |
590 | return xen_map_pirq_gsi(gsi, gsi, shareable, name); | |
591 | } | |
592 | ||
593 | /* xen_map_pirq_gsi might allocate irqs from the top down, as a | |
3a69e916 KRW |
594 | * consequence don't assume that the irq number returned has a low value |
595 | * or can be used as a pirq number unless you know otherwise. | |
596 | * | |
7a043f11 | 597 | * One notable exception is when xen_map_pirq_gsi is called passing an |
3a69e916 | 598 | * hardware gsi as argument, in that case the irq number returned |
7a043f11 SS |
599 | * matches the gsi number passed as second argument. |
600 | * | |
601 | * Note: We don't assign an event channel until the irq actually started | |
602 | * up. Return an existing irq if we've already got one for the gsi. | |
d46a78b0 | 603 | */ |
7a043f11 | 604 | int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name) |
d46a78b0 | 605 | { |
7a043f11 | 606 | int irq = 0; |
d46a78b0 JF |
607 | struct physdev_irq irq_op; |
608 | ||
609 | spin_lock(&irq_mapping_update_lock); | |
610 | ||
e5fc7345 | 611 | if ((pirq > nr_irqs) || (gsi > nr_irqs)) { |
01557baf | 612 | printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n", |
e5fc7345 SS |
613 | pirq > nr_irqs ? "pirq" :"", |
614 | gsi > nr_irqs ? "gsi" : ""); | |
01557baf SS |
615 | goto out; |
616 | } | |
617 | ||
d46a78b0 JF |
618 | irq = find_irq_by_gsi(gsi); |
619 | if (irq != -1) { | |
7a043f11 | 620 | printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n", |
d46a78b0 JF |
621 | irq, gsi); |
622 | goto out; /* XXX need refcount? */ | |
623 | } | |
624 | ||
c9df1ce5 | 625 | irq = xen_allocate_irq_gsi(gsi); |
d46a78b0 JF |
626 | |
627 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, | |
1a60d05f | 628 | handle_level_irq, name); |
d46a78b0 JF |
629 | |
630 | irq_op.irq = irq; | |
b5401a96 AN |
631 | irq_op.vector = 0; |
632 | ||
633 | /* Only the privileged domain can do this. For non-priv, the pcifront | |
634 | * driver provides a PCI bus that does the call to do exactly | |
635 | * this in the priv domain. */ | |
636 | if (xen_initial_domain() && | |
637 | HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) { | |
c9df1ce5 | 638 | xen_free_irq(irq); |
d46a78b0 JF |
639 | irq = -ENOSPC; |
640 | goto out; | |
641 | } | |
642 | ||
7a043f11 | 643 | irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector); |
15ebbb82 | 644 | irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0; |
7a043f11 | 645 | pirq_to_irq[pirq] = irq; |
d46a78b0 JF |
646 | |
647 | out: | |
648 | spin_unlock(&irq_mapping_update_lock); | |
649 | ||
650 | return irq; | |
651 | } | |
652 | ||
f731e3ef QH |
653 | #ifdef CONFIG_PCI_MSI |
654 | #include <linux/msi.h> | |
655 | #include "../pci/msi.h" | |
656 | ||
cbf6aa89 IC |
657 | static int find_unbound_pirq(int type) |
658 | { | |
659 | int rc, i; | |
660 | struct physdev_get_free_pirq op_get_free_pirq; | |
661 | op_get_free_pirq.type = type; | |
662 | ||
663 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq); | |
664 | if (!rc) | |
665 | return op_get_free_pirq.pirq; | |
666 | ||
667 | for (i = 0; i < nr_irqs; i++) { | |
668 | if (pirq_to_irq[i] < 0) | |
669 | return i; | |
670 | } | |
671 | return -1; | |
672 | } | |
673 | ||
af42b8d1 | 674 | void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc) |
809f9267 SS |
675 | { |
676 | spin_lock(&irq_mapping_update_lock); | |
677 | ||
af42b8d1 | 678 | if (alloc & XEN_ALLOC_IRQ) { |
c9df1ce5 | 679 | *irq = xen_allocate_irq_dynamic(); |
af42b8d1 SS |
680 | if (*irq == -1) |
681 | goto out; | |
682 | } | |
809f9267 | 683 | |
af42b8d1 SS |
684 | if (alloc & XEN_ALLOC_PIRQ) { |
685 | *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI); | |
686 | if (*pirq == -1) | |
687 | goto out; | |
688 | } | |
809f9267 SS |
689 | |
690 | set_irq_chip_and_handler_name(*irq, &xen_pirq_chip, | |
691 | handle_level_irq, name); | |
692 | ||
693 | irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0); | |
694 | pirq_to_irq[*pirq] = *irq; | |
695 | ||
696 | out: | |
697 | spin_unlock(&irq_mapping_update_lock); | |
698 | } | |
699 | ||
f731e3ef QH |
700 | int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type) |
701 | { | |
702 | int irq = -1; | |
703 | struct physdev_map_pirq map_irq; | |
704 | int rc; | |
705 | int pos; | |
706 | u32 table_offset, bir; | |
707 | ||
708 | memset(&map_irq, 0, sizeof(map_irq)); | |
709 | map_irq.domid = DOMID_SELF; | |
710 | map_irq.type = MAP_PIRQ_TYPE_MSI; | |
711 | map_irq.index = -1; | |
712 | map_irq.pirq = -1; | |
713 | map_irq.bus = dev->bus->number; | |
714 | map_irq.devfn = dev->devfn; | |
715 | ||
716 | if (type == PCI_CAP_ID_MSIX) { | |
717 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
718 | ||
719 | pci_read_config_dword(dev, msix_table_offset_reg(pos), | |
720 | &table_offset); | |
721 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
722 | ||
723 | map_irq.table_base = pci_resource_start(dev, bir); | |
724 | map_irq.entry_nr = msidesc->msi_attrib.entry_nr; | |
725 | } | |
726 | ||
727 | spin_lock(&irq_mapping_update_lock); | |
728 | ||
c9df1ce5 | 729 | irq = xen_allocate_irq_dynamic(); |
f731e3ef QH |
730 | |
731 | if (irq == -1) | |
732 | goto out; | |
733 | ||
734 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
735 | if (rc) { | |
736 | printk(KERN_WARNING "xen map irq failed %d\n", rc); | |
737 | ||
c9df1ce5 | 738 | xen_free_irq(irq); |
f731e3ef QH |
739 | |
740 | irq = -1; | |
741 | goto out; | |
742 | } | |
743 | irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index); | |
744 | ||
745 | set_irq_chip_and_handler_name(irq, &xen_pirq_chip, | |
746 | handle_level_irq, | |
747 | (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi"); | |
748 | ||
749 | out: | |
750 | spin_unlock(&irq_mapping_update_lock); | |
751 | return irq; | |
752 | } | |
753 | #endif | |
754 | ||
b5401a96 AN |
755 | int xen_destroy_irq(int irq) |
756 | { | |
757 | struct irq_desc *desc; | |
38aa66fc JF |
758 | struct physdev_unmap_pirq unmap_irq; |
759 | struct irq_info *info = info_for_irq(irq); | |
b5401a96 AN |
760 | int rc = -ENOENT; |
761 | ||
762 | spin_lock(&irq_mapping_update_lock); | |
763 | ||
764 | desc = irq_to_desc(irq); | |
765 | if (!desc) | |
766 | goto out; | |
767 | ||
38aa66fc | 768 | if (xen_initial_domain()) { |
12334715 | 769 | unmap_irq.pirq = info->u.pirq.pirq; |
38aa66fc JF |
770 | unmap_irq.domid = DOMID_SELF; |
771 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq); | |
772 | if (rc) { | |
773 | printk(KERN_WARNING "unmap irq failed %d\n", rc); | |
774 | goto out; | |
775 | } | |
af42b8d1 | 776 | pirq_to_irq[info->u.pirq.pirq] = -1; |
38aa66fc | 777 | } |
b5401a96 AN |
778 | irq_info[irq] = mk_unbound_info(); |
779 | ||
c9df1ce5 | 780 | xen_free_irq(irq); |
b5401a96 AN |
781 | |
782 | out: | |
783 | spin_unlock(&irq_mapping_update_lock); | |
784 | return rc; | |
785 | } | |
786 | ||
d46a78b0 JF |
787 | int xen_vector_from_irq(unsigned irq) |
788 | { | |
789 | return vector_from_irq(irq); | |
790 | } | |
791 | ||
792 | int xen_gsi_from_irq(unsigned irq) | |
793 | { | |
794 | return gsi_from_irq(irq); | |
e46cdb66 JF |
795 | } |
796 | ||
af42b8d1 SS |
797 | int xen_irq_from_pirq(unsigned pirq) |
798 | { | |
799 | return pirq_to_irq[pirq]; | |
800 | } | |
801 | ||
b536b4b9 | 802 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
803 | { |
804 | int irq; | |
805 | ||
806 | spin_lock(&irq_mapping_update_lock); | |
807 | ||
808 | irq = evtchn_to_irq[evtchn]; | |
809 | ||
810 | if (irq == -1) { | |
c9df1ce5 | 811 | irq = xen_allocate_irq_dynamic(); |
e46cdb66 | 812 | |
e46cdb66 | 813 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
3588fe2e | 814 | handle_fasteoi_irq, "event"); |
e46cdb66 JF |
815 | |
816 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 817 | irq_info[irq] = mk_evtchn_info(evtchn); |
e46cdb66 JF |
818 | } |
819 | ||
e46cdb66 JF |
820 | spin_unlock(&irq_mapping_update_lock); |
821 | ||
822 | return irq; | |
823 | } | |
b536b4b9 | 824 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 825 | |
f87e4cac JF |
826 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
827 | { | |
828 | struct evtchn_bind_ipi bind_ipi; | |
829 | int evtchn, irq; | |
830 | ||
831 | spin_lock(&irq_mapping_update_lock); | |
832 | ||
833 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 834 | |
f87e4cac | 835 | if (irq == -1) { |
c9df1ce5 | 836 | irq = xen_allocate_irq_dynamic(); |
f87e4cac JF |
837 | if (irq < 0) |
838 | goto out; | |
839 | ||
aaca4964 JF |
840 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
841 | handle_percpu_irq, "ipi"); | |
f87e4cac JF |
842 | |
843 | bind_ipi.vcpu = cpu; | |
844 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
845 | &bind_ipi) != 0) | |
846 | BUG(); | |
847 | evtchn = bind_ipi.port; | |
848 | ||
849 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 850 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
f87e4cac JF |
851 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; |
852 | ||
853 | bind_evtchn_to_cpu(evtchn, cpu); | |
854 | } | |
855 | ||
f87e4cac JF |
856 | out: |
857 | spin_unlock(&irq_mapping_update_lock); | |
858 | return irq; | |
859 | } | |
860 | ||
861 | ||
4fe7d5a7 | 862 | int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
e46cdb66 JF |
863 | { |
864 | struct evtchn_bind_virq bind_virq; | |
865 | int evtchn, irq; | |
866 | ||
867 | spin_lock(&irq_mapping_update_lock); | |
868 | ||
869 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
870 | ||
871 | if (irq == -1) { | |
c9df1ce5 | 872 | irq = xen_allocate_irq_dynamic(); |
a52521f1 JF |
873 | |
874 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, | |
875 | handle_percpu_irq, "virq"); | |
876 | ||
e46cdb66 JF |
877 | bind_virq.virq = virq; |
878 | bind_virq.vcpu = cpu; | |
879 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
880 | &bind_virq) != 0) | |
881 | BUG(); | |
882 | evtchn = bind_virq.port; | |
883 | ||
e46cdb66 | 884 | evtchn_to_irq[evtchn] = irq; |
ced40d0f | 885 | irq_info[irq] = mk_virq_info(evtchn, virq); |
e46cdb66 JF |
886 | |
887 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
888 | ||
889 | bind_evtchn_to_cpu(evtchn, cpu); | |
890 | } | |
891 | ||
e46cdb66 JF |
892 | spin_unlock(&irq_mapping_update_lock); |
893 | ||
894 | return irq; | |
895 | } | |
896 | ||
897 | static void unbind_from_irq(unsigned int irq) | |
898 | { | |
899 | struct evtchn_close close; | |
900 | int evtchn = evtchn_from_irq(irq); | |
901 | ||
902 | spin_lock(&irq_mapping_update_lock); | |
903 | ||
d77bbd4d | 904 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
905 | close.port = evtchn; |
906 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
907 | BUG(); | |
908 | ||
909 | switch (type_from_irq(irq)) { | |
910 | case IRQT_VIRQ: | |
911 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 912 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 913 | break; |
d68d82af AN |
914 | case IRQT_IPI: |
915 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 916 | [ipi_from_irq(irq)] = -1; |
d68d82af | 917 | break; |
e46cdb66 JF |
918 | default: |
919 | break; | |
920 | } | |
921 | ||
922 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
923 | bind_evtchn_to_cpu(evtchn, 0); | |
924 | ||
925 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
926 | } |
927 | ||
928 | if (irq_info[irq].type != IRQT_UNBOUND) { | |
ced40d0f | 929 | irq_info[irq] = mk_unbound_info(); |
e46cdb66 | 930 | |
c9df1ce5 | 931 | xen_free_irq(irq); |
e46cdb66 JF |
932 | } |
933 | ||
934 | spin_unlock(&irq_mapping_update_lock); | |
935 | } | |
936 | ||
937 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 938 | irq_handler_t handler, |
e46cdb66 JF |
939 | unsigned long irqflags, |
940 | const char *devname, void *dev_id) | |
941 | { | |
942 | unsigned int irq; | |
943 | int retval; | |
944 | ||
945 | irq = bind_evtchn_to_irq(evtchn); | |
946 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
947 | if (retval != 0) { | |
948 | unbind_from_irq(irq); | |
949 | return retval; | |
950 | } | |
951 | ||
952 | return irq; | |
953 | } | |
954 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
955 | ||
956 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 957 | irq_handler_t handler, |
e46cdb66 JF |
958 | unsigned long irqflags, const char *devname, void *dev_id) |
959 | { | |
960 | unsigned int irq; | |
961 | int retval; | |
962 | ||
963 | irq = bind_virq_to_irq(virq, cpu); | |
964 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
965 | if (retval != 0) { | |
966 | unbind_from_irq(irq); | |
967 | return retval; | |
968 | } | |
969 | ||
970 | return irq; | |
971 | } | |
972 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
973 | ||
f87e4cac JF |
974 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
975 | unsigned int cpu, | |
976 | irq_handler_t handler, | |
977 | unsigned long irqflags, | |
978 | const char *devname, | |
979 | void *dev_id) | |
980 | { | |
981 | int irq, retval; | |
982 | ||
983 | irq = bind_ipi_to_irq(ipi, cpu); | |
984 | if (irq < 0) | |
985 | return irq; | |
986 | ||
4877c737 | 987 | irqflags |= IRQF_NO_SUSPEND; |
f87e4cac JF |
988 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
989 | if (retval != 0) { | |
990 | unbind_from_irq(irq); | |
991 | return retval; | |
992 | } | |
993 | ||
994 | return irq; | |
995 | } | |
996 | ||
e46cdb66 JF |
997 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
998 | { | |
999 | free_irq(irq, dev_id); | |
1000 | unbind_from_irq(irq); | |
1001 | } | |
1002 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
1003 | ||
f87e4cac JF |
1004 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
1005 | { | |
1006 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
1007 | BUG_ON(irq < 0); | |
1008 | notify_remote_via_irq(irq); | |
1009 | } | |
1010 | ||
ee523ca1 JF |
1011 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
1012 | { | |
1013 | struct shared_info *sh = HYPERVISOR_shared_info; | |
1014 | int cpu = smp_processor_id(); | |
cb52e6d9 | 1015 | unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu); |
ee523ca1 JF |
1016 | int i; |
1017 | unsigned long flags; | |
1018 | static DEFINE_SPINLOCK(debug_lock); | |
cb52e6d9 | 1019 | struct vcpu_info *v; |
ee523ca1 JF |
1020 | |
1021 | spin_lock_irqsave(&debug_lock, flags); | |
1022 | ||
cb52e6d9 | 1023 | printk("\nvcpu %d\n ", cpu); |
ee523ca1 JF |
1024 | |
1025 | for_each_online_cpu(i) { | |
cb52e6d9 IC |
1026 | int pending; |
1027 | v = per_cpu(xen_vcpu, i); | |
1028 | pending = (get_irq_regs() && i == cpu) | |
1029 | ? xen_irqs_disabled(get_irq_regs()) | |
1030 | : v->evtchn_upcall_mask; | |
1031 | printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i, | |
1032 | pending, v->evtchn_upcall_pending, | |
1033 | (int)(sizeof(v->evtchn_pending_sel)*2), | |
1034 | v->evtchn_pending_sel); | |
1035 | } | |
1036 | v = per_cpu(xen_vcpu, cpu); | |
1037 | ||
1038 | printk("\npending:\n "); | |
1039 | for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
1040 | printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2, | |
1041 | sh->evtchn_pending[i], | |
1042 | i % 8 == 0 ? "\n " : " "); | |
1043 | printk("\nglobal mask:\n "); | |
1044 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1045 | printk("%0*lx%s", | |
1046 | (int)(sizeof(sh->evtchn_mask[0])*2), | |
1047 | sh->evtchn_mask[i], | |
1048 | i % 8 == 0 ? "\n " : " "); | |
1049 | ||
1050 | printk("\nglobally unmasked:\n "); | |
1051 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
1052 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1053 | sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
1054 | i % 8 == 0 ? "\n " : " "); | |
1055 | ||
1056 | printk("\nlocal cpu%d mask:\n ", cpu); | |
1057 | for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--) | |
1058 | printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2), | |
1059 | cpu_evtchn[i], | |
1060 | i % 8 == 0 ? "\n " : " "); | |
1061 | ||
1062 | printk("\nlocally unmasked:\n "); | |
1063 | for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) { | |
1064 | unsigned long pending = sh->evtchn_pending[i] | |
1065 | & ~sh->evtchn_mask[i] | |
1066 | & cpu_evtchn[i]; | |
1067 | printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2), | |
1068 | pending, i % 8 == 0 ? "\n " : " "); | |
ee523ca1 | 1069 | } |
ee523ca1 JF |
1070 | |
1071 | printk("\npending list:\n"); | |
cb52e6d9 | 1072 | for (i = 0; i < NR_EVENT_CHANNELS; i++) { |
ee523ca1 | 1073 | if (sync_test_bit(i, sh->evtchn_pending)) { |
cb52e6d9 IC |
1074 | int word_idx = i / BITS_PER_LONG; |
1075 | printk(" %d: event %d -> irq %d%s%s%s\n", | |
ced40d0f | 1076 | cpu_from_evtchn(i), i, |
cb52e6d9 IC |
1077 | evtchn_to_irq[i], |
1078 | sync_test_bit(word_idx, &v->evtchn_pending_sel) | |
1079 | ? "" : " l2-clear", | |
1080 | !sync_test_bit(i, sh->evtchn_mask) | |
1081 | ? "" : " globally-masked", | |
1082 | sync_test_bit(i, cpu_evtchn) | |
1083 | ? "" : " locally-masked"); | |
ee523ca1 JF |
1084 | } |
1085 | } | |
1086 | ||
1087 | spin_unlock_irqrestore(&debug_lock, flags); | |
1088 | ||
1089 | return IRQ_HANDLED; | |
1090 | } | |
1091 | ||
245b2e70 TH |
1092 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
1093 | ||
e46cdb66 JF |
1094 | /* |
1095 | * Search the CPUs pending events bitmasks. For each one found, map | |
1096 | * the event number to an irq, and feed it into do_IRQ() for | |
1097 | * handling. | |
1098 | * | |
1099 | * Xen uses a two-level bitmap to speed searching. The first level is | |
1100 | * a bitset of words which contain pending event bits. The second | |
1101 | * level is a bitset of pending events themselves. | |
1102 | */ | |
38e20b07 | 1103 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 JF |
1104 | { |
1105 | int cpu = get_cpu(); | |
1106 | struct shared_info *s = HYPERVISOR_shared_info; | |
780f36d8 | 1107 | struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu); |
229664be | 1108 | unsigned count; |
e46cdb66 | 1109 | |
229664be JF |
1110 | do { |
1111 | unsigned long pending_words; | |
e46cdb66 | 1112 | |
229664be | 1113 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 1114 | |
b2e4ae69 | 1115 | if (__this_cpu_inc_return(xed_nesting_count) - 1) |
229664be | 1116 | goto out; |
e46cdb66 | 1117 | |
e849c3e9 IY |
1118 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
1119 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 1120 | wmb(); |
e849c3e9 | 1121 | #endif |
229664be JF |
1122 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
1123 | while (pending_words != 0) { | |
1124 | unsigned long pending_bits; | |
1125 | int word_idx = __ffs(pending_words); | |
1126 | pending_words &= ~(1UL << word_idx); | |
1127 | ||
1128 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
1129 | int bit_idx = __ffs(pending_bits); | |
1130 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
1131 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 1132 | struct irq_desc *desc; |
229664be | 1133 | |
3588fe2e JF |
1134 | mask_evtchn(port); |
1135 | clear_evtchn(port); | |
1136 | ||
ca4dbc66 EB |
1137 | if (irq != -1) { |
1138 | desc = irq_to_desc(irq); | |
1139 | if (desc) | |
1140 | generic_handle_irq_desc(irq, desc); | |
1141 | } | |
e46cdb66 JF |
1142 | } |
1143 | } | |
e46cdb66 | 1144 | |
229664be JF |
1145 | BUG_ON(!irqs_disabled()); |
1146 | ||
780f36d8 CL |
1147 | count = __this_cpu_read(xed_nesting_count); |
1148 | __this_cpu_write(xed_nesting_count, 0); | |
183d03cc | 1149 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
1150 | |
1151 | out: | |
38e20b07 SY |
1152 | |
1153 | put_cpu(); | |
1154 | } | |
1155 | ||
1156 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
1157 | { | |
1158 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1159 | ||
1160 | exit_idle(); | |
1161 | irq_enter(); | |
1162 | ||
1163 | __xen_evtchn_do_upcall(); | |
1164 | ||
3445a8fd JF |
1165 | irq_exit(); |
1166 | set_irq_regs(old_regs); | |
38e20b07 | 1167 | } |
3445a8fd | 1168 | |
38e20b07 SY |
1169 | void xen_hvm_evtchn_do_upcall(void) |
1170 | { | |
1171 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 1172 | } |
183d03cc | 1173 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 1174 | |
eb1e305f JF |
1175 | /* Rebind a new event channel to an existing irq. */ |
1176 | void rebind_evtchn_irq(int evtchn, int irq) | |
1177 | { | |
d77bbd4d JF |
1178 | struct irq_info *info = info_for_irq(irq); |
1179 | ||
eb1e305f JF |
1180 | /* Make sure the irq is masked, since the new event channel |
1181 | will also be masked. */ | |
1182 | disable_irq(irq); | |
1183 | ||
1184 | spin_lock(&irq_mapping_update_lock); | |
1185 | ||
1186 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
1187 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
1188 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
1189 | so there should be a proper type */ |
1190 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
1191 | |
1192 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1193 | irq_info[irq] = mk_evtchn_info(evtchn); |
eb1e305f JF |
1194 | |
1195 | spin_unlock(&irq_mapping_update_lock); | |
1196 | ||
1197 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 1198 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
1199 | |
1200 | /* Unmask the event channel. */ | |
1201 | enable_irq(irq); | |
1202 | } | |
1203 | ||
e46cdb66 | 1204 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 1205 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
1206 | { |
1207 | struct evtchn_bind_vcpu bind_vcpu; | |
1208 | int evtchn = evtchn_from_irq(irq); | |
1209 | ||
183d03cc SS |
1210 | /* events delivered via platform PCI interrupts are always |
1211 | * routed to vcpu 0 */ | |
1212 | if (!VALID_EVTCHN(evtchn) || | |
1213 | (xen_hvm_domain() && !xen_have_vector_callback)) | |
d5dedd45 | 1214 | return -1; |
e46cdb66 JF |
1215 | |
1216 | /* Send future instances of this interrupt to other vcpu. */ | |
1217 | bind_vcpu.port = evtchn; | |
1218 | bind_vcpu.vcpu = tcpu; | |
1219 | ||
1220 | /* | |
1221 | * If this fails, it usually just indicates that we're dealing with a | |
1222 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
1223 | * it, but don't do the xenlinux-level rebind in that case. | |
1224 | */ | |
1225 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
1226 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 1227 | |
d5dedd45 YL |
1228 | return 0; |
1229 | } | |
e46cdb66 | 1230 | |
d5dedd45 | 1231 | static int set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 1232 | { |
0de26520 | 1233 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 YL |
1234 | |
1235 | return rebind_irq_to_cpu(irq, tcpu); | |
e46cdb66 JF |
1236 | } |
1237 | ||
642e0c88 IY |
1238 | int resend_irq_on_evtchn(unsigned int irq) |
1239 | { | |
1240 | int masked, evtchn = evtchn_from_irq(irq); | |
1241 | struct shared_info *s = HYPERVISOR_shared_info; | |
1242 | ||
1243 | if (!VALID_EVTCHN(evtchn)) | |
1244 | return 1; | |
1245 | ||
1246 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
1247 | sync_set_bit(evtchn, s->evtchn_pending); | |
1248 | if (!masked) | |
1249 | unmask_evtchn(evtchn); | |
1250 | ||
1251 | return 1; | |
1252 | } | |
1253 | ||
e46cdb66 JF |
1254 | static void enable_dynirq(unsigned int irq) |
1255 | { | |
1256 | int evtchn = evtchn_from_irq(irq); | |
1257 | ||
1258 | if (VALID_EVTCHN(evtchn)) | |
1259 | unmask_evtchn(evtchn); | |
1260 | } | |
1261 | ||
1262 | static void disable_dynirq(unsigned int irq) | |
1263 | { | |
1264 | int evtchn = evtchn_from_irq(irq); | |
1265 | ||
1266 | if (VALID_EVTCHN(evtchn)) | |
1267 | mask_evtchn(evtchn); | |
1268 | } | |
1269 | ||
1270 | static void ack_dynirq(unsigned int irq) | |
1271 | { | |
1272 | int evtchn = evtchn_from_irq(irq); | |
1273 | ||
3588fe2e | 1274 | move_masked_irq(irq); |
e46cdb66 JF |
1275 | |
1276 | if (VALID_EVTCHN(evtchn)) | |
3588fe2e | 1277 | unmask_evtchn(evtchn); |
e46cdb66 JF |
1278 | } |
1279 | ||
1280 | static int retrigger_dynirq(unsigned int irq) | |
1281 | { | |
1282 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 1283 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
1284 | int ret = 0; |
1285 | ||
1286 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
1287 | int masked; |
1288 | ||
1289 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
1290 | sync_set_bit(evtchn, sh->evtchn_pending); | |
1291 | if (!masked) | |
1292 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
1293 | ret = 1; |
1294 | } | |
1295 | ||
1296 | return ret; | |
1297 | } | |
1298 | ||
9a069c33 SS |
1299 | static void restore_cpu_pirqs(void) |
1300 | { | |
1301 | int pirq, rc, irq, gsi; | |
1302 | struct physdev_map_pirq map_irq; | |
1303 | ||
1304 | for (pirq = 0; pirq < nr_irqs; pirq++) { | |
1305 | irq = pirq_to_irq[pirq]; | |
1306 | if (irq == -1) | |
1307 | continue; | |
1308 | ||
1309 | /* save/restore of PT devices doesn't work, so at this point the | |
1310 | * only devices present are GSI based emulated devices */ | |
1311 | gsi = gsi_from_irq(irq); | |
1312 | if (!gsi) | |
1313 | continue; | |
1314 | ||
1315 | map_irq.domid = DOMID_SELF; | |
1316 | map_irq.type = MAP_PIRQ_TYPE_GSI; | |
1317 | map_irq.index = gsi; | |
1318 | map_irq.pirq = pirq; | |
1319 | ||
1320 | rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); | |
1321 | if (rc) { | |
1322 | printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n", | |
1323 | gsi, irq, pirq, rc); | |
1324 | irq_info[irq] = mk_unbound_info(); | |
1325 | pirq_to_irq[pirq] = -1; | |
1326 | continue; | |
1327 | } | |
1328 | ||
1329 | printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq); | |
1330 | ||
1331 | startup_pirq(irq); | |
1332 | } | |
1333 | } | |
1334 | ||
0e91398f JF |
1335 | static void restore_cpu_virqs(unsigned int cpu) |
1336 | { | |
1337 | struct evtchn_bind_virq bind_virq; | |
1338 | int virq, irq, evtchn; | |
1339 | ||
1340 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
1341 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
1342 | continue; | |
1343 | ||
ced40d0f | 1344 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
1345 | |
1346 | /* Get a new binding from Xen. */ | |
1347 | bind_virq.virq = virq; | |
1348 | bind_virq.vcpu = cpu; | |
1349 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
1350 | &bind_virq) != 0) | |
1351 | BUG(); | |
1352 | evtchn = bind_virq.port; | |
1353 | ||
1354 | /* Record the new mapping. */ | |
1355 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1356 | irq_info[irq] = mk_virq_info(evtchn, virq); |
0e91398f | 1357 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1358 | } |
1359 | } | |
1360 | ||
1361 | static void restore_cpu_ipis(unsigned int cpu) | |
1362 | { | |
1363 | struct evtchn_bind_ipi bind_ipi; | |
1364 | int ipi, irq, evtchn; | |
1365 | ||
1366 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
1367 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
1368 | continue; | |
1369 | ||
ced40d0f | 1370 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
1371 | |
1372 | /* Get a new binding from Xen. */ | |
1373 | bind_ipi.vcpu = cpu; | |
1374 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
1375 | &bind_ipi) != 0) | |
1376 | BUG(); | |
1377 | evtchn = bind_ipi.port; | |
1378 | ||
1379 | /* Record the new mapping. */ | |
1380 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 1381 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
0e91398f | 1382 | bind_evtchn_to_cpu(evtchn, cpu); |
0e91398f JF |
1383 | } |
1384 | } | |
1385 | ||
2d9e1e2f JF |
1386 | /* Clear an irq's pending state, in preparation for polling on it */ |
1387 | void xen_clear_irq_pending(int irq) | |
1388 | { | |
1389 | int evtchn = evtchn_from_irq(irq); | |
1390 | ||
1391 | if (VALID_EVTCHN(evtchn)) | |
1392 | clear_evtchn(evtchn); | |
1393 | } | |
d9a8814f | 1394 | EXPORT_SYMBOL(xen_clear_irq_pending); |
168d2f46 JF |
1395 | void xen_set_irq_pending(int irq) |
1396 | { | |
1397 | int evtchn = evtchn_from_irq(irq); | |
1398 | ||
1399 | if (VALID_EVTCHN(evtchn)) | |
1400 | set_evtchn(evtchn); | |
1401 | } | |
1402 | ||
1403 | bool xen_test_irq_pending(int irq) | |
1404 | { | |
1405 | int evtchn = evtchn_from_irq(irq); | |
1406 | bool ret = false; | |
1407 | ||
1408 | if (VALID_EVTCHN(evtchn)) | |
1409 | ret = test_evtchn(evtchn); | |
1410 | ||
1411 | return ret; | |
1412 | } | |
1413 | ||
d9a8814f KRW |
1414 | /* Poll waiting for an irq to become pending with timeout. In the usual case, |
1415 | * the irq will be disabled so it won't deliver an interrupt. */ | |
1416 | void xen_poll_irq_timeout(int irq, u64 timeout) | |
2d9e1e2f JF |
1417 | { |
1418 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
1419 | ||
1420 | if (VALID_EVTCHN(evtchn)) { | |
1421 | struct sched_poll poll; | |
1422 | ||
1423 | poll.nr_ports = 1; | |
d9a8814f | 1424 | poll.timeout = timeout; |
ff3c5362 | 1425 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
1426 | |
1427 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
1428 | BUG(); | |
1429 | } | |
1430 | } | |
d9a8814f KRW |
1431 | EXPORT_SYMBOL(xen_poll_irq_timeout); |
1432 | /* Poll waiting for an irq to become pending. In the usual case, the | |
1433 | * irq will be disabled so it won't deliver an interrupt. */ | |
1434 | void xen_poll_irq(int irq) | |
1435 | { | |
1436 | xen_poll_irq_timeout(irq, 0 /* no timeout */); | |
1437 | } | |
2d9e1e2f | 1438 | |
0e91398f JF |
1439 | void xen_irq_resume(void) |
1440 | { | |
1441 | unsigned int cpu, irq, evtchn; | |
6903591f | 1442 | struct irq_desc *desc; |
0e91398f JF |
1443 | |
1444 | init_evtchn_cpu_bindings(); | |
1445 | ||
1446 | /* New event-channel space is not 'live' yet. */ | |
1447 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1448 | mask_evtchn(evtchn); | |
1449 | ||
1450 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 1451 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
1452 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
1453 | ||
1454 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
1455 | evtchn_to_irq[evtchn] = -1; | |
1456 | ||
1457 | for_each_possible_cpu(cpu) { | |
1458 | restore_cpu_virqs(cpu); | |
1459 | restore_cpu_ipis(cpu); | |
1460 | } | |
6903591f IC |
1461 | |
1462 | /* | |
1463 | * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These | |
1464 | * are not handled by the IRQ core. | |
1465 | */ | |
1466 | for_each_irq_desc(irq, desc) { | |
1467 | if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND)) | |
1468 | continue; | |
1469 | if (desc->status & IRQ_DISABLED) | |
1470 | continue; | |
1471 | ||
1472 | evtchn = evtchn_from_irq(irq); | |
1473 | if (evtchn == -1) | |
1474 | continue; | |
1475 | ||
1476 | unmask_evtchn(evtchn); | |
1477 | } | |
9a069c33 SS |
1478 | |
1479 | restore_cpu_pirqs(); | |
0e91398f JF |
1480 | } |
1481 | ||
e46cdb66 JF |
1482 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
1483 | .name = "xen-dyn", | |
54a353a0 JF |
1484 | |
1485 | .disable = disable_dynirq, | |
e46cdb66 JF |
1486 | .mask = disable_dynirq, |
1487 | .unmask = enable_dynirq, | |
54a353a0 | 1488 | |
3588fe2e | 1489 | .eoi = ack_dynirq, |
e46cdb66 JF |
1490 | .set_affinity = set_affinity_irq, |
1491 | .retrigger = retrigger_dynirq, | |
1492 | }; | |
1493 | ||
d46a78b0 JF |
1494 | static struct irq_chip xen_pirq_chip __read_mostly = { |
1495 | .name = "xen-pirq", | |
1496 | ||
1497 | .startup = startup_pirq, | |
1498 | .shutdown = shutdown_pirq, | |
1499 | ||
1500 | .enable = enable_pirq, | |
1501 | .unmask = enable_pirq, | |
1502 | ||
1503 | .disable = disable_pirq, | |
1504 | .mask = disable_pirq, | |
1505 | ||
1506 | .ack = ack_pirq, | |
1507 | .end = end_pirq, | |
1508 | ||
1509 | .set_affinity = set_affinity_irq, | |
1510 | ||
1511 | .retrigger = retrigger_dynirq, | |
1512 | }; | |
1513 | ||
aaca4964 JF |
1514 | static struct irq_chip xen_percpu_chip __read_mostly = { |
1515 | .name = "xen-percpu", | |
1516 | ||
1517 | .disable = disable_dynirq, | |
1518 | .mask = disable_dynirq, | |
1519 | .unmask = enable_dynirq, | |
1520 | ||
1521 | .ack = ack_dynirq, | |
1522 | }; | |
1523 | ||
38e20b07 SY |
1524 | int xen_set_callback_via(uint64_t via) |
1525 | { | |
1526 | struct xen_hvm_param a; | |
1527 | a.domid = DOMID_SELF; | |
1528 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
1529 | a.value = via; | |
1530 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
1531 | } | |
1532 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
1533 | ||
ca65f9fc | 1534 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
1535 | /* Vector callbacks are better than PCI interrupts to receive event |
1536 | * channel notifications because we can receive vector callbacks on any | |
1537 | * vcpu and we don't need PCI support or APIC interactions. */ | |
1538 | void xen_callback_vector(void) | |
1539 | { | |
1540 | int rc; | |
1541 | uint64_t callback_via; | |
1542 | if (xen_have_vector_callback) { | |
1543 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1544 | rc = xen_set_callback_via(callback_via); | |
1545 | if (rc) { | |
1546 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1547 | " failed.\n"); | |
1548 | xen_have_vector_callback = 0; | |
1549 | return; | |
1550 | } | |
1551 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1552 | "enabled\n"); | |
1553 | /* in the restore case the vector has already been allocated */ | |
1554 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1555 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1556 | } | |
1557 | } | |
ca65f9fc SS |
1558 | #else |
1559 | void xen_callback_vector(void) {} | |
1560 | #endif | |
38e20b07 | 1561 | |
e46cdb66 JF |
1562 | void __init xen_init_IRQ(void) |
1563 | { | |
e5fc7345 | 1564 | int i; |
c7a3589e | 1565 | |
a70c352a PE |
1566 | cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s), |
1567 | GFP_KERNEL); | |
b21ddbf5 JF |
1568 | irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL); |
1569 | ||
e5fc7345 SS |
1570 | /* We are using nr_irqs as the maximum number of pirq available but |
1571 | * that number is actually chosen by Xen and we don't know exactly | |
1572 | * what it is. Be careful choosing high pirq numbers. */ | |
1573 | pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL); | |
1574 | for (i = 0; i < nr_irqs; i++) | |
7a043f11 SS |
1575 | pirq_to_irq[i] = -1; |
1576 | ||
b21ddbf5 JF |
1577 | evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq), |
1578 | GFP_KERNEL); | |
1579 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1580 | evtchn_to_irq[i] = -1; | |
e46cdb66 JF |
1581 | |
1582 | init_evtchn_cpu_bindings(); | |
1583 | ||
1584 | /* No event channels are 'live' right now. */ | |
1585 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1586 | mask_evtchn(i); | |
1587 | ||
38e20b07 SY |
1588 | if (xen_hvm_domain()) { |
1589 | xen_callback_vector(); | |
1590 | native_init_IRQ(); | |
3942b740 SS |
1591 | /* pci_xen_hvm_init must be called after native_init_IRQ so that |
1592 | * __acpi_register_gsi can point at the right function */ | |
1593 | pci_xen_hvm_init(); | |
38e20b07 SY |
1594 | } else { |
1595 | irq_ctx_init(smp_processor_id()); | |
38aa66fc JF |
1596 | if (xen_initial_domain()) |
1597 | xen_setup_pirqs(); | |
38e20b07 | 1598 | } |
e46cdb66 | 1599 | } |